; -------------------------------------------------------------------------------- ; @Title: LPC55xx On-Chip Peripherals ; @Props: Released ; @Author: BGI, KWI, PIW, KRZ ; @Changelog: 2019-04-24 BGI ; 2021-06-25 KWI ; 2022-01-27 PIW ; 2023-01-31 KRZ ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: SVD generated (SVD2PER 1.8.6), based on: ; LPC5502.svd (Ver. 1.0), LPC5504.svd (Ver. 1.0), LPC5506.svd (Ver. 1.0), ; LPC5512.svd (Ver. 1.0), LPC5514.svd (Ver. 1.0), LPC5516.svd (Ver. 1.0), ; LPC5526.svd (Ver. 1.0), LPC5528.svd (Ver. 1.0), LPC5534.svd (Ver. 1.0), ; LPC5536.svd (Ver. 1.0) ; @Core: Cortex-M33F ; @Chip: LPC5502JBD64, LPC5502JHI48, LPC5504JBD64, LPC5504JHI48, LPC5506JBD64, ; LPC5506JHI48, LPC5512JBD100, LPC5512JBD64, LPC5514JBD100, LPC5514JBD64, ; LPC5516JBD100, LPC5516JBD64, LPC5516JEV98, LPC5526JBD100, LPC5526JBD64, ; LPC5526JEV98, LPC5528JBD100, LPC5528JBD64, LPC5528JEV98, LPC5534JBD100, ; LPC5534JBD64, LPC5534JHI48, LPC5536JBD100, LPC5536JBD64, LPC5536JHI48 ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perlpc55xx.per 15701 2023-01-31 17:02:04Z kwisniewski $ sif (CORENAME()=="CORTEXM33F") tree.close "Core Registers (Cortex-M33F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" textline " " bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes" group.long 0x0C++0x0F line.long 0x00 "CPPWR,Coprocessor Power Control Register" bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted" textline " " bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only" textline " " bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted" bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only" bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted" line.long 0x04 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x08 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x0C "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..." group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" textline " " bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure" rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending" textline " " hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" line.long 0x14 "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV" hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending" bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending" bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active" bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active" textline " " bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active" bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "UFSR,Usage Fault Status Register" eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error" textline " " eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error" textline " " eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x03 line.long 0x00 "HFSR,HardFault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full" if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48) group.long 0xD8C++0x03 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled" bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled" bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled" bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled" bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled" bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled" bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled" else hgroup.long 0xD8C++0x03 hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)" endif wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended" tree "Memory System" width 10. rgroup.long 0xD78++0x03 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest" bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..." textline " " bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..." bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..." bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..." textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..." bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..." bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..." textline " " bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000) rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..." bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..." textline " " bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.long 0xD7C++0x03 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..." endif rgroup.long 0xD80++0x03 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported" bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported" hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512" group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU" wgroup.long 0xF58++0x23 line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU" line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC" line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way" hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU" line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC" line.long 0x14 "DCCSW,D-Cache Clean by Set-Way" hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC" line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way" hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on" bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8" line.long 0x20 "BPIALL,Branch Predictor Invalidate All" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..." rgroup.long 0xD4C++0x03 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..." rgroup.long 0xD54++0x03 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD5C++0x03 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..." rgroup.long 0xD60++0x03 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." rgroup.long 0xD64++0x03 line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..." rgroup.long 0xD68++0x03 line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..." textline " " bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..." rgroup.long 0xD6C++0x03 line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..." textline " " bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..." rgroup.long 0xD70++0x03 line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..." bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..." bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..." textline " " bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..." bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..." tree.end tree "CoreSight Identification Registers" base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 11. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFE0++0x0F line.long 0x00 "DPIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "DPIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "DPIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "DPIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "DCIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DCIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DCIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "DCIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any" textline " " bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15" hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region" bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" textline " " hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15" endif tree.end newline group.long 0xDC0++0x07 line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1" bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" newline bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate" bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Security Attribution Unit (SAU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. group.long 0xDD0++0x03 line.long 0x00 "SAU_CTRL,SAU Control Register" bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure" bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled" rgroup.long 0xDD4++0x03 line.long 0x00 "SAU_TYPE,SAU Type Register" bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..." group.long 0xDD8++0x03 line.long 0x00 "SAU_RNR,SAU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR" tree.close "SAU regions" if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0) if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0 group.long 0xDDC++0x03 "Region 0" saveout 0xDD8 %l 0x0 line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 0 (not implemented)" saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1 group.long 0xDDC++0x03 "Region 1" saveout 0xDD8 %l 0x1 line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 1 (not implemented)" saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2 group.long 0xDDC++0x03 "Region 2" saveout 0xDD8 %l 0x2 line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 2 (not implemented)" saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3 group.long 0xDDC++0x03 "Region 3" saveout 0xDD8 %l 0x3 line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 3 (not implemented)" saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4 group.long 0xDDC++0x03 "Region 4" saveout 0xDD8 %l 0x4 line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 4 (not implemented)" saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5 group.long 0xDDC++0x03 "Region 5" saveout 0xDD8 %l 0x5 line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 5 (not implemented)" saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6 group.long 0xDDC++0x03 "Region 6" saveout 0xDD8 %l 0x6 line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 6 (not implemented)" saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" endif if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7 group.long 0xDDC++0x03 "Region 7" saveout 0xDD8 %l 0x7 line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region" bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted" bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled" else hgroup.long 0xDDC++0x03 "Region 7 (not implemented)" saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif else hgroup.long 0xDDC++0x03 "Region 0 (not accessible)" saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x0 hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0" hgroup.long 0xDDC++0x03 "Region 1 (not accessible)" saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x1 hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1" hgroup.long 0xDDC++0x03 "Region 2 (not accessible)" saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x2 hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2" hgroup.long 0xDDC++0x03 "Region 3 (not accessible)" saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x3 hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3" hgroup.long 0xDDC++0x03 "Region 4 (not accessible)" saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x4 hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4" hgroup.long 0xDDC++0x03 "Region 5 (not accessible)" saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x5 hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5" hgroup.long 0xDDC++0x03 "Region 6 (not accessible)" saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x6 hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6" hgroup.long 0xDDC++0x03 "Region 7 (not accessible)" saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7" hgroup.long 0xDE0++0x03 saveout 0xDD8 %l 0x7 hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7" endif tree.end group.long 0xDE4++0x03 line.long 0x00 "SFSR,Secure Fault Status Register" bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred" bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid" bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred" bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred" bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred" bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred" group.long 0xDE8++0x03 line.long 0x00 "SFAR,Secure Fault Address Register" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. group.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511" width 24. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x104++0x03 line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x104++0x03 hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x108++0x03 line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x108++0x03 hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x10C++0x03 line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x10C++0x03 hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x110++0x03 line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x110++0x03 hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x114++0x03 line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x114++0x03 hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x118++0x03 line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x118++0x03 hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x11C++0x03 line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x11C++0x03 hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x120++0x03 line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x120++0x03 hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x124++0x03 line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x124++0x03 hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x128++0x03 line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x128++0x03 hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x12C++0x03 line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x12C++0x03 hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x130++0x03 line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x130++0x03 hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x134++0x03 line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x134++0x03 hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x138++0x03 line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x138++0x03 hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F) group.long 0x13C++0x03 line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x13C++0x03 hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register" endif tree.end width 24. tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x204++0x03 line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x204++0x03 hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x208++0x03 line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x208++0x03 hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x20C++0x03 line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x20C++0x03 hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x210++0x03 line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x210++0x03 hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x214++0x03 line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x214++0x03 hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x218++0x03 line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x218++0x03 hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x21C++0x03 line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x21C++0x03 hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x220++0x03 line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x220++0x03 hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x224++0x03 line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x224++0x03 hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x228++0x03 line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x228++0x03 hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x22C++0x03 line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x22C++0x03 hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x230++0x03 line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x230++0x03 hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x234++0x03 line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x234++0x03 hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x238++0x03 line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x238++0x03 hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F) group.long 0x23C++0x03 line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x23C++0x03 hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register" endif tree.end width 11. tree "Interrupt Active Bit Registers" rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE0,Active Bit Register 0" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) rgroup.long 0x304++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x304++0x03 hide.long 0x00 "ACTIVE1,Active Bit Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) rgroup.long 0x308++0x03 line.long 0x00 "ACTIVE2,Active Bit Register 2" bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x308++0x03 hide.long 0x00 "ACTIVE2,Active Bit Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) rgroup.long 0x30C++0x03 line.long 0x00 "ACTIVE3,Active Bit Register 3" bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x30C++0x03 hide.long 0x00 "ACTIVE3,Active Bit Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) rgroup.long 0x310++0x03 line.long 0x00 "ACTIVE4,Active Bit Register 4" bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x310++0x03 hide.long 0x00 "ACTIVE4,Active Bit Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) rgroup.long 0x314++0x03 line.long 0x00 "ACTIVE5,Active Bit Register 5" bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x314++0x03 hide.long 0x00 "ACTIVE5,Active Bit Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) rgroup.long 0x318++0x03 line.long 0x00 "ACTIVE6,Active Bit Register 6" bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x318++0x03 hide.long 0x00 "ACTIVE6,Active Bit Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) rgroup.long 0x31C++0x03 line.long 0x00 "ACTIVE7,Active Bit Register 7" bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x31C++0x03 hide.long 0x00 "ACTIVE7,Active Bit Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) rgroup.long 0x320++0x03 line.long 0x00 "ACTIVE8,Active Bit Register 8" bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x320++0x03 hide.long 0x00 "ACTIVE8,Active Bit Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) rgroup.long 0x324++0x03 line.long 0x00 "ACTIVE9,Active Bit Register 9" bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x324++0x03 hide.long 0x00 "ACTIVE9,Active Bit Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) rgroup.long 0x328++0x03 line.long 0x00 "ACTIVE10,Active Bit Register 10" bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x328++0x03 hide.long 0x00 "ACTIVE10,Active Bit Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) rgroup.long 0x32C++0x03 line.long 0x00 "ACTIVE11,Active Bit Register 11" bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x32C++0x03 hide.long 0x00 "ACTIVE11,Active Bit Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) rgroup.long 0x330++0x03 line.long 0x00 "ACTIVE12,Active Bit Register 12" bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x330++0x03 hide.long 0x00 "ACTIVE12,Active Bit Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) rgroup.long 0x334++0x03 line.long 0x00 "ACTIVE13,Active Bit Register 13" bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x334++0x03 hide.long 0x00 "ACTIVE13,Active Bit Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) rgroup.long 0x338++0x03 line.long 0x00 "ACTIVE14,Active Bit Register 14" bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x338++0x03 hide.long 0x00 "ACTIVE14,Active Bit Register 14" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F) rgroup.long 0x33C++0x03 line.long 0x00 "ACTIVE15,Active Bit Register 15" bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x33C++0x03 hide.long 0x00 "ACTIVE15,Active Bit Register 15" endif tree.end width 13. tree "Interrupt Target Non-Secure Registers" group.long 0x380++0x03 line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0" bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x384++0x03 line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure" else hgroup.long 0x384++0x03 hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x388++0x03 line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure" else hgroup.long 0x388++0x03 hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x38C++0x03 line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure" else hgroup.long 0x38C++0x03 hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x390++0x03 line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure" else hgroup.long 0x390++0x03 hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x394++0x03 line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure" else hgroup.long 0x394++0x03 hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x398++0x03 line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure" else hgroup.long 0x398++0x03 hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x39C++0x03 line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure" else hgroup.long 0x39C++0x03 hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x3A0++0x03 line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure" else hgroup.long 0x3A0++0x03 hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x3A4++0x03 line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure" else hgroup.long 0x3A4++0x03 hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x3A8++0x03 line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure" else hgroup.long 0x3A8++0x03 hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x3AC++0x03 line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure" else hgroup.long 0x3AC++0x03 hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x3B0++0x03 line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure" else hgroup.long 0x3B0++0x03 hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x3B4++0x03 line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure" else hgroup.long 0x3B4++0x03 hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x3B8++0x03 line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure" else hgroup.long 0x3B8++0x03 hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F) group.long 0x3BC++0x03 line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15" bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure" bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure" bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure" textline " " bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure" bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure" bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure" textline " " bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure" bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure" bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure" textline " " bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure" bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure" bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure" textline " " bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure" bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure" bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure" textline " " bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure" bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure" bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure" textline " " bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure" bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure" bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure" textline " " bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure" bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure" bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure" textline " " bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure" bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure" bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure" textline " " bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure" bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure" bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure" textline " " bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure" bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure" else hgroup.long 0x3BC++0x03 hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15" endif tree.end tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01) group.long 0x420++0x1F line.long 0x0 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x4 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x8 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0xC "IPR11,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x10 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x14 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x18 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x1C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" else hgroup.long 0x420++0x1F hide.long 0x0 "IPR8,Interrupt Priority Register" hide.long 0x4 "IPR9,Interrupt Priority Register" hide.long 0x8 "IPR10,Interrupt Priority Register" hide.long 0xC "IPR11,Interrupt Priority Register" hide.long 0x10 "IPR12,Interrupt Priority Register" hide.long 0x14 "IPR13,Interrupt Priority Register" hide.long 0x18 "IPR14,Interrupt Priority Register" hide.long 0x1C "IPR15,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02) group.long 0x440++0x1F line.long 0x0 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x4 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x8 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0xC "IPR19,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x10 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x14 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x18 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x1C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" else hgroup.long 0x440++0x1F hide.long 0x0 "IPR16,Interrupt Priority Register" hide.long 0x4 "IPR17,Interrupt Priority Register" hide.long 0x8 "IPR18,Interrupt Priority Register" hide.long 0xC "IPR19,Interrupt Priority Register" hide.long 0x10 "IPR20,Interrupt Priority Register" hide.long 0x14 "IPR21,Interrupt Priority Register" hide.long 0x18 "IPR22,Interrupt Priority Register" hide.long 0x1C "IPR23,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03) group.long 0x460++0x1F line.long 0x0 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x4 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x8 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0xC "IPR27,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x10 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x14 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x18 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x1C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" else hgroup.long 0x460++0x1F hide.long 0x0 "IPR24,Interrupt Priority Register" hide.long 0x4 "IPR25,Interrupt Priority Register" hide.long 0x8 "IPR26,Interrupt Priority Register" hide.long 0xC "IPR27,Interrupt Priority Register" hide.long 0x10 "IPR28,Interrupt Priority Register" hide.long 0x14 "IPR29,Interrupt Priority Register" hide.long 0x18 "IPR30,Interrupt Priority Register" hide.long 0x1C "IPR31,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04) group.long 0x480++0x1F line.long 0x0 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x4 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x8 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0xC "IPR35,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x10 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x14 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x18 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x1C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" else hgroup.long 0x480++0x1F hide.long 0x0 "IPR32,Interrupt Priority Register" hide.long 0x4 "IPR33,Interrupt Priority Register" hide.long 0x8 "IPR34,Interrupt Priority Register" hide.long 0xC "IPR35,Interrupt Priority Register" hide.long 0x10 "IPR36,Interrupt Priority Register" hide.long 0x14 "IPR37,Interrupt Priority Register" hide.long 0x18 "IPR38,Interrupt Priority Register" hide.long 0x1C "IPR39,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05) group.long 0x4A0++0x1F line.long 0x0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0x4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0x8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0x10 "IPR44,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0x14 "IPR45,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0x18 "IPR46,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0x1C "IPR47,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" else hgroup.long 0x4A0++0x1F hide.long 0x0 "IPR40,Interrupt Priority Register" hide.long 0x4 "IPR41,Interrupt Priority Register" hide.long 0x8 "IPR42,Interrupt Priority Register" hide.long 0xC "IPR43,Interrupt Priority Register" hide.long 0x10 "IPR44,Interrupt Priority Register" hide.long 0x14 "IPR45,Interrupt Priority Register" hide.long 0x18 "IPR46,Interrupt Priority Register" hide.long 0x1C "IPR47,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06) group.long 0x4C0++0x1F line.long 0x0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0x4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0x8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0x10 "IPR52,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0x14 "IPR53,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0x18 "IPR54,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0x1C "IPR55,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" else hgroup.long 0x4C0++0x1F hide.long 0x0 "IPR48,Interrupt Priority Register" hide.long 0x4 "IPR49,Interrupt Priority Register" hide.long 0x8 "IPR50,Interrupt Priority Register" hide.long 0xC "IPR51,Interrupt Priority Register" hide.long 0x10 "IPR52,Interrupt Priority Register" hide.long 0x14 "IPR53,Interrupt Priority Register" hide.long 0x18 "IPR54,Interrupt Priority Register" hide.long 0x1C "IPR55,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07) group.long 0x4E0++0x1F line.long 0x0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0x4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0x8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" line.long 0x10 "IPR60,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority" line.long 0x14 "IPR61,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority" line.long 0x18 "IPR62,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority" line.long 0x1C "IPR63,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority" else hgroup.long 0x4E0++0x1F hide.long 0x0 "IPR56,Interrupt Priority Register" hide.long 0x4 "IPR57,Interrupt Priority Register" hide.long 0x8 "IPR58,Interrupt Priority Register" hide.long 0xC "IPR59,Interrupt Priority Register" hide.long 0x10 "IPR60,Interrupt Priority Register" hide.long 0x14 "IPR61,Interrupt Priority Register" hide.long 0x18 "IPR62,Interrupt Priority Register" hide.long 0x1C "IPR63,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08) group.long 0x500++0x1F line.long 0x0 "IPR64,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority" line.long 0x4 "IPR65,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority" line.long 0x8 "IPR66,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority" line.long 0xC "IPR67,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority" line.long 0x10 "IPR68,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority" line.long 0x14 "IPR69,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority" line.long 0x18 "IPR70,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority" line.long 0x1C "IPR71,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority" else hgroup.long 0x500++0x1F hide.long 0x0 "IPR64,Interrupt Priority Register" hide.long 0x4 "IPR65,Interrupt Priority Register" hide.long 0x8 "IPR66,Interrupt Priority Register" hide.long 0xC "IPR67,Interrupt Priority Register" hide.long 0x10 "IPR68,Interrupt Priority Register" hide.long 0x14 "IPR69,Interrupt Priority Register" hide.long 0x18 "IPR70,Interrupt Priority Register" hide.long 0x1C "IPR71,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09) group.long 0x520++0x1F line.long 0x0 "IPR72,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority" line.long 0x4 "IPR73,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority" line.long 0x8 "IPR74,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority" line.long 0xC "IPR75,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority" line.long 0x10 "IPR76,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority" line.long 0x14 "IPR77,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority" line.long 0x18 "IPR78,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority" line.long 0x1C "IPR79,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority" else hgroup.long 0x520++0x1F hide.long 0x0 "IPR72,Interrupt Priority Register" hide.long 0x4 "IPR73,Interrupt Priority Register" hide.long 0x8 "IPR74,Interrupt Priority Register" hide.long 0xC "IPR75,Interrupt Priority Register" hide.long 0x10 "IPR76,Interrupt Priority Register" hide.long 0x14 "IPR77,Interrupt Priority Register" hide.long 0x18 "IPR78,Interrupt Priority Register" hide.long 0x1C "IPR79,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A) group.long 0x540++0x1F line.long 0x0 "IPR80,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority" line.long 0x4 "IPR81,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority" line.long 0x8 "IPR82,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority" line.long 0xC "IPR83,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority" line.long 0x10 "IPR84,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority" line.long 0x14 "IPR85,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority" line.long 0x18 "IPR86,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority" line.long 0x1C "IPR87,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority" else hgroup.long 0x540++0x1F hide.long 0x0 "IPR80,Interrupt Priority Register" hide.long 0x4 "IPR81,Interrupt Priority Register" hide.long 0x8 "IPR82,Interrupt Priority Register" hide.long 0xC "IPR83,Interrupt Priority Register" hide.long 0x10 "IPR84,Interrupt Priority Register" hide.long 0x14 "IPR85,Interrupt Priority Register" hide.long 0x18 "IPR86,Interrupt Priority Register" hide.long 0x1C "IPR87,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B) group.long 0x560++0x1F line.long 0x0 "IPR88,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority" line.long 0x4 "IPR89,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority" line.long 0x8 "IPR90,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority" line.long 0xC "IPR91,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority" line.long 0x10 "IPR92,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority" line.long 0x14 "IPR93,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority" line.long 0x18 "IPR94,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority" line.long 0x1C "IPR95,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority" else hgroup.long 0x560++0x1F hide.long 0x0 "IPR88,Interrupt Priority Register" hide.long 0x4 "IPR89,Interrupt Priority Register" hide.long 0x8 "IPR90,Interrupt Priority Register" hide.long 0xC "IPR91,Interrupt Priority Register" hide.long 0x10 "IPR92,Interrupt Priority Register" hide.long 0x14 "IPR93,Interrupt Priority Register" hide.long 0x18 "IPR94,Interrupt Priority Register" hide.long 0x1C "IPR95,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C) group.long 0x580++0x1F line.long 0x0 "IPR96,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority" line.long 0x4 "IPR97,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority" line.long 0x8 "IPR98,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority" line.long 0xC "IPR99,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority" line.long 0x10 "IPR100,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority" line.long 0x14 "IPR101,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority" line.long 0x18 "IPR102,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority" line.long 0x1C "IPR103,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority" else hgroup.long 0x580++0x1F hide.long 0x0 "IPR96,Interrupt Priority Register" hide.long 0x4 "IPR97,Interrupt Priority Register" hide.long 0x8 "IPR98,Interrupt Priority Register" hide.long 0xC "IPR99,Interrupt Priority Register" hide.long 0x10 "IPR100,Interrupt Priority Register" hide.long 0x14 "IPR101,Interrupt Priority Register" hide.long 0x18 "IPR102,Interrupt Priority Register" hide.long 0x1C "IPR103,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D) group.long 0x5A0++0x1F line.long 0x0 "IPR104,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority" line.long 0x4 "IPR105,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority" line.long 0x8 "IPR106,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority" line.long 0xC "IPR107,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority" line.long 0x10 "IPR108,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority" line.long 0x14 "IPR109,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority" line.long 0x18 "IPR110,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority" line.long 0x1C "IPR111,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority" else hgroup.long 0x5A0++0x1F hide.long 0x0 "IPR104,Interrupt Priority Register" hide.long 0x4 "IPR105,Interrupt Priority Register" hide.long 0x8 "IPR106,Interrupt Priority Register" hide.long 0xC "IPR107,Interrupt Priority Register" hide.long 0x10 "IPR108,Interrupt Priority Register" hide.long 0x14 "IPR109,Interrupt Priority Register" hide.long 0x18 "IPR110,Interrupt Priority Register" hide.long 0x1C "IPR111,Interrupt Priority Register" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E) group.long 0x5C0++0x1F line.long 0x0 "IPR112,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority" line.long 0x4 "IPR113,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority" line.long 0x8 "IPR114,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority" line.long 0xC "IPR115,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority" line.long 0x10 "IPR116,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority" line.long 0x14 "IPR117,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority" line.long 0x18 "IPR118,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority" line.long 0x1C "IPR119,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority" else hgroup.long 0x5C0++0x1F hide.long 0x0 "IPR112,Interrupt Priority Register" hide.long 0x4 "IPR113,Interrupt Priority Register" hide.long 0x8 "IPR114,Interrupt Priority Register" hide.long 0xC "IPR115,Interrupt Priority Register" hide.long 0x10 "IPR116,Interrupt Priority Register" hide.long 0x14 "IPR117,Interrupt Priority Register" hide.long 0x18 "IPR118,Interrupt Priority Register" hide.long 0x1C "IPR119,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif (CORENAME()=="CORTEXM33F") tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored" newline bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled" bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only" bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled" newline bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able" bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" newline bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able" bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" newline bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure" newline bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" newline bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." newline bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." newline bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..." line.long 0x08 "MVFR2,Media and FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 13. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" newline bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" newline bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif newline group.long 0xE04++0x07 line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register" bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN" bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled" bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN" line.long 0x04 "DSCSR,Debug Security Control and Status Register" bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure" bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure" bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled" rgroup.long 0xFB8++0x03 line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1" bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented" bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1" newline bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1" bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 12. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..." rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline " " if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000) rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported" hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address" else rgroup.long 0x04++0x03 line.long 0x00 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled" hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" textfld " " hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode" endif tree "CoreSight Identification Registers" width 12. rgroup.long 0xFCC++0x03 line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type" hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFE0++0x0F line.long 0x00 "FP_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "FP_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "FP_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "FP_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "FP_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "FP_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "FP_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0b else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 16. group.long 0x00++0x03 line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..." rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" textline " " rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000) group.long 0x04++0x03 line.long 0x00 "DWT_CYCCNT,Cycle Count register" endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000) group.long 0x08++0x17 line.long 0x00 "DWT_CPICNT,CPI Count register" hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter" line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x10 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter" line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register" hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter" endif rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF) group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" endif group.long (0x20+0x08)++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF) group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" endif group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF) group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" endif group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value" elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF) group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address" else group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" endif group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3" bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" textline " " bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address" bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved" tree "CoreSight Identification Registers" width 13. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000) rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part" else rgroup.long 0xFBC++0x03 line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register" bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present" endif rgroup.long 0xFCC++0x03 line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register" hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type" hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type" rgroup.long 0xFE0++0x0F line.long 0x00 "DWT_PIDR0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "DWT_PIDR1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "DWT_PIDR2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "DWT_PIDR3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)" hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble" line.long 0x04 "DWT_CIDR1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class" line.long 0x08 "DWT_CIDR2,Component ID2" hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble" line.long 0x0c "DWT_CIDR3,Component ID3" hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble" tree.end width 0x0b else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif autoindent.on center tree tree "ADC (Analog-to-Digital Converter)" tree "ADC0" base ad:0x400A0000 rgroup.long 0x00++0x03 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number" newline bitfld.long 0x00 12.--14. "NUM_FIFO,Number of FIFOs" "0: NUM_FIFO_0,1: This design supports one result FIFO,2: This design supports two result FIFOs,3: This design supports three result FIFOs,4: This design supports four result FIFOs,?..." bitfld.long 0x00 11. "NUM_SEC,Number of Single Ended Outputs Supported" "0: This design supports one single ended..,1: This design supports two simultanious single.." newline bitfld.long 0x00 10. "CALOFSI,Calibration Function Implemented" "0: Calibration Not Implemented,1: Calibration Implemented" bitfld.long 0x00 9. "IADCKI,Internal ADC Clock implemented" "0: Internal clock source not implemented,1: Internal clock source (and CFG[ADCKEN]).." newline bitfld.long 0x00 8. "VR1RNGI,Voltage Reference 1 Range Control Bit Implemented" "0: Range control not required,1: Range control required" bitfld.long 0x00 4.--6. "CSW,Channel Scale Width" "0: Channel scaling not supported,1: Channel scaling supported,?,?,?,?,6: Channel scaling supported,?..." newline bitfld.long 0x00 3. "MVI,Multi Vref Implemented" "0: Single voltage reference high (VREFH) input..,1: Multiple voltage reference high (VREFH).." bitfld.long 0x00 1. "DIFFEN,Differential Supported" "0: Differential operation not supported,1: Differential operation supported" newline bitfld.long 0x00 0. "RES,Resolution" "0: Up to 13-bit differential/12-bit single ended..,1: Up to 16-bit differential/16-bit single ended.." rgroup.long 0x04++0x03 line.long 0x00 "PARAM,Parameter Register" hexmask.long.byte 0x00 24.--31. 1. "CMD_NUM,Command Buffer Number" hexmask.long.byte 0x00 16.--23. 1. "CV_NUM,Compare Value Number" newline hexmask.long.byte 0x00 8.--15. 1. "FIFOSIZE,Result FIFO Depth" hexmask.long.byte 0x00 0.--7. 1. "TRIG_NUM,Trigger Number" group.long 0x10++0x03 line.long 0x00 "CTRL,ADC Control Register" bitfld.long 0x00 16.--18. "CAL_AVGS,Auto-Calibration Averages" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 9. "RSTFIFO1,Reset FIFO 1" "0: RSTFIFO1_0,1: FIFO 1 is reset" newline bitfld.long 0x00 8. "RSTFIFO0,Reset FIFO 0" "0: RSTFIFO0_0,1: FIFO 0 is reset" bitfld.long 0x00 4. "CALOFS,Configure for offset calibration function" "0: Calibration function disabled,1: Request for offset calibration function" newline bitfld.long 0x00 3. "CAL_REQ,Auto-Calibration Request" "0: No request for auto-calibration has been made,1: A request for auto-calibration has been made" bitfld.long 0x00 2. "DOZEN,Doze Enable" "0: ADC is enabled in low power mode,1: ADC is disabled in low power mode" newline bitfld.long 0x00 1. "RST,Software Reset" "0: ADC logic is not reset,1: ADC logic is reset" bitfld.long 0x00 0. "ADCEN,ADC Enable" "0: ADC is disabled,1: ADC is enabled" group.long 0x10++0x03 line.long 0x00 "CTRL,ADC Control Register" bitfld.long 0x00 16.--18. "CAL_AVGS,Auto-Calibration Averages" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 9. "RSTFIFO1,Reset FIFO 1" "0: RSTFIFO1_0,1: FIFO 1 is reset" newline bitfld.long 0x00 8. "RSTFIFO0,Reset FIFO 0" "0: RSTFIFO0_0,1: FIFO 0 is reset" bitfld.long 0x00 4. "CALOFS,Configure for offset calibration function" "0: Calibration function disabled,1: Request for offset calibration function" newline bitfld.long 0x00 3. "CAL_REQ,Auto-Calibration Request" "0: No request for auto-calibration has been made,1: A request for auto-calibration has been made" bitfld.long 0x00 2. "DOZEN,Doze Enable" "0: ADC is enabled in Doze mode,1: ADC is disabled in Doze mode" newline bitfld.long 0x00 1. "RST,Software Reset" "0: ADC logic is not reset,1: ADC logic is reset" bitfld.long 0x00 0. "ADCEN,ADC Enable" "0: ADC is disabled,1: ADC is enabled" group.long 0x14++0x03 line.long 0x00 "STAT,ADC Status Register" rbitfld.long 0x00 24.--27. "CMDACT,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,3: Associated command number is currently being..,4: Associated command number is currently being..,5: Associated command number is currently being..,6: Associated command number is currently being..,7: Associated command number is currently being..,8: Associated command number is currently being..,9: Associated command number is currently being..,?..." rbitfld.long 0x00 16.--17. "TRGACT,Trigger Active" "0: Command (sequence) associated with Trigger 0..,1: Command (sequence) associated with Trigger 1..,2: Command (sequence) associated with Trigger 2..,3: Command (sequence) associated with Trigger 3.." newline rbitfld.long 0x00 11. "ADC_ACTIVE,ADC Active" "0: The ADC is IDLE,1: The ADC is processing a conversion running.." rbitfld.long 0x00 10. "CAL_RDY,Calibration Ready" "0: Calibration is incomplete or hasn't been ran,1: The ADC is calibrated" newline eventfld.long 0x00 9. "TCOMP_INT,Interrupt Flag For Trigger Completion" "0: Either IE[TCOMP_IE] is set to 0 or no trigger..,1: Trigger sequence has been completed and all.." eventfld.long 0x00 8. "TEXC_INT,Interrupt Flag For High Priority Trigger Exception" "0: No trigger exceptions have occurred,1: A trigger exception has occurred and is.." newline eventfld.long 0x00 3. "FOF1,Result FIFO1 Overflow Flag" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.." rbitfld.long 0x00 2. "RDY1,Result FIFO1 Ready Flag" "0: Result FIFO1 data level not above watermark..,1: Result FIFO1 holding data above watermark level" newline eventfld.long 0x00 1. "FOF0,Result FIFO 0 Overflow Flag" "0: No result FIFO 0 overflow has occurred since..,1: At least one result FIFO 0 overflow has.." rbitfld.long 0x00 0. "RDY0,Result FIFO 0 Ready Flag" "0: Result FIFO 0 data level not above watermark..,1: Result FIFO 0 holding data above watermark.." group.long 0x14++0x03 line.long 0x00 "STAT,ADC Status Register" rbitfld.long 0x00 24.--27. "CMDACT,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,3: Associated command number is currently being..,4: Associated command number is currently being..,5: Associated command number is currently being..,6: Associated command number is currently being..,7: Associated command number is currently being..,8: Associated command number is currently being..,9: Associated command number is currently being..,?..." rbitfld.long 0x00 16.--19. "TRGACT,Trigger Active" "0: Command (sequence) associated with Trigger 0..,1: Command (sequence) associated with Trigger 1..,2: Command (sequence) associated with Trigger 2..,3: Command (sequence) from the associated..,4: Command (sequence) from the associated..,5: Command (sequence) from the associated..,6: Command (sequence) from the associated..,7: Command (sequence) from the associated..,8: Command (sequence) from the associated..,9: Command (sequence) from the associated..,?..." newline rbitfld.long 0x00 11. "ADC_ACTIVE,ADC Active" "0: The ADC is IDLE,1: The ADC is processing a conversion running.." rbitfld.long 0x00 10. "CAL_RDY,Calibration Ready" "0: Calibration is incomplete or hasn't been ran,1: The ADC is calibrated" newline eventfld.long 0x00 9. "TCOMP_INT,Interrupt Flag For Trigger Completion" "0: Either IE[TCOMP_IE] is set to 0 or no trigger..,1: Trigger sequence has been completed and all.." eventfld.long 0x00 8. "TEXC_INT,Interrupt Flag For High Priority Trigger Exception" "0: No trigger exceptions have occurred,1: A trigger exception has occurred and is.." newline eventfld.long 0x00 3. "FOF1,Result FIFO1 Overflow Flag" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.." rbitfld.long 0x00 2. "RDY1,Result FIFO1 Ready Flag" "0: Result FIFO1 data level not above watermark..,1: Result FIFO1 holding data above watermark level" newline eventfld.long 0x00 1. "FOF0,Result FIFO 0 Overflow Flag" "0: No result FIFO 0 overflow has occurred since..,1: At least one result FIFO 0 overflow has.." rbitfld.long 0x00 0. "RDY0,Result FIFO 0 Ready Flag" "0: Result FIFO 0 data level not above watermark..,1: Result FIFO 0 holding data above watermark.." group.long 0x18++0x03 line.long 0x00 "IE,Interrupt Enable Register" bitfld.long 0x00 16.--19. "TCOMP_IE,Trigger Completion Interrupt Enable" "0: Trigger completion interrupts are disabled,1: Trigger completion interrupts are enabled for..,2: Trigger completion interrupts are enabled for..,3: Associated trigger completion interrupts are..,4: Associated trigger completion interrupts are..,5: Associated trigger completion interrupts are..,6: Associated trigger completion interrupts are..,7: Associated trigger completion interrupts are..,8: Associated trigger completion interrupts are..,9: Associated trigger completion interrupts are..,?,?,?,?,?,15: Trigger completion interrupts are enabled.." bitfld.long 0x00 8. "TEXC_IE,Trigger Exception Interrupt Enable" "0: Trigger exception interrupts are disabled,1: Trigger exception interrupts are enabled" newline bitfld.long 0x00 3. "FOFIE1,Result FIFO1 Overflow Interrupt Enable" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.." bitfld.long 0x00 2. "FWMIE1,FIFO1 Watermark Interrupt Enable" "0: FIFO1 watermark interrupts are not enabled,1: FIFO1 watermark interrupts are enabled" newline bitfld.long 0x00 1. "FOFIE0,Result FIFO 0 Overflow Interrupt Enable" "0: FIFO 0 overflow interrupts are not enabled,1: FIFO 0 overflow interrupts are enabled" bitfld.long 0x00 0. "FWMIE0,FIFO 0 Watermark Interrupt Enable" "0: FIFO 0 watermark interrupts are not enabled,1: FIFO 0 watermark interrupts are enabled" group.long 0x18++0x03 line.long 0x00 "IE,Interrupt Enable Register" hexmask.long.word 0x00 16.--31. 1. "TCOMP_IE,Trigger Completion Interrupt Enable" bitfld.long 0x00 8. "TEXC_IE,Trigger Exception Interrupt Enable" "0: Trigger exception interrupts are disabled,1: Trigger exception interrupts are enabled" newline bitfld.long 0x00 3. "FOFIE1,Result FIFO1 Overflow Interrupt Enable" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.." bitfld.long 0x00 2. "FWMIE1,FIFO1 Watermark Interrupt Enable" "0: FIFO1 watermark interrupts are not enabled,1: FIFO1 watermark interrupts are enabled" newline bitfld.long 0x00 1. "FOFIE0,Result FIFO 0 Overflow Interrupt Enable" "0: FIFO 0 overflow interrupts are not enabled,1: FIFO 0 overflow interrupts are enabled" bitfld.long 0x00 0. "FWMIE0,FIFO 0 Watermark Interrupt Enable" "0: FIFO 0 watermark interrupts are not enabled,1: FIFO 0 watermark interrupts are enabled" group.long 0x1C++0x03 line.long 0x00 "DE,DMA Enable Register" bitfld.long 0x00 1. "FWMDE1,FIFO1 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled" bitfld.long 0x00 0. "FWMDE0,FIFO 0 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled" group.long 0x20++0x03 line.long 0x00 "CFG,ADC Configuration Register" bitfld.long 0x00 28. "PWREN,ADC Analog Pre-Enable" "0: ADC analog circuits are only enabled while..,1: ADC analog circuits are pre-enabled and ready.." hexmask.long.byte 0x00 16.--23. 1. "PUDLY,Power Up Delay" newline bitfld.long 0x00 10. "HPT_EXDI,High Priority Trigger Exception Disable" "0: High priority trigger exceptions are enabled,1: High priority trigger exceptions are disabled" bitfld.long 0x00 9. "TCMDRES,Trigger Command Resume" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.." newline bitfld.long 0x00 8. "TRES,Trigger Resume Enable" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.." bitfld.long 0x00 6.--7. "REFSEL,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,?..." newline bitfld.long 0x00 4.--5. "PWRSEL,Power Configuration Select" "0: Low power setting,1: Low power setting,2: High power setting,3: High power setting" bitfld.long 0x00 0.--1. "TPRICTRL,ADC trigger priority control" "0: If a higher priority trigger is detected..,1: If a higher priority trigger is received..,2: If a higher priority trigger is received..,?..." group.long 0x20++0x03 line.long 0x00 "CFG,ADC Configuration Register" bitfld.long 0x00 28. "PWREN,ADC Analog Pre-Enable" "0: ADC analog circuits are only enabled while..,1: ADC analog circuits are pre-enabled and ready.." hexmask.long.byte 0x00 16.--23. 1. "PUDLY,Power Up Delay" newline bitfld.long 0x00 10. "HPT_EXDI,High Priority Trigger Exception Disable" "0: High priority trigger exceptions are enabled,1: High priority trigger exceptions are disabled" bitfld.long 0x00 9. "TCMDRES,Trigger Command Resume" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.." newline bitfld.long 0x00 8. "TRES,Trigger Resume Enable" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.." bitfld.long 0x00 6.--7. "REFSEL,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,?..." newline bitfld.long 0x00 4.--5. "PWRSEL,Power Configuration Select" "0: Lowest power setting,1: Higher power setting than 0b0,2: Higher power setting than 0b1,3: Highest power setting" bitfld.long 0x00 0.--1. "TPRICTRL,ADC trigger priority control" "0: If a higher priority trigger is detected..,1: If a higher priority trigger is received..,2: If a higher priority trigger is received..,?..." group.long 0x24++0x03 line.long 0x00 "PAUSE,ADC Pause Register" bitfld.long 0x00 31. "PAUSEEN,PAUSE Option Enable" "0: Pause operation disabled,1: Pause operation enabled" hexmask.long.word 0x00 0.--8. 1. "PAUSEDLY,Pause Delay" group.long 0x34++0x03 line.long 0x00 "SWTRIG,Software Trigger Register" bitfld.long 0x00 15. "SWT15,Software trigger 15 event" "0: No trigger 15 event generated,1: Trigger 15 event generated" bitfld.long 0x00 14. "SWT14,Software trigger 14 event" "0: No trigger 14 event generated,1: Trigger 14 event generated" newline bitfld.long 0x00 13. "SWT13,Software trigger 13 event" "0: No trigger 13 event generated,1: Trigger 13 event generated" bitfld.long 0x00 12. "SWT12,Software trigger 12 event" "0: No trigger 12 event generated,1: Trigger 12 event generated" newline bitfld.long 0x00 11. "SWT11,Software trigger 11 event" "0: No trigger 11 event generated,1: Trigger 11 event generated" bitfld.long 0x00 10. "SWT10,Software trigger 10 event" "0: No trigger 10 event generated,1: Trigger 10 event generated" newline bitfld.long 0x00 9. "SWT9,Software trigger 9 event" "0: No trigger 9 event generated,1: Trigger 9 event generated" bitfld.long 0x00 8. "SWT8,Software trigger 8 event" "0: No trigger 8 event generated,1: Trigger 8 event generated" newline bitfld.long 0x00 7. "SWT7,Software trigger 7 event" "0: No trigger 7 event generated,1: Trigger 7 event generated" bitfld.long 0x00 6. "SWT6,Software trigger 6 event" "0: No trigger 6 event generated,1: Trigger 6 event generated" newline bitfld.long 0x00 5. "SWT5,Software trigger 5 event" "0: No trigger 5 event generated,1: Trigger 5 event generated" bitfld.long 0x00 4. "SWT4,Software trigger 4 event" "0: No trigger 4 event generated,1: Trigger 4 event generated" newline bitfld.long 0x00 3. "SWT3,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated" bitfld.long 0x00 2. "SWT2,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated" newline bitfld.long 0x00 1. "SWT1,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated" bitfld.long 0x00 0. "SWT0,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated" group.long 0x34++0x03 line.long 0x00 "SWTRIG,Software Trigger Register" bitfld.long 0x00 3. "SWT3,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated" bitfld.long 0x00 2. "SWT2,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated" newline bitfld.long 0x00 1. "SWT1,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated" bitfld.long 0x00 0. "SWT0,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated" group.long 0x38++0x03 line.long 0x00 "TSTAT,Trigger Status Register" hexmask.long.word 0x00 16.--31. 1. "TCOMP_FLAG,Trigger Completion Flag" hexmask.long.word 0x00 0.--15. 1. "TEXC_NUM,Trigger Exception Number" group.long 0x38++0x03 line.long 0x00 "TSTAT,Trigger Status Register" eventfld.long 0x00 16.--19. "TCOMP_FLAG,Trigger Completion Flag" "0: No triggers have been completed,1: Trigger 0 has been completed and triger 0 has..,2: Trigger 1 has been completed and triger 1 has..,3: Associated trigger sequence has completed and..,4: Associated trigger sequence has completed and..,5: Associated trigger sequence has completed and..,6: Associated trigger sequence has completed and..,7: Associated trigger sequence has completed and..,8: Associated trigger sequence has completed and..,9: Associated trigger sequence has completed and..,?,?,?,?,?,15: Every trigger sequence has been completed.." eventfld.long 0x00 0.--3. "TEXC_NUM,Trigger Exception Number" "0: No triggers have been interrupted by a high..,1: Trigger 0 has been interrupted by a high..,2: Trigger 1 has been interrupted by a high..,3: Associated trigger sequence has interrupted..,4: Associated trigger sequence has interrupted..,5: Associated trigger sequence has interrupted..,6: Associated trigger sequence has interrupted..,7: Associated trigger sequence has interrupted..,8: Associated trigger sequence has interrupted..,9: Associated trigger sequence has interrupted..,?,?,?,?,?,15: Every trigger sequence has been interrupted.." group.long 0x40++0x03 line.long 0x00 "OFSTRIM,ADC Offset Trim Register" bitfld.long 0x00 16.--20. "OFSTRIM_B,Trim for offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "OFSTRIM_A,Trim for offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xA0++0x03 line.long 0x00 "TCTRL[0],Trigger Control Register" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--11. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,?,?,?,?,?,15: Set to lowest priority Level 16" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" repeat 2. (increment 0 1) (increment 0 0x4) group.long ($2+0xA0)++0x03 line.long 0x00 "TCTRL[$1],Trigger Control Register $1" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--9. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to lowest priority Level 4" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" repeat.end group.long 0xA4++0x03 line.long 0x00 "TCTRL[1],Trigger Control Register" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--11. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,?,?,?,?,?,15: Set to lowest priority Level 16" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" group.long 0xA8++0x03 line.long 0x00 "TCTRL[2],Trigger Control Register" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--9. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to lowest priority Level 4" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" repeat 2. (increment 0 1) (increment 0 0x4) group.long ($2+0xA8)++0x03 line.long 0x00 "TCTRL[$1],Trigger Control Register $1" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--11. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,?,?,?,?,?,15: Set to lowest priority Level 16" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" repeat.end group.long 0xAC++0x03 line.long 0x00 "TCTRL[3],Trigger Control Register" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--9. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to lowest priority Level 4" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" repeat 12. (increment 0 1) (increment 0 0x4) group.long ($2+0xB0)++0x03 line.long 0x00 "TCTRL[$1],Trigger Control Register $1" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--11. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,?,?,?,?,?,15: Set to lowest priority Level 16" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" repeat.end repeat 2. (increment 0 1) (increment 0 0x4) group.long ($2+0xE0)++0x03 line.long 0x00 "FCTRL[$1],FIFO Control Register $1" bitfld.long 0x00 16.--19. "FWMARK,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--4. "FCOUNT,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat.end repeat 2. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0xF0)++0x03 line.long 0x00 "GCC[$1],Gain Calibration Control $1" bitfld.long 0x00 24. "RDY,Gain Calibration Value Valid" "0: The gain calibration value is invalid,1: The gain calibration value is valid" hexmask.long.word 0x00 0.--15. 1. "GAIN_CAL,Gain Calibration Value" repeat.end repeat 2. (increment 0 1) (increment 0 0x4) group.long ($2+0xF8)++0x03 line.long 0x00 "GCR[$1],Gain Calculation Result $1" bitfld.long 0x00 24. "RDY,Gain Calculation Ready" "0: The gain offset calculation value is invalid,1: The gain calibration value is valid" hexmask.long.word 0x00 0.--15. 1. "GCALR,Gain Calculation Result" repeat.end group.long 0x100++0x03 line.long 0x00 "CMDL1,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x100++0x03 line.long 0x00 "CMDL1,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x104++0x03 line.long 0x00 "CMDH1,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x104++0x03 line.long 0x00 "CMDH1,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x108++0x03 line.long 0x00 "CMDL2,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x108++0x03 line.long 0x00 "CMDL2,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x10C++0x03 line.long 0x00 "CMDH2,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x10C++0x03 line.long 0x00 "CMDH2,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x110++0x03 line.long 0x00 "CMDL3,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x110++0x03 line.long 0x00 "CMDL3,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x114++0x03 line.long 0x00 "CMDH3,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x114++0x03 line.long 0x00 "CMDH3,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x118++0x03 line.long 0x00 "CMDL4,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x118++0x03 line.long 0x00 "CMDL4,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x11C++0x03 line.long 0x00 "CMDH4,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x11C++0x03 line.long 0x00 "CMDH4,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x120++0x03 line.long 0x00 "CMDL5,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x120++0x03 line.long 0x00 "CMDL5,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x124++0x03 line.long 0x00 "CMDH5,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x124++0x03 line.long 0x00 "CMDH5,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x128++0x03 line.long 0x00 "CMDL6,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x128++0x03 line.long 0x00 "CMDL6,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x12C++0x03 line.long 0x00 "CMDH6,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x12C++0x03 line.long 0x00 "CMDH6,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x130++0x03 line.long 0x00 "CMDL7,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x130++0x03 line.long 0x00 "CMDL7,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x134++0x03 line.long 0x00 "CMDH7,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x134++0x03 line.long 0x00 "CMDH7,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x138++0x03 line.long 0x00 "CMDL8,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x138++0x03 line.long 0x00 "CMDL8,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x13C++0x03 line.long 0x00 "CMDH8,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x13C++0x03 line.long 0x00 "CMDH8,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x140++0x03 line.long 0x00 "CMDL9,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x140++0x03 line.long 0x00 "CMDL9,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x144++0x03 line.long 0x00 "CMDH9,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x144++0x03 line.long 0x00 "CMDH9,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x148++0x03 line.long 0x00 "CMDL10,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x148++0x03 line.long 0x00 "CMDL10,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x14C++0x03 line.long 0x00 "CMDH10,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x14C++0x03 line.long 0x00 "CMDH10,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x150++0x03 line.long 0x00 "CMDL11,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x150++0x03 line.long 0x00 "CMDL11,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x154++0x03 line.long 0x00 "CMDH11,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x154++0x03 line.long 0x00 "CMDH11,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x158++0x03 line.long 0x00 "CMDL12,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x158++0x03 line.long 0x00 "CMDL12,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x15C++0x03 line.long 0x00 "CMDH12,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x15C++0x03 line.long 0x00 "CMDH12,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x160++0x03 line.long 0x00 "CMDL13,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x160++0x03 line.long 0x00 "CMDL13,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x164++0x03 line.long 0x00 "CMDH13,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x164++0x03 line.long 0x00 "CMDH13,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x168++0x03 line.long 0x00 "CMDL14,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x168++0x03 line.long 0x00 "CMDL14,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x16C++0x03 line.long 0x00 "CMDH14,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." group.long 0x16C++0x03 line.long 0x00 "CMDH14,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x170++0x03 line.long 0x00 "CMDL15,ADC Command Low Buffer Register" bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x170++0x03 line.long 0x00 "CMDL15,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x174++0x03 line.long 0x00 "CMDH15,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x174++0x03 line.long 0x00 "CMDH15,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." repeat 15. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) group.long ($2+0x200)++0x03 line.long 0x00 "CV$1,Compare Value Register" sif cpuis("LPC5534*")||cpuis("LPC5536*") hexmask.long.word 0x00 16.--31. 1. "CVH,Compare Value High" hexmask.long.word 0x00 0.--15. 1. "CVL,Compare Value Low" endif repeat.end rgroup.long 0x300++0x03 line.long 0x00 "RESFIFO[0],ADC Data Result FIFO Register" bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid" bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.." newline bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command" bitfld.long 0x00 16.--17. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this..,3: Trigger source 3 initiated this conversion" newline hexmask.long.word 0x00 0.--15. 1. "D,Data result" repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0x300)++0x03 line.long 0x00 "RESFIFO[$1],ADC Data Result FIFO Register $1" bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid" bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.." newline bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command" bitfld.long 0x00 16.--19. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this..,3: Corresponding trigger source initiated this..,4: Corresponding trigger source initiated this..,5: Corresponding trigger source initiated this..,6: Corresponding trigger source initiated this..,7: Corresponding trigger source initiated this..,8: Corresponding trigger source initiated this..,9: Corresponding trigger source initiated this..,?,?,?,?,?,15: Trigger source 15 initiated this conversion" newline hexmask.long.word 0x00 0.--15. 1. "D,Data result" repeat.end rgroup.long 0x304++0x03 line.long 0x00 "RESFIFO[1],ADC Data Result FIFO Register" bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid" bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.." newline bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command" bitfld.long 0x00 16.--17. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this..,3: Trigger source 3 initiated this conversion" newline hexmask.long.word 0x00 0.--15. 1. "D,Data result" repeat 33. (increment 0 1) (increment 0 0x04) group.long ($2+0x400)++0x03 line.long 0x00 "CAL_GAR[$1],Calibration General A-Side Registers $1" hexmask.long.word 0x00 0.--15. 1. "CAL_GAR_VAL,Calibration General A Side Register Element" repeat.end repeat 33. (increment 0 1) (increment 0 0x04) group.long ($2+0x500)++0x03 line.long 0x00 "CAL_GBR[$1],Calibration General B-Side Registers $1" hexmask.long.word 0x00 0.--15. 1. "CAL_GBR_VAL,Calibration General B Side Register Element" repeat.end group.long 0xFFC++0x03 line.long 0x00 "TST,ADC Test Register" bitfld.long 0x00 23. "TESTEN,Enable test configuration" "0: Normal operation,1: Hardware BIST Test in progress" bitfld.long 0x00 11. "FOFFP2,Force P-side negative offset" "0: Normal operation,1: Test configuration" newline bitfld.long 0x00 10. "FOFFM2,Force M-side negative offset" "0: Normal operation,1: Test configuration" bitfld.long 0x00 9. "FOFFP,Force P-side positive offset" "0: Normal operation,1: Test configuration" newline bitfld.long 0x00 8. "FOFFM,Force M-side positive offset" "0: Normal operation,1: Test configuration" bitfld.long 0x00 0. "CST_LONG,Calibration Sample Time Long" "0: Normal sample time,1: Increased sample time" tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "ADC1" base ad:0x400B1000 rgroup.long 0x00++0x03 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number" newline bitfld.long 0x00 12.--14. "NUM_FIFO,Number of FIFOs" "0: NUM_FIFO_0,1: This design supports one result FIFO,2: This design supports two result FIFOs,3: This design supports three result FIFOs,4: This design supports four result FIFOs,?..." bitfld.long 0x00 11. "NUM_SEC,Number of Single Ended Outputs Supported" "0: This design supports one single ended..,1: This design supports two simultanious single.." newline bitfld.long 0x00 10. "CALOFSI,Calibration Function Implemented" "0: Calibration Not Implemented,1: Calibration Implemented" bitfld.long 0x00 9. "IADCKI,Internal ADC Clock implemented" "0: Internal clock source not implemented,1: Internal clock source (and CFG[ADCKEN]).." newline bitfld.long 0x00 8. "VR1RNGI,Voltage Reference 1 Range Control Bit Implemented" "0: Range control not required,1: Range control required" bitfld.long 0x00 4.--6. "CSW,Channel Scale Width" "0: Channel scaling not supported,1: Channel scaling supported,?,?,?,?,6: Channel scaling supported,?..." newline bitfld.long 0x00 3. "MVI,Multi Vref Implemented" "0: Single voltage reference high (VREFH) input..,1: Multiple voltage reference high (VREFH).." bitfld.long 0x00 1. "DIFFEN,Differential Supported" "0: Differential operation not supported,1: Differential operation supported" newline bitfld.long 0x00 0. "RES,Resolution" "0: Up to 13-bit differential/12-bit single ended..,1: Up to 16-bit differential/16-bit single ended.." rgroup.long 0x04++0x03 line.long 0x00 "PARAM,Parameter Register" hexmask.long.byte 0x00 24.--31. 1. "CMD_NUM,Command Buffer Number" hexmask.long.byte 0x00 16.--23. 1. "CV_NUM,Compare Value Number" newline hexmask.long.byte 0x00 8.--15. 1. "FIFOSIZE,Result FIFO Depth" hexmask.long.byte 0x00 0.--7. 1. "TRIG_NUM,Trigger Number" group.long 0x10++0x03 line.long 0x00 "CTRL,ADC Control Register" bitfld.long 0x00 16.--18. "CAL_AVGS,Auto-Calibration Averages" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 9. "RSTFIFO1,Reset FIFO 1" "0: RSTFIFO1_0,1: FIFO 1 is reset" newline bitfld.long 0x00 8. "RSTFIFO0,Reset FIFO 0" "0: RSTFIFO0_0,1: FIFO 0 is reset" bitfld.long 0x00 4. "CALOFS,Configure for offset calibration function" "0: Calibration function disabled,1: Request for offset calibration function" newline bitfld.long 0x00 3. "CAL_REQ,Auto-Calibration Request" "0: No request for auto-calibration has been made,1: A request for auto-calibration has been made" bitfld.long 0x00 2. "DOZEN,Doze Enable" "0: ADC is enabled in low power mode,1: ADC is disabled in low power mode" newline bitfld.long 0x00 1. "RST,Software Reset" "0: ADC logic is not reset,1: ADC logic is reset" bitfld.long 0x00 0. "ADCEN,ADC Enable" "0: ADC is disabled,1: ADC is enabled" group.long 0x14++0x03 line.long 0x00 "STAT,ADC Status Register" rbitfld.long 0x00 24.--27. "CMDACT,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,3: Associated command number is currently being..,4: Associated command number is currently being..,5: Associated command number is currently being..,6: Associated command number is currently being..,7: Associated command number is currently being..,8: Associated command number is currently being..,9: Associated command number is currently being..,?..." rbitfld.long 0x00 16.--17. "TRGACT,Trigger Active" "0: Command (sequence) associated with Trigger 0..,1: Command (sequence) associated with Trigger 1..,2: Command (sequence) associated with Trigger 2..,3: Command (sequence) associated with Trigger 3.." newline rbitfld.long 0x00 11. "ADC_ACTIVE,ADC Active" "0: The ADC is IDLE,1: The ADC is processing a conversion running.." rbitfld.long 0x00 10. "CAL_RDY,Calibration Ready" "0: Calibration is incomplete or hasn't been ran,1: The ADC is calibrated" newline eventfld.long 0x00 9. "TCOMP_INT,Interrupt Flag For Trigger Completion" "0: Either IE[TCOMP_IE] is set to 0 or no trigger..,1: Trigger sequence has been completed and all.." eventfld.long 0x00 8. "TEXC_INT,Interrupt Flag For High Priority Trigger Exception" "0: No trigger exceptions have occurred,1: A trigger exception has occurred and is.." newline eventfld.long 0x00 3. "FOF1,Result FIFO1 Overflow Flag" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.." rbitfld.long 0x00 2. "RDY1,Result FIFO1 Ready Flag" "0: Result FIFO1 data level not above watermark..,1: Result FIFO1 holding data above watermark level" newline eventfld.long 0x00 1. "FOF0,Result FIFO 0 Overflow Flag" "0: No result FIFO 0 overflow has occurred since..,1: At least one result FIFO 0 overflow has.." rbitfld.long 0x00 0. "RDY0,Result FIFO 0 Ready Flag" "0: Result FIFO 0 data level not above watermark..,1: Result FIFO 0 holding data above watermark.." group.long 0x18++0x03 line.long 0x00 "IE,Interrupt Enable Register" bitfld.long 0x00 16.--19. "TCOMP_IE,Trigger Completion Interrupt Enable" "0: Trigger completion interrupts are disabled,1: Trigger completion interrupts are enabled for..,2: Trigger completion interrupts are enabled for..,3: Associated trigger completion interrupts are..,4: Associated trigger completion interrupts are..,5: Associated trigger completion interrupts are..,6: Associated trigger completion interrupts are..,7: Associated trigger completion interrupts are..,8: Associated trigger completion interrupts are..,9: Associated trigger completion interrupts are..,?,?,?,?,?,15: Trigger completion interrupts are enabled.." bitfld.long 0x00 8. "TEXC_IE,Trigger Exception Interrupt Enable" "0: Trigger exception interrupts are disabled,1: Trigger exception interrupts are enabled" newline bitfld.long 0x00 3. "FOFIE1,Result FIFO1 Overflow Interrupt Enable" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.." bitfld.long 0x00 2. "FWMIE1,FIFO1 Watermark Interrupt Enable" "0: FIFO1 watermark interrupts are not enabled,1: FIFO1 watermark interrupts are enabled" newline bitfld.long 0x00 1. "FOFIE0,Result FIFO 0 Overflow Interrupt Enable" "0: FIFO 0 overflow interrupts are not enabled,1: FIFO 0 overflow interrupts are enabled" bitfld.long 0x00 0. "FWMIE0,FIFO 0 Watermark Interrupt Enable" "0: FIFO 0 watermark interrupts are not enabled,1: FIFO 0 watermark interrupts are enabled" group.long 0x1C++0x03 line.long 0x00 "DE,DMA Enable Register" bitfld.long 0x00 1. "FWMDE1,FIFO1 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled" bitfld.long 0x00 0. "FWMDE0,FIFO 0 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled" group.long 0x20++0x03 line.long 0x00 "CFG,ADC Configuration Register" bitfld.long 0x00 28. "PWREN,ADC Analog Pre-Enable" "0: ADC analog circuits are only enabled while..,1: ADC analog circuits are pre-enabled and ready.." hexmask.long.byte 0x00 16.--23. 1. "PUDLY,Power Up Delay" newline bitfld.long 0x00 10. "HPT_EXDI,High Priority Trigger Exception Disable" "0: High priority trigger exceptions are enabled,1: High priority trigger exceptions are disabled" bitfld.long 0x00 9. "TCMDRES,Trigger Command Resume" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.." newline bitfld.long 0x00 8. "TRES,Trigger Resume Enable" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.." bitfld.long 0x00 6.--7. "REFSEL,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,?..." newline bitfld.long 0x00 4.--5. "PWRSEL,Power Configuration Select" "0: Low power setting,1: Low power setting,2: High power setting,3: High power setting" bitfld.long 0x00 0.--1. "TPRICTRL,ADC trigger priority control" "0: If a higher priority trigger is detected..,1: If a higher priority trigger is received..,2: If a higher priority trigger is received..,?..." group.long 0x24++0x03 line.long 0x00 "PAUSE,ADC Pause Register" bitfld.long 0x00 31. "PAUSEEN,PAUSE Option Enable" "0: Pause operation disabled,1: Pause operation enabled" hexmask.long.word 0x00 0.--8. 1. "PAUSEDLY,Pause Delay" group.long 0x34++0x03 line.long 0x00 "SWTRIG,Software Trigger Register" bitfld.long 0x00 3. "SWT3,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated" bitfld.long 0x00 2. "SWT2,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated" newline bitfld.long 0x00 1. "SWT1,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated" bitfld.long 0x00 0. "SWT0,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated" group.long 0x38++0x03 line.long 0x00 "TSTAT,Trigger Status Register" eventfld.long 0x00 16.--19. "TCOMP_FLAG,Trigger Completion Flag" "0: No triggers have been completed,1: Trigger 0 has been completed and triger 0 has..,2: Trigger 1 has been completed and triger 1 has..,3: Associated trigger sequence has completed and..,4: Associated trigger sequence has completed and..,5: Associated trigger sequence has completed and..,6: Associated trigger sequence has completed and..,7: Associated trigger sequence has completed and..,8: Associated trigger sequence has completed and..,9: Associated trigger sequence has completed and..,?,?,?,?,?,15: Every trigger sequence has been completed.." eventfld.long 0x00 0.--3. "TEXC_NUM,Trigger Exception Number" "0: No triggers have been interrupted by a high..,1: Trigger 0 has been interrupted by a high..,2: Trigger 1 has been interrupted by a high..,3: Associated trigger sequence has interrupted..,4: Associated trigger sequence has interrupted..,5: Associated trigger sequence has interrupted..,6: Associated trigger sequence has interrupted..,7: Associated trigger sequence has interrupted..,8: Associated trigger sequence has interrupted..,9: Associated trigger sequence has interrupted..,?,?,?,?,?,15: Every trigger sequence has been interrupted.." group.long 0x40++0x03 line.long 0x00 "OFSTRIM,ADC Offset Trim Register" bitfld.long 0x00 16.--20. "OFSTRIM_B,Trim for offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "OFSTRIM_A,Trim for offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0xA0)++0x03 line.long 0x00 "TCTRL[$1],Trigger Control Register $1" bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed" bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1" bitfld.long 0x00 8.--9. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to lowest priority Level 4" newline bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1" bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1" newline bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled" repeat.end repeat 2. (increment 0 1) (increment 0 0x4) group.long ($2+0xE0)++0x03 line.long 0x00 "FCTRL[$1],FIFO Control Register $1" bitfld.long 0x00 16.--19. "FWMARK,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--4. "FCOUNT,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat.end repeat 2. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0xF0)++0x03 line.long 0x00 "GCC[$1],Gain Calibration Control $1" bitfld.long 0x00 24. "RDY,Gain Calibration Value Valid" "0: The gain calibration value is invalid,1: The gain calibration value is valid" hexmask.long.word 0x00 0.--15. 1. "GAIN_CAL,Gain Calibration Value" repeat.end repeat 2. (increment 0 1) (increment 0 0x4) group.long ($2+0xF8)++0x03 line.long 0x00 "GCR[$1],Gain Calculation Result $1" bitfld.long 0x00 24. "RDY,Gain Calculation Ready" "0: The gain offset calculation value is invalid,1: The gain calibration value is valid" hexmask.long.word 0x00 0.--15. 1. "GCALR,Gain Calculation Result" repeat.end group.long 0x100++0x03 line.long 0x00 "CMDL1,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x104++0x03 line.long 0x00 "CMDH1,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x108++0x03 line.long 0x00 "CMDL2,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x10C++0x03 line.long 0x00 "CMDH2,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x110++0x03 line.long 0x00 "CMDL3,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x114++0x03 line.long 0x00 "CMDH3,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x118++0x03 line.long 0x00 "CMDL4,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x11C++0x03 line.long 0x00 "CMDH4,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x120++0x03 line.long 0x00 "CMDL5,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x124++0x03 line.long 0x00 "CMDH5,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x128++0x03 line.long 0x00 "CMDL6,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x12C++0x03 line.long 0x00 "CMDH6,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x130++0x03 line.long 0x00 "CMDL7,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x134++0x03 line.long 0x00 "CMDH7,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x138++0x03 line.long 0x00 "CMDL8,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x13C++0x03 line.long 0x00 "CMDH8,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x140++0x03 line.long 0x00 "CMDL9,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x144++0x03 line.long 0x00 "CMDH9,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x148++0x03 line.long 0x00 "CMDL10,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x14C++0x03 line.long 0x00 "CMDH10,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x150++0x03 line.long 0x00 "CMDL11,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x154++0x03 line.long 0x00 "CMDH11,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x158++0x03 line.long 0x00 "CMDL12,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x15C++0x03 line.long 0x00 "CMDH12,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x160++0x03 line.long 0x00 "CMDL13,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x164++0x03 line.long 0x00 "CMDH13,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x168++0x03 line.long 0x00 "CMDL14,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x16C++0x03 line.long 0x00 "CMDH14,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" group.long 0x170++0x03 line.long 0x00 "CMDL15,ADC Command Low Buffer Register" bitfld.long 0x00 21. "ALTBEN,Alternate Channel B Select Enable" "0: ALTBEN_ADCH disabled,1: ALTBEN_ADCH enabled" bitfld.long 0x00 16.--20. "ALTB_ADCH,Alternate Channel B Input channel select" "0: ALTB_ADCH_0,1: ALTB_ADCH_1,2: ALTB_ADCH_2,3: ALTB_ADCH_3,4: Select corresponding channel CHnB,5: Select corresponding channel CHnB,6: Select corresponding channel CHnB,7: Select corresponding channel CHnB,8: Select corresponding channel CHnB,9: Select corresponding channel CHnB,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: ALTB_ADCH_30,31: ALTB_ADCH_31" newline bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution" bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode" newline bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair" group.long 0x174++0x03 line.long 0x00 "CMDH15,ADC Command High Buffer Register" bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.." bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times" newline bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged" bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3.5 ADCK cycles,1: 3.5 + 21 ADCK cycles 5.5 ADCK cycles total..,2: 3.5 + 22 ADCK cycles 7.5 ADCK cycles total..,3: 3.5 + 23 ADCK cycles 11.5 ADCK cycles total..,4: 3.5 + 24 ADCK cycles 19.5 ADCK cycles total..,5: 3.5 + 25 ADCK cycles 35.5 ADCK cycles total..,6: 3.5 + 26 ADCK cycles 67.5 ADCK cycles total..,7: 3.5 + 27 ADCK cycles 131.5 ADCK cycles total.." newline bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled" bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.." newline bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled" repeat 15. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) group.long ($2+0x200)++0x03 line.long 0x00 "CV$1,Compare Value Register" hexmask.long.word 0x00 16.--31. 1. "CVH,Compare Value High" hexmask.long.word 0x00 0.--15. 1. "CVL,Compare Value Low" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0x300)++0x03 line.long 0x00 "RESFIFO[$1],ADC Data Result FIFO Register $1" bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid" bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.." newline bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command" bitfld.long 0x00 16.--17. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this..,3: Trigger source 3 initiated this conversion" newline hexmask.long.word 0x00 0.--15. 1. "D,Data result" repeat.end repeat 33. (increment 0 1) (increment 0 0x04) group.long ($2+0x400)++0x03 line.long 0x00 "CAL_GAR[$1],Calibration General A-Side Registers $1" hexmask.long.word 0x00 0.--15. 1. "CAL_GAR_VAL,Calibration General A Side Register Element" repeat.end repeat 33. (increment 0 1) (increment 0 0x04) group.long ($2+0x500)++0x03 line.long 0x00 "CAL_GBR[$1],Calibration General B-Side Registers $1" hexmask.long.word 0x00 0.--15. 1. "CAL_GBR_VAL,Calibration General B Side Register Element" repeat.end tree.end endif tree.end sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "AHB_SECURE_CTRL (AHB Secure Controller)" base ad:0x400AC000 group.long 0x00++0x03 line.long 0x00 "SEC_CTRL_FLASH_ROM_SLAVE_RULE,Security access rules for Flash and ROM slaves" bitfld.long 0x00 4.--5. "ROM_RULE,Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 0.--1. "FLASH_RULE,Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--1. "FLASH_RULE,Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif group.long 0x10++0x03 line.long 0x00 "SEC_CTRL_FLASH_MEM_RULE0,Security access rules for FLASH sector 0 to sector 20" bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x10++0x03 line.long 0x00 "SEC_CTRL_FLASH_MEM_RULE0,Security access rules for FLASH sector 0 to sector 7" bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" repeat 2. (strings "1" "2" )(list 0x0 0x4 ) group.long ($2+0x14)++0x03 line.long 0x00 "SEC_CTRL_FLASH_MEM_RULE$1,Security access rules for FLASH sector 0 to sector 20" bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" repeat.end repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x20)++0x03 line.long 0x00 "SEC_CTRL_ROM_MEM_RULE$1,Security access rules for ROM sector 0 to sector 31" bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" repeat.end group.long 0x30++0x03 line.long 0x00 "SEC_CTRL_RAMX_SLAVE_RULE,Security access rules for RAMX slaves" bitfld.long 0x00 0.--1. "RAMX_RULE,Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x40++0x03 line.long 0x00 "SEC_CTRL_RAMX_MEM_RULE0,Security access rules for RAMX slaves" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x50++0x03 line.long 0x00 "SEC_CTRL_RAM0_SLAVE_RULE,Security access rules for RAM0 slaves" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 0.--1. "RAM0_RULE,Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--1. "RAM0_RULE,Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0x60)++0x03 line.long 0x00 "SEC_CTRL_RAM0_MEM_RULE$1,Security access rules for RAM0 slaves" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif repeat.end group.long 0x70++0x03 line.long 0x00 "SEC_CTRL_RAM1_SLAVE_RULE,Security access rules for RAM1 slaves" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--1. "RAM1_RULE,Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF name= 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 0.--1. "RAM1_RULE,Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif group.long 0x80++0x03 line.long 0x00 "SEC_CTRL_RAM1_MEM_RULE0,Security access rules for RAM1 slaves" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x84++0x03 line.long 0x00 "SEC_CTRL_RAM1_MEM_RULE1,Security access rules for RAM1 slaves" bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x90++0x03 line.long 0x00 "SEC_CTRL_RAM2_SLAVE_RULE,Security access rules for RAM2 slaves" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 0.--1. "RAM2_RULE,Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--1. "RAM2_RULE,Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0xA0)++0x03 line.long 0x00 "SEC_CTRL_RAM2_MEM_RULE$1,Security access rules for RAM2 slaves" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif repeat.end group.long 0xB0++0x03 line.long 0x00 "SEC_CTRL_USB_HS_SLAVE_RULE,Security access rules for USB High speed RAM slaves" bitfld.long 0x00 0.--1. "RAM_USB_HS_RULE,Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5526*")||cpuis("LPC5528*") group.long 0xB0++0x03 line.long 0x00 "SEC_CTRL_RAM3_SLAVE_RULE,Security access rules for RAM3 slaves" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--1. "RAM3_RULE,Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 0.--1. "RAM3_RULE,Security access rules for the whole RAM3 : 0x2001_0000 - 0x2001_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif endif group.long 0xC0++0x03 line.long 0x00 "SEC_CTRL_USB_HS_MEM_RULE,Security access rules for RAM_USB_HS" bitfld.long 0x00 12.--13. "SRAM_SECT_3_RULE,Address space: 0x2001_3000 - 0x2001_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "SRAM_SECT_2_RULE,Address space: 0x2001_2000 - 0x2001_2FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "SRAM_SECT_1_RULE,Address space: 0x2001_1000 - 0x2001_1FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "SRAM_SECT_0_RULE,Address space: 0x2001_0000 - 0x2001_0FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xC0++0x03 line.long 0x00 "SEC_CTRL_RAM3_MEM_RULE0,Security access rules for RAM3" bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0xC0)++0x03 line.long 0x00 "SEC_CTRL_RAM3_MEM_RULE$1,Security access rules for RAM3 slaves" bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" repeat.end group.long 0xD0++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE_SLAVE_RULE,Security access rules for both APB Bridges slaves" bitfld.long 0x00 4.--5. "APBBRIDGE1_RULE,Security access rules for the whole APB Bridge 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "APBBRIDGE0_RULE,Security access rules for the whole APB Bridge 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xD0++0x03 line.long 0x00 "SEC_CTRL_RAM4_SLAVE_RULE,Security access rules for RAM4 slaves" bitfld.long 0x00 0.--1. "RAM4_RULE,Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xE0++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE0_MEM_CTRL0,Security access rules for APB Bridge 0 peripherals" bitfld.long 0x00 24.--25. "INPUTMUX_RULE,Peripheral input multiplexing" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "SEC_PINT_RULE,Secure Pin Interrupt and Pattern match" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "PINT_RULE,Pin Interrupt and Pattern match" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "GINT1_RULE,GPIO input Interrupt 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "GINT0_RULE,GPIO input Interrupt 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "IOCON_RULE,I/O Configuration" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "SYSCON_RULE,System Configuration" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xE0++0x03 line.long 0x00 "SEC_CTRL_RAM4_MEM_RULE0,Security access rules for RAM4 slaves" bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xE4++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE0_MEM_CTRL1,Security access rules for APB Bridge 0 peripherals" bitfld.long 0x00 24.--25. "UTICK_RULE,Micro-Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "MRT_RULE,Multi-rate Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "WWDT_RULE,Windiwed wtachdog Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "CTIMER1_RULE,Standard counter/Timer 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "CTIMER0_RULE,Standard counter/Timer 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xE8++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE0_MEM_CTRL2,Security access rules for APB Bridge 0 peripherals" bitfld.long 0x00 12.--13. "ANACTRL_RULE,Analog Modules controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xF0++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL0,Security access rules for APB Bridge 1 peripherals" bitfld.long 0x00 16.--17. "SPI_FILTER_RULE,SPI FILTER control" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "SYSCTRL_RULE,System Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "PMC_RULE,Power Management Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xF4++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL1,Security access rules for APB Bridge 1 peripherals" bitfld.long 0x00 20.--21. "OSEVENT_RULE,OS Event Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "RTC_RULE,Real Time Counter" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "CTIMER4_RULE,Standard counter/Timer 4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "CTIMER3_RULE,Standard counter/Timer 3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "CTIMER2_RULE,Standard counter/Timer 2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xF8++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL2,Security access rules for APB Bridge 1 peripherals" bitfld.long 0x00 20.--21. "PRINCE_RULE,Prince" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "FLASH_CTRL_RULE,Flash Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0xFC++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL3,Security access rules for APB Bridge 1 peripherals" bitfld.long 0x00 20.--21. "PLU_RULE,Programmable Look-Up logic" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "PUF_RULE,PUF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "RNG_RULE,True Random Number Generator" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--1. "USBHPHY_RULE,USB High Speed Phy controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif group.long 0x100++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT7_SLAVE0_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "FLEXCOMM1_RULE,Flexcomm interface 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "FLEXCOMM0_RULE,Flexcomm interface 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "SCT_RULE,SCTimer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 16.--17. "FS_USB_DEV_RULE,USB Full-speed device" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif bitfld.long 0x00 8.--9. "DMA0_RULE,DMA Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x104++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT7_SLAVE1_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 16.--17. "GPIO0_RULE,High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "FLEXCOMM4_RULE,Flexcomm interface 4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "FLEXCOMM3_RULE,Flexcomm interface 3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "FLEXCOMM2_RULE,Flexcomm interface 2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x110++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE0_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "FLEXCOMM6_RULE,Flexcomm interface 6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "FLEXCOMM5_RULE,Flexcomm interface 5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "CRC_RULE,CRC engine" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 16.--17. "USB_HS_DEV_RULE,USB high Speed device registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif group.long 0x110++0x03 line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL0,Security access rules for APB Bridge 1 peripherals" bitfld.long 0x00 12.--13. "SYSCTRL_RULE,System Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "PMC_RULE,Power Management Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x114++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE1_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "HS_LSPI_RULE,High Speed SPI" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "CAN0_RULE,CAN-FD" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "DBG_MAILBOX_RULE,Debug mailbox (aka ISP-AP)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "FLEXCOMM7_RULE,Flexcomm interface 7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x120++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE0_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "FLEXCOMM1_RULE,Flexcomm interface 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "FLEXCOMM0_RULE,Flexcomm interface 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "SCT_RULE,SCTimer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "FS_USB_DEV_RULE,USB Full-speed device" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "DMA0_RULE,DMA Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x120++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE0_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "DMA1_RULE,DMA Controller (Secure)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "CASPER_RULE,RSA/ECC crypto accelerator" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "HASH_RULE,SHA-2 crypto registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 12.--13. "USB_HS_HOST_RULE,USB High speed host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "USB_FS_HOST_RULE,USB Full Speed Host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif bitfld.long 0x00 0.--1. "ADC_RULE,ADC" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x124++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE1_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 4.--5. "AHB_SEC_CTRL_RULE,AHB Secure Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "GPIO1_RULE,Secure High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x124++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE1_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 16.--17. "GPIO0_RULE,High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "MAILBOX_RULE,Inter CPU communication Mailbox" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "FLEXCOMM4_RULE,Flexcomm interface 4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "FLEXCOMM3_RULE,Flexcomm interface 3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "FLEXCOMM2_RULE,Flexcomm interface 2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x130++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE0_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "FLEXCOMM6_RULE,Flexcomm interface 6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "FLEXCOMM5_RULE,Flexcomm interface 5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "CRC_RULE,CRC engine" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "USB_HS_DEV_RULE,USB high Speed device registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x130++0x03 line.long 0x00 "SEC_CTRL_AHB_SEC_CTRL_MEM_RULE,Security access rules for AHB_SEC_CTRL_AHB" bitfld.long 0x00 12.--13. "AHB_SEC_CTRL_SECT_3_RULE,Address space: 0x400A_F000 - 0x400A_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "AHB_SEC_CTRL_SECT_2_RULE,Address space: 0x400A_E000 - 0x400A_EFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "AHB_SEC_CTRL_SECT_1_RULE,Address space: 0x400A_D000 - 0x400A_DFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "AHB_SEC_CTRL_SECT_0_RULE,Address space: 0x400A_0000 - 0x400A_CFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x134++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE1_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "HS_LSPI_RULE,High Speed SPI" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "DBG_MAILBOX_RULE,Debug mailbox (aka ISP-AP)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "SDIO_RULE,SDMMC card interface" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "FLEXCOMM7_RULE,Flexcomm interface 7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x140++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT10_SLAVE0_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 28.--29. "DMA1_RULE,DMA Controller (Secure)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 24.--25. "PQ_RULE,Power Quad (CPU0 processor hardware accelerator)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 20.--21. "CASPER_RULE,RSA/ECC crypto accelerator" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "HASH_RULE,SHA-2 crypto registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 12.--13. "USB_HS_HOST_RULE,USB High speed host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "USB_FS_HOST_RULE,USB Full Speed Host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "ADC_RULE,ADC" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x144++0x03 line.long 0x00 "SEC_CTRL_AHB_PORT10_SLAVE1_RULE,Security access rules for AHB peripherals" bitfld.long 0x00 4.--5. "AHB_SEC_CTRL_RULE,AHB Secure Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "GPIO1_RULE,Secure High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x160++0x03 line.long 0x00 "SEC_CTRL_USB_HS_SLAVE_RULE,Security access rules for USB High speed RAM slaves" bitfld.long 0x00 0.--1. "RAM_USB_HS_RULE,Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" group.long 0x170++0x03 line.long 0x00 "SEC_CTRL_USB_HS_MEM_RULE,Security access rules for RAM_USB_HS" bitfld.long 0x00 12.--13. "SRAM_SECT_3_RULE,Address space: 0x4010_3000 - 0x4010_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 8.--9. "SRAM_SECT_2_RULE,Address space: 0x4010_2000 - 0x4010_2FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "SRAM_SECT_1_RULE,Address space: 0x4010_1000 - 0x4010_1FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 0.--1. "SRAM_SECT_0_RULE,Address space: 0x4010_0000 - 0x4010_0FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" rgroup.long 0xE00++0x03 line.long 0x00 "sec_vio_addr[0],most recent security violation address for AHB layer n" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer" repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE00)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE04)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE08)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE0C)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE10)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE14)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE18)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port" repeat.end rgroup.long 0xE1C++0x03 line.long 0x00 "sec_vio_addr[7],most recent security violation address for AHB layer n" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer" rgroup.long 0xE20++0x03 line.long 0x00 "sec_vio_addr[8],most recent security violation address for AHB port n" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port" repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE20)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer" repeat.end repeat 3. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE24)++0x03 line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1" hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port" repeat.end rgroup.long 0xE80++0x03 line.long 0x00 "sec_vio_misc_info[0],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE80++0x03 line.long 0x00 "sec_vio_misc_info[0],most recent security violation miscellaneous information for AHB port n" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE84++0x03 line.long 0x00 "sec_vio_misc_info[1],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE84++0x03 line.long 0x00 "sec_vio_misc_info[1],most recent security violation miscellaneous information for AHB port n" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE88++0x03 line.long 0x00 "sec_vio_misc_info[2],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE88)++0x03 line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB port n $1" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE8C)++0x03 line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB layer n $1" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xE90)++0x03 line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB port n $1" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" repeat.end rgroup.long 0xE94++0x03 line.long 0x00 "sec_vio_misc_info[5],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE98++0x03 line.long 0x00 "sec_vio_misc_info[6],most recent security violation miscellaneous information for AHB port n" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE98++0x03 line.long 0x00 "sec_vio_misc_info[6],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE9C++0x03 line.long 0x00 "sec_vio_misc_info[7],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xE9C++0x03 line.long 0x00 "sec_vio_misc_info[7],most recent security violation miscellaneous information for AHB port n" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xEA0++0x03 line.long 0x00 "sec_vio_misc_info[8],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xEA0++0x03 line.long 0x00 "sec_vio_misc_info[8],most recent security violation miscellaneous information for AHB port n" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" rgroup.long 0xEA4++0x03 line.long 0x00 "sec_vio_misc_info[9],most recent security violation miscellaneous information for AHB layer n" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..." newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..." newline endif bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" repeat 3. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0xEA4)++0x03 line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB port n $1" bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..." newline bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access" newline bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access" repeat.end group.long 0xF00++0x03 line.long 0x00 "SEC_VIO_INFO_VALID,security violation address/information registers valid flags" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 11. "VIO_INFO_VALID11,violation information valid flag for AHB port 11" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 10. "VIO_INFO_VALID10,violation information valid flag for AHB port 10" "0: Not valid,1: Valid (violation occurred)" newline endif bitfld.long 0x00 9. "VIO_INFO_VALID9,violation information valid flag for AHB port 9" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 8. "VIO_INFO_VALID8,violation information valid flag for AHB port 8" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 7. "VIO_INFO_VALID7,violation information valid flag for AHB port 7" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 6. "VIO_INFO_VALID6,violation information valid flag for AHB port 6" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 5. "VIO_INFO_VALID5,violation information valid flag for AHB port 5" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 4. "VIO_INFO_VALID4,violation information valid flag for AHB port 4" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 3. "VIO_INFO_VALID3,violation information valid flag for AHB port 3" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 2. "VIO_INFO_VALID2,violation information valid flag for AHB port 2" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 1. "VIO_INFO_VALID1,violation information valid flag for AHB port 1" "0: Not valid,1: Valid (violation occurred)" newline bitfld.long 0x00 0. "VIO_INFO_VALID0,violation information valid flag for AHB port 0" "0: Not valid,1: Valid (violation occurred)" group.long 0xF80++0x03 line.long 0x00 "SEC_GPIO_MASK0,Secure GPIO mask for port 0 pins" bitfld.long 0x00 31. "PIO0_PIN31_SEC_MASK,Secure mask for pin P0_31" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 30. "PIO0_PIN30_SEC_MASK,Secure mask for pin P0_30" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 29. "PIO0_PIN29_SEC_MASK,Secure mask for pin P0_29" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 28. "PIO0_PIN28_SEC_MASK,Secure mask for pin P0_28" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 27. "PIO0_PIN27_SEC_MASK,Secure mask for pin P0_27" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 26. "PIO0_PIN26_SEC_MASK,Secure mask for pin P0_26" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 25. "PIO0_PIN25_SEC_MASK,Secure mask for pin P0_25" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 24. "PIO0_PIN24_SEC_MASK,Secure mask for pin P0_24" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 23. "PIO0_PIN23_SEC_MASK,Secure mask for pin P0_23" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 22. "PIO0_PIN22_SEC_MASK,Secure mask for pin P0_22" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 21. "PIO0_PIN21_SEC_MASK,Secure mask for pin P0_21" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 20. "PIO0_PIN20_SEC_MASK,Secure mask for pin P0_20" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 19. "PIO0_PIN19_SEC_MASK,Secure mask for pin P0_19" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 18. "PIO0_PIN18_SEC_MASK,Secure mask for pin P0_18" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 17. "PIO0_PIN17_SEC_MASK,Secure mask for pin P0_17" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 16. "PIO0_PIN16_SEC_MASK,Secure mask for pin P0_16" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 15. "PIO0_PIN15_SEC_MASK,Secure mask for pin P0_15" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 14. "PIO0_PIN14_SEC_MASK,Secure mask for pin P0_14" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 13. "PIO0_PIN13_SEC_MASK,Secure mask for pin P0_13" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 12. "PIO0_PIN12_SEC_MASK,Secure mask for pin P0_12" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 11. "PIO0_PIN11_SEC_MASK,Secure mask for pin P0_11" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 10. "PIO0_PIN10_SEC_MASK,Secure mask for pin P0_10" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 9. "PIO0_PIN9_SEC_MASK,Secure mask for pin P0_9" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 8. "PIO0_PIN8_SEC_MASK,Secure mask for pin P0_8" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 7. "PIO0_PIN7_SEC_MASK,Secure mask for pin P0_7" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 6. "PIO0_PIN6_SEC_MASK,Secure mask for pin P0_6" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 5. "PIO0_PIN5_SEC_MASK,Secure mask for pin P0_5" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 4. "PIO0_PIN4_SEC_MASK,Secure mask for pin P0_4" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 3. "PIO0_PIN3_SEC_MASK,Secure mask for pin P0_3" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 2. "PIO0_PIN2_SEC_MASK,Secure mask for pin P0_2" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 1. "PIO0_PIN1_SEC_MASK,Secure mask for pin P0_1" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 0. "PIO0_PIN0_SEC_MASK,Secure mask for pin P0_0" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" group.long 0xF84++0x03 line.long 0x00 "SEC_GPIO_MASK1,Secure GPIO mask for port 1 pins" bitfld.long 0x00 31. "PIO1_PIN31_SEC_MASK,Secure mask for pin P1_31" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 30. "PIO1_PIN30_SEC_MASK,Secure mask for pin P1_30" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 29. "PIO1_PIN29_SEC_MASK,Secure mask for pin P1_29" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 28. "PIO1_PIN28_SEC_MASK,Secure mask for pin P1_28" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 27. "PIO1_PIN27_SEC_MASK,Secure mask for pin P1_27" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 26. "PIO1_PIN26_SEC_MASK,Secure mask for pin P1_26" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 25. "PIO1_PIN25_SEC_MASK,Secure mask for pin P1_25" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 24. "PIO1_PIN24_SEC_MASK,Secure mask for pin P1_24" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 23. "PIO1_PIN23_SEC_MASK,Secure mask for pin P1_23" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 22. "PIO1_PIN22_SEC_MASK,Secure mask for pin P1_22" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 21. "PIO1_PIN21_SEC_MASK,Secure mask for pin P1_21" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 20. "PIO1_PIN20_SEC_MASK,Secure mask for pin P1_20" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 19. "PIO1_PIN19_SEC_MASK,Secure mask for pin P1_19" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 18. "PIO1_PIN18_SEC_MASK,Secure mask for pin P1_18" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 17. "PIO1_PIN17_SEC_MASK,Secure mask for pin P1_17" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 16. "PIO1_PIN16_SEC_MASK,Secure mask for pin P1_16" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 15. "PIO1_PIN15_SEC_MASK,Secure mask for pin P1_15" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 14. "PIO1_PIN14_SEC_MASK,Secure mask for pin P1_14" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 13. "PIO1_PIN13_SEC_MASK,Secure mask for pin P1_13" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 12. "PIO1_PIN12_SEC_MASK,Secure mask for pin P1_12" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 11. "PIO1_PIN11_SEC_MASK,Secure mask for pin P1_11" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 10. "PIO1_PIN10_SEC_MASK,Secure mask for pin P1_10" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 9. "PIO1_PIN9_SEC_MASK,Secure mask for pin P1_9" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 8. "PIO1_PIN8_SEC_MASK,Secure mask for pin P1_8" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 7. "PIO1_PIN7_SEC_MASK,Secure mask for pin P1_7" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 6. "PIO1_PIN6_SEC_MASK,Secure mask for pin P1_6" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 5. "PIO1_PIN5_SEC_MASK,Secure mask for pin P1_5" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 4. "PIO1_PIN4_SEC_MASK,Secure mask for pin P1_4" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 3. "PIO1_PIN3_SEC_MASK,Secure mask for pin P1_3" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 2. "PIO1_PIN2_SEC_MASK,Secure mask for pin P1_2" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 1. "PIO1_PIN1_SEC_MASK,Secure mask for pin P1_1" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" newline bitfld.long 0x00 0. "PIO1_PIN0_SEC_MASK,Secure mask for pin P1_0" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world" group.long 0xF90++0x03 line.long 0x00 "SEC_CPU_INT_MASK0,Secure Interrupt mask for CPU1" bitfld.long 0x00 31. "MAILBOX_IRQ,Mailbox interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 30. "RESERVED3,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 29. "RTC_IRQ,RTC_LITE0_ALARM_IRQ RTC_LITE0_WAKEUP_IRQ" "0: no description available,1: no description available" newline bitfld.long 0x00 28. "USB0_IRQ,USB Full Speed Controller interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 27. "USB0_NEEDCLK,USB Full Speed Controller Clock request interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 26. "RESERVED2,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 25. "RESERVED1,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 24. "ACMP_IRQ,Analog Comparator interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 23. "RESERVED0,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 22. "ADC_IRQ,General Purpose ADC interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 21. "FLEXCOMM7_IRQ,Flexcomm 7 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 20. "FLEXCOMM6_IRQ,Flexcomm 6 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 19. "FLEXCOMM5_IRQ,Flexcomm 5 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 18. "FLEXCOMM4_IRQ,Flexcomm 4 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 17. "FLEXCOMM3_IRQ,Flexcomm 3 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 16. "FLEXCOMM2_IRQ,Flexcomm 2 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 15. "FLEXCOMM1_IRQ,Flexcomm 1 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 14. "FLEXCOMM0_IRQ,Flexcomm 0 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available" newline bitfld.long 0x00 13. "CTIMER3_IRQ,Standard counter/timer 3 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 12. "SCT_IRQ,SCTimer/PWM interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 11. "CTIMER1_IRQ,Standard counter/timer 1 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 10. "CTIMER0_IRQ,Standard counter/timer 0 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 9. "MRT_IRQ,Multi-Rate Timer interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 8. "UTICK_IRQ,Micro Tick Timer interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 7. "GPIO_INT0_IRQ3,Pin interrupt 3 or pattern match engine slice 3 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 6. "GPIO_INT0_IRQ2,Pin interrupt 2 or pattern match engine slice 2 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 5. "GPIO_INT0_IRQ1,Pin interrupt 1 or pattern match engine slice 1 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 4. "GPIO_INT0_IRQ0,Pin interrupt 0 or pattern match engine slice 0 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 3. "GPIO_GLOBALINT1_IRQ,GPIO Group 1 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 2. "GPIO_GLOBALINT0_IRQ,GPIO Group 0 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 1. "SDMA0_IRQ,System DMA 0 (non-secure) interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 0. "SYS_IRQ,Watchdog Timer Brown Out Detectors and Flash Controller interrupts" "0: no description available,1: no description available" group.long 0xF94++0x03 line.long 0x00 "SEC_CPU_INT_MASK1,Secure Interrupt mask for CPU1" bitfld.long 0x00 27. "LSPI_HS_IRQ,High Speed SPI interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 26. "SDMA1_IRQ,System DMA 1 (Secure) interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 25. "PQ_IRQ,Power Quad interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 24. "PUFKEY_IRQ,PUF interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 23. "CASPER_IRQ,CASPER interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 22. "SHA_IRQ,HASH-AES interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 21. "SEC_VIO_IRQ,Security Violation interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 20. "PLU_IRQ,Programmable Look-Up Controller interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 19. "SEC_GPIO_INT0_IRQ1,Secure Pin interrupt 1 or pattern match engine slice 1 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 18. "SEC_GPIO_INT0_IRQ0,Secure Pin interrupt 0 or pattern match engine slice 0 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 17. "SEC_HYPERVISOR_CALL_IRQ,Secure fault Hyper Visor call interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 16. "USB1_NEEDCLK,USB High Speed Controller Clock request interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 15. "USB1_IRQ,USB High Speed Controller interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 14. "USB1_PHY_IRQ,USB High Speed PHY Controller interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 13. "RESERVED5,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 12. "RESERVED4,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 11. "RESERVED3,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 10. "SDIO_IRQ,SDIO Controller interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 9. "RESERVED2,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 8. "RESERVED1,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 7. "RESERVED0,Reserved" "0: no description available,1: no description available" newline bitfld.long 0x00 6. "OS_EVENT_TIMER_IRQ,OS Event Timer and OS Event Timer Wakeup interrupts" "0: no description available,1: no description available" newline bitfld.long 0x00 5. "CTIMER4_IRQ,Standard counter/timer 4 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 4. "CTIMER2_IRQ,Standard counter/timer 2 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 3. "GPIO_INT0_IRQ7,Pin interrupt 7 or pattern match engine slice 7 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 2. "GPIO_INT0_IRQ6,Pin interrupt 6 or pattern match engine slice 6 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 1. "GPIO_INT0_IRQ5,Pin interrupt 5 or pattern match engine slice 5 interrupt" "0: no description available,1: no description available" newline bitfld.long 0x00 0. "GPIO_INT0_IRQ4,Pin interrupt 4 or pattern match engine slice 4 interrupt" "0: no description available,1: no description available" group.long 0xFBC++0x03 line.long 0x00 "SEC_MASK_LOCK,Security General Purpose register access control" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 10.--11. "SEC_CPU1_INT_MASK1_LOCK,SEC_CPU_INT_MASK1 register write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 8.--9. "SEC_CPU1_INT_MASK0_LOCK,SEC_CPU_INT_MASK0 register write-lock" "?,1: Restricted mode,2: Writable,?..." newline endif bitfld.long 0x00 2.--3. "SEC_GPIO_MASK1_LOCK,SEC_GPIO_MASK1 register write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 0.--1. "SEC_GPIO_MASK0_LOCK,SEC_GPIO_MASK0 register write-lock" "?,1: Restricted mode,2: Writable,?..." group.long 0xFD0++0x03 line.long 0x00 "MASTER_SEC_LEVEL,master secure level register" bitfld.long 0x00 30.--31. "MASTER_SEC_LEVEL_LOCK,MASTER_SEC_LEVEL write-lock" "?,1: Restricted mode,2: Writable,?..." newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 26.--27. "CANFD,CAN FD" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif bitfld.long 0x00 24.--25. "SDMA1,System DMA 1 security level" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 22.--23. "USBFSH,USB Full speed Host" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif bitfld.long 0x00 20.--21. "HASH,Hash" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18.--19. "PQ,Power Quad" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 16.--17. "SDIO,SDIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif bitfld.long 0x00 10.--11. "SDMA0,System DMA 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 8.--9. "USBFSD,USB Full Speed Device" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6.--7. "CPU1S,Micro-Cortex M33 (CPU1) System bus" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" newline bitfld.long 0x00 4.--5. "CPU1C,Micro-Cortex M33 (CPU1) Code bus" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed" endif group.long 0xFD4++0x03 line.long 0x00 "MASTER_SEC_ANTI_POL_REG,master secure level anti-pole register" bitfld.long 0x00 30.--31. "MASTER_SEC_LEVEL_ANTIPOL_LOCK,MASTER_SEC_ANTI_POL_REG register write-lock" "?,1: Restricted mode,2: Writable,?..." newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 26.--27. "CANFD,CAN FD" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline endif bitfld.long 0x00 24.--25. "SDMA1,System DMA 1 security level" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 22.--23. "USBFSH,USB Full speed Host" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline endif bitfld.long 0x00 20.--21. "HASH,Hash" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18.--19. "PQ,Power Quad" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline bitfld.long 0x00 16.--17. "SDIO,SDIO" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline endif bitfld.long 0x00 10.--11. "SDMA0,System DMA 0" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 8.--9. "USBFSD,USB Full Speed Device" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6.--7. "CPU1S,Micro-Cortex M33 (CPU1) System bus" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." newline bitfld.long 0x00 4.--5. "CPU1C,Micro-Cortex M33 (CPU1) Code bus" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.." endif group.long 0xFEC++0x03 line.long 0x00 "CPU0_LOCK_REG,Miscalleneous control signals for in Cortex M33 (CPU0)" bitfld.long 0x00 30.--31. "CPU0_LOCK_REG_LOCK,CPU0_LOCK_REG write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 8.--9. "LOCK_SAU,Cortex M33 (CPU0) SAU registers write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 6.--7. "LOCK_S_MPU,Cortex M33 (CPU0) Secure MPU registers write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 4.--5. "LOCK_S_VTAIRCR,Cortex M33 (CPU0) VTOR_S AIRCR.PRIS IRCR.BFHFNMINS registers write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 2.--3. "LOCK_NS_MPU,Cortex M33 (CPU0) non-secure MPU register write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 0.--1. "LOCK_NS_VTOR,Cortex M33 (CPU0) VTOR_NS register write-lock" "?,1: Restricted mode,2: Writable,?..." group.long 0xFF0++0x03 line.long 0x00 "CPU1_LOCK_REG,Miscalleneous control signals for in micro-Cortex M33 (CPU1)" bitfld.long 0x00 30.--31. "CPU1_LOCK_REG_LOCK,CPU1_LOCK_REG write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 2.--3. "LOCK_NS_MPU,micro-Cortex M33 (CPU1) non-secure MPU register write-lock" "?,1: Restricted mode,2: Writable,?..." newline bitfld.long 0x00 0.--1. "LOCK_NS_VTOR,micro-Cortex M33 (CPU1) VTOR_NS register write-lock" "?,1: Restricted mode,2: Writable,?..." group.long 0xFF8++0x03 line.long 0x00 "MISC_CTRL_DP_REG,secure control duplicate register" bitfld.long 0x00 14.--15. "IDAU_ALL_NS,Disable IDAU" "?,1: IDAU is disable,2: IDAU is enabled,?..." newline bitfld.long 0x00 12.--13. "DISABLE_SMART_MASTER_STRICT_MODE,Disable smart master strict mode" "?,1: Smart master in tier mode,2: Smart master in strict mode,?..." newline bitfld.long 0x00 10.--11. "DISABLE_SIMPLE_MASTER_STRICT_MODE,Disable simple master strict mode" "?,1: Simple master in tier mode,2: Simple master in strict mode,?..." newline bitfld.long 0x00 8.--9. "DISABLE_VIOLATION_ABORT,Disable secure violation abort" "?,1: Disable abort fort secure checker,2: Enable abort fort secure checker,?..." newline bitfld.long 0x00 6.--7. "ENABLE_NS_PRIV_CHECK,Enable non-secure privilege check for AHB matrix" "?,1: Restricted mode,2: Disable check,?..." newline bitfld.long 0x00 4.--5. "ENABLE_S_PRIV_CHECK,Enable secure privilege check for AHB matrix" "?,1: Restricted mode,2: Disable check,?..." newline bitfld.long 0x00 2.--3. "ENABLE_SECURE_CHECKING,Enable secure check for AHB matrix" "?,1: Restricted mode,2: Disable check,?..." newline bitfld.long 0x00 0.--1. "WRITE_LOCK,Write lock" "?,1: Restricted mode,2: Secure control registers can be written,?..." group.long 0xFFC++0x03 line.long 0x00 "MISC_CTRL_REG,secure control register" bitfld.long 0x00 14.--15. "IDAU_ALL_NS,Disable IDAU" "?,1: IDAU is disable,2: IDAU is enabled,?..." newline bitfld.long 0x00 12.--13. "DISABLE_SMART_MASTER_STRICT_MODE,Disable smart master strict mode" "?,1: Smart master in tier mode,2: Smart master in strict mode,?..." newline bitfld.long 0x00 10.--11. "DISABLE_SIMPLE_MASTER_STRICT_MODE,Disable simple master strict mode" "?,1: Simple master in tier mode,2: Simple master in strict mode,?..." newline bitfld.long 0x00 8.--9. "DISABLE_VIOLATION_ABORT,Disable secure violation abort" "?,1: Disable abort fort secure checker,2: Enable abort fort secure checker,?..." newline bitfld.long 0x00 6.--7. "ENABLE_NS_PRIV_CHECK,Enable non-secure privilege check for AHB matrix" "?,1: Enabled (restricted mode),2: Disable check,?..." newline bitfld.long 0x00 4.--5. "ENABLE_S_PRIV_CHECK,Enable secure privilege check for AHB matrix" "?,1: Enabled (restricted mode),2: Disable check,?..." newline bitfld.long 0x00 2.--3. "ENABLE_SECURE_CHECKING,Enable secure check for AHB matrix" "?,1: Enabled (restricted mode),2: Disable check,?..." newline bitfld.long 0x00 0.--1. "WRITE_LOCK,Write lock" "?,1: Restricted mode,2: Secure control registers can be written,?..." tree.end endif tree "ANACTRL (Analog Controller)" base ad:0x40013000 group.long 0x00++0x03 line.long 0x00 "ANALOG_CTRL_CFG,Various Analog blocks configuration (like FRO 192MHz trimmings source ...)" bitfld.long 0x00 0. "FRO192M_TRIM_SRC,FRO192M trimming and 'Enable' source" "0: FRO192M trimming and 'Enable' comes from eFUSE,1: FRO192M trimming and 'Enable' comes from.." rgroup.long 0x04++0x03 line.long 0x00 "ANALOG_CTRL_STATUS,Analog Control and Status" bitfld.long 0x00 16. "FLASH_ECC_ERROR_FLAG,Flash ECC Error Flag" "0,1" newline bitfld.long 0x00 13. "FLASH_INIT_ERROR,Flash initialization error status" "0: No error,1: At least one error occurred" newline bitfld.long 0x00 12. "FLASH_PWRDWN,Flash Power Down status" "0: Not in power down mode,1: In power down mode" group.long 0x10++0x03 line.long 0x00 "FRO192M_CTRL,192MHz Free Running Oscillator (FRO) Control" bitfld.long 0x00 31. "WRTRIM,This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields" "0,1" newline bitfld.long 0x00 30. "ENA_96MHZCLK,96 MHz clock control" "0: Disable the 96 MHz clock,1: Enable the 96 MHz clock" newline rbitfld.long 0x00 25. "USBMODCHG,USBCLKADJ mode trim change" "0,1" newline bitfld.long 0x00 24. "USBCLKADJ,If USBCLKADJ bit is set and the USB peripheral is enabled for full speed device mode the USB block will provide FRO clock adjustments to synchronize the frequency to the host clock using the SOF packets" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. "FREQ_TRIM,Frequency trim" newline bitfld.long 0x00 14. "ENA_12MHZCLK,12 MHz clock control" "0: Disable the 12 MHz clock,1: Enable the 12 MHz clock" rgroup.long 0x14++0x03 line.long 0x00 "FRO192M_STATUS,192MHz Free Running Oscillator (FRO) Status" bitfld.long 0x00 1. "ATB_VCTRL,CCO threshold voltage detector output (signal vcco_ok)" "0,1" newline bitfld.long 0x00 0. "CLK_VALID,Output clock valid" "0: No output clock available,1: Output clock is available" group.long 0x18++0x03 line.long 0x00 "ADC_CTRL,General Purpose ADC VBAT Divider branch control" bitfld.long 0x00 0. "VBATDIVENABLE,Switch On/Off VBAT divider branch" "0: VBAT divider branch is disabled,1: VBAT divider branch is enabled" group.long 0x20++0x03 line.long 0x00 "XO32M_CTRL,High speed Crystal Oscillator Control register" bitfld.long 0x00 24. "ENABLE_SYSTEM_CLK_OUT,Enable High speed Crystal oscillator output to CPU system" "0: Disable the oscillator,1: Enable the oscillator" newline bitfld.long 0x00 22. "ACBUF_PASS_ENABLE,Allows XO32M to be configured in bypass mode" "0: XO bypass is disabled,1: XO bypass is enabled" newline hexmask.long.byte 0x00 15.--21. 1. "OSC_CAP_OUT,Tune capa banks of High speed Crystal Oscillator output pin" newline hexmask.long.byte 0x00 8.--14. 1. "OSC_CAP_IN,Tune capa banks of High speed Crystal Oscillator input pin" newline bitfld.long 0x00 4. "SLAVE,XO in slave mode" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "XO32M_STATUS,High speed Crystal Oscillator Status" bitfld.long 0x00 0. "XO_READY,Crystal Oscillator Ready" "0: Frequency is not yet stable,1: Frequency is stable" group.long 0x30++0x03 line.long 0x00 "BOD_DCDC_INT_CTRL,Brown Out Detectors & DCDC interrupt control" bitfld.long 0x00 5. "DCDC_INT_CLEAR,DCDC interrupt clear.1: Clear the interrupt" "0,1" newline bitfld.long 0x00 4. "DCDC_INT_ENABLE,DCDC interrupt control" "0: Disable the interrupt,1: Enable the interrupt" newline bitfld.long 0x00 3. "BODCORE_INT_CLEAR,BOD CORE interrupt clear.1: Clear the interrupt" "0,1" newline bitfld.long 0x00 2. "BODCORE_INT_ENABLE,BOD CORE interrupt control" "0: Disable the interrupt,1: Enable the interrupt" newline bitfld.long 0x00 1. "BODVDDMAIN_INT_CLEAR,BOD VDDMAIN interrupt clear.1: Clear the interrupt" "0,1" newline bitfld.long 0x00 0. "BODVDDMAIN_INT_ENABLE,BOD VDDMAIN interrupt control" "0: Disable the interrupt,1: Enable the interrupt" rgroup.long 0x34++0x03 line.long 0x00 "BOD_DCDC_INT_STATUS,BoDs & DCDC interrupt status" bitfld.long 0x00 8. "DCDC_VAL,DCDC power status" "0: Below the target,1: Above the target" newline bitfld.long 0x00 7. "DCDC_INT_STATUS,DCDC Interrupt status after Interrupt Enable" "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x00 6. "DCDC_STATUS,DCDC Interrupt status before Interrupt Enable" "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x00 5. "BODCORE_VAL,BOD CORE power status" "0: Below the threshold,1: Above the threshold" newline bitfld.long 0x00 4. "BODCORE_INT_STATUS,BOD CORE Interrupt status after Interrupt Enable" "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x00 3. "BODCORE_STATUS,BOD CORE Interrupt status before Interrupt Enable" "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x00 2. "BODVDDMAIN_VAL,BOD VDDMAIN power status" "0: Below the threshold,1: Above the threshold" newline bitfld.long 0x00 1. "BODVDDMAIN_INT_STATUS,BOD VDDMAIN Interrupt status after Interrupt Enable" "0: No interrupt pending,1: Interrupt pending" newline bitfld.long 0x00 0. "BODVDDMAIN_STATUS,BOD VDDMAIN Interrupt status before Interrupt Enable" "0: No interrupt pending,1: Interrupt pending" group.long 0xB0++0x03 line.long 0x00 "LDO_XO32M,High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register" bitfld.long 0x00 8.--9. "STABMODE,Stability configuration" "0,1,2,3" newline bitfld.long 0x00 6.--7. "IBIAS,Adjust the biasing current" "0,1,2,3" newline bitfld.long 0x00 3.--5. "VOUT,Sets the LDO output level" "0: 0.750 V,1: 0.775 V,2: 0.800 V,3: 0.825 V,4: 0.850 V,5: 0.875 V,6: 0.900 V,7: 0.925 V" newline bitfld.long 0x00 2. "HIGHZ," "0: Output in High normal state,1: Output in High Impedance state" newline bitfld.long 0x00 1. "BYPASS,Activate LDO bypass" "0: Disable bypass mode (for normal operations),1: Activate LDO bypass" group.long 0xF0++0x03 line.long 0x00 "OSC_TESTBUS,Oscillators Analog Macrobloc ACBUS and DCBUS control" bitfld.long 0x00 16.--21. "DCBUS,Direct current BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. "ACBUS,Alternate current BUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "DUMMY_CTRL,Dummy Control bus to analog modules" bitfld.long 0x00 10.--11. "XO32M_ADC_CLK_MODE,Control High speed Crystal oscillator mode of the ADC clock" "0: High speed Crystal oscillator output to ADC..,1: High speed Crystal oscillator output to ADC..,?..." tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "AOI" repeat 2. (list 0. 1.) (list ad:0x400C7000 ad:0x400C8000) tree "AOI$1" base $2 group.word 0x00++0x01 line.word 0x00 "BFCRT010,Boolean Function Term 0 and 1 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT0_AC,Product term 0 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT0_BC,Product term 0 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT0_CC,Product term 0 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT0_DC,Product term 0 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT1_AC,Product term 1 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT1_BC,Product term 1 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT1_CC,Product term 1 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT1_DC,Product term 1 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." group.word 0x02++0x01 line.word 0x00 "BFCRT230,Boolean Function Term 2 and 3 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT2_AC,Product term 2 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT2_BC,Product term 2 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT2_CC,Product term 2 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT2_DC,Product term 2 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT3_AC,Product term 3 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT3_BC,Product term 3 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT3_CC,Product term 3 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT3_DC,Product term 3 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." group.word 0x04++0x01 line.word 0x00 "BFCRT011,Boolean Function Term 0 and 1 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT0_AC,Product term 0 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT0_BC,Product term 0 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT0_CC,Product term 0 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT0_DC,Product term 0 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT1_AC,Product term 1 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT1_BC,Product term 1 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT1_CC,Product term 1 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT1_DC,Product term 1 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." group.word 0x06++0x01 line.word 0x00 "BFCRT231,Boolean Function Term 2 and 3 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT2_AC,Product term 2 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT2_BC,Product term 2 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT2_CC,Product term 2 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT2_DC,Product term 2 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT3_AC,Product term 3 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT3_BC,Product term 3 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT3_CC,Product term 3 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT3_DC,Product term 3 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." group.word 0x08++0x01 line.word 0x00 "BFCRT012,Boolean Function Term 0 and 1 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT0_AC,Product term 0 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT0_BC,Product term 0 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT0_CC,Product term 0 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT0_DC,Product term 0 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT1_AC,Product term 1 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT1_BC,Product term 1 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT1_CC,Product term 1 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT1_DC,Product term 1 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." group.word 0x0A++0x01 line.word 0x00 "BFCRT232,Boolean Function Term 2 and 3 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT2_AC,Product term 2 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT2_BC,Product term 2 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT2_CC,Product term 2 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT2_DC,Product term 2 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT3_AC,Product term 3 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT3_BC,Product term 3 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT3_CC,Product term 3 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT3_DC,Product term 3 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." group.word 0x0C++0x01 line.word 0x00 "BFCRT013,Boolean Function Term 0 and 1 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT0_AC,Product term 0 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT0_BC,Product term 0 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT0_CC,Product term 0 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT0_DC,Product term 0 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT1_AC,Product term 1 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT1_BC,Product term 1 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT1_CC,Product term 1 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT1_DC,Product term 1 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." group.word 0x0E++0x01 line.word 0x00 "BFCRT233,Boolean Function Term 2 and 3 Configuration Register for EVENTn" bitfld.word 0x00 14.--15. "PT2_AC,Product term 2 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 12.--13. "PT2_BC,Product term 2 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 10.--11. "PT2_CC,Product term 2 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 8.--9. "PT2_DC,Product term 2 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." newline bitfld.word 0x00 6.--7. "PT3_AC,Product term 3 A input configuration" "0: Force the A input in this product term to a..,1: Pass the A input in this product term,2: Complement the A input in this product term,3: Force the A input in this product term to a.." bitfld.word 0x00 4.--5. "PT3_BC,Product term 3 B input configuration" "0: Force the B input in this product term to a..,1: Pass the B input in this product term,2: Complement the B input in this product term,3: Force the B input in this product term to a.." newline bitfld.word 0x00 2.--3. "PT3_CC,Product term 3 C input configuration" "0: Force the C input in this product term to a..,1: Pass the C input in this product term,2: Complement the C input in this product term,3: Force the C input in this product term to a.." bitfld.word 0x00 0.--1. "PT3_DC,Product term 3 D input configuration" "0: Force the D input in this product term to a..,1: Pass the D input in this product term,2: Complement the D input in this product term,3: Force the D input in this product term to a.." tree.end repeat.end tree.end tree "CACHE64_CTRL (CACHE64)" base ad:0x4002E000 group.long 0x800++0x03 line.long 0x00 "CCR,Cache control register" bitfld.long 0x00 31. "GO,Initiate Cache Command" "0: Write: no effect,1: Write: initiate command indicated by bits 27-24" bitfld.long 0x00 27. "PUSHW1,Push Way 1" "0: no_operation,1: When setting the GO bit push all modified.." newline bitfld.long 0x00 26. "INVW1,Invalidate Way 1" "0: no_operation,1: When setting the GO bit invalidate all lines.." bitfld.long 0x00 25. "PUSHW0,Push Way 0" "0: no_operation,1: When setting the GO bit push all modified.." newline bitfld.long 0x00 24. "INVW0,Invalidate Way 0" "0: no_operation,1: When setting the GO bit invalidate all lines.." bitfld.long 0x00 1. "ENWRBUF,Enable Write Buffer" "0: Write buffer disabled,1: Write buffer enabled" newline bitfld.long 0x00 0. "ENCACHE,Cache enable" "0: Cache disabled,1: Cache enabled" group.long 0x804++0x03 line.long 0x00 "CLCR,Cache line control register" bitfld.long 0x00 27. "LACC,Line access type" "0: read,1: write" bitfld.long 0x00 26. "LADSEL,Line Address Select" "0: Cache address,1: Physical address" newline bitfld.long 0x00 24.--25. "LCMD,Line Command" "0: Search and read or write,1: invalidate,2: push,3: clear" bitfld.long 0x00 22. "LCWAY,Line Command Way" "0,1" newline bitfld.long 0x00 21. "LCIMB,Line Command Initial Modified Bit" "0,1" bitfld.long 0x00 20. "LCIVB,Line Command Initial Valid Bit" "0,1" newline bitfld.long 0x00 16. "TDSEL,Tag/Data Select" "0: data,1: tag" bitfld.long 0x00 14. "WSEL,Way select" "0: Way 0,1: Way 1" newline hexmask.long.word 0x00 2.--13. 1. "CACHEADDR,Cache address" bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.." group.long 0x808++0x03 line.long 0x00 "CSAR,Cache search address register" hexmask.long 0x00 1.--31. 1. "PHYADDR,Physical Address" bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.." group.long 0x80C++0x03 line.long 0x00 "CCVR,Cache read/write value register" hexmask.long 0x00 0.--31. 1. "DATA,Cache read/write Data" tree.end tree "CACHE64_POLSEL" base ad:0x4002E000 group.long 0x14++0x03 line.long 0x00 "REG0_TOP,Region 0 Top Boundary" hexmask.long.tbyte 0x00 10.--26. 1. "REG0_TOP,Upper limit of Region 0" group.long 0x18++0x03 line.long 0x00 "REG1_TOP,Region 1 Top Boundary" hexmask.long.tbyte 0x00 10.--26. 1. "REG1_TOP,Upper limit of Region 1" group.long 0x1C++0x03 line.long 0x00 "POLSEL,Policy Select" bitfld.long 0x00 4.--5. "REG02_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG2_11" bitfld.long 0x00 2.--3. "REG1_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG1_11" bitfld.long 0x00 0.--1. "REG0_POLICY,Policy Select for Region 0" "0: Non-cache,1: Write-thru,2: Write-back,3: REG0_11" tree.end endif sif cpuis("LPC5534*")||cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5536*") tree "CAN (MCAN)" sif cpuis("LPC5534*")||cpuis("LPC5536*") base ad:0x4009D000 group.long 0x0C++0x03 line.long 0x00 "DBTP,Data Bit Timing and Prescaler" bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0: Transmitter delay compensation disabled,1: Transmitter delay compensation enabled" bitfld.long 0x00 16.--20. "DBRP,Data Bit Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "DTSEG1,Data Time Segment Before Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. "DTSEG2,Data Time Segment After Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "TEST,Test" bitfld.long 0x00 7. "RX,Monitors the Actual Value of the CAN_RXD" "0: The CAN bus is dominant (CAN_RXD = 0),1: The CAN bus is recessive (CAN_RXD = 1)" bitfld.long 0x00 5.--6. "TX,Control of Transmit Pin" "0: Loop back mode is disabled,1: The sample point can be monitored at the..,2: CAN_TXD pin is driven LOW/dominant,3: CAN_TXD is driven HIGH/recessive" newline bitfld.long 0x00 4. "LBCK,Loop Back Mode" "0: Loop back mode is disabled,1: Loop back mode is enabled" group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control" bitfld.long 0x00 15. "NISO,Non ISO Operation" "0: CAN FD frame format will follow according to..,1: CAN FD frame format will follow according to.." bitfld.long 0x00 14. "TXP,Transmit Pause" "0: Transmit pause is disabled,1: Transmit pause is enabled" newline bitfld.long 0x00 13. "EFBI,Edge Filtering During Bus Integration" "0: Edge filtering is disabled,1: Two consecutive dominant quanta required to.." bitfld.long 0x00 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling is enabled,1: Protocol exception handling is disabled" newline bitfld.long 0x00 9. "BRSE,Bit Rate Switching Enable" "0: Bit rate switching for transmissions is..,1: Bit rate switching for transmission is enabled" bitfld.long 0x00 8. "FDOE,CAN FD Operation Enable" "0: CAN FD operation is disabled,1: CAN FD operation is enabled" newline bitfld.long 0x00 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test mode enabled" bitfld.long 0x00 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x00 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring mode is disabled,1: Bus Monitoring mode is enabled" bitfld.long 0x00 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested" newline bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: MCAN may be set in Power Down mode by.." bitfld.long 0x00 2. "ASM,Restricted Operational Mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x00 1. "CCE,Configuration Change Enable" "0: No write access,1: Write access" bitfld.long 0x00 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started" group.long 0x1C++0x03 line.long 0x00 "NBTP,Nominal Bit Timing and Prescaler" hexmask.long.byte 0x00 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width" hexmask.long.word 0x00 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler" newline hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point" hexmask.long.byte 0x00 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point" group.long 0x20++0x03 line.long 0x00 "TSCC,Timestamp Counter Configuration" bitfld.long 0x00 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value static at 0x0000,1: Timestamp counter value incremented according..,2: External timestamp counter value used,3: Timestamp counter value static at 0x0000" rgroup.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value" hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp Counter" group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration" hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x00 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout is controlled by Tx event FIFO,2: Timeout is controlled by Rx FIFO 0,3: Timeout is controlled by Rx FIFO 1" newline bitfld.long 0x00 0. "ETOC,Enable Timeout Counter" "0: Timeout counter is disabled,1: Timeout counter is enabled" rgroup.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value" hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout Counter" rgroup.long 0x40++0x03 line.long 0x00 "ECR,Error Counter" hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x00 15. "RP,Receive Error Passive" "0: Below error level,1: At error level" newline hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter" rgroup.long 0x44++0x03 line.long 0x00 "PSR,Protocol Status" hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x00 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since..,1: Protocol exception event occurred" newline bitfld.long 0x00 13. "RFDF,Received a CAN FD Message" "0: No CAN FD message received since the last CPU..,1: Message in CAN FD format with FDF flag set.." bitfld.long 0x00 12. "RBRS,BRS Flag of Last Received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag.." newline bitfld.long 0x00 11. "RESI,ESI Flag of the Last Received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag.." bitfld.long 0x00 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "BO,Bus Off Status" "0: DISABLED,1: ENABLED" bitfld.long 0x00 6. "EW,Warning Status" "0: Both error counters are below the..,1: At least one of error counter has reached the.." newline bitfld.long 0x00 5. "EP,Error Passive" "0: The MCAN is in Error_Active state,1: The MCAN is in the Error_Passive state" bitfld.long 0x00 3.--4. "ACT,Activity" "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,2: Receiver - node is operating as receiver,3: Transmitter - node is operating as transmitter" newline bitfld.long 0x00 0.--2. "LEC,Last Error Code" "0: No error,1: Stuff error,2: Form error,3: AckError,4: Bit1Error,5: Bit0Error,6: CRCError,7: NoChange" group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensator" hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0x03 line.long 0x00 "IR,Interrupt" bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected" newline bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x00 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x00 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x00 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from..,1: Bit error detected uncorrected (example.." bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from..,1: Bit error detected and corrected (example ECC)" newline bitfld.long 0x00 19. "DRX,Message Stored in Dedicated Rx Buffer" "0: No Rx buffer updated,1: At least one received message stored into an.." bitfld.long 0x00 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wrapped around" newline bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after.." bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx Handler wrote Tx event FIFO element" newline bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x00 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x00 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" group.long 0x54++0x03 line.long 0x00 "IE,Interrupt Enable" bitfld.long 0x00 29. "ARAE,Access to Reserved Address Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 19. "DRXE,Message Stored in Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 15. "TEFLE,Tx Event FIFO Element Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" group.long 0x58++0x03 line.long 0x00 "ILS,Interrupt Line Select" bitfld.long 0x00 29. "ARAL,Access to Reserved Address Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 19. "DRXL,Message Stored in Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 16. "TSWL,Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 15. "TEFLL,Tx Event FIFO Element Lost Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" group.long 0x5C++0x03 line.long 0x00 "ILE,Interrupt Line Enable" bitfld.long 0x00 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line to MCANx_INT1 is disabled,1: Interrupt line to MCANx_INT1 is enabled" bitfld.long 0x00 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line to MCANx_INT0 is disabled,1: Interrupt line to MCANx_INT0 is enabled" group.long 0x80++0x03 line.long 0x00 "GFC,Global Filter Configuration" bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: REJECT,3: REJECT" bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: REJECT,3: REJECT" newline bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard.." bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended.." group.long 0x84++0x03 line.long 0x00 "SIDFC,Standard ID Filter Configuration" hexmask.long.byte 0x00 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x00 2.--15. 1. "FLSSA,Filter List Standard Start Address" group.long 0x88++0x03 line.long 0x00 "XIDFC,Extended ID Filter Configuration" hexmask.long.byte 0x00 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x00 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask" hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status" bitfld.long 0x00 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x00 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x00 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,2: Message stored in FIFO 0,3: Message stored in FIFO 1" bitfld.long 0x00 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" repeat 2. (strings "1" "2" )(list 0x0 0x4 ) group.long ($2+0x98)++0x03 line.long 0x00 "NDAT$1,New Data $1" hexmask.long 0x00 0.--31. 1. "ND,New Data" repeat.end group.long 0xA0++0x03 line.long 0x00 "RXF0C,Rx FIFO 0 Configuration" bitfld.long 0x00 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,Rx FIFO 0 Status" bitfld.long 0x00 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x00 24. "F0F,Rx FIFO 0 Full" "0: RX_FIFO_0_NOT_FULL,1: RX_FIFO_0_FULL" newline bitfld.long 0x00 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge" bitfld.long 0x00 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xAC++0x03 line.long 0x00 "RXBC,Rx Buffer Configuration" hexmask.long.word 0x00 2.--15. 1. "RBSA,Rx Buffer Start Address" group.long 0xB0++0x03 line.long 0x00 "RXF1C,Rx FIFO 1 Configuration" bitfld.long 0x00 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x00 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x00 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x00 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,Rx FIFO 1 Status" bitfld.long 0x00 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x00 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x00 16.--21. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge" bitfld.long 0x00 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBC++0x03 line.long 0x00 "RXESC,Rx Buffer and FIFO Element Size Configuration" bitfld.long 0x00 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x00 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x00 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" group.long 0xC0++0x03 line.long 0x00 "TXBC,Tx Buffer Configuration" bitfld.long 0x00 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx queue operation" bitfld.long 0x00 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 2.--15. 1. "TBSA,Tx Buffers Start Address" group.long 0xC4++0x03 line.long 0x00 "TXFQS,Tx FIFO/Queue Status" bitfld.long 0x00 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" bitfld.long 0x00 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "TFGI,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC8++0x03 line.long 0x00 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x00 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,Tx Buffer Request Pending" hexmask.long 0x00 0.--31. 1. "TRP,Transmission Request Pending" group.long 0xD0++0x03 line.long 0x00 "TXBAR,Tx Buffer Add Request" hexmask.long 0x00 0.--31. 1. "AR,Add Request" group.long 0xD4++0x03 line.long 0x00 "TXBCR,Tx Buffer Cancellation Request" hexmask.long 0x00 0.--31. 1. "CR,Cancellation Request" rgroup.long 0xD8++0x03 line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred" hexmask.long 0x00 0.--31. 1. "TO,Transmission Occurred" rgroup.long 0xDC++0x03 line.long 0x00 "TXBCF,Tx Buffer Cancellation Finished" hexmask.long 0x00 0.--31. 1. "TO,Cancellation Finished" group.long 0xE0++0x03 line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable" hexmask.long 0x00 0.--31. 1. "TIE,Transmission Interrupt Enable" group.long 0xE4++0x03 line.long 0x00 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable" hexmask.long 0x00 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0xF0++0x03 line.long 0x00 "TXEFC,Tx Event FIFO Configuration" bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,Tx Event FIFO Status" bitfld.long 0x00 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after.." bitfld.long 0x00 24. "EFF,Event FIFO Full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x00 16.--21. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge" bitfld.long 0x00 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x200++0x03 line.long 0x00 "MRBA,Message RAM Base Address" hexmask.long.word 0x00 16.--31. 1. "BA,Base Address for the message RAM in the chip memory map" group.long 0x400++0x03 line.long 0x00 "ETSCC,External Timestamp Counter Configuration" bitfld.long 0x00 31. "ETCE,External Timestamp Counter Enable" "0: External timestamp counter is disabled,1: External timestamp counter is enabled" hexmask.long.word 0x00 0.--10. 1. "ETCP,External Timestamp Prescaler Value" group.long 0x600++0x03 line.long 0x00 "ETSCV,External Timestamp Counter Value" hexmask.long.word 0x00 0.--15. 1. "ETSC,External Timestamp Counter" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") base ad:0x4009D000 group.long 0x0C++0x03 line.long 0x00 "DBTP,Data Bit Timing and Prescaler" bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0: Transmitter delay compensation disabled,1: Transmitter delay compensation enabled" bitfld.long 0x00 16.--20. "DBRP,Data Bit Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "DTSEG1,Data Time Segment Before Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. "DTSEG2,Data Time Segment After Sample Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "TEST,Test" bitfld.long 0x00 7. "RX,Monitors the Actual Value of the CAN_RXD" "0: The CAN bus is dominant (CAN_RXD = 0),1: The CAN bus is recessive (CAN_RXD = 1)" bitfld.long 0x00 5.--6. "TX,Control of Transmit Pin" "0: Loop back mode is disabled,1: The sample point can be monitored at the..,2: CAN_TXD pin is driven LOW/dominant,3: CAN_TXD is driven HIGH/recessive" newline bitfld.long 0x00 4. "LBCK,Loop Back Mode" "0: Loop back mode is disabled,1: Loop back mode is enabled" group.long 0x18++0x03 line.long 0x00 "CCCR,CC Control" bitfld.long 0x00 15. "NISO,Non ISO Operation" "0: CAN FD frame format will follow according to..,1: CAN FD frame format will follow according to.." bitfld.long 0x00 14. "TXP,Transmit Pause" "0: Transmit pause is disabled,1: Transmit pause is enabled" newline bitfld.long 0x00 13. "EFBI,Edge Filtering During Bus Integration" "0: Edge filtering is disabled,1: Two consecutive dominant quanta required to.." bitfld.long 0x00 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling is enabled,1: Protocol exception handling is disabled" newline bitfld.long 0x00 9. "BRSE,Bit Rate Switching Enable" "0: Bit rate switching for transmissions is..,1: Bit rate switching for transmission is enabled" bitfld.long 0x00 8. "FDOE,CAN FD Operation Enable" "0: CAN FD operation is disabled,1: CAN FD operation is enabled" newline bitfld.long 0x00 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test mode enabled" bitfld.long 0x00 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled" newline bitfld.long 0x00 5. "MON,Bus Monitoring Mode" "0: Bus Monitoring mode is disabled,1: Bus Monitoring mode is enabled" bitfld.long 0x00 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested" newline bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: MCAN may be set in Power Down mode by.." bitfld.long 0x00 2. "ASM,Restricted Operational Mode" "0: Normal CAN operation,1: Restricted operation mode active" newline bitfld.long 0x00 1. "CCE,Configuration Change Enable" "0: No write access,1: Write access" bitfld.long 0x00 0. "INIT,Initialization" "0: Normal operation,1: Initialization is started" group.long 0x1C++0x03 line.long 0x00 "NBTP,Nominal Bit Timing and Prescaler" hexmask.long.byte 0x00 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width" hexmask.long.word 0x00 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler" newline hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point" hexmask.long.byte 0x00 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point" group.long 0x20++0x03 line.long 0x00 "TSCC,Timestamp Counter Configuration" bitfld.long 0x00 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value static at 0x0000,1: Timestamp counter value incremented according..,2: External timestamp counter value used,3: Timestamp counter value static at 0x0000" rgroup.long 0x24++0x03 line.long 0x00 "TSCV,Timestamp Counter Value" hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp Counter" group.long 0x28++0x03 line.long 0x00 "TOCC,Timeout Counter Configuration" hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x00 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout is controlled by Tx event FIFO,2: Timeout is controlled by Rx FIFO 0,3: Timeout is controlled by Rx FIFO 1" newline bitfld.long 0x00 0. "ETOC,Enable Timeout Counter" "0: Timeout counter is disabled,1: Timeout counter is enabled" rgroup.long 0x2C++0x03 line.long 0x00 "TOCV,Timeout Counter Value" hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout Counter" rgroup.long 0x40++0x03 line.long 0x00 "ECR,Error Counter" hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x00 15. "RP,Receive Error Passive" "0: Below error level,1: At error level" newline hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter" rgroup.long 0x44++0x03 line.long 0x00 "PSR,Protocol Status" hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x00 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since..,1: Protocol exception event occurred" newline bitfld.long 0x00 13. "RFDF,Received a CAN FD Message" "0: No CAN FD message received since the last CPU..,1: Message in CAN FD format with FDF flag set.." bitfld.long 0x00 12. "RBRS,BRS Flag of Last Received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag.." newline bitfld.long 0x00 11. "RESI,ESI Flag of the Last Received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag.." bitfld.long 0x00 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "BO,Bus Off Status" "0: DISABLED,1: ENABLED" bitfld.long 0x00 6. "EW,Warning Status" "0: Both error counters are below the..,1: At least one of error counter has reached the.." newline bitfld.long 0x00 5. "EP,Error Passive" "0: The MCAN is in Error_Active state,1: The MCAN is in the Error_Passive state" bitfld.long 0x00 3.--4. "ACT,Activity" "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,2: Receiver - node is operating as receiver,3: Transmitter - node is operating as transmitter" newline bitfld.long 0x00 0.--2. "LEC,Last Error Code" "0: No error,1: Stuff error,2: Form error,3: AckError,4: Bit1Error,5: Bit0Error,6: CRCError,7: NoChange" group.long 0x48++0x03 line.long 0x00 "TDCR,Transmitter Delay Compensator" hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" group.long 0x50++0x03 line.long 0x00 "IR,Interrupt" bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred" bitfld.long 0x00 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected" newline bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected" bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY" newline bitfld.long 0x00 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed" bitfld.long 0x00 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed" newline bitfld.long 0x00 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed" bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0: CAN error logging counter did not overflow,1: Overflow of CAN error logging counter occurred" newline bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from..,1: Bit error detected uncorrected (example.." bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0: No bit error detected when reading from..,1: Bit error detected and corrected (example ECC)" newline bitfld.long 0x00 19. "DRX,Message Stored in Dedicated Rx Buffer" "0: No Rx buffer updated,1: At least one received message stored into an.." bitfld.long 0x00 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached" newline bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred" bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wraparound,1: Timestamp counter wrapped around" newline bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after.." bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx event FIFO fill level below watermark,1: Tx event FIFO fill level reached watermark" bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx Handler wrote Tx event FIFO element" newline bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty" bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished" newline bitfld.long 0x00 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed" bitfld.long 0x00 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received" newline bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark" bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1" newline bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.." bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full" newline bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark" bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0" group.long 0x54++0x03 line.long 0x00 "IE,Interrupt Enable" bitfld.long 0x00 29. "ARAE,Access to Reserved Address Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 19. "DRXE,Message Stored in Dedicated Rx Buffer Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 15. "TEFLE,Tx Event FIFO Element Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x00 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" group.long 0x58++0x03 line.long 0x00 "ILS,Interrupt Line Select" bitfld.long 0x00 29. "ARAL,Access to Reserved Address Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 20. "BECL,Bit Error Corrected Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 19. "DRXL,Message Stored in Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 16. "TSWL,Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 15. "TEFLL,Tx Event FIFO Element Lost Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" newline bitfld.long 0x00 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" bitfld.long 0x00 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to interrupt line MCANx_INT0,1: Interrupt assigned to interrupt line MCANx_INT1" group.long 0x5C++0x03 line.long 0x00 "ILE,Interrupt Line Enable" bitfld.long 0x00 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line to MCANx_INT1 is disabled,1: Interrupt line to MCANx_INT1 is enabled" bitfld.long 0x00 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line to MCANx_INT0 is disabled,1: Interrupt line to MCANx_INT0 is enabled" group.long 0x80++0x03 line.long 0x00 "GFC,Global Filter Configuration" bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: REJECT,3: REJECT" bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: REJECT,3: REJECT" newline bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard.." bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended.." group.long 0x84++0x03 line.long 0x00 "SIDFC,Standard ID Filter Configuration" hexmask.long.byte 0x00 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x00 2.--15. 1. "FLSSA,Filter List Standard Start Address" group.long 0x88++0x03 line.long 0x00 "XIDFC,Extended ID Filter Configuration" hexmask.long.byte 0x00 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x00 2.--15. 1. "FLESA,Filter List Extended Start Address" group.long 0x90++0x03 line.long 0x00 "XIDAM,Extended ID AND Mask" hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0x03 line.long 0x00 "HPMS,High Priority Message Status" bitfld.long 0x00 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list" hexmask.long.byte 0x00 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x00 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,2: Message stored in FIFO 0,3: Message stored in FIFO 1" bitfld.long 0x00 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" repeat 2. (strings "1" "2" )(list 0x0 0x4 ) group.long ($2+0x98)++0x03 line.long 0x00 "NDAT$1,New Data $1" hexmask.long 0x00 0.--31. 1. "ND,New Data" repeat.end group.long 0xA0++0x03 line.long 0x00 "RXF0C,Rx FIFO 0 Configuration" bitfld.long 0x00 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode" hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" newline hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0xA4++0x03 line.long 0x00 "RXF0S,Rx FIFO 0 Status" bitfld.long 0x00 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x00 24. "F0F,Rx FIFO 0 Full" "0: RX_FIFO_0_NOT_FULL,1: RX_FIFO_0_FULL" newline bitfld.long 0x00 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0xA8++0x03 line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge" bitfld.long 0x00 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xAC++0x03 line.long 0x00 "RXBC,Rx Buffer Configuration" hexmask.long.word 0x00 2.--15. 1. "RBSA,Rx Buffer Start Address" group.long 0xB0++0x03 line.long 0x00 "RXF1C,Rx FIFO 1 Configuration" bitfld.long 0x00 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode" hexmask.long.byte 0x00 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" newline hexmask.long.byte 0x00 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x00 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" rgroup.long 0xB4++0x03 line.long 0x00 "RXF1S,Rx FIFO 1 Status" bitfld.long 0x00 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.." bitfld.long 0x00 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full" newline bitfld.long 0x00 16.--21. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" group.long 0xB8++0x03 line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge" bitfld.long 0x00 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBC++0x03 line.long 0x00 "RXESC,Rx Buffer and FIFO Element Size Configuration" bitfld.long 0x00 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" bitfld.long 0x00 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" newline bitfld.long 0x00 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" group.long 0xC0++0x03 line.long 0x00 "TXBC,Tx Buffer Configuration" bitfld.long 0x00 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx queue operation" bitfld.long 0x00 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 2.--15. 1. "TBSA,Tx Buffers Start Address" group.long 0xC4++0x03 line.long 0x00 "TXFQS,Tx FIFO/Queue Status" bitfld.long 0x00 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full" bitfld.long 0x00 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "TFGI,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC8++0x03 line.long 0x00 "TXESC,Tx Buffer Element Size Configuration" bitfld.long 0x00 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field" rgroup.long 0xCC++0x03 line.long 0x00 "TXBRP,Tx Buffer Request Pending" hexmask.long 0x00 0.--31. 1. "TRP,Transmission Request Pending" group.long 0xD0++0x03 line.long 0x00 "TXBAR,Tx Buffer Add Request" hexmask.long 0x00 0.--31. 1. "AR,Add Request" group.long 0xD4++0x03 line.long 0x00 "TXBCR,Tx Buffer Cancellation Request" hexmask.long 0x00 0.--31. 1. "CR,Cancellation Request" rgroup.long 0xD8++0x03 line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred" hexmask.long 0x00 0.--31. 1. "TO,Transmission Occurred" rgroup.long 0xDC++0x03 line.long 0x00 "TXBCF,Tx Buffer Cancellation Finished" hexmask.long 0x00 0.--31. 1. "TO,Cancellation Finished" group.long 0xE0++0x03 line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable" hexmask.long 0x00 0.--31. 1. "TIE,Transmission Interrupt Enable" group.long 0xE4++0x03 line.long 0x00 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable" hexmask.long 0x00 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" group.long 0xF0++0x03 line.long 0x00 "TXEFC,Tx Event FIFO Configuration" bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0xF4++0x03 line.long 0x00 "TXEFS,Tx Event FIFO Status" bitfld.long 0x00 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost also set after.." bitfld.long 0x00 24. "EFF,Event FIFO Full" "0: Tx event FIFO not full,1: Tx event FIFO full" newline bitfld.long 0x00 16.--21. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--5. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF8++0x03 line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge" bitfld.long 0x00 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x200++0x03 line.long 0x00 "MRBA,Message RAM Base Address" hexmask.long.word 0x00 16.--31. 1. "BA,Base Address for the message RAM in the chip memory map" group.long 0x400++0x03 line.long 0x00 "ETSCC,External Timestamp Counter Configuration" bitfld.long 0x00 31. "ETCE,External Timestamp Counter Enable" "0: External timestamp counter is disabled,1: External timestamp counter is enabled" hexmask.long.word 0x00 0.--10. 1. "ETCP,External Timestamp Prescaler Value" group.long 0x600++0x03 line.long 0x00 "ETSCV,External Timestamp Counter Value" hexmask.long.word 0x00 0.--15. 1. "ETSC,External Timestamp Counter" endif tree.end endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") tree "CDOG" base ad:0x400A1000 group.long 0x00++0x03 line.long 0x00 "CONTROL,The control fields which constitute CONTROL control all controllable attributes of the module including those of CONTROL itself" bitfld.long 0x00 30.--31. "DEBUG_HALT_CTRL,DEBUG_HALT control field" "0,1,2,3" bitfld.long 0x00 28.--29. "IRQ_PAUSE,IRQ pause control field" "0,1,2,3" bitfld.long 0x00 17.--19. "ADDRESS_CTRL,ADDRESS control field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "STATE_CTRL,STATE control field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11.--13. "CONTROL_CTRL,CONTROL control field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "SEQUENCE_CTRL,SEQUENCE control field" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5.--7. "MISCOMPARE_CTRL,MISCOMPARE control field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. "TIMEOUT_CTRL,TIMEOUT control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. "LOCK_CTRL,Lock control field" "0,1,2,3" group.long 0x04++0x03 line.long 0x00 "RELOAD,Instruction timer reload" hexmask.long 0x00 0.--31. 1. "RLOAD,Inst" group.long 0x08++0x03 line.long 0x00 "INSTRUCTION_TIMER,The INSTRUCTION TIMER itself" hexmask.long 0x00 0.--31. 1. "INSTIM,INSTRUCTION TIMER 32-bit value" group.long 0x0C++0x03 line.long 0x00 "SECURE_COUNTER,Also known as SEC_CNT" hexmask.long 0x00 0.--31. 1. "SECCNT,Secure Counter" rgroup.long 0x10++0x03 line.long 0x00 "STATUS,Status register (1 of 2)" bitfld.long 0x00 28.--31. "CURST,Current State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. "NUMILSEQF,Number of illegal sequence faults" hexmask.long.byte 0x00 8.--15. 1. "NUMMISCOMPF,Number of Miscompare Faults" hexmask.long.byte 0x00 0.--7. 1. "NUMTOF,Number of Timeout Faults" rgroup.long 0x14++0x03 line.long 0x00 "STATUS2,STATUS register (2 of 2)" hexmask.long.byte 0x00 16.--23. 1. "NUMILLA,Number of (illegal) address faults" hexmask.long.byte 0x00 8.--15. 1. "NUMILLSTF,Number (of) state faults" hexmask.long.byte 0x00 0.--7. 1. "NUMCNTF,Number (of) control faults" group.long 0x18++0x03 line.long 0x00 "FLAGS,Hardware flags" bitfld.long 0x00 16. "POR_FLAG,Power-on reset flag" "0,1" bitfld.long 0x00 5. "ADDR_FLAG,Address flag" "0,1" bitfld.long 0x00 4. "STATE_FLAG,State flag" "0,1" bitfld.long 0x00 3. "CNT_FLAG,Control (fault) flag" "0,1" bitfld.long 0x00 2. "SEQ_FLAG,Sequence flag" "0,1" bitfld.long 0x00 1. "MISCOM_FLAG,Miscompare flag" "0,1" newline bitfld.long 0x00 0. "TO_FLAG,Timeout flag" "0,1" group.long 0x1C++0x03 line.long 0x00 "PERSISTENT,Persistent (Ad. Hoc. quasi-NV) data storage" hexmask.long 0x00 0.--31. 1. "PERSIS,32 regs free for user SW to enjoy" wgroup.long 0x20++0x03 line.long 0x00 "START,Write address for issuing the START command" hexmask.long 0x00 0.--31. 1. "STRT,Address of start command access" wgroup.long 0x24++0x03 line.long 0x00 "STOP,Write address for issuing the STOP command" hexmask.long 0x00 0.--31. 1. "STP,Address of stop command access" wgroup.long 0x28++0x03 line.long 0x00 "RESTART,Write address for issuing the RESTART command" hexmask.long 0x00 0.--31. 1. "RSTRT,Write address for issuing the RESTART command" wgroup.long 0x2C++0x03 line.long 0x00 "ADD,Write address for issuing the ADD command" hexmask.long 0x00 0.--31. 1. "AD,Address of ADD command" wgroup.long 0x30++0x03 line.long 0x00 "ADD1,Write address for issuing the ADD1 command" hexmask.long 0x00 0.--31. 1. "AD1,Address of ADD1 command" wgroup.long 0x34++0x03 line.long 0x00 "ADD16,Write address for issuing the ADD16 command" hexmask.long 0x00 0.--31. 1. "AD16,Address of ADD16" wgroup.long 0x38++0x03 line.long 0x00 "ADD256,Write address for issuing the ADD16 command" hexmask.long 0x00 0.--31. 1. "AD256,Address of ADD256 command" wgroup.long 0x3C++0x03 line.long 0x00 "SUB,Write address for issuing the SUB command" hexmask.long 0x00 0.--31. 1. "S0B,Address of SUB command" wgroup.long 0x40++0x03 line.long 0x00 "SUB1,Write address for issuing the SUB1 command" hexmask.long 0x00 0.--31. 1. "S1B,Address of SUB1 command" wgroup.long 0x44++0x03 line.long 0x00 "SUB16,Write address for issuing the SUB16 command" hexmask.long 0x00 0.--31. 1. "SB16,Address of SUB16 command" wgroup.long 0x48++0x03 line.long 0x00 "SUB256,Write address for issuing the SUB256 command" hexmask.long 0x00 0.--31. 1. "SB256,Address of (you guessed it) SUB256 command" tree.end endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "CRC (CRC engine)" base ad:0x40095000 group.long 0x00++0x03 line.long 0x00 "MODE,CRC mode register" bitfld.long 0x00 5. "CMPL_SUM,CRC sum complement" "0: No 1's complement for CRC_SUM,1: 1's complement for CRC_SUM" bitfld.long 0x00 4. "BIT_RVS_SUM,CRC sum bit order" "0: No bit order reverse for CRC_SUM,1: Bit order reverse for CRC_SUM" newline bitfld.long 0x00 3. "CMPL_WR,Data complement" "0: No 1's complement for CRC_WR_DATA,1: 1's complement for CRC_WR_DATA" bitfld.long 0x00 2. "BIT_RVS_WR,Data bit order" "0: No bit order reverse for CRC_WR_DATA (per byte),1: Bit order reverse for CRC_WR_DATA (per byte)" newline bitfld.long 0x00 0.--1. "CRC_POLY,CRC polynomial: 1X = CRC-32 polynomial" "0: CRC-CCITT polynomial,1: CRC-16 polynomial,?..." group.long 0x04++0x03 line.long 0x00 "SEED,CRC seed register" hexmask.long 0x00 0.--31. 1. "CRC_SEED,A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes" rgroup.long 0x08++0x03 line.long 0x00 "SUM,CRC checksum register" hexmask.long 0x00 0.--31. 1. "CRC_SUM,The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes" wgroup.long 0x08++0x03 line.long 0x00 "WR_DATA,CRC data register" hexmask.long 0x00 0.--31. 1. "CRC_WR_DATA,Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process" tree.end endif tree "CTIMER (Counter/Timer)" tree "CTIMER0" base ad:0x40008000 group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" bitfld.long 0x00 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1" bitfld.long 0x00 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1" newline bitfld.long 0x00 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1" bitfld.long 0x00 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1" newline bitfld.long 0x00 3. "MR3INT,Interrupt flag for match channel 3" "0,1" bitfld.long 0x00 2. "MR2INT,Interrupt flag for match channel 2" "0,1" newline bitfld.long 0x00 1. "MR1INT,Interrupt flag for match channel 1" "0,1" bitfld.long 0x00 0. "MR0INT,Interrupt flag for match channel 0" "0,1" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take.." bitfld.long 0x00 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take.." newline bitfld.long 0x00 1. "CRST,Counter reset" "0: Disabled,1: ENABLED" bitfld.long 0x00 0. "CEN,Counter enable" "0: Disabled,1: Enabled" group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter" hexmask.long 0x00 0.--31. 1. "TCVAL,Timer counter value" group.long 0x0C++0x03 line.long 0x00 "PR,Prescale Register" hexmask.long 0x00 0.--31. 1. "PRVAL,Prescale reload value" group.long 0x10++0x03 line.long 0x00 "PC,Prescale Counter" hexmask.long 0x00 0.--31. 1. "PCVAL,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 27. "MR3RL,Reload MR3" "0: Disabled,1: MR3RL_1" bitfld.long 0x00 26. "MR2RL,Reload MR2" "0: Disabled,1: MR2RL_1" newline bitfld.long 0x00 25. "MR1RL,Reload MR1" "0: Disabled,1: MR1RL_1" bitfld.long 0x00 24. "MR0RL,Reload MR0" "0: Disabled,1: MR0RL_1" newline bitfld.long 0x00 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled" newline bitfld.long 0x00 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled" bitfld.long 0x00 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x18)++0x03 line.long 0x00 "MR[$1],Match Register $1" hexmask.long 0x00 0.--31. 1. "MATCH,Timer counter match value" repeat.end group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" bitfld.long 0x00 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0: Disabled,1: CAP3I_1" bitfld.long 0x00 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC" "0: CAP3FE_0,1: CAP3FE_1" newline bitfld.long 0x00 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC" "0: CAP3RE_0,1: CAP3RE_1" bitfld.long 0x00 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0: Disabled,1: CAP2I_1" newline bitfld.long 0x00 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC" "0: CAP2FE_0,1: CAP2FE_1" bitfld.long 0x00 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC" "0: CAP2RE_0,1: CAP2RE_1" newline bitfld.long 0x00 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0: Disabled,1: CAP1I_1" bitfld.long 0x00 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC" "0: CAP1FE_0,1: CAP1FE_1" newline bitfld.long 0x00 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC" "0: CAP1RE_0,1: CAP1RE_1" bitfld.long 0x00 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0: Disabled,1: CAPOI_1" newline bitfld.long 0x00 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC" "0: CAP0FE_0,1: CAPOFE_1" bitfld.long 0x00 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC" "0: CAP0RE_0,1: CAPORE_1" repeat 4. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0x2C)++0x03 line.long 0x00 "CR[$1],Capture Register $1" hexmask.long 0x00 0.--31. 1. "CAP,Timer counter capture value" repeat.end group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. "EMC3,External Match Control 3" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 8.--9. "EMC2,External Match Control 2" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 6.--7. "EMC1,External Match Control 1" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 4.--5. "EMC0,External Match Control 0" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 3. "EM3,External Match 3" "0,1" bitfld.long 0x00 2. "EM2,External Match 2" "0,1" newline bitfld.long 0x00 1. "EM1,External Match 1" "0,1" bitfld.long 0x00 0. "EM0,External Match 0" "0,1" group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,?..." bitfld.long 0x00 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1" newline bitfld.long 0x00 2.--3. "CINSEL,Count Input Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3" bitfld.long 0x00 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting" "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge" group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control Register" bitfld.long 0x00 3. "PWMEN3,PWM mode enable for channel 3" "0: Match,1: PWM" bitfld.long 0x00 2. "PWMEN2,PWM mode enable for channel 2" "0: Match,1: PWM" newline bitfld.long 0x00 1. "PWMEN1,PWM mode enable for channel 1" "0: Match,1: PWM" bitfld.long 0x00 0. "PWMEN0,PWM mode enable for channel 0" "0: Match,1: PWM" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x78)++0x03 line.long 0x00 "MSR[$1],Match Shadow Register $1" hexmask.long 0x00 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value" repeat.end tree.end tree "CTIMER1" base ad:0x40009000 group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" bitfld.long 0x00 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1" bitfld.long 0x00 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1" newline bitfld.long 0x00 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1" bitfld.long 0x00 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1" newline bitfld.long 0x00 3. "MR3INT,Interrupt flag for match channel 3" "0,1" bitfld.long 0x00 2. "MR2INT,Interrupt flag for match channel 2" "0,1" newline bitfld.long 0x00 1. "MR1INT,Interrupt flag for match channel 1" "0,1" bitfld.long 0x00 0. "MR0INT,Interrupt flag for match channel 0" "0,1" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take.." bitfld.long 0x00 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take.." newline bitfld.long 0x00 1. "CRST,Counter reset" "0: Disabled,1: ENABLED" bitfld.long 0x00 0. "CEN,Counter enable" "0: Disabled,1: Enabled" group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter" hexmask.long 0x00 0.--31. 1. "TCVAL,Timer counter value" group.long 0x0C++0x03 line.long 0x00 "PR,Prescale Register" hexmask.long 0x00 0.--31. 1. "PRVAL,Prescale reload value" group.long 0x10++0x03 line.long 0x00 "PC,Prescale Counter" hexmask.long 0x00 0.--31. 1. "PCVAL,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 27. "MR3RL,Reload MR3" "0: Disabled,1: MR3RL_1" bitfld.long 0x00 26. "MR2RL,Reload MR2" "0: Disabled,1: MR2RL_1" newline bitfld.long 0x00 25. "MR1RL,Reload MR1" "0: Disabled,1: MR1RL_1" bitfld.long 0x00 24. "MR0RL,Reload MR0" "0: Disabled,1: MR0RL_1" newline bitfld.long 0x00 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled" newline bitfld.long 0x00 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled" bitfld.long 0x00 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x18)++0x03 line.long 0x00 "MR[$1],Match Register $1" hexmask.long 0x00 0.--31. 1. "MATCH,Timer counter match value" repeat.end group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" bitfld.long 0x00 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0: Disabled,1: CAP3I_1" bitfld.long 0x00 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC" "0: CAP3FE_0,1: CAP3FE_1" newline bitfld.long 0x00 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC" "0: CAP3RE_0,1: CAP3RE_1" bitfld.long 0x00 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0: Disabled,1: CAP2I_1" newline bitfld.long 0x00 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC" "0: CAP2FE_0,1: CAP2FE_1" bitfld.long 0x00 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC" "0: CAP2RE_0,1: CAP2RE_1" newline bitfld.long 0x00 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0: Disabled,1: CAP1I_1" bitfld.long 0x00 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC" "0: CAP1FE_0,1: CAP1FE_1" newline bitfld.long 0x00 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC" "0: CAP1RE_0,1: CAP1RE_1" bitfld.long 0x00 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0: Disabled,1: CAPOI_1" newline bitfld.long 0x00 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC" "0: CAP0FE_0,1: CAPOFE_1" bitfld.long 0x00 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC" "0: CAP0RE_0,1: CAPORE_1" repeat 4. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0x2C)++0x03 line.long 0x00 "CR[$1],Capture Register $1" hexmask.long 0x00 0.--31. 1. "CAP,Timer counter capture value" repeat.end group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. "EMC3,External Match Control 3" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 8.--9. "EMC2,External Match Control 2" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 6.--7. "EMC1,External Match Control 1" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 4.--5. "EMC0,External Match Control 0" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 3. "EM3,External Match 3" "0,1" bitfld.long 0x00 2. "EM2,External Match 2" "0,1" newline bitfld.long 0x00 1. "EM1,External Match 1" "0,1" bitfld.long 0x00 0. "EM0,External Match 0" "0,1" group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,?..." bitfld.long 0x00 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1" newline bitfld.long 0x00 2.--3. "CINSEL,Count Input Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3" bitfld.long 0x00 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting" "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge" group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control Register" bitfld.long 0x00 3. "PWMEN3,PWM mode enable for channel 3" "0: Match,1: PWM" bitfld.long 0x00 2. "PWMEN2,PWM mode enable for channel 2" "0: Match,1: PWM" newline bitfld.long 0x00 1. "PWMEN1,PWM mode enable for channel 1" "0: Match,1: PWM" bitfld.long 0x00 0. "PWMEN0,PWM mode enable for channel 0" "0: Match,1: PWM" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x78)++0x03 line.long 0x00 "MSR[$1],Match Shadow Register $1" hexmask.long 0x00 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value" repeat.end tree.end tree "CTIMER2" base ad:0x40028000 group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" bitfld.long 0x00 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1" bitfld.long 0x00 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1" newline bitfld.long 0x00 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1" bitfld.long 0x00 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1" newline bitfld.long 0x00 3. "MR3INT,Interrupt flag for match channel 3" "0,1" bitfld.long 0x00 2. "MR2INT,Interrupt flag for match channel 2" "0,1" newline bitfld.long 0x00 1. "MR1INT,Interrupt flag for match channel 1" "0,1" bitfld.long 0x00 0. "MR0INT,Interrupt flag for match channel 0" "0,1" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take.." bitfld.long 0x00 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take.." newline bitfld.long 0x00 1. "CRST,Counter reset" "0: Disabled,1: ENABLED" bitfld.long 0x00 0. "CEN,Counter enable" "0: Disabled,1: Enabled" group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter" hexmask.long 0x00 0.--31. 1. "TCVAL,Timer counter value" group.long 0x0C++0x03 line.long 0x00 "PR,Prescale Register" hexmask.long 0x00 0.--31. 1. "PRVAL,Prescale reload value" group.long 0x10++0x03 line.long 0x00 "PC,Prescale Counter" hexmask.long 0x00 0.--31. 1. "PCVAL,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 27. "MR3RL,Reload MR3" "0: Disabled,1: MR3RL_1" bitfld.long 0x00 26. "MR2RL,Reload MR2" "0: Disabled,1: MR2RL_1" newline bitfld.long 0x00 25. "MR1RL,Reload MR1" "0: Disabled,1: MR1RL_1" bitfld.long 0x00 24. "MR0RL,Reload MR0" "0: Disabled,1: MR0RL_1" newline bitfld.long 0x00 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled" newline bitfld.long 0x00 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled" bitfld.long 0x00 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x18)++0x03 line.long 0x00 "MR[$1],Match Register $1" hexmask.long 0x00 0.--31. 1. "MATCH,Timer counter match value" repeat.end group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" bitfld.long 0x00 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0: Disabled,1: CAP3I_1" bitfld.long 0x00 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC" "0: CAP3FE_0,1: CAP3FE_1" newline bitfld.long 0x00 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC" "0: CAP3RE_0,1: CAP3RE_1" bitfld.long 0x00 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0: Disabled,1: CAP2I_1" newline bitfld.long 0x00 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC" "0: CAP2FE_0,1: CAP2FE_1" bitfld.long 0x00 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC" "0: CAP2RE_0,1: CAP2RE_1" newline bitfld.long 0x00 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0: Disabled,1: CAP1I_1" bitfld.long 0x00 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC" "0: CAP1FE_0,1: CAP1FE_1" newline bitfld.long 0x00 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC" "0: CAP1RE_0,1: CAP1RE_1" bitfld.long 0x00 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0: Disabled,1: CAPOI_1" newline bitfld.long 0x00 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC" "0: CAP0FE_0,1: CAPOFE_1" bitfld.long 0x00 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC" "0: CAP0RE_0,1: CAPORE_1" repeat 4. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0x2C)++0x03 line.long 0x00 "CR[$1],Capture Register $1" hexmask.long 0x00 0.--31. 1. "CAP,Timer counter capture value" repeat.end group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. "EMC3,External Match Control 3" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 8.--9. "EMC2,External Match Control 2" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 6.--7. "EMC1,External Match Control 1" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 4.--5. "EMC0,External Match Control 0" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 3. "EM3,External Match 3" "0,1" bitfld.long 0x00 2. "EM2,External Match 2" "0,1" newline bitfld.long 0x00 1. "EM1,External Match 1" "0,1" bitfld.long 0x00 0. "EM0,External Match 0" "0,1" group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,?..." bitfld.long 0x00 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1" newline bitfld.long 0x00 2.--3. "CINSEL,Count Input Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3" bitfld.long 0x00 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting" "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge" group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control Register" bitfld.long 0x00 3. "PWMEN3,PWM mode enable for channel 3" "0: Match,1: PWM" bitfld.long 0x00 2. "PWMEN2,PWM mode enable for channel 2" "0: Match,1: PWM" newline bitfld.long 0x00 1. "PWMEN1,PWM mode enable for channel 1" "0: Match,1: PWM" bitfld.long 0x00 0. "PWMEN0,PWM mode enable for channel 0" "0: Match,1: PWM" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x78)++0x03 line.long 0x00 "MSR[$1],Match Shadow Register $1" hexmask.long 0x00 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value" repeat.end tree.end tree "CTIMER3" base ad:0x40029000 group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" bitfld.long 0x00 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1" bitfld.long 0x00 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1" newline bitfld.long 0x00 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1" bitfld.long 0x00 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1" newline bitfld.long 0x00 3. "MR3INT,Interrupt flag for match channel 3" "0,1" bitfld.long 0x00 2. "MR2INT,Interrupt flag for match channel 2" "0,1" newline bitfld.long 0x00 1. "MR1INT,Interrupt flag for match channel 1" "0,1" bitfld.long 0x00 0. "MR0INT,Interrupt flag for match channel 0" "0,1" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take.." bitfld.long 0x00 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take.." newline bitfld.long 0x00 1. "CRST,Counter reset" "0: Disabled,1: ENABLED" bitfld.long 0x00 0. "CEN,Counter enable" "0: Disabled,1: Enabled" group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter" hexmask.long 0x00 0.--31. 1. "TCVAL,Timer counter value" group.long 0x0C++0x03 line.long 0x00 "PR,Prescale Register" hexmask.long 0x00 0.--31. 1. "PRVAL,Prescale reload value" group.long 0x10++0x03 line.long 0x00 "PC,Prescale Counter" hexmask.long 0x00 0.--31. 1. "PCVAL,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 27. "MR3RL,Reload MR3" "0: Disabled,1: MR3RL_1" bitfld.long 0x00 26. "MR2RL,Reload MR2" "0: Disabled,1: MR2RL_1" newline bitfld.long 0x00 25. "MR1RL,Reload MR1" "0: Disabled,1: MR1RL_1" bitfld.long 0x00 24. "MR0RL,Reload MR0" "0: Disabled,1: MR0RL_1" newline bitfld.long 0x00 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled" newline bitfld.long 0x00 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled" bitfld.long 0x00 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x18)++0x03 line.long 0x00 "MR[$1],Match Register $1" hexmask.long 0x00 0.--31. 1. "MATCH,Timer counter match value" repeat.end group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" bitfld.long 0x00 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0: Disabled,1: CAP3I_1" bitfld.long 0x00 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC" "0: CAP3FE_0,1: CAP3FE_1" newline bitfld.long 0x00 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC" "0: CAP3RE_0,1: CAP3RE_1" bitfld.long 0x00 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0: Disabled,1: CAP2I_1" newline bitfld.long 0x00 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC" "0: CAP2FE_0,1: CAP2FE_1" bitfld.long 0x00 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC" "0: CAP2RE_0,1: CAP2RE_1" newline bitfld.long 0x00 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0: Disabled,1: CAP1I_1" bitfld.long 0x00 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC" "0: CAP1FE_0,1: CAP1FE_1" newline bitfld.long 0x00 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC" "0: CAP1RE_0,1: CAP1RE_1" bitfld.long 0x00 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0: Disabled,1: CAPOI_1" newline bitfld.long 0x00 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC" "0: CAP0FE_0,1: CAPOFE_1" bitfld.long 0x00 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC" "0: CAP0RE_0,1: CAPORE_1" repeat 4. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0x2C)++0x03 line.long 0x00 "CR[$1],Capture Register $1" hexmask.long 0x00 0.--31. 1. "CAP,Timer counter capture value" repeat.end group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. "EMC3,External Match Control 3" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 8.--9. "EMC2,External Match Control 2" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 6.--7. "EMC1,External Match Control 1" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 4.--5. "EMC0,External Match Control 0" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 3. "EM3,External Match 3" "0,1" bitfld.long 0x00 2. "EM2,External Match 2" "0,1" newline bitfld.long 0x00 1. "EM1,External Match 1" "0,1" bitfld.long 0x00 0. "EM0,External Match 0" "0,1" group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,?..." bitfld.long 0x00 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1" newline bitfld.long 0x00 2.--3. "CINSEL,Count Input Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3" bitfld.long 0x00 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting" "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge" group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control Register" bitfld.long 0x00 3. "PWMEN3,PWM mode enable for channel 3" "0: Match,1: PWM" bitfld.long 0x00 2. "PWMEN2,PWM mode enable for channel 2" "0: Match,1: PWM" newline bitfld.long 0x00 1. "PWMEN1,PWM mode enable for channel 1" "0: Match,1: PWM" bitfld.long 0x00 0. "PWMEN0,PWM mode enable for channel 0" "0: Match,1: PWM" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x78)++0x03 line.long 0x00 "MSR[$1],Match Shadow Register $1" hexmask.long 0x00 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value" repeat.end tree.end tree "CTIMER4" base ad:0x4002A000 group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" bitfld.long 0x00 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1" bitfld.long 0x00 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1" newline bitfld.long 0x00 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1" bitfld.long 0x00 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1" newline bitfld.long 0x00 3. "MR3INT,Interrupt flag for match channel 3" "0,1" bitfld.long 0x00 2. "MR2INT,Interrupt flag for match channel 2" "0,1" newline bitfld.long 0x00 1. "MR1INT,Interrupt flag for match channel 1" "0,1" bitfld.long 0x00 0. "MR0INT,Interrupt flag for match channel 0" "0,1" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 5. "ATCEN,Allow Trigger Count Enable" "0: Not allowed,1: Allow input trigger_enable=1 action to take.." bitfld.long 0x00 4. "AGCEN,Allow Global Count Enable" "0: Not allowed,1: Allow input global_enable=1 action to take.." newline bitfld.long 0x00 1. "CRST,Counter reset" "0: Disabled,1: ENABLED" bitfld.long 0x00 0. "CEN,Counter enable" "0: Disabled,1: Enabled" group.long 0x08++0x03 line.long 0x00 "TC,Timer Counter" hexmask.long 0x00 0.--31. 1. "TCVAL,Timer counter value" group.long 0x0C++0x03 line.long 0x00 "PR,Prescale Register" hexmask.long 0x00 0.--31. 1. "PRVAL,Prescale reload value" group.long 0x10++0x03 line.long 0x00 "PC,Prescale Counter" hexmask.long 0x00 0.--31. 1. "PCVAL,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 27. "MR3RL,Reload MR3" "0: Disabled,1: MR3RL_1" bitfld.long 0x00 26. "MR2RL,Reload MR2" "0: Disabled,1: MR2RL_1" newline bitfld.long 0x00 25. "MR1RL,Reload MR1" "0: Disabled,1: MR1RL_1" bitfld.long 0x00 24. "MR0RL,Reload MR0" "0: Disabled,1: MR0RL_1" newline bitfld.long 0x00 11. "MR3S,Stop on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 10. "MR3R,Reset on MR3" "0: Disabled,1: Enabled" newline bitfld.long 0x00 9. "MR3I,Interrupt on MR3" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "MR2S,Stop on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MR2R,Reset on MR2" "0: Disabled,1: Enabled" bitfld.long 0x00 6. "MR2I,Interrupt on MR2" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "MR1S,Stop on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MR1R,Reset on MR1" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "MR1I,Interrupt on MR1" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MR0S,Stop on MR0" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "MR0R,Reset on MR0" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MR0I,Interrupt on MR0" "0: Disabled,1: Enabled" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x18)++0x03 line.long 0x00 "MR[$1],Match Register $1" hexmask.long 0x00 0.--31. 1. "MATCH,Timer counter match value" repeat.end group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" bitfld.long 0x00 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0: Disabled,1: CAP3I_1" bitfld.long 0x00 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC" "0: CAP3FE_0,1: CAP3FE_1" newline bitfld.long 0x00 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC" "0: CAP3RE_0,1: CAP3RE_1" bitfld.long 0x00 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0: Disabled,1: CAP2I_1" newline bitfld.long 0x00 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC" "0: CAP2FE_0,1: CAP2FE_1" bitfld.long 0x00 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC" "0: CAP2RE_0,1: CAP2RE_1" newline bitfld.long 0x00 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0: Disabled,1: CAP1I_1" bitfld.long 0x00 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC" "0: CAP1FE_0,1: CAP1FE_1" newline bitfld.long 0x00 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC" "0: CAP1RE_0,1: CAP1RE_1" bitfld.long 0x00 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0: Disabled,1: CAPOI_1" newline bitfld.long 0x00 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC" "0: CAP0FE_0,1: CAPOFE_1" bitfld.long 0x00 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC" "0: CAP0RE_0,1: CAPORE_1" repeat 4. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0x2C)++0x03 line.long 0x00 "CR[$1],Capture Register $1" hexmask.long 0x00 0.--31. 1. "CAP,Timer counter capture value" repeat.end group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. "EMC3,External Match Control 3" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 8.--9. "EMC2,External Match Control 2" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 6.--7. "EMC1,External Match Control 1" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" bitfld.long 0x00 4.--5. "EMC0,External Match Control 0" "0: DO_NOTHING,1: Clear,2: Set,3: Toggle" newline bitfld.long 0x00 3. "EM3,External Match 3" "0,1" bitfld.long 0x00 2. "EM2,External Match 2" "0,1" newline bitfld.long 0x00 1. "EM1,External Match 1" "0,1" bitfld.long 0x00 0. "EM0,External Match 0" "0,1" group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" bitfld.long 0x00 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,?..." bitfld.long 0x00 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1" newline bitfld.long 0x00 2.--3. "CINSEL,Count Input Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3" bitfld.long 0x00 0.--1. "CTMODE,The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting" "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge" group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control Register" bitfld.long 0x00 3. "PWMEN3,PWM mode enable for channel 3" "0: Match,1: PWM" bitfld.long 0x00 2. "PWMEN2,PWM mode enable for channel 2" "0: Match,1: PWM" newline bitfld.long 0x00 1. "PWMEN1,PWM mode enable for channel 1" "0: Match,1: PWM" bitfld.long 0x00 0. "PWMEN0,PWM mode enable for channel 0" "0: Match,1: PWM" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x78)++0x03 line.long 0x00 "MSR[$1],Match Shadow Register $1" hexmask.long 0x00 0.--31. 1. "MATCH_SHADOW,Timer counter match shadow value" repeat.end tree.end tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "DAC" repeat 3. (list 0. 1. 2.) (list ad:0x400B2000 ad:0x400B6000 ad:0x400B9000) tree "DAC$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "VERID,Version Identifier Register" hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major version number" hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor version number" newline hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number" rgroup.long 0x04++0x03 line.long 0x00 "PARAM,Parameter Register" bitfld.long 0x00 0.--2. "FIFOSZ,FIFO size" "?,1: FIFO depth is 4,2: FIFO depth is 8,3: FIFO depth is 16,4: FIFO depth is 32,5: FIFO depth is 64,6: FIFO depth is 128,7: FIFO depth is 256" group.long 0x08++0x03 line.long 0x00 "DATA,Data Register" hexmask.long.word 0x00 0.--11. 1. "DATA,FIFO entry or Buffer entry" group.long 0x0C++0x03 line.long 0x00 "GCR,Global Control Register" bitfld.long 0x00 23. "BUF_SPD_CTRL,OPAMP as buffer speed control signal" "0: Lower low power mode,1: Low power mode" bitfld.long 0x00 21. "IREF_ZTC_EXT_SEL,Internal ZTC Current Reference Select" "0: Internal ZTC Current Reference not selected,1: Internal ZTC Current Reference selected" newline bitfld.long 0x00 20. "IREF_PTAT_EXT_SEL,Internal PTAT Current Reference Select" "0: Internal PTAT Current Reference not selected,1: Internal PTAT Current Reference selected" bitfld.long 0x00 17. "BUF_EN,Buffer Enable" "0: Opamp is not used as buffer,1: Opamp is used as buffer" newline bitfld.long 0x00 8.--11. "LATCH_CYC,RCLK cycles before data latch" "0: Sync time is 1 RCLK cycle RCLK <= 25MHz,1: Sync time is 2 RCLK cycles 25MHz < RCLK <=..,2: Sync time is 3 RCLK cycles 50MHz < RCLK <=..,3: Sync time is 4 RCLK cycles 75MHz < RCLK <=..,4: Sync time is 5 RCLK cycles 100MHz < RCLK <=..,5: Sync time is 6 RCLK cycles 125MHz < RCLK <=..,6: Sync time is 7 RCLK cycles 150MHz < RCLK <=..,7: Sync time is 8 RCLK cycles 175MHz < RCLK <=..,8: Sync time is 9 RCLK cycles 200MHz < RCLK <=..,9: Sync time is 10 RCLK cycles 225MHz < RCLK <=..,10: Sync time is 11 RCLK cycles 250MHz < RCLK <=..,11: Sync time is 12 RCLK cycles 275MHz < RCLK <=..,12: Sync time is 13 RCLK cycles 300MHz < RCLK <=..,13: Sync time is 14 RCLK cycles 325MHz < RCLK <=..,14: Sync time is 15 RCLK cycles 350MHz < RCLK <=..,15: Sync time is 16 RCLK cycles 375MHz < RCLK <=.." bitfld.long 0x00 6. "PTGEN,DAC periodic trigger mode enable" "0: DAC periodic trigger mode is disabled,1: DAC periodic trigger mode is enabled" newline bitfld.long 0x00 5. "TRGSEL,DAC Trigger Select" "0: The DAC hardware trigger is selected,1: The DAC software trigger is selected" bitfld.long 0x00 4. "SWMD,Swing Back Mode" "0: Swing back mode disable,1: Swing back mode enable" newline bitfld.long 0x00 3. "FIFOEN,FIFO Enable" "0: FIFO mode is disabled and buffer mode is..,1: FIFO mode is enabled" bitfld.long 0x00 1.--2. "DACRFS,DAC Reference Select" "0: The DAC selects VREFH1 as the reference voltage,1: The DAC selects VREFH2 as the reference voltage,2: The DAC selects VREFH3 as the reference voltage,?..." newline bitfld.long 0x00 0. "DACEN,DAC Enable" "0: The DAC system is disabled,1: The DAC system is enabled" group.long 0x10++0x03 line.long 0x00 "FCR,DAC FIFO Control Register" bitfld.long 0x00 0.--3. "WML,Watermark Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x14++0x03 line.long 0x00 "FPR,DAC FIFO Pointer Register" bitfld.long 0x00 16.--19. "FIFO_WPT,FIFO Write Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "FIFO_RPT,FIFO Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x03 line.long 0x00 "FSR,FIFO Status Register" eventfld.long 0x00 8. "PTGCOCO,Period trigger mode conversion complete flag" "0: PTG mode conversion is not completed or not..,1: PTG mode conversion is completed" eventfld.long 0x00 7. "UF,FIFO Underflow Flag" "0: No underflow has occurred since the last time..,1: At least one trigger underflow has occurred.." newline eventfld.long 0x00 6. "OF,FIFO Overflow Flag" "0: No overflow has occurred since the last time..,1: At least one FIFO overflow has occurred since.." eventfld.long 0x00 3. "SWBK,Swing Back One Cycle Complete Flag" "0: No swing back cycle has completed since the..,1: At least one swing back cycle has occurred.." newline rbitfld.long 0x00 2. "WM,FIFO Watermark Status Flag" "0: Data in FIFO is more than watermark level,1: Data in FIFO is less than or equal to.." rbitfld.long 0x00 1. "EMPTY,FIFO Empty Flag" "0: FIFO is not empty,1: FIFO is empty" newline rbitfld.long 0x00 0. "FULL,FIFO Full Flag" "0: FIFO is not full,1: FIFO is full" group.long 0x1C++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 8. "PTGCOCO_IE,PTG mode conversion complete interrupt enable" "0: PTG mode conversion complete interrupt is..,1: PTG mode conversion complete interrupt is.." bitfld.long 0x00 7. "UF_IE,FIFO Underflow Interrupt Enable" "0: Underflow interrupt is disabled,1: Underflow interrupt is enabled" newline bitfld.long 0x00 6. "OF_IE,FIFO Overflow Interrupt Enable" "0: Overflow interrupt is disabled,1: Overflow interrupt is enabled" bitfld.long 0x00 3. "SWBK_IE,Swing back One Cycle Complete Interrupt Enable" "0: Swing back one time complete interrupt is..,1: Swing back one time complete interrupt is.." newline bitfld.long 0x00 2. "WM_IE,FIFO Watermark Interrupt Enable" "0: Watermark interrupt is disabled,1: Watermark interrupt is enabled" bitfld.long 0x00 1. "EMPTY_IE,FIFO Empty Interrupt Enable" "0: FIFO Empty interrupt is disabled,1: FIFO Empty interrupt is enabled" newline bitfld.long 0x00 0. "FULL_IE,FIFO Full Interrupt Enable" "0: FIFO Full interrupt is disabled,1: FIFO Full interrupt is enabled" group.long 0x20++0x03 line.long 0x00 "DER,DMA Enable Register" bitfld.long 0x00 2. "WM_DMAEN,FIFO Watermark DMA Enable" "0: Watermark DMA request is disabled,1: Watermark DMA request is enabled" bitfld.long 0x00 1. "EMPTY_DMAEN,FIFO Empty DMA Enable" "0: FIFO Empty DMA request is disabled,1: FIFO Empty DMA request is enabled" group.long 0x24++0x03 line.long 0x00 "RCR,Reset Control Register" bitfld.long 0x00 1. "FIFORST,FIFO Reset" "0: NO_EFFECT,1: FIFO_RESET" bitfld.long 0x00 0. "SWRST,Software Reset" "0: NO_EFFECT,1: SOFTWARE_RESET" group.long 0x28++0x03 line.long 0x00 "TCR,Trigger Control Register" bitfld.long 0x00 0. "SWTRG,Software Trigger" "0: The DAC soft trigger is not valid,1: The DAC soft trigger is valid" group.long 0x2C++0x03 line.long 0x00 "PCR,Periodic Trigger Control Register" hexmask.long.word 0x00 16.--31. 1. "PTG_PERIOD,Periodic trigger period width" hexmask.long.word 0x00 0.--15. 1. "PTG_NUM,Periodic trigger number" tree.end repeat.end tree.end endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "DBGMAILBOX (MCU Debugger Mailbox)" base ad:0x4009C000 group.long 0x00++0x03 line.long 0x00 "CSW,CRC mode register" bitfld.long 0x00 5. "CHIP_RESET_REQ,Write only bit" "0,1" bitfld.long 0x00 4. "SOFT_RESET,Soft Reset for DM (write-only from AHB not readable and selfclearing)" "0,1" bitfld.long 0x00 3. "AHB_OR_ERR,AHB overrun Error (Return value overwritten by ROM)" "0,1" bitfld.long 0x00 2. "DBG_OR_ERR,Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)" "0,1" bitfld.long 0x00 1. "REQ_PENDING,Request is pending from debugger (i.e unread value in REQUEST)" "0,1" bitfld.long 0x00 0. "RESYNCH_REQ,Debugger will set this bit to 1 to request a resynchronrisation" "0,1" group.long 0x04++0x03 line.long 0x00 "REQUEST,CRC seed register" hexmask.long 0x00 0.--31. 1. "REQ,Request Value" group.long 0x08++0x03 line.long 0x00 "RETURN,Return value from ROM" hexmask.long 0x00 0.--31. 1. "RET,The Return value from ROM" rgroup.long 0xFC++0x03 line.long 0x00 "ID,Identification register" hexmask.long 0x00 0.--31. 1. "ID,Identification value" tree.end endif sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "DEBUGGER_MAILBOX (Debug)" base ad:0x4009C000 group.long 0x00++0x03 line.long 0x00 "CSW,Command and status word" bitfld.long 0x00 5. "CHIP_RESET_REQ,Chip Reset Request" "0,1" bitfld.long 0x00 4. "SOFT_RESET,Soft Reset" "0,1" newline bitfld.long 0x00 3. "AHB_OR_ERR,AHB Overrun Error" "0: No AHB Overrun Error,1: AHB Overrun Error" bitfld.long 0x00 2. "DBG_OR_ERR,Debug Overrun Error" "0: No Debug Overrun error,1: Debug Overrun Error" newline bitfld.long 0x00 1. "REQ_PENDING,Request Pending" "0: NO_REQUEST_PENDING,1: Request for Re-synchronization Pending" bitfld.long 0x00 0. "RESYNCH_REQ,Re-synchronization Request" "0: NO_REQUEST,1: Request for re-synchronization" group.long 0x04++0x03 line.long 0x00 "REQUEST,Request Value" hexmask.long 0x00 0.--31. 1. "REQUEST,Request Value" group.long 0x08++0x03 line.long 0x00 "RETURN,Return Value" hexmask.long 0x00 0.--31. 1. "RET,Return Value" rgroup.long 0xFC++0x03 line.long 0x00 "ID,Identification" hexmask.long 0x00 0.--31. 1. "ID,Identification Value" tree.end endif tree "DMA (DMA0 controller)" sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "DMA0" base ad:0x40082000 group.long 0x00++0x03 line.long 0x00 "CTRL,DMA control" bitfld.long 0x00 0. "ENABLE,DMA controller master enable" "0: DMA controller is disabled,1: Enabled" rgroup.long 0x04++0x03 line.long 0x00 "INTSTAT,Interrupt status" bitfld.long 0x00 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending" "0: No error interrupts are pending,1: At least one error interrupt is pending" bitfld.long 0x00 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: No enabled interrupts are pending,1: At least one enabled interrupt is pending" group.long 0x08++0x03 line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table" hexmask.long.tbyte 0x00 10.--31. 1. "OFFSET,Offset" group.long 0x20++0x03 line.long 0x00 "ENABLESET0,Channel Enable read and set for all DMA channels" bitfld.long 0x00 31. "ENABLE31,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 30. "ENABLE30,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 29. "ENABLE29,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 28. "ENABLE28,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 27. "ENABLE27,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 26. "ENABLE26,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 25. "ENABLE25,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 24. "ENABLE24,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 23. "ENABLE23,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 22. "ENABLE22,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 21. "ENABLE21,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 20. "ENABLE20,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 19. "ENABLE19,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 18. "ENABLE18,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 17. "ENABLE17,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 16. "ENABLE16,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 15. "ENABLE15,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 14. "ENABLE14,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 13. "ENABLE13,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 12. "ENABLE12,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 11. "ENABLE11,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 10. "ENABLE10,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 9. "ENABLE9,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 8. "ENABLE8,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 7. "ENABLE7,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 6. "ENABLE6,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 5. "ENABLE5,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 4. "ENABLE4,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 3. "ENABLE3,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 2. "ENABLE2,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 1. "ENABLE1,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 0. "ENABLE0,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" group.long 0x24++0x03 line.long 0x00 "ENABLESET1,Channel Enable read and set for all DMA channels" bitfld.long 0x00 19. "ENABLE51,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 18. "ENABLE50,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 17. "ENABLE49,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 16. "ENABLE48,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 15. "ENABLE47,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 14. "ENABLE46,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 13. "ENABLE45,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 12. "ENABLE44,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 11. "ENABLE43,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 10. "ENABLE42,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 9. "ENABLE41,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 8. "ENABLE40,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 7. "ENABLE39,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 6. "ENABLE38,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 5. "ENABLE37,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 4. "ENABLE36,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 3. "ENABLE35,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 2. "ENABLE34,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 1. "ENABLE33,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 0. "ENABLE32,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" group.long 0x28++0x03 line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels" eventfld.long 0x00 31. "CLR31,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 30. "CLR30,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 29. "CLR29,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 28. "CLR28,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 27. "CLR27,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 26. "CLR26,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 25. "CLR25,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 24. "CLR24,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 23. "CLR23,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 22. "CLR22,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 21. "CLR21,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 20. "CLR20,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 19. "CLR19,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 18. "CLR18,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 17. "CLR17,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 16. "CLR16,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 15. "CLR15,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 14. "CLR14,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 13. "CLR13,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 12. "CLR12,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 11. "CLR11,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 10. "CLR10,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 9. "CLR9,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 8. "CLR8,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 7. "CLR7,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 6. "CLR6,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 5. "CLR5,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 4. "CLR4,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 3. "CLR3,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 2. "CLR2,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 1. "CLR1,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 0. "CLR0,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" group.long 0x2C++0x03 line.long 0x00 "ENABLECLR1,Channel Enable Clear for all DMA channels" eventfld.long 0x00 19. "CLR51,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 18. "CLR50,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 17. "CLR49,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 16. "CLR48,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 15. "CLR47,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 14. "CLR46,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 13. "CLR45,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 12. "CLR44,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 11. "CLR43,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 10. "CLR42,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 9. "CLR41,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 8. "CLR40,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 7. "CLR39,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 6. "CLR38,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 5. "CLR37,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 4. "CLR36,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 3. "CLR35,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 2. "CLR34,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 1. "CLR33,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 0. "CLR32,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" rgroup.long 0x30++0x03 line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels" bitfld.long 0x00 31. "ACTIVE31,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 30. "ACTIVE30,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 29. "ACTIVE29,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 28. "ACTIVE28,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 27. "ACTIVE27,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 26. "ACTIVE26,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 25. "ACTIVE25,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 24. "ACTIVE24,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 23. "ACTIVE23,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 22. "ACTIVE22,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 21. "ACTIVE21,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 20. "ACTIVE20,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 19. "ACTIVE19,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 18. "ACTIVE18,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 17. "ACTIVE17,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 16. "ACTIVE16,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 15. "ACTIVE15,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 14. "ACTIVE14,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 13. "ACTIVE13,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 12. "ACTIVE12,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 11. "ACTIVE11,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 10. "ACTIVE10,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 9. "ACTIVE9,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 8. "ACTIVE8,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 7. "ACTIVE7,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 6. "ACTIVE6,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 5. "ACTIVE5,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 4. "ACTIVE4,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 3. "ACTIVE3,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 2. "ACTIVE2,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 1. "ACTIVE1,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 0. "ACTIVE0,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" rgroup.long 0x34++0x03 line.long 0x00 "ACTIVE1,Channel Active status for all DMA channels" bitfld.long 0x00 19. "ACTIVE51,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 18. "ACTIVE50,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 17. "ACTIVE49,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 16. "ACTIVE48,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 15. "ACTIVE47,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 14. "ACTIVE46,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 13. "ACTIVE45,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 12. "ACTIVE44,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 11. "ACTIVE43,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 10. "ACTIVE42,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 9. "ACTIVE41,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 8. "ACTIVE40,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 7. "ACTIVE39,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 6. "ACTIVE38,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 5. "ACTIVE37,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 4. "ACTIVE36,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 3. "ACTIVE35,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 2. "ACTIVE34,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 1. "ACTIVE33,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 0. "ACTIVE32,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" rgroup.long 0x38++0x03 line.long 0x00 "BUSY0,Channel Busy status for all DMA channels" bitfld.long 0x00 31. "BUSY31,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 30. "BUSY30,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 29. "BUSY29,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 28. "BUSY28,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 27. "BUSY27,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 26. "BUSY26,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 25. "BUSY25,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 24. "BUSY24,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 23. "BUSY23,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 22. "BUSY22,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 21. "BUSY21,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 20. "BUSY20,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 19. "BUSY19,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 18. "BUSY18,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 17. "BUSY17,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 16. "BUSY16,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 15. "BUSY15,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 14. "BUSY14,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 13. "BUSY13,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 12. "BUSY12,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 11. "BUSY11,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 10. "BUSY10,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 9. "BUSY9,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 8. "BUSY8,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 7. "BUSY7,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 6. "BUSY6,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 5. "BUSY5,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 4. "BUSY4,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 3. "BUSY3,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 2. "BUSY2,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 1. "BUSY1,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 0. "BUSY0,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" rgroup.long 0x3C++0x03 line.long 0x00 "BUSY1,Channel Busy status for all DMA channels" bitfld.long 0x00 19. "BUSY51,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 18. "BUSY50,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 17. "BUSY49,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 16. "BUSY48,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 15. "BUSY47,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 14. "BUSY46,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 13. "BUSY45,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 12. "BUSY44,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 11. "BUSY43,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 10. "BUSY42,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 9. "BUSY41,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 8. "BUSY40,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 7. "BUSY39,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 6. "BUSY38,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 5. "BUSY37,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 4. "BUSY36,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 3. "BUSY35,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 2. "BUSY34,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 1. "BUSY33,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 0. "BUSY32,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" group.long 0x40++0x03 line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels" bitfld.long 0x00 31. "ERR31,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 30. "ERR30,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 29. "ERR29,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 28. "ERR28,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 27. "ERR27,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 26. "ERR26,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 25. "ERR25,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 24. "ERR24,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 23. "ERR23,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 22. "ERR22,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 21. "ERR21,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 20. "ERR20,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 19. "ERR19,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 18. "ERR18,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 17. "ERR17,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 16. "ERR16,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 15. "ERR15,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 14. "ERR14,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 13. "ERR13,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 12. "ERR12,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 11. "ERR11,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 10. "ERR10,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 9. "ERR9,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 8. "ERR8,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 7. "ERR7,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 6. "ERR6,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 5. "ERR5,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 4. "ERR4,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 3. "ERR3,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 2. "ERR2,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 1. "ERR1,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 0. "ERR0,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" group.long 0x44++0x03 line.long 0x00 "ERRINT1,Error Interrupt status for all DMA channels" bitfld.long 0x00 19. "ERR51,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 18. "ERR50,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 17. "ERR49,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 16. "ERR48,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 15. "ERR47,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 14. "ERR46,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 13. "ERR45,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 12. "ERR44,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 11. "ERR43,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 10. "ERR42,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 9. "ERR41,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 8. "ERR40,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 7. "ERR39,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 6. "ERR38,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 5. "ERR37,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 4. "ERR36,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 3. "ERR35,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 2. "ERR34,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 1. "ERR33,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 0. "ERR32,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" group.long 0x48++0x03 line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels" bitfld.long 0x00 31. "INTEN31,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 30. "INTEN30,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 29. "INTEN29,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 28. "INTEN28,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 27. "INTEN27,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 26. "INTEN26,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 25. "INTEN25,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 24. "INTEN24,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 23. "INTEN23,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 22. "INTEN22,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 21. "INTEN21,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 20. "INTEN20,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 19. "INTEN19,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 18. "INTEN18,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 17. "INTEN17,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 16. "INTEN16,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 15. "INTEN15,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 14. "INTEN14,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 13. "INTEN13,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 12. "INTEN12,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 11. "INTEN11,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 10. "INTEN10,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 9. "INTEN9,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 8. "INTEN8,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 7. "INTEN7,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 6. "INTEN6,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 5. "INTEN5,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 4. "INTEN4,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 3. "INTEN3,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 2. "INTEN2,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 1. "INTEN1,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 0. "INTEN0,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" group.long 0x4C++0x03 line.long 0x00 "INTENSET1,Interrupt Enable read and Set for all DMA channels" bitfld.long 0x00 19. "INTEN51,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 18. "INTEN50,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 17. "INTEN49,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 16. "INTEN48,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 15. "INTEN47,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 14. "INTEN46,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 13. "INTEN45,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 12. "INTEN44,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 11. "INTEN43,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 10. "INTEN42,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 9. "INTEN41,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 8. "INTEN40,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 7. "INTEN39,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 6. "INTEN38,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 5. "INTEN37,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 4. "INTEN36,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 3. "INTEN35,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 2. "INTEN34,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 1. "INTEN33,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 0. "INTEN32,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" wgroup.long 0x50++0x03 line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels" bitfld.long 0x00 31. "CLR31,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 30. "CLR30,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 29. "CLR29,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 28. "CLR28,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 27. "CLR27,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 26. "CLR26,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 25. "CLR25,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 24. "CLR24,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 23. "CLR23,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 22. "CLR22,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 21. "CLR21,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 20. "CLR20,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 19. "CLR19,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 18. "CLR18,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 17. "CLR17,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 16. "CLR16,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 15. "CLR15,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 14. "CLR14,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 13. "CLR13,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 12. "CLR12,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 11. "CLR11,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 10. "CLR10,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 9. "CLR9,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 8. "CLR8,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 7. "CLR7,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 6. "CLR6,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 5. "CLR5,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 4. "CLR4,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 3. "CLR3,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 2. "CLR2,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 1. "CLR1,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 0. "CLR0,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" wgroup.long 0x54++0x03 line.long 0x00 "INTENCLR1,Interrupt Enable Clear for all DMA channels" bitfld.long 0x00 19. "CLR51,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 18. "CLR50,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 17. "CLR49,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 16. "CLR48,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 15. "CLR47,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 14. "CLR46,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 13. "CLR45,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 12. "CLR44,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 11. "CLR43,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 10. "CLR42,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 9. "CLR41,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 8. "CLR40,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 7. "CLR39,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 6. "CLR38,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 5. "CLR37,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 4. "CLR36,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 3. "CLR35,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 2. "CLR34,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 1. "CLR33,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 0. "CLR32,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" group.long 0x58++0x03 line.long 0x00 "INTA0,Interrupt A status for all DMA channels" bitfld.long 0x00 31. "INTA31,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 30. "INTA30,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 29. "INTA29,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 28. "INTA28,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 27. "INTA27,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 26. "INTA26,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 25. "INTA25,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 24. "INTA24,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 23. "INTA23,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 22. "INTA22,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 21. "INTA21,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 20. "INTA20,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 19. "INTA19,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 18. "INTA18,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 17. "INTA17,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 16. "INTA16,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 15. "INTA15,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 14. "INTA14,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 13. "INTA13,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 12. "INTA12,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 11. "INTA11,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 10. "INTA10,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 9. "INTA9,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 8. "INTA8,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 7. "INTA7,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 6. "INTA6,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 5. "INTA5,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 4. "INTA4,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 3. "INTA3,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 2. "INTA2,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 1. "INTA1,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 0. "INTA0,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" group.long 0x5C++0x03 line.long 0x00 "INTA1,Interrupt A status for all DMA channels" bitfld.long 0x00 19. "INTA51,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 18. "INTA50,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 17. "INTA49,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 16. "INTA48,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 15. "INTA47,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 14. "INTA46,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 13. "INTA45,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 12. "INTA44,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 11. "INTA43,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 10. "INTA42,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 9. "INTA41,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 8. "INTA40,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 7. "INTA39,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 6. "INTA38,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 5. "INTA37,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 4. "INTA36,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 3. "INTA35,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 2. "INTA34,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 1. "INTA33,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 0. "INTA32,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" group.long 0x60++0x03 line.long 0x00 "INTB0,Interrupt B status for all DMA channels" bitfld.long 0x00 31. "INTB31,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 30. "INTB30,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 29. "INTB29,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 28. "INTB28,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 27. "INTB27,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 26. "INTB26,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 25. "INTB25,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 24. "INTB24,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 23. "INTB23,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 22. "INTB22,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 21. "INTB21,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 20. "INTB20,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 19. "INTB19,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 18. "INTB18,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 17. "INTB17,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 16. "INTB16,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" group.long 0x64++0x03 line.long 0x00 "INTB1,Interrupt B status for all DMA channels" bitfld.long 0x00 19. "INTB19,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 18. "INTB18,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 17. "INTB17,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 16. "INTB16,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" wgroup.long 0x68++0x03 line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels" bitfld.long 0x00 31. "SETVALID31,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 30. "SETVALID30,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 29. "SETVALID29,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 28. "SETVALID28,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 27. "SETVALID27,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 26. "SETVALID26,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 25. "SETVALID25,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 24. "SETVALID24,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 23. "SETVALID23,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 22. "SETVALID22,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 21. "SETVALID21,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 20. "SETVALID20,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 19. "SETVALID19,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 18. "SETVALID18,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 17. "SETVALID17,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 16. "SETVALID16,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 15. "SETVALID15,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 14. "SETVALID14,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 13. "SETVALID13,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 12. "SETVALID12,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 11. "SETVALID11,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 10. "SETVALID10,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 9. "SETVALID9,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 8. "SETVALID8,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 7. "SETVALID7,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 6. "SETVALID6,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 5. "SETVALID5,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 4. "SETVALID4,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 3. "SETVALID3,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 2. "SETVALID2,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 1. "SETVALID1,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 0. "SETVALID0,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." wgroup.long 0x6C++0x03 line.long 0x00 "SETVALID1,Set ValidPending control bits for all DMA channels" bitfld.long 0x00 19. "SETVALID51,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 18. "SETVALID50,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 17. "SETVALID49,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 16. "SETVALID48,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 15. "SETVALID47,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 14. "SETVALID46,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 13. "SETVALID45,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 12. "SETVALID44,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 11. "SETVALID43,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 10. "SETVALID42,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 9. "SETVALID41,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 8. "SETVALID40,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 7. "SETVALID39,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 6. "SETVALID38,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 5. "SETVALID37,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 4. "SETVALID36,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 3. "SETVALID35,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 2. "SETVALID34,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 1. "SETVALID33,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 0. "SETVALID32,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." wgroup.long 0x70++0x03 line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels" bitfld.long 0x00 31. "SETTRIG31,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 30. "SETTRIG30,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 29. "SETTRIG29,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 28. "SETTRIG28,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 27. "SETTRIG27,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 26. "SETTRIG26,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 25. "SETTRIG25,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 24. "SETTRIG24,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 23. "SETTRIG23,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 22. "SETTRIG22,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 21. "SETTRIG21,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 20. "SETTRIG20,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 19. "SETTRIG19,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 18. "SETTRIG18,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 17. "SETTRIG17,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 16. "SETTRIG16,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 15. "SETTRIG15,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 14. "SETTRIG14,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 13. "SETTRIG13,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 12. "SETTRIG12,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 11. "SETTRIG11,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 10. "SETTRIG10,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 9. "SETTRIG9,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 8. "SETTRIG8,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 7. "SETTRIG7,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 6. "SETTRIG6,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 5. "SETTRIG5,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 4. "SETTRIG4,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 3. "SETTRIG3,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 2. "SETTRIG2,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 1. "SETTRIG1,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 0. "SETTRIG0,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" wgroup.long 0x74++0x03 line.long 0x00 "SETTRIG1,Set Trigger control bits for all DMA channels" bitfld.long 0x00 19. "SETTRIG51,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 18. "SETTRIG50,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 17. "SETTRIG49,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 16. "SETTRIG48,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 15. "SETTRIG47,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 14. "SETTRIG46,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 13. "SETTRIG45,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 12. "SETTRIG44,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 11. "SETTRIG43,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 10. "SETTRIG42,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 9. "SETTRIG41,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 8. "SETTRIG40,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 7. "SETTRIG39,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 6. "SETTRIG38,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 5. "SETTRIG37,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 4. "SETTRIG36,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 3. "SETTRIG35,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 2. "SETTRIG34,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 1. "SETTRIG33,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 0. "SETTRIG32,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" wgroup.long 0x78++0x03 line.long 0x00 "ABORT0,Channel Abort control for all DMA channels" bitfld.long 0x00 31. "ABORT31,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 30. "ABORT30,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 29. "ABORT29,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 28. "ABORT28,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 27. "ABORT27,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 26. "ABORT26,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 25. "ABORT25,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 24. "ABORT24,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 23. "ABORT23,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 22. "ABORT22,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 21. "ABORT21,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 20. "ABORT20,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 19. "ABORT19,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 18. "ABORT18,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 17. "ABORT17,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 16. "ABORT16,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 15. "ABORT15,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 14. "ABORT14,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 13. "ABORT13,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 12. "ABORT12,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 11. "ABORT11,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 10. "ABORT10,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 9. "ABORT9,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 8. "ABORT8,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 7. "ABORT7,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 6. "ABORT6,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 5. "ABORT5,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 4. "ABORT4,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 3. "ABORT3,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 2. "ABORT2,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 1. "ABORT1,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 0. "ABORT0,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" wgroup.long 0x7C++0x03 line.long 0x00 "ABORT1,Channel Abort control for all DMA channels" bitfld.long 0x00 19. "ABORT51,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 18. "ABORT50,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 17. "ABORT49,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 16. "ABORT48,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 15. "ABORT47,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 14. "ABORT46,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 13. "ABORT45,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 12. "ABORT44,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 11. "ABORT43,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 10. "ABORT42,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 9. "ABORT41,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 8. "ABORT40,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 7. "ABORT39,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 6. "ABORT38,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 5. "ABORT37,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 4. "ABORT36,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 3. "ABORT35,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 2. "ABORT34,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 1. "ABORT33,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 0. "ABORT32,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" repeat 52. (increment 0 1)(increment 0 0x10) tree "CHANNEL[$1]" group.long ($2+0x400)++0x03 line.long 0x00 "CFG,Configuration register for DMA channel" bitfld.long 0x00 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. "DSTBURSTWRAP,Destination Burst Wrap" "0: Disabled,1: Enabled" newline bitfld.long 0x00 14. "SRCBURSTWRAP,Source Burst Wrap" "0: Disabled,1: Enabled" bitfld.long 0x00 8.--11. "BURSTPOWER,Burst Power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. "TRIGBURST,Trigger Burst" "0: Single transfer,1: Burst transfer" bitfld.long 0x00 5. "TRIGTYPE,Trigger Type" "0: Edge,1: Level" newline bitfld.long 0x00 4. "TRIGPOL,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge" bitfld.long 0x00 1. "HWTRIGEN,Hardware Triggering Enable for channel" "0: Hardware triggering not used for channel,1: Hardware triggering used for channel" newline bitfld.long 0x00 0. "PERIPHREQEN,Peripheral request Enable" "0: Peripheral DMA requests disabled,1: Peripheral DMA requests enabled" rgroup.long ($2+0x404)++0x03 line.long 0x00 "CTLSTAT,Control and status register for DMA channel" bitfld.long 0x00 2. "TRIG,Trigger flag" "0: Not triggered,1: Triggered" bitfld.long 0x00 0. "VALIDPENDING,Valid pending flag for this channel" "0: No effect on DMA operation,1: Valid pending" group.long ($2+0x408)++0x03 line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel" hexmask.long.word 0x00 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. "DSTINC,Destination address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" newline bitfld.long 0x00 12.--13. "SRCINC,Source address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" bitfld.long 0x00 8.--9. "WIDTH,Transfer width used for this DMA channel" "0: 8-bit,1: 16-bit,2: 32-bit,?..." newline bitfld.long 0x00 5. "SETINTB,Set Interrupt flag B for channel" "0: No effect,1: Set" bitfld.long 0x00 4. "SETINTA,Set Interrupt flag A for channel" "0: No effect,1: Set" newline bitfld.long 0x00 3. "CLRTRIG,Clear Trigger" "0: Not cleared,1: Cleared" bitfld.long 0x00 2. "SWTRIG,Software Trigger" "0: Not set,1: Set" newline bitfld.long 0x00 1. "RELOAD,Reload" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "CFGVALID,Configuration Valid flag" "0: Not valid,1: Valid" tree.end repeat.end tree.end endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "DMA0" base ad:0x40082000 group.long 0x00++0x03 line.long 0x00 "CTRL,DMA control" bitfld.long 0x00 0. "ENABLE,DMA controller master enable" "0: DMA controller is disabled,1: Enabled" rgroup.long 0x04++0x03 line.long 0x00 "INTSTAT,Interrupt status" bitfld.long 0x00 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending" "0: No error interrupts are pending,1: At least one error interrupt is pending" bitfld.long 0x00 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: No enabled interrupts are pending,1: At least one enabled interrupt is pending" group.long 0x08++0x03 line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table" hexmask.long.tbyte 0x00 10.--31. 1. "OFFSET,Offset" group.long 0x20++0x03 line.long 0x00 "ENABLESET0,Channel Enable read and set for all DMA channels" bitfld.long 0x00 31. "ENABLE31,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 30. "ENABLE30,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 29. "ENABLE29,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 28. "ENABLE28,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 27. "ENABLE27,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 26. "ENABLE26,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 25. "ENABLE25,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 24. "ENABLE24,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 23. "ENABLE23,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 22. "ENABLE22,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 21. "ENABLE21,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 20. "ENABLE20,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 19. "ENABLE19,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 18. "ENABLE18,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 17. "ENABLE17,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 16. "ENABLE16,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 15. "ENABLE15,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 14. "ENABLE14,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 13. "ENABLE13,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 12. "ENABLE12,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 11. "ENABLE11,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 10. "ENABLE10,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 9. "ENABLE9,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 8. "ENABLE8,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 7. "ENABLE7,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 6. "ENABLE6,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 5. "ENABLE5,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 4. "ENABLE4,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 3. "ENABLE3,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 2. "ENABLE2,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 1. "ENABLE1,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 0. "ENABLE0,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" group.long 0x24++0x03 line.long 0x00 "ENABLESET1,Channel Enable read and set for all DMA channels" bitfld.long 0x00 19. "ENABLE51,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 18. "ENABLE50,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 17. "ENABLE49,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 16. "ENABLE48,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 15. "ENABLE47,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 14. "ENABLE46,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 13. "ENABLE45,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 12. "ENABLE44,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 11. "ENABLE43,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 10. "ENABLE42,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 9. "ENABLE41,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 8. "ENABLE40,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 7. "ENABLE39,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 6. "ENABLE38,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 5. "ENABLE37,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 4. "ENABLE36,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 3. "ENABLE35,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 2. "ENABLE34,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 1. "ENABLE33,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 0. "ENABLE32,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" group.long 0x28++0x03 line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels" eventfld.long 0x00 31. "CLR31,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 30. "CLR30,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 29. "CLR29,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 28. "CLR28,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 27. "CLR27,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 26. "CLR26,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 25. "CLR25,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 24. "CLR24,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 23. "CLR23,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 22. "CLR22,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 21. "CLR21,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 20. "CLR20,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 19. "CLR19,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 18. "CLR18,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 17. "CLR17,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 16. "CLR16,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 15. "CLR15,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 14. "CLR14,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 13. "CLR13,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 12. "CLR12,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 11. "CLR11,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 10. "CLR10,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 9. "CLR9,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 8. "CLR8,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 7. "CLR7,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 6. "CLR6,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 5. "CLR5,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 4. "CLR4,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 3. "CLR3,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 2. "CLR2,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 1. "CLR1,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 0. "CLR0,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" group.long 0x2C++0x03 line.long 0x00 "ENABLECLR1,Channel Enable Clear for all DMA channels" eventfld.long 0x00 19. "CLR51,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 18. "CLR50,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 17. "CLR49,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 16. "CLR48,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 15. "CLR47,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 14. "CLR46,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 13. "CLR45,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 12. "CLR44,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 11. "CLR43,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 10. "CLR42,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 9. "CLR41,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 8. "CLR40,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 7. "CLR39,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 6. "CLR38,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 5. "CLR37,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 4. "CLR36,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 3. "CLR35,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 2. "CLR34,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 1. "CLR33,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 0. "CLR32,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" rgroup.long 0x30++0x03 line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels" bitfld.long 0x00 31. "ACTIVE31,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 30. "ACTIVE30,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 29. "ACTIVE29,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 28. "ACTIVE28,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 27. "ACTIVE27,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 26. "ACTIVE26,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 25. "ACTIVE25,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 24. "ACTIVE24,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 23. "ACTIVE23,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 22. "ACTIVE22,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 21. "ACTIVE21,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 20. "ACTIVE20,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 19. "ACTIVE19,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 18. "ACTIVE18,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 17. "ACTIVE17,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 16. "ACTIVE16,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 15. "ACTIVE15,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 14. "ACTIVE14,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 13. "ACTIVE13,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 12. "ACTIVE12,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 11. "ACTIVE11,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 10. "ACTIVE10,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 9. "ACTIVE9,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 8. "ACTIVE8,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 7. "ACTIVE7,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 6. "ACTIVE6,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 5. "ACTIVE5,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 4. "ACTIVE4,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 3. "ACTIVE3,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 2. "ACTIVE2,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 1. "ACTIVE1,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 0. "ACTIVE0,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" rgroup.long 0x34++0x03 line.long 0x00 "ACTIVE1,Channel Active status for all DMA channels" bitfld.long 0x00 19. "ACTIVE51,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 18. "ACTIVE50,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 17. "ACTIVE49,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 16. "ACTIVE48,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 15. "ACTIVE47,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 14. "ACTIVE46,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 13. "ACTIVE45,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 12. "ACTIVE44,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 11. "ACTIVE43,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 10. "ACTIVE42,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 9. "ACTIVE41,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 8. "ACTIVE40,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 7. "ACTIVE39,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 6. "ACTIVE38,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 5. "ACTIVE37,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 4. "ACTIVE36,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 3. "ACTIVE35,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 2. "ACTIVE34,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 1. "ACTIVE33,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 0. "ACTIVE32,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" rgroup.long 0x38++0x03 line.long 0x00 "BUSY0,Channel Busy status for all DMA channels" bitfld.long 0x00 31. "BUSY31,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 30. "BUSY30,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 29. "BUSY29,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 28. "BUSY28,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 27. "BUSY27,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 26. "BUSY26,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 25. "BUSY25,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 24. "BUSY24,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 23. "BUSY23,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 22. "BUSY22,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 21. "BUSY21,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 20. "BUSY20,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 19. "BUSY19,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 18. "BUSY18,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 17. "BUSY17,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 16. "BUSY16,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 15. "BUSY15,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 14. "BUSY14,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 13. "BUSY13,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 12. "BUSY12,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 11. "BUSY11,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 10. "BUSY10,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 9. "BUSY9,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 8. "BUSY8,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 7. "BUSY7,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 6. "BUSY6,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 5. "BUSY5,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 4. "BUSY4,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 3. "BUSY3,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 2. "BUSY2,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 1. "BUSY1,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 0. "BUSY0,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" rgroup.long 0x3C++0x03 line.long 0x00 "BUSY1,Channel Busy status for all DMA channels" bitfld.long 0x00 19. "BUSY51,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 18. "BUSY50,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 17. "BUSY49,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 16. "BUSY48,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 15. "BUSY47,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 14. "BUSY46,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 13. "BUSY45,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 12. "BUSY44,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 11. "BUSY43,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 10. "BUSY42,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 9. "BUSY41,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 8. "BUSY40,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 7. "BUSY39,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 6. "BUSY38,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 5. "BUSY37,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 4. "BUSY36,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 3. "BUSY35,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 2. "BUSY34,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 1. "BUSY33,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 0. "BUSY32,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" group.long 0x40++0x03 line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels" bitfld.long 0x00 31. "ERR31,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 30. "ERR30,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 29. "ERR29,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 28. "ERR28,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 27. "ERR27,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 26. "ERR26,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 25. "ERR25,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 24. "ERR24,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 23. "ERR23,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 22. "ERR22,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 21. "ERR21,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 20. "ERR20,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 19. "ERR19,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 18. "ERR18,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 17. "ERR17,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 16. "ERR16,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 15. "ERR15,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 14. "ERR14,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 13. "ERR13,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 12. "ERR12,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 11. "ERR11,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 10. "ERR10,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 9. "ERR9,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 8. "ERR8,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 7. "ERR7,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 6. "ERR6,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 5. "ERR5,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 4. "ERR4,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 3. "ERR3,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 2. "ERR2,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 1. "ERR1,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 0. "ERR0,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" group.long 0x44++0x03 line.long 0x00 "ERRINT1,Error Interrupt status for all DMA channels" bitfld.long 0x00 19. "ERR51,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 18. "ERR50,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 17. "ERR49,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 16. "ERR48,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 15. "ERR47,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 14. "ERR46,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 13. "ERR45,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 12. "ERR44,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 11. "ERR43,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 10. "ERR42,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 9. "ERR41,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 8. "ERR40,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 7. "ERR39,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 6. "ERR38,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 5. "ERR37,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 4. "ERR36,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 3. "ERR35,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 2. "ERR34,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 1. "ERR33,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 0. "ERR32,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" group.long 0x48++0x03 line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels" bitfld.long 0x00 31. "INTEN31,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 30. "INTEN30,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 29. "INTEN29,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 28. "INTEN28,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 27. "INTEN27,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 26. "INTEN26,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 25. "INTEN25,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 24. "INTEN24,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 23. "INTEN23,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 22. "INTEN22,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 21. "INTEN21,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 20. "INTEN20,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 19. "INTEN19,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 18. "INTEN18,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 17. "INTEN17,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 16. "INTEN16,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 15. "INTEN15,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 14. "INTEN14,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 13. "INTEN13,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 12. "INTEN12,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 11. "INTEN11,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 10. "INTEN10,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 9. "INTEN9,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 8. "INTEN8,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 7. "INTEN7,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 6. "INTEN6,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 5. "INTEN5,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 4. "INTEN4,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 3. "INTEN3,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 2. "INTEN2,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 1. "INTEN1,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 0. "INTEN0,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" group.long 0x4C++0x03 line.long 0x00 "INTENSET1,Interrupt Enable read and Set for all DMA channels" bitfld.long 0x00 19. "INTEN51,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 18. "INTEN50,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 17. "INTEN49,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 16. "INTEN48,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 15. "INTEN47,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 14. "INTEN46,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 13. "INTEN45,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 12. "INTEN44,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 11. "INTEN43,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 10. "INTEN42,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 9. "INTEN41,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 8. "INTEN40,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 7. "INTEN39,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 6. "INTEN38,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 5. "INTEN37,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 4. "INTEN36,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 3. "INTEN35,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 2. "INTEN34,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 1. "INTEN33,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 0. "INTEN32,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" wgroup.long 0x50++0x03 line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels" bitfld.long 0x00 31. "CLR31,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 30. "CLR30,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 29. "CLR29,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 28. "CLR28,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 27. "CLR27,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 26. "CLR26,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 25. "CLR25,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 24. "CLR24,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 23. "CLR23,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 22. "CLR22,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 21. "CLR21,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 20. "CLR20,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 19. "CLR19,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 18. "CLR18,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 17. "CLR17,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 16. "CLR16,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 15. "CLR15,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 14. "CLR14,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 13. "CLR13,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 12. "CLR12,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 11. "CLR11,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 10. "CLR10,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 9. "CLR9,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 8. "CLR8,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 7. "CLR7,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 6. "CLR6,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 5. "CLR5,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 4. "CLR4,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 3. "CLR3,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 2. "CLR2,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 1. "CLR1,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 0. "CLR0,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" wgroup.long 0x54++0x03 line.long 0x00 "INTENCLR1,Interrupt Enable Clear for all DMA channels" bitfld.long 0x00 19. "CLR51,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 18. "CLR50,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 17. "CLR49,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 16. "CLR48,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 15. "CLR47,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 14. "CLR46,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 13. "CLR45,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 12. "CLR44,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 11. "CLR43,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 10. "CLR42,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 9. "CLR41,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 8. "CLR40,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 7. "CLR39,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 6. "CLR38,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 5. "CLR37,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 4. "CLR36,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 3. "CLR35,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 2. "CLR34,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 1. "CLR33,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 0. "CLR32,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" group.long 0x58++0x03 line.long 0x00 "INTA0,Interrupt A status for all DMA channels" bitfld.long 0x00 31. "INTA31,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 30. "INTA30,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 29. "INTA29,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 28. "INTA28,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 27. "INTA27,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 26. "INTA26,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 25. "INTA25,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 24. "INTA24,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 23. "INTA23,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 22. "INTA22,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 21. "INTA21,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 20. "INTA20,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 19. "INTA19,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 18. "INTA18,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 17. "INTA17,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 16. "INTA16,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 15. "INTA15,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 14. "INTA14,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 13. "INTA13,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 12. "INTA12,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 11. "INTA11,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 10. "INTA10,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 9. "INTA9,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 8. "INTA8,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 7. "INTA7,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 6. "INTA6,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 5. "INTA5,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 4. "INTA4,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 3. "INTA3,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 2. "INTA2,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 1. "INTA1,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 0. "INTA0,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" group.long 0x5C++0x03 line.long 0x00 "INTA1,Interrupt A status for all DMA channels" bitfld.long 0x00 19. "INTA51,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 18. "INTA50,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 17. "INTA49,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 16. "INTA48,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 15. "INTA47,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 14. "INTA46,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 13. "INTA45,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 12. "INTA44,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 11. "INTA43,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 10. "INTA42,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 9. "INTA41,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 8. "INTA40,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 7. "INTA39,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 6. "INTA38,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 5. "INTA37,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 4. "INTA36,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 3. "INTA35,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 2. "INTA34,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 1. "INTA33,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 0. "INTA32,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" group.long 0x60++0x03 line.long 0x00 "INTB0,Interrupt B status for all DMA channels" bitfld.long 0x00 31. "INTB31,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 30. "INTB30,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 29. "INTB29,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 28. "INTB28,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 27. "INTB27,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 26. "INTB26,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 25. "INTB25,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 24. "INTB24,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 23. "INTB23,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 22. "INTB22,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 21. "INTB21,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 20. "INTB20,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 19. "INTB19,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 18. "INTB18,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 17. "INTB17,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 16. "INTB16,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" group.long 0x64++0x03 line.long 0x00 "INTB1,Interrupt B status for all DMA channels" bitfld.long 0x00 19. "INTB19,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 18. "INTB18,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 17. "INTB17,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 16. "INTB16,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" wgroup.long 0x68++0x03 line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels" bitfld.long 0x00 31. "SETVALID31,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 30. "SETVALID30,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 29. "SETVALID29,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 28. "SETVALID28,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 27. "SETVALID27,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 26. "SETVALID26,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 25. "SETVALID25,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 24. "SETVALID24,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 23. "SETVALID23,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 22. "SETVALID22,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 21. "SETVALID21,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 20. "SETVALID20,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 19. "SETVALID19,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 18. "SETVALID18,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 17. "SETVALID17,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 16. "SETVALID16,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 15. "SETVALID15,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 14. "SETVALID14,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 13. "SETVALID13,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 12. "SETVALID12,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 11. "SETVALID11,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 10. "SETVALID10,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 9. "SETVALID9,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 8. "SETVALID8,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 7. "SETVALID7,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 6. "SETVALID6,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 5. "SETVALID5,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 4. "SETVALID4,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 3. "SETVALID3,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 2. "SETVALID2,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 1. "SETVALID1,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 0. "SETVALID0,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." wgroup.long 0x6C++0x03 line.long 0x00 "SETVALID1,Set ValidPending control bits for all DMA channels" bitfld.long 0x00 19. "SETVALID51,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 18. "SETVALID50,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 17. "SETVALID49,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 16. "SETVALID48,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 15. "SETVALID47,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 14. "SETVALID46,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 13. "SETVALID45,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 12. "SETVALID44,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 11. "SETVALID43,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 10. "SETVALID42,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 9. "SETVALID41,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 8. "SETVALID40,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 7. "SETVALID39,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 6. "SETVALID38,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 5. "SETVALID37,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 4. "SETVALID36,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 3. "SETVALID35,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 2. "SETVALID34,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 1. "SETVALID33,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 0. "SETVALID32,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." wgroup.long 0x70++0x03 line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels" bitfld.long 0x00 31. "SETTRIG31,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 30. "SETTRIG30,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 29. "SETTRIG29,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 28. "SETTRIG28,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 27. "SETTRIG27,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 26. "SETTRIG26,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 25. "SETTRIG25,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 24. "SETTRIG24,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 23. "SETTRIG23,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 22. "SETTRIG22,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 21. "SETTRIG21,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 20. "SETTRIG20,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 19. "SETTRIG19,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 18. "SETTRIG18,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 17. "SETTRIG17,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 16. "SETTRIG16,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 15. "SETTRIG15,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 14. "SETTRIG14,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 13. "SETTRIG13,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 12. "SETTRIG12,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 11. "SETTRIG11,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 10. "SETTRIG10,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 9. "SETTRIG9,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 8. "SETTRIG8,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 7. "SETTRIG7,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 6. "SETTRIG6,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 5. "SETTRIG5,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 4. "SETTRIG4,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 3. "SETTRIG3,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 2. "SETTRIG2,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 1. "SETTRIG1,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 0. "SETTRIG0,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" wgroup.long 0x74++0x03 line.long 0x00 "SETTRIG1,Set Trigger control bits for all DMA channels" bitfld.long 0x00 19. "SETTRIG51,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 18. "SETTRIG50,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 17. "SETTRIG49,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 16. "SETTRIG48,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 15. "SETTRIG47,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 14. "SETTRIG46,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 13. "SETTRIG45,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 12. "SETTRIG44,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 11. "SETTRIG43,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 10. "SETTRIG42,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 9. "SETTRIG41,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 8. "SETTRIG40,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 7. "SETTRIG39,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 6. "SETTRIG38,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 5. "SETTRIG37,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 4. "SETTRIG36,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 3. "SETTRIG35,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 2. "SETTRIG34,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 1. "SETTRIG33,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 0. "SETTRIG32,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" wgroup.long 0x78++0x03 line.long 0x00 "ABORT0,Channel Abort control for all DMA channels" bitfld.long 0x00 31. "ABORT31,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 30. "ABORT30,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 29. "ABORT29,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 28. "ABORT28,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 27. "ABORT27,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 26. "ABORT26,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 25. "ABORT25,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 24. "ABORT24,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 23. "ABORT23,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 22. "ABORT22,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 21. "ABORT21,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 20. "ABORT20,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 19. "ABORT19,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 18. "ABORT18,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 17. "ABORT17,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 16. "ABORT16,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 15. "ABORT15,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 14. "ABORT14,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 13. "ABORT13,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 12. "ABORT12,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 11. "ABORT11,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 10. "ABORT10,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 9. "ABORT9,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 8. "ABORT8,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 7. "ABORT7,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 6. "ABORT6,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 5. "ABORT5,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 4. "ABORT4,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 3. "ABORT3,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 2. "ABORT2,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 1. "ABORT1,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 0. "ABORT0,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" wgroup.long 0x7C++0x03 line.long 0x00 "ABORT1,Channel Abort control for all DMA channels" bitfld.long 0x00 19. "ABORT51,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 18. "ABORT50,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 17. "ABORT49,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 16. "ABORT48,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 15. "ABORT47,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 14. "ABORT46,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 13. "ABORT45,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 12. "ABORT44,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 11. "ABORT43,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 10. "ABORT42,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 9. "ABORT41,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 8. "ABORT40,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 7. "ABORT39,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 6. "ABORT38,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 5. "ABORT37,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 4. "ABORT36,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 3. "ABORT35,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 2. "ABORT34,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 1. "ABORT33,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 0. "ABORT32,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" repeat 52. (increment 0 1)(increment 0 0x10) tree "CHANNEL[$1]" group.long ($2+0x400)++0x03 line.long 0x00 "CFG,Configuration register for DMA channel" bitfld.long 0x00 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. "DSTBURSTWRAP,Destination Burst Wrap" "0: Disabled,1: Enabled" newline bitfld.long 0x00 14. "SRCBURSTWRAP,Source Burst Wrap" "0: Disabled,1: Enabled" bitfld.long 0x00 8.--11. "BURSTPOWER,Burst Power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. "TRIGBURST,Trigger Burst" "0: Single transfer,1: Burst transfer" bitfld.long 0x00 5. "TRIGTYPE,Trigger Type" "0: Edge,1: Level" newline bitfld.long 0x00 4. "TRIGPOL,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge" bitfld.long 0x00 1. "HWTRIGEN,Hardware Triggering Enable for channel" "0: Hardware triggering not used for channel,1: Hardware triggering used for channel" newline bitfld.long 0x00 0. "PERIPHREQEN,Peripheral request Enable" "0: Peripheral DMA requests disabled,1: Peripheral DMA requests enabled" rgroup.long ($2+0x404)++0x03 line.long 0x00 "CTLSTAT,Control and status register for DMA channel" bitfld.long 0x00 2. "TRIG,Trigger flag" "0: Not triggered,1: Triggered" bitfld.long 0x00 0. "VALIDPENDING,Valid pending flag for this channel" "0: No effect on DMA operation,1: Valid pending" group.long ($2+0x408)++0x03 line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel" hexmask.long.word 0x00 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. "DSTINC,Destination address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" newline bitfld.long 0x00 12.--13. "SRCINC,Source address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" bitfld.long 0x00 8.--9. "WIDTH,Transfer width used for this DMA channel" "0: 8-bit,1: 16-bit,2: 32-bit,?..." newline bitfld.long 0x00 5. "SETINTB,Set Interrupt flag B for channel" "0: No effect,1: Set" bitfld.long 0x00 4. "SETINTA,Set Interrupt flag A for channel" "0: No effect,1: Set" newline bitfld.long 0x00 3. "CLRTRIG,Clear Trigger" "0: Not cleared,1: Cleared" bitfld.long 0x00 2. "SWTRIG,Software Trigger" "0: Not set,1: Set" newline bitfld.long 0x00 1. "RELOAD,Reload" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "CFGVALID,Configuration Valid flag" "0: Not valid,1: Valid" tree.end repeat.end tree.end endif sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "DMA1" base ad:0x400A7000 group.long 0x00++0x03 line.long 0x00 "CTRL,DMA control" bitfld.long 0x00 0. "ENABLE,DMA controller master enable" "0: DMA controller is disabled,1: Enabled" rgroup.long 0x04++0x03 line.long 0x00 "INTSTAT,Interrupt status" bitfld.long 0x00 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending" "0: No error interrupts are pending,1: At least one error interrupt is pending" bitfld.long 0x00 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: No enabled interrupts are pending,1: At least one enabled interrupt is pending" group.long 0x08++0x03 line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table" hexmask.long.tbyte 0x00 8.--31. 1. "OFFSET,Offset" group.long 0x20++0x03 line.long 0x00 "ENABLESET0,Channel Enable read and set for all DMA channels" bitfld.long 0x00 15. "ENABLE15,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 14. "ENABLE14,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 13. "ENABLE13,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 12. "ENABLE12,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 11. "ENABLE11,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 10. "ENABLE10,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 9. "ENABLE9,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 8. "ENABLE8,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 7. "ENABLE7,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 6. "ENABLE6,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 5. "ENABLE5,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 4. "ENABLE4,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 3. "ENABLE3,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 2. "ENABLE2,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 1. "ENABLE1,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 0. "ENABLE0,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" group.long 0x28++0x03 line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels" eventfld.long 0x00 15. "CLR15,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 14. "CLR14,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 13. "CLR13,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 12. "CLR12,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 11. "CLR11,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 10. "CLR10,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 9. "CLR9,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 8. "CLR8,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 7. "CLR7,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 6. "CLR6,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 5. "CLR5,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 4. "CLR4,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 3. "CLR3,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 2. "CLR2,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 1. "CLR1,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 0. "CLR0,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" rgroup.long 0x30++0x03 line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels" bitfld.long 0x00 15. "ACTIVE15,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 14. "ACTIVE14,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 13. "ACTIVE13,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 12. "ACTIVE12,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 11. "ACTIVE11,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 10. "ACTIVE10,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 9. "ACTIVE9,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 8. "ACTIVE8,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 7. "ACTIVE7,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 6. "ACTIVE6,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 5. "ACTIVE5,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 4. "ACTIVE4,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 3. "ACTIVE3,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 2. "ACTIVE2,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 1. "ACTIVE1,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 0. "ACTIVE0,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" rgroup.long 0x38++0x03 line.long 0x00 "BUSY0,Channel Busy status for all DMA channels" bitfld.long 0x00 15. "BUSY15,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 14. "BUSY14,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 13. "BUSY13,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 12. "BUSY12,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 11. "BUSY11,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 10. "BUSY10,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 9. "BUSY9,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 8. "BUSY8,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 7. "BUSY7,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 6. "BUSY6,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 5. "BUSY5,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 4. "BUSY4,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 3. "BUSY3,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 2. "BUSY2,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 1. "BUSY1,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 0. "BUSY0,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" group.long 0x40++0x03 line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels" bitfld.long 0x00 15. "ERR15,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 14. "ERR14,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 13. "ERR13,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 12. "ERR12,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 11. "ERR11,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 10. "ERR10,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 9. "ERR9,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 8. "ERR8,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 7. "ERR7,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 6. "ERR6,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 5. "ERR5,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 4. "ERR4,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 3. "ERR3,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 2. "ERR2,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 1. "ERR1,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 0. "ERR0,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" group.long 0x48++0x03 line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels" bitfld.long 0x00 15. "INTEN15,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 14. "INTEN14,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 13. "INTEN13,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 12. "INTEN12,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 11. "INTEN11,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 10. "INTEN10,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 9. "INTEN9,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 8. "INTEN8,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 7. "INTEN7,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 6. "INTEN6,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 5. "INTEN5,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 4. "INTEN4,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 3. "INTEN3,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 2. "INTEN2,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 1. "INTEN1,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 0. "INTEN0,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" wgroup.long 0x50++0x03 line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels" bitfld.long 0x00 15. "CLR15,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 14. "CLR14,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 13. "CLR13,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 12. "CLR12,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 11. "CLR11,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 10. "CLR10,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 9. "CLR9,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 8. "CLR8,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 7. "CLR7,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 6. "CLR6,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 5. "CLR5,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 4. "CLR4,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 3. "CLR3,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 2. "CLR2,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 1. "CLR1,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 0. "CLR0,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" group.long 0x58++0x03 line.long 0x00 "INTA0,Interrupt A status for all DMA channels" bitfld.long 0x00 15. "INTA15,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 14. "INTA14,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 13. "INTA13,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 12. "INTA12,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 11. "INTA11,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 10. "INTA10,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 9. "INTA9,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 8. "INTA8,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 7. "INTA7,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 6. "INTA6,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 5. "INTA5,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 4. "INTA4,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 3. "INTA3,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 2. "INTA2,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 1. "INTA1,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 0. "INTA0,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" group.long 0x60++0x03 line.long 0x00 "INTB0,Interrupt B status for all DMA channels" bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" wgroup.long 0x68++0x03 line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels" bitfld.long 0x00 15. "SETVALID15,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 14. "SETVALID14,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 13. "SETVALID13,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 12. "SETVALID12,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 11. "SETVALID11,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 10. "SETVALID10,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 9. "SETVALID9,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 8. "SETVALID8,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 7. "SETVALID7,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 6. "SETVALID6,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 5. "SETVALID5,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 4. "SETVALID4,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 3. "SETVALID3,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 2. "SETVALID2,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 1. "SETVALID1,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 0. "SETVALID0,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." wgroup.long 0x70++0x03 line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels" bitfld.long 0x00 15. "SETTRIG15,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 14. "SETTRIG14,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 13. "SETTRIG13,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 12. "SETTRIG12,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 11. "SETTRIG11,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 10. "SETTRIG10,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 9. "SETTRIG9,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 8. "SETTRIG8,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 7. "SETTRIG7,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 6. "SETTRIG6,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 5. "SETTRIG5,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 4. "SETTRIG4,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 3. "SETTRIG3,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 2. "SETTRIG2,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 1. "SETTRIG1,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 0. "SETTRIG0,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" wgroup.long 0x78++0x03 line.long 0x00 "ABORT0,Channel Abort control for all DMA channels" bitfld.long 0x00 15. "ABORT15,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 14. "ABORT14,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 13. "ABORT13,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 12. "ABORT12,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 11. "ABORT11,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 10. "ABORT10,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 9. "ABORT9,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 8. "ABORT8,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 7. "ABORT7,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 6. "ABORT6,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 5. "ABORT5,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 4. "ABORT4,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 3. "ABORT3,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 2. "ABORT2,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 1. "ABORT1,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 0. "ABORT0,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" repeat 16. (increment 0 1)(increment 0 0x10) tree "CHANNEL[$1]" group.long ($2+0x400)++0x03 line.long 0x00 "CFG,Configuration register for DMA channel" bitfld.long 0x00 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. "DSTBURSTWRAP,Destination Burst Wrap" "0: Disabled,1: Enabled" newline bitfld.long 0x00 14. "SRCBURSTWRAP,Source Burst Wrap" "0: Disabled,1: Enabled" bitfld.long 0x00 8.--11. "BURSTPOWER,Burst Power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. "TRIGBURST,Trigger Burst" "0: Single transfer,1: Burst transfer" bitfld.long 0x00 5. "TRIGTYPE,Trigger Type" "0: Edge,1: Level" newline bitfld.long 0x00 4. "TRIGPOL,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge" bitfld.long 0x00 1. "HWTRIGEN,Hardware Triggering Enable for channel" "0: Hardware triggering not used for channel,1: Hardware triggering used for channel" newline bitfld.long 0x00 0. "PERIPHREQEN,Peripheral request Enable" "0: Peripheral DMA requests disabled,1: Peripheral DMA requests enabled" rgroup.long ($2+0x404)++0x03 line.long 0x00 "CTLSTAT,Control and status register for DMA channel" bitfld.long 0x00 2. "TRIG,Trigger flag" "0: Not triggered,1: Triggered" bitfld.long 0x00 0. "VALIDPENDING,Valid pending flag for this channel" "0: No effect on DMA operation,1: Valid pending" group.long ($2+0x408)++0x03 line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel" hexmask.long.word 0x00 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. "DSTINC,Destination address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" newline bitfld.long 0x00 12.--13. "SRCINC,Source address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" bitfld.long 0x00 8.--9. "WIDTH,Transfer width used for this DMA channel" "0: 8-bit,1: 16-bit,2: 32-bit,?..." newline bitfld.long 0x00 5. "SETINTB,Set Interrupt flag B for channel" "0: No effect,1: Set" bitfld.long 0x00 4. "SETINTA,Set Interrupt flag A for channel" "0: No effect,1: Set" newline bitfld.long 0x00 3. "CLRTRIG,Clear Trigger" "0: Not cleared,1: Cleared" bitfld.long 0x00 2. "SWTRIG,Software Trigger" "0: Not set,1: Set" newline bitfld.long 0x00 1. "RELOAD,Reload" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "CFGVALID,Configuration Valid flag" "0: Not valid,1: Valid" tree.end repeat.end tree.end endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "DMA1" base ad:0x400A7000 group.long 0x00++0x03 line.long 0x00 "CTRL,DMA control" bitfld.long 0x00 0. "ENABLE,DMA controller master enable" "0: DMA controller is disabled,1: Enabled" rgroup.long 0x04++0x03 line.long 0x00 "INTSTAT,Interrupt status" bitfld.long 0x00 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending" "0: No error interrupts are pending,1: At least one error interrupt is pending" bitfld.long 0x00 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: No enabled interrupts are pending,1: At least one enabled interrupt is pending" group.long 0x08++0x03 line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table" hexmask.long.tbyte 0x00 10.--31. 1. "OFFSET,Offset" group.long 0x20++0x03 line.long 0x00 "ENABLESET0,Channel Enable read and set for all DMA channels" bitfld.long 0x00 31. "ENABLE31,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 30. "ENABLE30,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 29. "ENABLE29,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 28. "ENABLE28,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 27. "ENABLE27,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 26. "ENABLE26,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 25. "ENABLE25,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 24. "ENABLE24,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 23. "ENABLE23,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 22. "ENABLE22,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 21. "ENABLE21,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 20. "ENABLE20,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 19. "ENABLE19,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 18. "ENABLE18,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 17. "ENABLE17,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 16. "ENABLE16,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 15. "ENABLE15,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 14. "ENABLE14,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 13. "ENABLE13,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 12. "ENABLE12,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 11. "ENABLE11,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 10. "ENABLE10,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 9. "ENABLE9,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 8. "ENABLE8,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 7. "ENABLE7,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 6. "ENABLE6,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 5. "ENABLE5,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 4. "ENABLE4,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 3. "ENABLE3,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 2. "ENABLE2,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 1. "ENABLE1,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 0. "ENABLE0,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" group.long 0x24++0x03 line.long 0x00 "ENABLESET1,Channel Enable read and set for all DMA channels" bitfld.long 0x00 19. "ENABLE51,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 18. "ENABLE50,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 17. "ENABLE49,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 16. "ENABLE48,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 15. "ENABLE47,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 14. "ENABLE46,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 13. "ENABLE45,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 12. "ENABLE44,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 11. "ENABLE43,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 10. "ENABLE42,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 9. "ENABLE41,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 8. "ENABLE40,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 7. "ENABLE39,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 6. "ENABLE38,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 5. "ENABLE37,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 4. "ENABLE36,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 3. "ENABLE35,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 2. "ENABLE34,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" newline bitfld.long 0x00 1. "ENABLE33,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" bitfld.long 0x00 0. "ENABLE32,Enable for DMA channel" "0: DMA channel is disabled,1: DMA channel is enabled" group.long 0x28++0x03 line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels" eventfld.long 0x00 31. "CLR31,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 30. "CLR30,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 29. "CLR29,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 28. "CLR28,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 27. "CLR27,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 26. "CLR26,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 25. "CLR25,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 24. "CLR24,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 23. "CLR23,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 22. "CLR22,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 21. "CLR21,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 20. "CLR20,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 19. "CLR19,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 18. "CLR18,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 17. "CLR17,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 16. "CLR16,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 15. "CLR15,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 14. "CLR14,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 13. "CLR13,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 12. "CLR12,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 11. "CLR11,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 10. "CLR10,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 9. "CLR9,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 8. "CLR8,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 7. "CLR7,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 6. "CLR6,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 5. "CLR5,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 4. "CLR4,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 3. "CLR3,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 2. "CLR2,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 1. "CLR1,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 0. "CLR0,Writing ones to this register clears the corresponding bits in ENABLESET0" "0: No effect,1: DMA channel is cleared" group.long 0x2C++0x03 line.long 0x00 "ENABLECLR1,Channel Enable Clear for all DMA channels" eventfld.long 0x00 19. "CLR51,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 18. "CLR50,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 17. "CLR49,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 16. "CLR48,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 15. "CLR47,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 14. "CLR46,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 13. "CLR45,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 12. "CLR44,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 11. "CLR43,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 10. "CLR42,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 9. "CLR41,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 8. "CLR40,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 7. "CLR39,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 6. "CLR38,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 5. "CLR37,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 4. "CLR36,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 3. "CLR35,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 2. "CLR34,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" newline eventfld.long 0x00 1. "CLR33,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" eventfld.long 0x00 0. "CLR32,Writing ones to this register clears the corresponding bits in ENABLESET1" "0: No effect,1: DMA channel is cleared" rgroup.long 0x30++0x03 line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels" bitfld.long 0x00 31. "ACTIVE31,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 30. "ACTIVE30,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 29. "ACTIVE29,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 28. "ACTIVE28,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 27. "ACTIVE27,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 26. "ACTIVE26,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 25. "ACTIVE25,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 24. "ACTIVE24,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 23. "ACTIVE23,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 22. "ACTIVE22,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 21. "ACTIVE21,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 20. "ACTIVE20,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 19. "ACTIVE19,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 18. "ACTIVE18,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 17. "ACTIVE17,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 16. "ACTIVE16,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 15. "ACTIVE15,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 14. "ACTIVE14,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 13. "ACTIVE13,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 12. "ACTIVE12,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 11. "ACTIVE11,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 10. "ACTIVE10,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 9. "ACTIVE9,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 8. "ACTIVE8,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 7. "ACTIVE7,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 6. "ACTIVE6,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 5. "ACTIVE5,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 4. "ACTIVE4,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 3. "ACTIVE3,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 2. "ACTIVE2,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 1. "ACTIVE1,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 0. "ACTIVE0,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" rgroup.long 0x34++0x03 line.long 0x00 "ACTIVE1,Channel Active status for all DMA channels" bitfld.long 0x00 19. "ACTIVE51,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 18. "ACTIVE50,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 17. "ACTIVE49,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 16. "ACTIVE48,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 15. "ACTIVE47,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 14. "ACTIVE46,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 13. "ACTIVE45,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 12. "ACTIVE44,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 11. "ACTIVE43,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 10. "ACTIVE42,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 9. "ACTIVE41,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 8. "ACTIVE40,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 7. "ACTIVE39,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 6. "ACTIVE38,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 5. "ACTIVE37,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 4. "ACTIVE36,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 3. "ACTIVE35,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 2. "ACTIVE34,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" newline bitfld.long 0x00 1. "ACTIVE33,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" bitfld.long 0x00 0. "ACTIVE32,Active flag for DMA channel" "0: DMA channel is not active,1: DMA channel is active" rgroup.long 0x38++0x03 line.long 0x00 "BUSY0,Channel Busy status for all DMA channels" bitfld.long 0x00 31. "BUSY31,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 30. "BUSY30,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 29. "BUSY29,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 28. "BUSY28,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 27. "BUSY27,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 26. "BUSY26,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 25. "BUSY25,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 24. "BUSY24,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 23. "BUSY23,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 22. "BUSY22,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 21. "BUSY21,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 20. "BUSY20,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 19. "BUSY19,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 18. "BUSY18,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 17. "BUSY17,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 16. "BUSY16,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 15. "BUSY15,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 14. "BUSY14,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 13. "BUSY13,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 12. "BUSY12,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 11. "BUSY11,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 10. "BUSY10,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 9. "BUSY9,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 8. "BUSY8,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 7. "BUSY7,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 6. "BUSY6,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 5. "BUSY5,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 4. "BUSY4,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 3. "BUSY3,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 2. "BUSY2,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 1. "BUSY1,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 0. "BUSY0,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" rgroup.long 0x3C++0x03 line.long 0x00 "BUSY1,Channel Busy status for all DMA channels" bitfld.long 0x00 19. "BUSY51,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 18. "BUSY50,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 17. "BUSY49,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 16. "BUSY48,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 15. "BUSY47,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 14. "BUSY46,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 13. "BUSY45,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 12. "BUSY44,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 11. "BUSY43,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 10. "BUSY42,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 9. "BUSY41,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 8. "BUSY40,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 7. "BUSY39,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 6. "BUSY38,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 5. "BUSY37,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 4. "BUSY36,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 3. "BUSY35,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 2. "BUSY34,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" newline bitfld.long 0x00 1. "BUSY33,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" bitfld.long 0x00 0. "BUSY32,Busy flag for DMA channel" "0: DMA channel is not busy,1: DMA channel is busy" group.long 0x40++0x03 line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels" bitfld.long 0x00 31. "ERR31,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 30. "ERR30,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 29. "ERR29,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 28. "ERR28,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 27. "ERR27,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 26. "ERR26,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 25. "ERR25,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 24. "ERR24,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 23. "ERR23,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 22. "ERR22,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 21. "ERR21,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 20. "ERR20,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 19. "ERR19,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 18. "ERR18,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 17. "ERR17,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 16. "ERR16,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 15. "ERR15,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 14. "ERR14,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 13. "ERR13,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 12. "ERR12,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 11. "ERR11,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 10. "ERR10,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 9. "ERR9,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 8. "ERR8,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 7. "ERR7,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 6. "ERR6,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 5. "ERR5,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 4. "ERR4,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 3. "ERR3,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 2. "ERR2,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 1. "ERR1,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 0. "ERR0,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" group.long 0x44++0x03 line.long 0x00 "ERRINT1,Error Interrupt status for all DMA channels" bitfld.long 0x00 19. "ERR51,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 18. "ERR50,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 17. "ERR49,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 16. "ERR48,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 15. "ERR47,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 14. "ERR46,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 13. "ERR45,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 12. "ERR44,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 11. "ERR43,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 10. "ERR42,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 9. "ERR41,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 8. "ERR40,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 7. "ERR39,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 6. "ERR38,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 5. "ERR37,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 4. "ERR36,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 3. "ERR35,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 2. "ERR34,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" newline bitfld.long 0x00 1. "ERR33,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" bitfld.long 0x00 0. "ERR32,Error Interrupt flag for DMA channel" "0: The Error Interrupt is not active for DMA..,1: The Error Interrupt is pending for DMA channel" group.long 0x48++0x03 line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels" bitfld.long 0x00 31. "INTEN31,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 30. "INTEN30,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 29. "INTEN29,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 28. "INTEN28,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 27. "INTEN27,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 26. "INTEN26,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 25. "INTEN25,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 24. "INTEN24,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 23. "INTEN23,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 22. "INTEN22,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 21. "INTEN21,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 20. "INTEN20,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 19. "INTEN19,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 18. "INTEN18,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 17. "INTEN17,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 16. "INTEN16,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 15. "INTEN15,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 14. "INTEN14,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 13. "INTEN13,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 12. "INTEN12,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 11. "INTEN11,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 10. "INTEN10,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 9. "INTEN9,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 8. "INTEN8,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 7. "INTEN7,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 6. "INTEN6,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 5. "INTEN5,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 4. "INTEN4,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 3. "INTEN3,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 2. "INTEN2,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 1. "INTEN1,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 0. "INTEN0,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" group.long 0x4C++0x03 line.long 0x00 "INTENSET1,Interrupt Enable read and Set for all DMA channels" bitfld.long 0x00 19. "INTEN51,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 18. "INTEN50,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 17. "INTEN49,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 16. "INTEN48,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 15. "INTEN47,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 14. "INTEN46,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 13. "INTEN45,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 12. "INTEN44,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 11. "INTEN43,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 10. "INTEN42,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 9. "INTEN41,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 8. "INTEN40,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 7. "INTEN39,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 6. "INTEN38,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 5. "INTEN37,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 4. "INTEN36,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 3. "INTEN35,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 2. "INTEN34,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" newline bitfld.long 0x00 1. "INTEN33,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" bitfld.long 0x00 0. "INTEN32,Interrupt Enable read and set for DMA channel" "0: The Interrupt for DMA channel is disabled,1: The Interrupt for DMA channel is enabled" wgroup.long 0x50++0x03 line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels" bitfld.long 0x00 31. "CLR31,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 30. "CLR30,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 29. "CLR29,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 28. "CLR28,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 27. "CLR27,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 26. "CLR26,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 25. "CLR25,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 24. "CLR24,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 23. "CLR23,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 22. "CLR22,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 21. "CLR21,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 20. "CLR20,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 19. "CLR19,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 18. "CLR18,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 17. "CLR17,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 16. "CLR16,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 15. "CLR15,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 14. "CLR14,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 13. "CLR13,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 12. "CLR12,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 11. "CLR11,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 10. "CLR10,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 9. "CLR9,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 8. "CLR8,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 7. "CLR7,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 6. "CLR6,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 5. "CLR5,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 4. "CLR4,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 3. "CLR3,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 2. "CLR2,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" newline bitfld.long 0x00 1. "CLR1,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" bitfld.long 0x00 0. "CLR0,Writing ones to this register clears corresponding bits in the DMAIntEnSet0" "0,1" wgroup.long 0x54++0x03 line.long 0x00 "INTENCLR1,Interrupt Enable Clear for all DMA channels" bitfld.long 0x00 19. "CLR51,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 18. "CLR50,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 17. "CLR49,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 16. "CLR48,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 15. "CLR47,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 14. "CLR46,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 13. "CLR45,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 12. "CLR44,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 11. "CLR43,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 10. "CLR42,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 9. "CLR41,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 8. "CLR40,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 7. "CLR39,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 6. "CLR38,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 5. "CLR37,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 4. "CLR36,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 3. "CLR35,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 2. "CLR34,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" newline bitfld.long 0x00 1. "CLR33,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" bitfld.long 0x00 0. "CLR32,Writing ones to this register clears corresponding bits in the DMAIntEnSet1" "0,1" group.long 0x58++0x03 line.long 0x00 "INTA0,Interrupt A status for all DMA channels" bitfld.long 0x00 31. "INTA31,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 30. "INTA30,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 29. "INTA29,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 28. "INTA28,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 27. "INTA27,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 26. "INTA26,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 25. "INTA25,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 24. "INTA24,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 23. "INTA23,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 22. "INTA22,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 21. "INTA21,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 20. "INTA20,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 19. "INTA19,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 18. "INTA18,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 17. "INTA17,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 16. "INTA16,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 15. "INTA15,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 14. "INTA14,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 13. "INTA13,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 12. "INTA12,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 11. "INTA11,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 10. "INTA10,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 9. "INTA9,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 8. "INTA8,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 7. "INTA7,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 6. "INTA6,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 5. "INTA5,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 4. "INTA4,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 3. "INTA3,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 2. "INTA2,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 1. "INTA1,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 0. "INTA0,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" group.long 0x5C++0x03 line.long 0x00 "INTA1,Interrupt A status for all DMA channels" bitfld.long 0x00 19. "INTA51,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 18. "INTA50,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 17. "INTA49,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 16. "INTA48,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 15. "INTA47,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 14. "INTA46,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 13. "INTA45,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 12. "INTA44,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 11. "INTA43,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 10. "INTA42,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 9. "INTA41,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 8. "INTA40,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 7. "INTA39,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 6. "INTA38,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 5. "INTA37,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 4. "INTA36,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 3. "INTA35,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 2. "INTA34,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" newline bitfld.long 0x00 1. "INTA33,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" bitfld.long 0x00 0. "INTA32,Interrupt A status for DMA channel" "0: The DMA channel interrupt A is not active,1: The DMA channel interrupt A is active" group.long 0x60++0x03 line.long 0x00 "INTB0,Interrupt B status for all DMA channels" bitfld.long 0x00 31. "INTB31,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 30. "INTB30,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 29. "INTB29,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 28. "INTB28,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 27. "INTB27,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 26. "INTB26,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 25. "INTB25,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 24. "INTB24,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 23. "INTB23,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 22. "INTB22,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 21. "INTB21,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 20. "INTB20,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 19. "INTB19,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 18. "INTB18,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 17. "INTB17,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 16. "INTB16,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" group.long 0x64++0x03 line.long 0x00 "INTB1,Interrupt B status for all DMA channels" bitfld.long 0x00 19. "INTB19,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 18. "INTB18,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 17. "INTB17,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 16. "INTB16,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 15. "INTB15,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 14. "INTB14,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 13. "INTB13,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 12. "INTB12,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 11. "INTB11,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 10. "INTB10,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 9. "INTB9,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 8. "INTB8,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 7. "INTB7,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 6. "INTB6,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 5. "INTB5,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 4. "INTB4,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 3. "INTB3,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 2. "INTB2,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" newline bitfld.long 0x00 1. "INTB1,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" bitfld.long 0x00 0. "INTB0,Interrupt B status for DMA channel" "0: The DMA channel interrupt B is not active,1: The DMA channel interrupt B is active" wgroup.long 0x68++0x03 line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels" bitfld.long 0x00 31. "SETVALID31,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 30. "SETVALID30,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 29. "SETVALID29,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 28. "SETVALID28,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 27. "SETVALID27,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 26. "SETVALID26,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 25. "SETVALID25,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 24. "SETVALID24,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 23. "SETVALID23,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 22. "SETVALID22,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 21. "SETVALID21,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 20. "SETVALID20,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 19. "SETVALID19,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 18. "SETVALID18,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 17. "SETVALID17,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 16. "SETVALID16,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 15. "SETVALID15,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 14. "SETVALID14,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 13. "SETVALID13,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 12. "SETVALID12,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 11. "SETVALID11,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 10. "SETVALID10,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 9. "SETVALID9,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 8. "SETVALID8,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 7. "SETVALID7,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 6. "SETVALID6,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 5. "SETVALID5,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 4. "SETVALID4,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 3. "SETVALID3,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 2. "SETVALID2,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 1. "SETVALID1,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 0. "SETVALID0,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." wgroup.long 0x6C++0x03 line.long 0x00 "SETVALID1,Set ValidPending control bits for all DMA channels" bitfld.long 0x00 19. "SETVALID51,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 18. "SETVALID50,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 17. "SETVALID49,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 16. "SETVALID48,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 15. "SETVALID47,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 14. "SETVALID46,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 13. "SETVALID45,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 12. "SETVALID44,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 11. "SETVALID43,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 10. "SETVALID42,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 9. "SETVALID41,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 8. "SETVALID40,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 7. "SETVALID39,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 6. "SETVALID38,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 5. "SETVALID37,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 4. "SETVALID36,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 3. "SETVALID35,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 2. "SETVALID34,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." newline bitfld.long 0x00 1. "SETVALID33,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." bitfld.long 0x00 0. "SETVALID32,SetValid control for DMA channel" "0: No effect,1: Sets the ValidPending control bit for DMA.." wgroup.long 0x70++0x03 line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels" bitfld.long 0x00 31. "SETTRIG31,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 30. "SETTRIG30,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 29. "SETTRIG29,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 28. "SETTRIG28,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 27. "SETTRIG27,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 26. "SETTRIG26,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 25. "SETTRIG25,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 24. "SETTRIG24,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 23. "SETTRIG23,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 22. "SETTRIG22,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 21. "SETTRIG21,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 20. "SETTRIG20,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 19. "SETTRIG19,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 18. "SETTRIG18,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 17. "SETTRIG17,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 16. "SETTRIG16,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 15. "SETTRIG15,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 14. "SETTRIG14,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 13. "SETTRIG13,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 12. "SETTRIG12,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 11. "SETTRIG11,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 10. "SETTRIG10,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 9. "SETTRIG9,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 8. "SETTRIG8,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 7. "SETTRIG7,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 6. "SETTRIG6,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 5. "SETTRIG5,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 4. "SETTRIG4,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 3. "SETTRIG3,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 2. "SETTRIG2,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 1. "SETTRIG1,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 0. "SETTRIG0,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" wgroup.long 0x74++0x03 line.long 0x00 "SETTRIG1,Set Trigger control bits for all DMA channels" bitfld.long 0x00 19. "SETTRIG51,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 18. "SETTRIG50,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 17. "SETTRIG49,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 16. "SETTRIG48,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 15. "SETTRIG47,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 14. "SETTRIG46,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 13. "SETTRIG45,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 12. "SETTRIG44,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 11. "SETTRIG43,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 10. "SETTRIG42,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 9. "SETTRIG41,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 8. "SETTRIG40,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 7. "SETTRIG39,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 6. "SETTRIG38,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 5. "SETTRIG37,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 4. "SETTRIG36,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 3. "SETTRIG35,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 2. "SETTRIG34,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" newline bitfld.long 0x00 1. "SETTRIG33,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" bitfld.long 0x00 0. "SETTRIG32,Set Trigger control bit for DMA channel" "0: No effect,1: Sets the Trig bit for DMA channel" wgroup.long 0x78++0x03 line.long 0x00 "ABORT0,Channel Abort control for all DMA channels" bitfld.long 0x00 31. "ABORT31,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 30. "ABORT30,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 29. "ABORT29,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 28. "ABORT28,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 27. "ABORT27,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 26. "ABORT26,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 25. "ABORT25,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 24. "ABORT24,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 23. "ABORT23,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 22. "ABORT22,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 21. "ABORT21,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 20. "ABORT20,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 19. "ABORT19,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 18. "ABORT18,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 17. "ABORT17,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 16. "ABORT16,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 15. "ABORT15,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 14. "ABORT14,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 13. "ABORT13,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 12. "ABORT12,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 11. "ABORT11,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 10. "ABORT10,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 9. "ABORT9,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 8. "ABORT8,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 7. "ABORT7,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 6. "ABORT6,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 5. "ABORT5,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 4. "ABORT4,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 3. "ABORT3,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 2. "ABORT2,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 1. "ABORT1,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 0. "ABORT0,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" wgroup.long 0x7C++0x03 line.long 0x00 "ABORT1,Channel Abort control for all DMA channels" bitfld.long 0x00 19. "ABORT51,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 18. "ABORT50,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 17. "ABORT49,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 16. "ABORT48,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 15. "ABORT47,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 14. "ABORT46,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 13. "ABORT45,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 12. "ABORT44,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 11. "ABORT43,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 10. "ABORT42,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 9. "ABORT41,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 8. "ABORT40,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 7. "ABORT39,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 6. "ABORT38,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 5. "ABORT37,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 4. "ABORT36,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 3. "ABORT35,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 2. "ABORT34,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" newline bitfld.long 0x00 1. "ABORT33,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" bitfld.long 0x00 0. "ABORT32,Abort control for DMA channel" "0: No effect,1: Aborts DMA operations on channel" repeat 52. (increment 0 1)(increment 0 0x10) tree "CHANNEL[$1]" group.long ($2+0x400)++0x03 line.long 0x00 "CFG,Configuration register for DMA channel" bitfld.long 0x00 16.--18. "CHPRIORITY,Priority of channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. "DSTBURSTWRAP,Destination Burst Wrap" "0: Disabled,1: Enabled" newline bitfld.long 0x00 14. "SRCBURSTWRAP,Source Burst Wrap" "0: Disabled,1: Enabled" bitfld.long 0x00 8.--11. "BURSTPOWER,Burst Power" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. "TRIGBURST,Trigger Burst" "0: Single transfer,1: Burst transfer" bitfld.long 0x00 5. "TRIGTYPE,Trigger Type" "0: Edge,1: Level" newline bitfld.long 0x00 4. "TRIGPOL,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge" bitfld.long 0x00 1. "HWTRIGEN,Hardware Triggering Enable for channel" "0: Hardware triggering not used for channel,1: Hardware triggering used for channel" newline bitfld.long 0x00 0. "PERIPHREQEN,Peripheral request Enable" "0: Peripheral DMA requests disabled,1: Peripheral DMA requests enabled" rgroup.long ($2+0x404)++0x03 line.long 0x00 "CTLSTAT,Control and status register for DMA channel" bitfld.long 0x00 2. "TRIG,Trigger flag" "0: Not triggered,1: Triggered" bitfld.long 0x00 0. "VALIDPENDING,Valid pending flag for this channel" "0: No effect on DMA operation,1: Valid pending" group.long ($2+0x408)++0x03 line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel" hexmask.long.word 0x00 16.--25. 1. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. "DSTINC,Destination address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" newline bitfld.long 0x00 12.--13. "SRCINC,Source address increment" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width" bitfld.long 0x00 8.--9. "WIDTH,Transfer width used for this DMA channel" "0: 8-bit,1: 16-bit,2: 32-bit,?..." newline bitfld.long 0x00 5. "SETINTB,Set Interrupt flag B for channel" "0: No effect,1: Set" bitfld.long 0x00 4. "SETINTA,Set Interrupt flag A for channel" "0: No effect,1: Set" newline bitfld.long 0x00 3. "CLRTRIG,Clear Trigger" "0: Not cleared,1: Cleared" bitfld.long 0x00 2. "SWTRIG,Software Trigger" "0: Not set,1: Set" newline bitfld.long 0x00 1. "RELOAD,Reload" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "CFGVALID,Configuration Valid flag" "0: Not valid,1: Valid" tree.end repeat.end tree.end endif tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "DMIC" base ad:0x40090000 group.long 0xF00++0x03 line.long 0x00 "CHANEN,Channel Enable" bitfld.long 0x00 1. "EN_CH1,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled" bitfld.long 0x00 0. "EN_CH0,Enable Channel n" "0: PDM channel n is disabled,1: PDM channel n is enabled" group.long 0xF10++0x03 line.long 0x00 "USE2FS,Use 2 FS register" bitfld.long 0x00 0. "USE2FS,Use 2FS register" "0: Use 1 FS output for PCM data,1: Use 2 FS output for PCM data" group.long 0xF14++0x03 line.long 0x00 "GLOBAL_SYNC_EN,Global Channel Synchronization Enable" bitfld.long 0x00 0.--1. "CH_SYNC_EN,Channel synch enable" "0,1,2,3" group.long 0xF18++0x03 line.long 0x00 "GLOBAL_COUNT_VAL,Global channel synchronization counter value" hexmask.long 0x00 0.--31. 1. "CCOUNTVAL,Channel Counter Value" group.long 0xF1C++0x03 line.long 0x00 "DECRESET,DMIC decimator reset" bitfld.long 0x00 0.--1. "DECRESET,Decimator reset" "0: DISABLE,1: ENABLE,?..." group.long 0xF80++0x03 line.long 0x00 "HWVADGAIN,HWVAD Input Gain" bitfld.long 0x00 0.--3. "INPUTGAIN,Input Gain" "0: minus10bits,1: minus8bits,2: minus6bits,3: minus4bits,4: minus2bits,5: 0 bits (default),6: plus2bits,7: plus4bits,8: plus6bits,9: plus8bits,10: plus10bits,11: plus12bits,12: plus14bits,?..." group.long 0xF84++0x03 line.long 0x00 "HWVADHPFS,HWVAD Filter Control" bitfld.long 0x00 0.--1. "HPFS,The HPFS field chooses the High Pass filter in first part of HWVAD" "0: BYPASS,1: High Pass 1750 Hz,2: High Pass 215 Hz,?..." group.long 0xF88++0x03 line.long 0x00 "HWVADST10,HWVAD Control" bitfld.long 0x00 0. "ST10,STAGE 1" "0: Normal operation waiting for HWVAD trigger..,1: Reset internal interrupt flag by writing a.." group.long 0xF8C++0x03 line.long 0x00 "HWVADRSTT,HWVAD Filter Reset" bitfld.long 0x00 0. "RSST,Reset HWVAD" "0,1" group.long 0xF90++0x03 line.long 0x00 "HWVADTHGN,HWVAD Noise Estimator Gain" bitfld.long 0x00 0.--3. "THGN,Gain Factor for Noise Estimator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF94++0x03 line.long 0x00 "HWVADTHGS,HWVAD Signal Estimator Gain" bitfld.long 0x00 0.--3. "THGS,Signal Gain Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xF98++0x03 line.long 0x00 "HWVADLOWZ,HWVAD Noise Envelope Estimator" hexmask.long.word 0x00 0.--15. 1. "LOWZ,Average Noise-floor Value" repeat 2. (increment 0 1)(increment 0 0x100) tree "CHANNEL[$1]" group.long ($2+0x00)++0x03 line.long 0x00 "OSR,Oversample Rate" hexmask.long.byte 0x00 0.--7. 1. "OSR,Oversample Rate" group.long ($2+0x04)++0x03 line.long 0x00 "DIVHFCLK,DMIC Clock" bitfld.long 0x00 0.--3. "PDMDIV,PDM Clock Divider Value" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 6,5: Divide by 8,6: Divide by 12,7: Divide by 16,8: Divide by 24,9: Divide by 32,10: Divide by 48,11: Divide by 64,12: Divide by 96,13: Divide by 128,?..." group.long ($2+0x08)++0x03 line.long 0x00 "PREAC2FSCOEF,Compensation Filter for 2 FS" bitfld.long 0x00 0.--1. "COMP,Compensation value" "0: Compensation = 0,1: Compensation = -0.16,2: Compensation = -0.15,3: Compensation = -0.13" group.long ($2+0x0C)++0x03 line.long 0x00 "PREAC4FSCOEF,Compensation Filter for 4 FS" bitfld.long 0x00 0.--1. "COMP,Compensation value" "0: Compensation = 0,1: Compensation = -0.16,2: Compensation = -0.15,3: Compensation = -0.13" group.long ($2+0x10)++0x03 line.long 0x00 "GAINSHIFT,Decimator Gain Shift" bitfld.long 0x00 0.--4. "GAIN,Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long ($2+0x80)++0x03 line.long 0x00 "FIFO_CTRL,FIFO Control" bitfld.long 0x00 16.--20. "TRIGLVL,FIFO Trigger Level for Interrupt" "0: Trigger when the FIFO has received one entry..,1: Trigger when the FIFO has received two entries,?,?,?,?,?,?,?,?,?,?,?,?,14: Trigger when the FIFO has received 15 entries,15: Trigger when the FIFO has received 16..,?..." bitfld.long 0x00 3. "DMAEN,DMA Enable" "0: DMA requests are not enabled,1: DMA requests based on FIFO level are enabled" newline bitfld.long 0x00 2. "INTEN,Interrupt Enable" "0: FIFO level interrupts are not enabled,1: FIFO level interrupts are enabled" bitfld.long 0x00 1. "RESETN,FIFO Reset" "0: Reset the FIFO,1: Normal operation" newline bitfld.long 0x00 0. "ENABLE,FIFO Enable" "0: Disabled,1: FIFO is enabled" group.long ($2+0x84)++0x03 line.long 0x00 "FIFO_STATUS,FIFO Status" eventfld.long 0x00 2. "UNDERRUN,Underrun Detected (write 1 to clear)" "0,1" eventfld.long 0x00 1. "OVERRUN,Overrun Detected (write 1 to clear)" "0,1" newline eventfld.long 0x00 0. "INT,Status of Interrupt (write 1 to clear)" "0,1" rgroup.long ($2+0x88)++0x03 line.long 0x00 "FIFO_DATA,FIFO Data" hexmask.long.tbyte 0x00 0.--23. 1. "DATA,PCM Data" group.long ($2+0x8C)++0x03 line.long 0x00 "PHY_CTRL,Physical Control" bitfld.long 0x00 1. "PHY_HALF,Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator is providing)" "0: Standard half rate sampling,1: Use half rate sampling" bitfld.long 0x00 0. "PHY_FALL,Capture DMIC on Falling edge (0 means on rising)" "0: Capture PDM_DATA on the rising edge of PDM_CLK,1: Capture PDM_DATA on the falling edge of PDM_CLK" group.long ($2+0x90)++0x03 line.long 0x00 "DC_CTRL,DC Filter Control" bitfld.long 0x00 9. "SIGNEXTEND,Sign Extend" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SATURATEAT16BIT,Saturate at 16 Bit" "0: Do not Saturate,1: Saturate" newline bitfld.long 0x00 4.--7. "DCGAIN,DC Gain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "DCPOLE,DC Block Filter" "0: Flat Response no filter,1: HZ_155,2: HZ_78,3: HZ_39" tree.end repeat.end tree.end tree "ENC" repeat 2. (list 0. 1.) (list ad:0x400C4000 ad:0x400C6000) tree "ENC$1" base $2 group.word 0x00++0x01 line.word 0x00 "CTRL,Control Register" eventfld.word 0x00 15. "HIRQ,HOME Signal Transition Interrupt Request" "0: No transition on the HOME signal has occurred,1: A transition on the HOME signal has occurred" bitfld.word 0x00 14. "HIE,HOME Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x00 13. "HIP,Enable HOME to Initialize Position Counters UPOS and LPOS" "0: No action,1: HOME signal initializes the position counter" bitfld.word 0x00 12. "HNE,Use Negative Edge of HOME Input" "0: Use positive-going edge-to-trigger..,1: Use negative-going edge-to-trigger.." newline bitfld.word 0x00 11. "SWIP,Software-Triggered Initialization of Position Counters UPOS and LPOS" "0: No action,1: Initialize position counter (using upper and.." bitfld.word 0x00 10. "REV,Enable Reverse Direction Counting" "0: Count normally,1: Count in the reverse direction" newline bitfld.word 0x00 9. "PH1,Enable Signal Phase Count Mode" "0: Use the standard quadrature decoder where..,1: Bypass the quadrature decoder" eventfld.word 0x00 8. "XIRQ,INDEX Pulse Interrupt Request" "0: INDEX pulse has not occurred,1: INDEX pulse has occurred" newline bitfld.word 0x00 7. "XIE,INDEX Pulse Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x00 6. "XIP,INDEX Triggered Initialization of Position Counters UPOS and LPOS" "0: INDEX pulse does not initialize the position..,1: INDEX pulse initializes the position counter" newline bitfld.word 0x00 5. "XNE,Use Negative Edge of INDEX Pulse" "0: Use positive edge of INDEX pulse,1: Use negative edge of INDEX pulse" eventfld.word 0x00 4. "DIRQ,Watchdog Timeout Interrupt Request" "0: No Watchdog timeout interrupt has occurred,1: Watchdog timeout interrupt has occurred" newline bitfld.word 0x00 3. "DIE,Watchdog Timeout Interrupt Enable" "0: Disabled,1: Enabled" bitfld.word 0x00 2. "WDE,Watchdog Enable" "0: Disabled,1: Enabled" newline eventfld.word 0x00 1. "CMPIRQ,Compare Interrupt Request" "0: No match has occurred (the counter does not..,1: COMP match has occurred (the counter matches.." bitfld.word 0x00 0. "CMPIE,Compare Interrupt Enable" "0: Disabled,1: CMPIE_1" group.word 0x02++0x01 line.word 0x00 "FILT,Input Filter Register" bitfld.word 0x00 13.--15. "FILT_PRSC,prescaler divide IPbus clock to FILT clk" "0,1,2,3,4,5,6,7" bitfld.word 0x00 8.--10. "FILT_CNT,Input Filter Sample Count" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x00 0.--7. 1. "FILT_PER,Input Filter Sample Period" group.word 0x04++0x01 line.word 0x00 "WTR,Watchdog Timeout Register" hexmask.word 0x00 0.--15. 1. "WDOG,WDOG" group.word 0x06++0x01 line.word 0x00 "POSD,Position Difference Counter Register" hexmask.word 0x00 0.--15. 1. "POSD,POSD" rgroup.word 0x08++0x01 line.word 0x00 "POSDH,Position Difference Hold Register" hexmask.word 0x00 0.--15. 1. "POSDH,POSDH" group.word 0x0A++0x01 line.word 0x00 "REV,Revolution Counter Register" hexmask.word 0x00 0.--15. 1. "REV,REV" rgroup.word 0x0C++0x01 line.word 0x00 "REVH,Revolution Hold Register" hexmask.word 0x00 0.--15. 1. "REVH,REVH" group.word 0x0E++0x01 line.word 0x00 "UPOS,Upper Position Counter Register" hexmask.word 0x00 0.--15. 1. "POS,POS" group.word 0x10++0x01 line.word 0x00 "LPOS,Lower Position Counter Register" hexmask.word 0x00 0.--15. 1. "POS,POS" rgroup.word 0x12++0x01 line.word 0x00 "UPOSH,Upper Position Hold Register" hexmask.word 0x00 0.--15. 1. "POSH,POSH" rgroup.word 0x14++0x01 line.word 0x00 "LPOSH,Lower Position Hold Register" hexmask.word 0x00 0.--15. 1. "POSH,POSH" group.word 0x16++0x01 line.word 0x00 "UINIT,Upper Initialization Register" hexmask.word 0x00 0.--15. 1. "INIT,INIT" group.word 0x18++0x01 line.word 0x00 "LINIT,Lower Initialization Register" hexmask.word 0x00 0.--15. 1. "INIT,INIT" rgroup.word 0x1A++0x01 line.word 0x00 "IMR,Input Monitor Register" bitfld.word 0x00 7. "FPHA,FPHA" "0,1" bitfld.word 0x00 6. "FPHB,FPHB" "0,1" newline bitfld.word 0x00 5. "FIND,FIND" "0,1" bitfld.word 0x00 4. "FHOM,FHOM" "0,1" newline bitfld.word 0x00 3. "PHA,PHA" "0,1" bitfld.word 0x00 2. "PHB,PHB" "0,1" newline bitfld.word 0x00 1. "INDEX,INDEX" "0,1" bitfld.word 0x00 0. "HOME,HOME" "0,1" group.word 0x1C++0x01 line.word 0x00 "TST,Test Register" bitfld.word 0x00 15. "TEN,Test Mode Enable" "0: Disabled,1: Enabled" bitfld.word 0x00 14. "TCE,Test Counter Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x00 13. "QDN,Quadrature Decoder Negative Signal" "0: Generates a positive quadrature decoder signal,1: Generates a negative quadrature decoder signal" bitfld.word 0x00 8.--12. "TEST_PERIOD,TEST_PERIOD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.word.byte 0x00 0.--7. 1. "TEST_COUNT,TEST_COUNT" group.word 0x1E++0x01 line.word 0x00 "CTRL2,Control 2 Register" eventfld.word 0x00 11. "SABIRQ,Simultaneous PHASEA and PHASEB Change Interrupt Request" "0: No simultaneous change of PHASEA and PHASEB..,1: A simultaneous change of PHASEA and PHASEB.." bitfld.word 0x00 10. "SABIE,Simultaneous PHASEA and PHASEB Change Interrupt Enable" "0: Disabled,1: SABIE_1" newline bitfld.word 0x00 9. "OUTCTL,Output Control" "0: POSMATCH pulses when a match occurs between..,1: POSMATCH pulses when the UPOS LPOS REV or.." bitfld.word 0x00 8. "REVMOD,Revolution Counter Modulus Enable" "0: Use INDEX pulse to increment/decrement..,1: Use modulus counting roll-over/under to.." newline eventfld.word 0x00 7. "ROIRQ,Roll-over Interrupt Request" "0: No roll-over has occurred,1: Roll-over has occurred" bitfld.word 0x00 6. "ROIE,Roll-over Interrupt Enable" "0: Disabled,1: Enabled" newline eventfld.word 0x00 5. "RUIRQ,Roll-under Interrupt Request" "0: No roll-under has occurred,1: Roll-under has occurred" bitfld.word 0x00 4. "RUIE,Roll-under Interrupt Enable" "0: Disabled,1: Enabled" newline rbitfld.word 0x00 3. "DIR,Count Direction Flag" "0: Last count was in the down direction,1: Last count was in the up direction" bitfld.word 0x00 2. "MOD,Enable Modulo Counting" "0: Disable modulo counting,1: Enable modulo counting" newline bitfld.word 0x00 1. "UPDPOS,Update Position Registers" "0: No action for POSD REV UPOS and LPOS..,1: Clear POSD REV UPOS and LPOS registers on.." bitfld.word 0x00 0. "UPDHLD,Update Hold Registers" "0: Disable updates of hold registers on the..,1: Enable updates of hold registers on the.." group.word 0x20++0x01 line.word 0x00 "UMOD,Upper Modulus Register" hexmask.word 0x00 0.--15. 1. "MOD,MOD" group.word 0x22++0x01 line.word 0x00 "LMOD,Lower Modulus Register" hexmask.word 0x00 0.--15. 1. "MOD,MOD" group.word 0x24++0x01 line.word 0x00 "UCOMP,Upper Position Compare Register" hexmask.word 0x00 0.--15. 1. "COMP,COMP" group.word 0x26++0x01 line.word 0x00 "LCOMP,Lower Position Compare Register" hexmask.word 0x00 0.--15. 1. "COMP,COMP" rgroup.word 0x28++0x01 line.word 0x00 "LASTEDGE,Last Edge Time Register" hexmask.word 0x00 0.--15. 1. "LASTEDGE,Last Edge Time Counter" rgroup.word 0x2A++0x01 line.word 0x00 "LASTEDGEH,Last Edge Time Hold Register" hexmask.word 0x00 0.--15. 1. "LASTEDGEH,Last Edge Time Hold" rgroup.word 0x2C++0x01 line.word 0x00 "POSDPER,Position Difference Period Counter Register" hexmask.word 0x00 0.--15. 1. "POSDPER,Position difference period" rgroup.word 0x2E++0x01 line.word 0x00 "POSDPERBFR,Position Difference Period Buffer Register" hexmask.word 0x00 0.--15. 1. "POSDPERBFR,Position difference period buffer" rgroup.word 0x30++0x01 line.word 0x00 "POSDPERH,Position Difference Period Hold Register" hexmask.word 0x00 0.--15. 1. "POSDPERH,Position difference period hold" group.word 0x32++0x01 line.word 0x00 "CTRL3,Control 3 Register" bitfld.word 0x00 4.--7. "PRSC,Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0. "PMEN,Period measurement function enable" "0: Period measurement functions are not used,1: Period measurement functions are used" tree.end repeat.end tree.end endif tree "FLASH" base ad:0x40034000 wgroup.long 0x00++0x03 line.long 0x00 "CMD,command register" hexmask.long 0x00 0.--31. 1. "CMD,command register" wgroup.long 0x00++0x03 line.long 0x00 "CMD,Command" hexmask.long 0x00 0.--31. 1. "CMD,command register" wgroup.long 0x04++0x03 line.long 0x00 "EVENT,event register" bitfld.long 0x00 2. "ABORT,When bit is set a running program/erase command is aborted" "0,1" bitfld.long 0x00 1. "WAKEUP,When bit is set the controller wakes up from whatever low power or powerdown mode was active" "0,1" bitfld.long 0x00 0. "RST,When bit is set the controller and flash are reset" "0,1" wgroup.long 0x04++0x03 line.long 0x00 "EVENT,Event" bitfld.long 0x00 2. "ABORT,When bit is set a running program/erase command is aborted" "0,1" bitfld.long 0x00 1. "WAKEUP,When bit is set the controller wakes up from whatever low power or powerdown mode was active" "0,1" bitfld.long 0x00 0. "RST,When bit is set the controller and flash are reset" "0,1" group.long 0x10++0x03 line.long 0x00 "STARTA,start (or only) address for next flash command" hexmask.long.tbyte 0x00 0.--17. 1. "STARTA,Address / Start address for commands that take an address (range) as a parameter" group.long 0x10++0x03 line.long 0x00 "STARTA,Start address for next flash command" hexmask.long.word 0x00 0.--13. 1. "STARTA,Address / Start address for commands that take an address (range) as a parameter" group.long 0x14++0x03 line.long 0x00 "STOPA,end address for next flash command if command operates on address ranges" hexmask.long.tbyte 0x00 0.--17. 1. "STOPA,Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range)" group.long 0x14++0x03 line.long 0x00 "STOPA,End address for next flash command" hexmask.long.tbyte 0x00 0.--17. 1. "STOPA,Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range)" group.long 0x80++0x03 line.long 0x00 "DATAW[0],data register word 0-7 Memory data or command parameter or command result" hexmask.long 0x00 0.--31. 1. "DATAW,no description available" group.long 0x80++0x03 line.long 0x00 "DATAW[0],Data register" hexmask.long 0x00 0.--31. 1. "DATAW,Memory data or command parameter or command result" group.long 0x84++0x03 line.long 0x00 "DATAW[1],data register word 0-7 Memory data or command parameter or command result" hexmask.long 0x00 0.--31. 1. "DATAW,no description available" group.long 0x84++0x03 line.long 0x00 "DATAW[1],Data register" hexmask.long 0x00 0.--31. 1. "DATAW,Memory data or command parameter or command result" group.long 0x88++0x03 line.long 0x00 "DATAW[2],data register word 0-7 Memory data or command parameter or command result" hexmask.long 0x00 0.--31. 1. "DATAW,no description available" group.long 0x88++0x03 line.long 0x00 "DATAW[2],Data register" hexmask.long 0x00 0.--31. 1. "DATAW,Memory data or command parameter or command result" group.long 0x8C++0x03 line.long 0x00 "DATAW[3],data register word 0-7 Memory data or command parameter or command result" hexmask.long 0x00 0.--31. 1. "DATAW,no description available" group.long 0x8C++0x03 line.long 0x00 "DATAW[3],Data register" hexmask.long 0x00 0.--31. 1. "DATAW,Memory data or command parameter or command result" wgroup.long 0xFD8++0x03 line.long 0x00 "INTEN_CLR,Clear interrupt enables" bitfld.long 0x00 3. "ECC_ERR,Clears the ECC error interrupt" "0,1" bitfld.long 0x00 2. "DONE,Clears the done interrupt" "0,1" bitfld.long 0x00 1. "ERR,Clears the error interrupt" "0,1" bitfld.long 0x00 0. "FAIL,Clears the fail interrupt" "0,1" wgroup.long 0xFD8++0x03 line.long 0x00 "INT_CLR_ENABLE,Clear interrupt enable bits" bitfld.long 0x00 3. "ECC_ERR,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1" bitfld.long 0x00 2. "DONE,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1" bitfld.long 0x00 1. "ERR,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1" bitfld.long 0x00 0. "FAIL,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1" wgroup.long 0xFDC++0x03 line.long 0x00 "INT_SET_ENABLE,Set interrupt enable bits" bitfld.long 0x00 3. "ECC_ERR,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1" bitfld.long 0x00 2. "DONE,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1" bitfld.long 0x00 1. "ERR,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1" bitfld.long 0x00 0. "FAIL,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1" wgroup.long 0xFDC++0x03 line.long 0x00 "INTEN_SET,Set interrupt enables" bitfld.long 0x00 3. "ECC_ERR,Sets ECC error interrupt" "0,1" bitfld.long 0x00 2. "DONE,Sets done interrupt" "0,1" bitfld.long 0x00 1. "ERR,Sets error interrupt" "0,1" bitfld.long 0x00 0. "FAIL,Sets Fail interrupt" "0,1" rgroup.long 0xFE0++0x03 line.long 0x00 "INTSTAT,Interrupt status" bitfld.long 0x00 3. "ECC_ERR,This status bit is set if during a memory read operation (either a user-requested read or a speculative read or reads performed by a controller command) a correctable or uncorrectable error is detected by ECC decoding logic" "0,1" bitfld.long 0x00 2. "DONE,This status bit is set at the end of command execution" "0,1" bitfld.long 0x00 1. "ERR,This status bit is set if execution of an illegal command is detected" "0,1" bitfld.long 0x00 0. "FAIL,This status bit is set if execution of a (legal) command failed" "0,1" group.long 0xFE0++0x03 line.long 0x00 "INT_STATUS,Interrupt status bits" rbitfld.long 0x00 3. "ECC_ERR,This status bit is set if during a memory read operation (either a user-requested read or a speculative read or reads performed by a controller command) a correctable or uncorrectable error is detected by ECC decoding logic" "0,1" rbitfld.long 0x00 2. "DONE,This status bit is set at the end of command execution" "0,1" rbitfld.long 0x00 1. "ERR,This status bit is set if execution of an illegal command is detected" "0,1" rbitfld.long 0x00 0. "FAIL,This status bit is set if execution of a (legal) command failed" "0,1" rgroup.long 0xFE4++0x03 line.long 0x00 "INTEN,Interrupt enable" bitfld.long 0x00 3. "ECC_ERR,Enables ECC error interrupt" "0,1" bitfld.long 0x00 2. "DONE,Enables done interrupt" "0,1" bitfld.long 0x00 1. "ERR,Enables error interrupt" "0,1" bitfld.long 0x00 0. "FAIL,Enables fail interrupt" "0,1" group.long 0xFE4++0x03 line.long 0x00 "INT_ENABLE,Interrupt enable bits" rbitfld.long 0x00 3. "ECC_ERR,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1" rbitfld.long 0x00 2. "DONE,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1" rbitfld.long 0x00 1. "ERR,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1" rbitfld.long 0x00 0. "FAIL,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1" wgroup.long 0xFE8++0x03 line.long 0x00 "INTSTAT_CLR,Clear interrupt status" bitfld.long 0x00 3. "ECC_ERR,Clears ECC error interrupt status" "0,1" bitfld.long 0x00 2. "DONE,Clears done interrupt status" "0,1" bitfld.long 0x00 1. "ERR,Clears error interrupt status" "0,1" bitfld.long 0x00 0. "FAIL,Clears fail interrupt status" "0,1" wgroup.long 0xFE8++0x03 line.long 0x00 "INT_CLR_STATUS,Clear interrupt status bits" bitfld.long 0x00 3. "ECC_ERR,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1" bitfld.long 0x00 2. "DONE,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1" bitfld.long 0x00 1. "ERR,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1" bitfld.long 0x00 0. "FAIL,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1" wgroup.long 0xFEC++0x03 line.long 0x00 "INTSTAT_SET,Set interrupt status" bitfld.long 0x00 3. "ECC_ERR,Sets ECC error interrupt status" "0,1" bitfld.long 0x00 2. "DONE,Sets done interrupt status" "0,1" bitfld.long 0x00 1. "ERR,Sets error interrupt status" "0,1" bitfld.long 0x00 0. "FAIL,Sets fail interrupt status" "0,1" wgroup.long 0xFEC++0x03 line.long 0x00 "INT_SET_STATUS,Set interrupt status bits" bitfld.long 0x00 3. "ECC_ERR,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1" bitfld.long 0x00 2. "DONE,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1" bitfld.long 0x00 1. "ERR,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1" bitfld.long 0x00 0. "FAIL,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1" rgroup.long 0xFFC++0x03 line.long 0x00 "MODULE_ID,Controller+Memory module identification" hexmask.long.word 0x00 16.--31. 1. "ID,Identifier" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture i" rgroup.long 0xFFC++0x03 line.long 0x00 "MODULE_ID,Module identification" hexmask.long.word 0x00 16.--31. 1. "ID,Identifier" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "FLASH_CFPA" repeat 2. (list 0. 1.) (list ad:0x3E000 ad:0x3E200) (list ad:0x9E000 ad:0x9E200) tree "FLASH_CFPA$1" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") base $2 elif cpuis("LPC5526*")||cpuis("LPC5528*") base $3 endif group.long 0x00++0x03 line.long 0x00 "HEADER,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x04++0x03 line.long 0x00 "VERSION,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x08++0x03 line.long 0x00 "S_FW_Version,Secure firmware version (Monotonic counter)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x0C++0x03 line.long 0x00 "NS_FW_Version,Non-Secure firmware version (Monotonic counter)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x10++0x03 line.long 0x00 "IMAGE_KEY_REVOKE,Image key revocation ID (Monotonic counter)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x18++0x03 line.long 0x00 "ROTKH_REVOKE,no description available" bitfld.long 0x00 6.--7. "RoTK3_EN,RoT Key 3 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" bitfld.long 0x00 4.--5. "RoTK2_EN,RoT Key 2 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" bitfld.long 0x00 2.--3. "RoTK1_EN,RoT Key 1 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" newline bitfld.long 0x00 0.--1. "RoTK0_EN,RoT Key 0 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" group.long 0x1C++0x03 line.long 0x00 "VENDOR_USAGE,no description available" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" hexmask.long.word 0x00 0.--15. 1. "DBG_VENDOR_USAGE,DBG_VENDOR_USAGE" group.long 0x20++0x03 line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1" bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 7. "FA_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" group.long 0x20++0x03 line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1" bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" group.long 0x24++0x03 line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" group.long 0x24++0x03 line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 7. "FA_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" group.long 0x28++0x03 line.long 0x00 "ENABLE_FA_MODE,Enable FA mode" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x2C++0x03 line.long 0x00 "CMPA_PROG_IN_PROGRESS,CMPA Page programming on going" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x30++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x30++0x03 line.long 0x00 "PRINCE_REGION0_IV_HEADER0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x34++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x34++0x03 line.long 0x00 "PRINCE_REGION0_IV_HEADER1,no description available" bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3" group.long 0x38++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x38++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x3C++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "1" "2" )(list 0x0 0x4 ) group.long ($2+0x3C)++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x40++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE4,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x44++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x44++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x48++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY4,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x48++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x4C++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "7" "8" )(list 0x0 0x4 ) group.long ($2+0x4C)++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "6" "7" )(list 0x0 0x4 ) group.long ($2+0x50)++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x54++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x58++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY8,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x58++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x5C++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "11" "12" )(list 0x0 0x4 ) group.long ($2+0x5C)++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x60++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x64++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE13,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x64++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x68++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x68++0x03 line.long 0x00 "PRINCE_REGION1_IV_HEADER0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x6C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x6C++0x03 line.long 0x00 "PRINCE_REGION1_IV_HEADER1,no description available" bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3" group.long 0x70++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x70++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x74++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "3" "4" )(list 0x0 0x4 ) group.long ($2+0x74)++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "2" "3" )(list 0x0 0x4 ) group.long ($2+0x78)++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x7C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x80++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY4,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x80++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x84++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "7" "8" )(list 0x0 0x4 ) group.long ($2+0x84)++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x88++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x8C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "7" "8" )(list 0x0 0x4 ) group.long ($2+0x8C)++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x90++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x94++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x94++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x98++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x98++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE12,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x9C++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x9C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE13,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xA0++0x03 line.long 0x00 "PRINCE_REGION2_IV_HEADER0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0xA0)++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0xA4++0x03 line.long 0x00 "PRINCE_REGION2_IV_HEADER1,no description available" bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3" group.long 0xA8++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xA8++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xAC++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xAC++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xB0++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "4" "5" )(list 0x0 0x4 ) group.long ($2+0xB0)++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "3" "4" )(list 0x0 0x4 ) group.long ($2+0xB4)++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0xB8++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xBC++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xBC++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE7,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xC0++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xC0++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE8,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xC4++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY7,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "9" "10" )(list 0x0 0x4 ) group.long ($2+0xC4)++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "8" "9" )(list 0x0 0x4 ) group.long ($2+0xC8)++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0xCC++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD0++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD0++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE12,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD4++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD4++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE13,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 56. (increment 0 1) (increment 0 0x04) group.long ($2+0x100)++0x03 line.long 0x00 "CUSTOMER_DEFINED[$1],Customer Defined (Programable through ROM API $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x1E0)++0x03 line.long 0x00 "SHA256_DIGEST[$1],SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end tree.end repeat.end tree "FLASH_CFPA_SCRATCH" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") base ad:0x3DE00 elif cpuis("LPC5526*")||cpuis("LPC5528*") base ad:0x9DE00 endif group.long 0x00++0x03 line.long 0x00 "HEADER,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x04++0x03 line.long 0x00 "VERSION,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x08++0x03 line.long 0x00 "S_FW_Version,Secure firmware version (Monotonic counter)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x0C++0x03 line.long 0x00 "NS_FW_Version,Non-Secure firmware version (Monotonic counter)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x10++0x03 line.long 0x00 "IMAGE_KEY_REVOKE,Image key revocation ID (Monotonic counter)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x18++0x03 line.long 0x00 "ROTKH_REVOKE,no description available" bitfld.long 0x00 6.--7. "RoTK3_EN,RoT Key 3 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" bitfld.long 0x00 4.--5. "RoTK2_EN,RoT Key 2 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" bitfld.long 0x00 2.--3. "RoTK1_EN,RoT Key 1 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" newline bitfld.long 0x00 0.--1. "RoTK0_EN,RoT Key 0 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked" group.long 0x1C++0x03 line.long 0x00 "VENDOR_USAGE,no description available" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" hexmask.long.word 0x00 0.--15. 1. "DBG_VENDOR_USAGE,DBG_VENDOR_USAGE" group.long 0x20++0x03 line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1" bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 7. "FA_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" group.long 0x20++0x03 line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1" bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" group.long 0x24++0x03 line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" group.long 0x24++0x03 line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 7. "FA_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE" bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" group.long 0x28++0x03 line.long 0x00 "ENABLE_FA_MODE,Enable FA mode" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x2C++0x03 line.long 0x00 "CMPA_PROG_IN_PROGRESS,CMPA Page programming on going" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x30++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x30++0x03 line.long 0x00 "PRINCE_REGION0_IV_HEADER0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x34++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x34++0x03 line.long 0x00 "PRINCE_REGION0_IV_HEADER1,no description available" bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3" group.long 0x38++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x38++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x3C++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "1" "2" )(list 0x0 0x4 ) group.long ($2+0x3C)++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x40++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE4,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x44++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x44++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x48++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY4,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x48++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x4C++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "7" "8" )(list 0x0 0x4 ) group.long ($2+0x4C)++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "6" "7" )(list 0x0 0x4 ) group.long ($2+0x50)++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x54++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x58++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY8,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x58++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x5C++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "11" "12" )(list 0x0 0x4 ) group.long ($2+0x5C)++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x60++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x64++0x03 line.long 0x00 "PRINCE_REGION0_IV_CODE13,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x64++0x03 line.long 0x00 "PRINCE_REGION0_IV_BODY11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x68++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x68++0x03 line.long 0x00 "PRINCE_REGION1_IV_HEADER0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x6C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x6C++0x03 line.long 0x00 "PRINCE_REGION1_IV_HEADER1,no description available" bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3" group.long 0x70++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x70++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x74++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "3" "4" )(list 0x0 0x4 ) group.long ($2+0x74)++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "2" "3" )(list 0x0 0x4 ) group.long ($2+0x78)++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x7C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x80++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY4,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x80++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x84++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "7" "8" )(list 0x0 0x4 ) group.long ($2+0x84)++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x88++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x8C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "7" "8" )(list 0x0 0x4 ) group.long ($2+0x8C)++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x90++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x94++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY9,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x94++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x98++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x98++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE12,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x9C++0x03 line.long 0x00 "PRINCE_REGION1_IV_BODY11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x9C++0x03 line.long 0x00 "PRINCE_REGION1_IV_CODE13,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xA0++0x03 line.long 0x00 "PRINCE_REGION2_IV_HEADER0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0xA0)++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0xA4++0x03 line.long 0x00 "PRINCE_REGION2_IV_HEADER1,no description available" bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3" group.long 0xA8++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xA8++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xAC++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xAC++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xB0++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "4" "5" )(list 0x0 0x4 ) group.long ($2+0xB0)++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "3" "4" )(list 0x0 0x4 ) group.long ($2+0xB4)++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0xB8++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xBC++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY5,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xBC++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE7,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xC0++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY6,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xC0++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE8,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xC4++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY7,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "9" "10" )(list 0x0 0x4 ) group.long ($2+0xC4)++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 2. (strings "8" "9" )(list 0x0 0x4 ) group.long ($2+0xC8)++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0xCC++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD0++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY10,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD0++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE12,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD4++0x03 line.long 0x00 "PRINCE_REGION2_IV_BODY11,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xD4++0x03 line.long 0x00 "PRINCE_REGION2_IV_CODE13,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 56. (increment 0 1) (increment 0 0x04) group.long ($2+0x100)++0x03 line.long 0x00 "CUSTOMER_DEFINED[$1],Customer Defined (Programable through ROM API $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x1E0)++0x03 line.long 0x00 "SHA256_DIGEST[$1],SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end tree.end tree.end tree "FLASH_CMPA" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") base ad:0x3E400 elif cpuis("LPC5526*")||cpuis("LPC5528*") base ad:0x9E400 endif group.long 0x00++0x03 line.long 0x00 "BOOT_CFG,no description available" hexmask.long.byte 0x00 24.--31. 1. "BOOT_FAILURE_PIN,GPIO port and pin number to use for indicating failure reason" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 7.--8. "BOOT_SPEED,Core clock" "0: Defined by NMPA.SYSTEM_SPEED_CODE,?,2: 48MHz FRO,?..." newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 7.--8. "BOOT_SPEED,Core clock" "0: Defined by NMPA.SYSTEM_SPEED_CODE,1: 96MHz FRO,2: 48MHz FRO,?..." newline endif bitfld.long 0x00 4.--6. "DEFAULT_ISP_MODE,Default ISP mode" "0: AUTO_ISP,1: USB_HID_ISP,2: UART_ISP,3: SPI Slave ISP,4: I2C Slave ISP,?,?,7: Disable ISP fall through" group.long 0x04++0x03 line.long 0x00 "SPI_FLASH_CFG,no description available" bitfld.long 0x00 0.--4. "SPI_RECOVERY_BOOT_EN,SPI flash recovery boot is enabled if non-zero value is written to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x08++0x03 line.long 0x00 "USB_ID,no description available" hexmask.long.word 0x00 16.--31. 1. "USB_PRODUCT_ID,no description available" newline hexmask.long.word 0x00 0.--15. 1. "USB_VENDOR_ID,no description available" group.long 0x0C++0x03 line.long 0x00 "SDIO_CFG,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x10++0x03 line.long 0x00 "CC_SOCU_PIN,no description available" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" newline bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command enable" "0: Use DAP to enable,1: Fixed state" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 7. "FA_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state" newline endif bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline endif bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state" newline bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state" group.long 0x14++0x03 line.long 0x00 "CC_SOCU_DFLT,no description available" hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command fixed state" "0: DISABLE,1: ENABLE" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 7. "FA_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE" newline endif bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug fixed state" "0: DISABLE,1: ENABLE" newline endif bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE" group.long 0x18++0x03 line.long 0x00 "VENDOR_USAGE,no description available" hexmask.long.word 0x00 16.--31. 1. "VENDOR_USAGE,Upper 16 bits of vendor usage field defined in DAP" group.long 0x1C++0x03 line.long 0x00 "SECURE_BOOT_CFG,Secure boot configuration flags" bitfld.long 0x00 30.--31. "SEC_BOOT_EN,Secure boot enable" "0: Plain image (internal flash with or without..,1: Boot signed images,2: Boot signed images,3: Boot signed images" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 22.--23. "BOOT_SEED_INC_EPOCH,Include security epoch area in BOOT_SEED computation" "0: not included,1: included,2: included,3: included" newline bitfld.long 0x00 20.--21. "BOOT_SEED_CUST_CFG,Include CMPA area in BOOT SEED computation" "0: not included,1: included,2: included,3: included" newline bitfld.long 0x00 18.--19. "BOOT_SEED_INC_NXP_CFG,Include NXP area in BOOT SEED computation" "0: not included,1: included,2: included,3: included" newline bitfld.long 0x00 16.--17. "SKIP_BOOT_SEED,Skip boot seed computation" "0: Enable BOOT_SEED,1: Disable BOOT_SEED,2: Disable BOOT_SEED,3: Disable BOOT_SEED" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 14.--15. "DICE_INC_SEC_EPOCH,Include security EPOCH in DICE" "0,1,2,3" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 14.--15. "DICE_INC_SEC_EPOCH,Include security EPOCH in DICE" "0: not included,1: included,2: included,3: included" newline endif bitfld.long 0x00 12.--13. "BLOCK_ENROLL,Block PUF enrollement" "0: Allow PUF enroll operation,1: Disable PUF enroll operation,2: Disable PUF enroll operation,3: Disable PUF enroll operation" newline bitfld.long 0x00 10.--11. "BLOCK_SET_KEY,Block PUF key code generation" "0: Allow PUF Key Code generation,1: Disable PUF Key Code generation,2: Disable PUF Key Code generation,3: Disable PUF Key Code generation" newline bitfld.long 0x00 8.--9. "TZM_IMAGE_TYPE,TrustZone-M mode" "0: TZ-M image mode is taken from application..,1: TZ-M disabled image boots to non-secure mode,2: TZ-M enabled image boots to secure mode,3: TZ-M enabled image with TZ-M preset boot to.." newline bitfld.long 0x00 6.--7. "SKIP_DICE,Skip DICE computation" "0: Enable DICE,1: Disable DICE,2: Disable DICE,3: Disable DICE" newline bitfld.long 0x00 4.--5. "DICE_CUST_CFG,Include Customer factory area (including keys) in DICE computation" "0: not included,1: included,2: included,3: included" newline bitfld.long 0x00 2.--3. "DICE_INC_NXP_CFG,Include NXP area in DICE computation" "0: not included,1: included,2: included,3: included" newline bitfld.long 0x00 0.--1. "RSA4K,Use RSA4096 keys only" "0: Allow RSA2048 and higher,1: RSA4096 only,2: RSA4096 only,3: RSA4096 only" group.long 0x20++0x03 line.long 0x00 "PRINCE_BASE_ADDR,no description available" bitfld.long 0x00 28.--29. "REG2_ERASE_CHECK_EN,For PRINCE region2 enable checking whether all encrypted pages are erased together" "0: Region is disabled,1: Region is enabled,2: Region is enabled,3: Region is enabled" newline bitfld.long 0x00 26.--27. "REG1_ERASE_CHECK_EN,For PRINCE region1 enable checking whether all encrypted pages are erased together" "0: Region is disabled,1: Region is enabled,2: Region is enabled,3: Region is enabled" newline bitfld.long 0x00 24.--25. "REG0_ERASE_CHECK_EN,For PRINCE region0 enable checking whether all encrypted pages are erased together" "0: Region is disabled,1: Region is enabled,2: Region is enabled,3: Region is enabled" newline bitfld.long 0x00 20.--21. "LOCK_REG1,Lock PRINCE region1 settings" "0: Region is not locked,1: Region is locked,2: Region is locked,3: Region is locked" newline bitfld.long 0x00 18.--19. "LOCK_REG0,Lock PRINCE region0 settings" "0: Region is not locked,1: Region is locked,2: Region is locked,3: Region is locked" newline bitfld.long 0x00 8.--11. "ADDR2_PRG,Programmable portion of the base address of region 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "ADDR1_PRG,Programmable portion of the base address of region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "ADDR0_PRG,Programmable portion of the base address of region 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x03 line.long 0x00 "PRINCE_SR_0,Region 0 sub-region enable" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x28++0x03 line.long 0x00 "PRINCE_SR_1,Region 1 sub-region enable" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x2C++0x03 line.long 0x00 "PRINCE_SR_2,Region 2 sub-region enable" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x30++0x03 line.long 0x00 "XTAL_32KHZ_CAPABANK_TRIM,Xtal 32kHz capabank triming" hexmask.long.word 0x00 21.--30. 1. "PCB_XOUT_PARA_CAP_PF_X100,PCB XOUT parasitic capacitance pF x 100" newline hexmask.long.word 0x00 11.--20. 1. "PCB_XIN_PARA_CAP_PF_X100,PCB XIN parasitic capacitance pF x 100" newline hexmask.long.word 0x00 1.--10. 1. "XTAL_LOAD_CAP_IEC_PF_X100,Load capacitance pF x 100" newline bitfld.long 0x00 0. "TRIM_VALID,XTAL 32kHz capa bank trimmings" "0: Capa Bank trimmings not valid,1: Capa Bank trimmings valid" group.long 0x34++0x03 line.long 0x00 "XTAL_16MHZ_CAPABANK_TRIM,Xtal 16MHz capabank triming" hexmask.long.word 0x00 21.--30. 1. "PCB_XOUT_PARA_CAP_PF_X100,PCB XOUT parasitic capacitance pF x 100" newline hexmask.long.word 0x00 11.--20. 1. "PCB_XIN_PARA_CAP_PF_X100,PCB XIN parasitic capacitance pF x 100" newline hexmask.long.word 0x00 1.--10. 1. "XTAL_LOAD_CAP_IEC_PF_X100,Load capacitance pF x 100" newline bitfld.long 0x00 0. "TRIM_VALID,XTAL 16MHz capa bank trimmings" "0: Capa Bank trimmings not valid,1: Capa Bank trimmings valid" group.long 0x38++0x03 line.long 0x00 "FLASH_REMAP_SIZE,This 32-bit register contains the size of the image to remap in bytes" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x3C++0x03 line.long 0x00 "FLASH_REMAP_OFFSET,This 32-bit register contains the offset by which the image is to be remapped" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 8. (increment 0 1) (increment 0 0x4) group.long ($2+0x50)++0x03 line.long 0x00 "ROTKH[$1],ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 56. (increment 0 1) (increment 0 0x04) group.long ($2+0x100)++0x03 line.long 0x00 "CUSTOMER_DEFINED[$1],Customer Defined (Programable through ROM API $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x1E0)++0x03 line.long 0x00 "SHA256_DIGEST[$1],SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end tree.end tree "FLASH_KEY_STORE" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") base ad:0x3E600 elif cpuis("LPC5526*")||cpuis("LPC5528*") base ad:0x9E600 endif group.long 0x00++0x03 line.long 0x00 "HEADER,Valid Key Sore Header : 0x95959595" hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x04++0x03 line.long 0x00 "puf_discharge_time_in_ms,puf discharge time in ms" hexmask.long 0x00 0.--31. 1. "FIELD," repeat 298. (increment 0 1) (increment 0 0x4) group.long ($2+0x08)++0x03 line.long 0x00 "ACTIVATION_CODE[$1],$1" hexmask.long 0x00 0.--31. 1. "FIELD," repeat.end group.long 0x4B0++0x03 line.long 0x00 "SBKEY_HEADER0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4B0++0x03 line.long 0x00 "SBKEY_KEY_CODE0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4B4++0x03 line.long 0x00 "SBKEY_HEADER1," bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3" group.long 0x4B4++0x03 line.long 0x00 "SBKEY_KEY_CODE1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4B8++0x03 line.long 0x00 "SBKEY_BODY0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4B8++0x03 line.long 0x00 "SBKEY_KEY_CODE2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4BC++0x03 line.long 0x00 "SBKEY_BODY1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4BC++0x03 line.long 0x00 "SBKEY_KEY_CODE3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4C0++0x03 line.long 0x00 "SBKEY_BODY2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4C0++0x03 line.long 0x00 "SBKEY_KEY_CODE4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4C4++0x03 line.long 0x00 "SBKEY_BODY3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4C4++0x03 line.long 0x00 "SBKEY_KEY_CODE5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4C8++0x03 line.long 0x00 "SBKEY_BODY4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4C8++0x03 line.long 0x00 "SBKEY_KEY_CODE6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4CC++0x03 line.long 0x00 "SBKEY_BODY5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4CC++0x03 line.long 0x00 "SBKEY_KEY_CODE7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4D0++0x03 line.long 0x00 "SBKEY_BODY6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4D0++0x03 line.long 0x00 "SBKEY_KEY_CODE8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4D4++0x03 line.long 0x00 "SBKEY_BODY7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4D4++0x03 line.long 0x00 "SBKEY_KEY_CODE9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4D8++0x03 line.long 0x00 "SBKEY_BODY8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4D8++0x03 line.long 0x00 "SBKEY_KEY_CODE10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4DC++0x03 line.long 0x00 "SBKEY_BODY9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4DC++0x03 line.long 0x00 "SBKEY_KEY_CODE11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4E0++0x03 line.long 0x00 "SBKEY_BODY10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4E0++0x03 line.long 0x00 "SBKEY_KEY_CODE12," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4E4++0x03 line.long 0x00 "SBKEY_BODY11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4E4++0x03 line.long 0x00 "SBKEY_KEY_CODE13," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4E8++0x03 line.long 0x00 "USER_KEK_HEADER0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4E8++0x03 line.long 0x00 "USER_KEK_KEY_CODE0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4EC++0x03 line.long 0x00 "USER_KEK_HEADER1," bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3" group.long 0x4EC++0x03 line.long 0x00 "USER_KEK_KEY_CODE1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4F0++0x03 line.long 0x00 "USER_KEK_BODY0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4F0++0x03 line.long 0x00 "USER_KEK_KEY_CODE2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4F4++0x03 line.long 0x00 "USER_KEK_BODY1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4F4++0x03 line.long 0x00 "USER_KEK_KEY_CODE3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4F8++0x03 line.long 0x00 "USER_KEK_BODY2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4F8++0x03 line.long 0x00 "USER_KEK_KEY_CODE4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4FC++0x03 line.long 0x00 "USER_KEK_BODY3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x4FC++0x03 line.long 0x00 "USER_KEK_KEY_CODE5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x500++0x03 line.long 0x00 "USER_KEK_BODY4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x500++0x03 line.long 0x00 "USER_KEK_KEY_CODE6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x504++0x03 line.long 0x00 "USER_KEK_BODY5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x504++0x03 line.long 0x00 "USER_KEK_KEY_CODE7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x508++0x03 line.long 0x00 "USER_KEK_BODY6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x508++0x03 line.long 0x00 "USER_KEK_KEY_CODE8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x50C++0x03 line.long 0x00 "USER_KEK_BODY7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x50C++0x03 line.long 0x00 "USER_KEK_KEY_CODE9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x510++0x03 line.long 0x00 "USER_KEK_BODY8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x510++0x03 line.long 0x00 "USER_KEK_KEY_CODE10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x514++0x03 line.long 0x00 "USER_KEK_BODY9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x514++0x03 line.long 0x00 "USER_KEK_KEY_CODE11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x518++0x03 line.long 0x00 "USER_KEK_BODY10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x518++0x03 line.long 0x00 "USER_KEK_KEY_CODE12," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x51C++0x03 line.long 0x00 "USER_KEK_BODY11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x51C++0x03 line.long 0x00 "USER_KEK_KEY_CODE13," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x520++0x03 line.long 0x00 "UDS_HEADER0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x520++0x03 line.long 0x00 "UDS_KEY_CODE0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x524++0x03 line.long 0x00 "UDS_HEADER1," bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3" group.long 0x524++0x03 line.long 0x00 "UDS_KEY_CODE1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x528++0x03 line.long 0x00 "UDS_BODY0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x528++0x03 line.long 0x00 "UDS_KEY_CODE2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x52C++0x03 line.long 0x00 "UDS_BODY1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x52C++0x03 line.long 0x00 "UDS_KEY_CODE3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x530++0x03 line.long 0x00 "UDS_BODY2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x530++0x03 line.long 0x00 "UDS_KEY_CODE4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x534++0x03 line.long 0x00 "UDS_BODY3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x534++0x03 line.long 0x00 "UDS_KEY_CODE5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x538++0x03 line.long 0x00 "UDS_BODY4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x538++0x03 line.long 0x00 "UDS_KEY_CODE6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x53C++0x03 line.long 0x00 "UDS_BODY5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x53C++0x03 line.long 0x00 "UDS_KEY_CODE7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x540++0x03 line.long 0x00 "UDS_BODY6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x540++0x03 line.long 0x00 "UDS_KEY_CODE8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x544++0x03 line.long 0x00 "UDS_BODY7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x544++0x03 line.long 0x00 "UDS_KEY_CODE9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x548++0x03 line.long 0x00 "UDS_BODY8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x548++0x03 line.long 0x00 "UDS_KEY_CODE10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x54C++0x03 line.long 0x00 "UDS_BODY9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x54C++0x03 line.long 0x00 "UDS_KEY_CODE11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x550++0x03 line.long 0x00 "UDS_BODY10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x550++0x03 line.long 0x00 "UDS_KEY_CODE12," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x554++0x03 line.long 0x00 "UDS_BODY11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x554++0x03 line.long 0x00 "UDS_KEY_CODE13," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x558++0x03 line.long 0x00 "PRINCE_REGION0_HEADER0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x558++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x55C++0x03 line.long 0x00 "PRINCE_REGION0_HEADER1," bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3" group.long 0x55C++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x560++0x03 line.long 0x00 "PRINCE_REGION0_BODY0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x560++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x564++0x03 line.long 0x00 "PRINCE_REGION0_BODY1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x564++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x568++0x03 line.long 0x00 "PRINCE_REGION0_BODY2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x568++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x56C++0x03 line.long 0x00 "PRINCE_REGION0_BODY3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x56C++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x570++0x03 line.long 0x00 "PRINCE_REGION0_BODY4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x570++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x574++0x03 line.long 0x00 "PRINCE_REGION0_BODY5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x574++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x578++0x03 line.long 0x00 "PRINCE_REGION0_BODY6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x578++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x57C++0x03 line.long 0x00 "PRINCE_REGION0_BODY7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x57C++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x580++0x03 line.long 0x00 "PRINCE_REGION0_BODY8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x580++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x584++0x03 line.long 0x00 "PRINCE_REGION0_BODY9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x584++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x588++0x03 line.long 0x00 "PRINCE_REGION0_BODY10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x588++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE12," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x58C++0x03 line.long 0x00 "PRINCE_REGION0_BODY11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x58C++0x03 line.long 0x00 "PRINCE_REGION0_KEY_CODE13," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x590++0x03 line.long 0x00 "PRINCE_REGION1_HEADER0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x590++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x594++0x03 line.long 0x00 "PRINCE_REGION1_HEADER1," bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3" group.long 0x594++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x598++0x03 line.long 0x00 "PRINCE_REGION1_BODY0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x598++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x59C++0x03 line.long 0x00 "PRINCE_REGION1_BODY1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x59C++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5A0++0x03 line.long 0x00 "PRINCE_REGION1_BODY2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5A0++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5A4++0x03 line.long 0x00 "PRINCE_REGION1_BODY3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5A4++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5A8++0x03 line.long 0x00 "PRINCE_REGION1_BODY4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5A8++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5AC++0x03 line.long 0x00 "PRINCE_REGION1_BODY5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5AC++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5B0++0x03 line.long 0x00 "PRINCE_REGION1_BODY6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5B0++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5B4++0x03 line.long 0x00 "PRINCE_REGION1_BODY7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5B4++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5B8++0x03 line.long 0x00 "PRINCE_REGION1_BODY8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5B8++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5BC++0x03 line.long 0x00 "PRINCE_REGION1_BODY9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5BC++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5C0++0x03 line.long 0x00 "PRINCE_REGION1_BODY10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5C0++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE12," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5C4++0x03 line.long 0x00 "PRINCE_REGION1_BODY11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5C4++0x03 line.long 0x00 "PRINCE_REGION1_KEY_CODE13," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5C8++0x03 line.long 0x00 "PRINCE_REGION2_HEADER0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5C8++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5CC++0x03 line.long 0x00 "PRINCE_REGION2_HEADER1," bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3" group.long 0x5CC++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5D0++0x03 line.long 0x00 "PRINCE_REGION2_BODY0," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5D0++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5D4++0x03 line.long 0x00 "PRINCE_REGION2_BODY1," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5D4++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5D8++0x03 line.long 0x00 "PRINCE_REGION2_BODY2," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5D8++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5DC++0x03 line.long 0x00 "PRINCE_REGION2_BODY3," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5DC++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5E0++0x03 line.long 0x00 "PRINCE_REGION2_BODY4," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5E0++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5E4++0x03 line.long 0x00 "PRINCE_REGION2_BODY5," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5E4++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5E8++0x03 line.long 0x00 "PRINCE_REGION2_BODY6," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5E8++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5EC++0x03 line.long 0x00 "PRINCE_REGION2_BODY7," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5EC++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5F0++0x03 line.long 0x00 "PRINCE_REGION2_BODY8," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5F0++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5F4++0x03 line.long 0x00 "PRINCE_REGION2_BODY9," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5F4++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5F8++0x03 line.long 0x00 "PRINCE_REGION2_BODY10," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5F8++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE12," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5FC++0x03 line.long 0x00 "PRINCE_REGION2_BODY11," hexmask.long 0x00 0.--31. 1. "FIELD," group.long 0x5FC++0x03 line.long 0x00 "PRINCE_REGION2_KEY_CODE13," hexmask.long 0x00 0.--31. 1. "FIELD," tree.end endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") tree "FLASH_NMPA" base ad:0x3FC00 group.long 0x00++0x03 line.long 0x00 "GPO0_0,GPO0 register 0 description" hexmask.long.word 0x00 16.--31. 1. "FIELD,no description available" newline hexmask.long.word 0x00 7.--15. 1. "FRO32K_CAPCAL,no description available" newline bitfld.long 0x00 4.--6. "FRO32K_PTAT,no description available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--3. "FRO32K_NTAT,no description available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "FRO_TRIM_VALID,no description available" "0,1" group.long 0x00++0x03 line.long 0x00 "GPO0_ARRAY0,GPO0 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x04++0x03 line.long 0x00 "GPO0_1,GPO0 register 1 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x04++0x03 line.long 0x00 "GPO0_ARRAY1,GPO0 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x08++0x03 line.long 0x00 "GPO0_2,GPO0 register 2 description" hexmask.long 0x00 4.--31. 1. "FIELD,no description available" newline bitfld.long 0x00 2.--3. "FLASH_CTRL_OPMODE," "?,1: RCLK (back up clock),2: PCLK (back up clock),?..." newline bitfld.long 0x00 0.--1. "SYSTEM_SPEED_CODE," "?,1: FRO24MHz,2: FRO48MHz,3: FRO96MHz" group.long 0x08++0x03 line.long 0x00 "GPO0_ARRAY2,GPO0 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x0C++0x03 line.long 0x00 "GPO0_3,GPO0 register 3 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x0C++0x03 line.long 0x00 "GPO0_ARRAY3,GPO0 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x10++0x03 line.long 0x00 "GPO1_0,GPO1 register 0 description" bitfld.long 0x00 28.--31. "METAL_REVISION_ID,METAL REVISION ID[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 24.--27. "ROM_REVISION_MINOR,ROM Revision-Minor [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "FIELD,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "CPU0_SECURITY_EXTENSION_DISABLE,CPU0_SECURITY_EXTENSION_DISABLE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12.--15. "SRAM_SIZE,SRAM_SIZE[3:0]: (For Niobe4)" "0: 320 KB,1: 256 KB,2: 144 KB,3: 80 KB (For Niobe4 Mini),4: 96 KB,5: 80 KB,6: 64 KB,7: 48 KB All others,?..." newline bitfld.long 0x00 11. "DEVICE_TYPE_SEC,Security device type" "0: LPC55xxx (Non Secure Familly),1: LPC55Sxxx (Secure Familly)" newline hexmask.long.byte 0x00 4.--10. 1. "PARTCONFIG,Device type number" newline bitfld.long 0x00 0.--3. "FINAL_TEST_NOT_DONE,FINAL_TEST_NOT_DONE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "GPO1_ARRAY0,GPO1 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x14++0x03 line.long 0x00 "GPO1_1,GPO1 register 1 description" hexmask.long.tbyte 0x00 8.--31. 1. "FIELD,no description available" newline bitfld.long 0x00 4.--7. "CUSTOMER_REVISION_ID,CUSTOMER REVISION ID[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "ROM_PATCH_VERSION,ROM Patch Version [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x03 line.long 0x00 "GPO1_ARRAY1,GPO1 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x18++0x03 line.long 0x00 "GPO1_2,GPO1 register 2 description" hexmask.long 0x00 1.--31. 1. "FIELD,no description available" newline bitfld.long 0x00 0. "HVST,High Voltage Stress" "0: not done,1: done" group.long 0x18++0x03 line.long 0x00 "GPO1_ARRAY2,GPO1 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x1C++0x03 line.long 0x00 "GPO1_3,GPO1 register 3 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x1C++0x03 line.long 0x00 "GPO1_ARRAY3,GPO1 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x20++0x03 line.long 0x00 "GPO2_0,GPO2 register 0 description" bitfld.long 0x00 28.--31. "CPU0_SECURITY_EXTENSION_DISABLE,CPU0_SECURITY_EXTENSION_DISABLE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 25.--27. "FLASH_SIZE,(For Niobe4)" "0: 256 KB,1: 128 KB,2: 80 KB (reserved),3: 64 KB,4: 0 kB (reserved) All,?..." newline bitfld.long 0x00 22.--24. "TRIM_PLL_CTRL0_DIV_SEL,no description available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--21. "TRIM_USB2_REFBIAS_VBGADJ,no description available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17.--18. "TRIM_USB2_REFBIAS_TST,no description available" "0,1,2,3" newline bitfld.long 0x00 12.--16. "TRIM_USBPHY_TX_CAL45DN,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--11. "TRIM_USBPHY_TX_CAL45DP,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 3.--6. "TRIM_USBPHY_TX_D_CAL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--2. "TRIM_USB_REG_ENV_TAIL_ADJ_VD,no description available" "0,1,2,3" newline bitfld.long 0x00 0. "USBHS_PHY_TRIM_VALID,no description available" "0,1" group.long 0x20++0x03 line.long 0x00 "GPO2_ARRAY0,GPO2 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x24++0x03 line.long 0x00 "GPO2_1,GPO2 register 1 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x24++0x03 line.long 0x00 "GPO2_ARRAY1,GPO2 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x28++0x03 line.long 0x00 "GPO2_2,GPO2 register 2 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x28++0x03 line.long 0x00 "GPO2_ARRAY2,GPO2 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x2C++0x03 line.long 0x00 "GPO2_3,GPO2 register 3 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x2C++0x03 line.long 0x00 "GPO2_ARRAY3,GPO2 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x30++0x03 line.long 0x00 "GPO3_0,GPO3 register 0 description" bitfld.long 0x00 28.--31. "FINAL_TEST_NOT_DONE,FINAL_TEST_NOT_DONE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 25.--27. "MODELNUM_EXTENSION,ModelNumber extension[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19.--24. "FIELD,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 16.--18. "AUX_BIAS_VREF1_VCURVE_TRIM,no description available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11.--15. "AUX_BIAS_VREF1_VTRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--10. "AUX_BIAS_PTAT_ITRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 1.--5. "AUX_BIAS_ITRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0. "AUX_BIAS_TRIM_VALID,no description available" "0,1" group.long 0x30++0x03 line.long 0x00 "GPO3_ARRAY0,GPO3 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x34++0x03 line.long 0x00 "GPO3_1,GPO3 register 1 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x34++0x03 line.long 0x00 "GPO3_ARRAY1,GPO3 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x38++0x03 line.long 0x00 "GPO3_2,GPO3 register 2 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x38++0x03 line.long 0x00 "GPO3_ARRAY2,GPO3 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x3C++0x03 line.long 0x00 "GPO3_3,GPO3 register 3 description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x3C++0x03 line.long 0x00 "GPO3_ARRAY3,GPO3 array description" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x40++0x03 line.long 0x00 "GPO_CHECKSUM_0,checksum of the GPO data in words 0" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x40++0x03 line.long 0x00 "GPO_CHECKSUM_ARRAY0,checksum of the GPO data in words [3:0]" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x44++0x03 line.long 0x00 "GPO_CHECKSUM_1,checksum of the GPO data in words 1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x44++0x03 line.long 0x00 "GPO_CHECKSUM_ARRAY1,checksum of the GPO data in words [3:0]" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x48++0x03 line.long 0x00 "GPO_CHECKSUM_2,checksum of the GPO data in words 2" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x48++0x03 line.long 0x00 "GPO_CHECKSUM_ARRAY2,checksum of the GPO data in words [3:0]" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x4C++0x03 line.long 0x00 "GPO_CHECKSUM_3,checksum of the GPO data in words 3" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x4C++0x03 line.long 0x00 "GPO_CHECKSUM_ARRAY3,checksum of the GPO data in words [3:0]" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x50++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x50++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x54++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x54++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x58++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x58++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x5C++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x5C++0x03 line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x60++0x03 line.long 0x00 "DEVICE_TYPE,no description available" hexmask.long.byte 0x00 24.--31. 1. "DEVICE_TYPE_PIN,Number of pins on the package" newline bitfld.long 0x00 20.--23. "DEVICE_TYPE_PKG,Device package type" "0: HLQFP,1: HTQFP,2: HVQFN,?,4: VFBGA,?,?,?,8: WLCSP,?..." newline bitfld.long 0x00 16. "DEVICE_TYPE_SEC,Security device type" "0: LPC55xxx (Non Secure Familly),1: LPC55Sxxx (Secure Familly)" newline hexmask.long.word 0x00 0.--15. 1. "DEVICE_TYPE_NUM,Device type number" group.long 0x64++0x03 line.long 0x00 "FINAL_TEST_PROGRAM_VERSION,no description available" hexmask.long 0x00 0.--31. 1. "PROGRAM_VERSION,PROGRAM_VERSION [xx.yy stored as : 100*x+y]" group.long 0x68++0x03 line.long 0x00 "FINAL_TEST_DATE,no description available" hexmask.long 0x00 0.--31. 1. "DATE,DATE [stored as : year*10000+month*100+day]" group.long 0x6C++0x03 line.long 0x00 "FINAL_TEST_TIME,no description available" hexmask.long 0x00 0.--31. 1. "TIME,TIME [stored as : hour*10000+minute*100+seconde]" group.long 0x70++0x03 line.long 0x00 "UUID_0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x70++0x03 line.long 0x00 "UUID_ARRAY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x74++0x03 line.long 0x00 "UUID_1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x74++0x03 line.long 0x00 "UUID_ARRAY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x78++0x03 line.long 0x00 "UUID_2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x78++0x03 line.long 0x00 "UUID_ARRAY2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x7C++0x03 line.long 0x00 "UUID_3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x7C++0x03 line.long 0x00 "UUID_ARRAY3,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x80++0x03 line.long 0x00 "WAFER_TEST1_PROGRAM_VERSION,no description available" hexmask.long 0x00 0.--31. 1. "WT1_PROGRAM_VERSION,WT1_PROGRAM_VERSION [xx.yy stored as : 100*x+y]" group.long 0x84++0x03 line.long 0x00 "WAFER_TEST1_DATE,no description available" hexmask.long 0x00 0.--31. 1. "WT1_DATE,WT1_DATE [stored as : year*10000+month*100+day]" group.long 0x88++0x03 line.long 0x00 "WAFER_TEST1_TIME,no description available" hexmask.long 0x00 0.--31. 1. "WT1_TIME,WT1_TIME [stored as : hour*10000+minute*100+seconde]" group.long 0x90++0x03 line.long 0x00 "WAFER_TEST2_PROGRAM_VERSION,no description available" hexmask.long 0x00 0.--31. 1. "WT2_PROGRAM_VERSION,WT2_PROGRAM_VERSION [xx.yy stored as : 100*x+y]" group.long 0x94++0x03 line.long 0x00 "WAFER_TEST2_DATE,no description available" hexmask.long 0x00 0.--31. 1. "WT2_DATE,WT2_DATE [stored as : year*10000+month*100+day]" group.long 0x98++0x03 line.long 0x00 "WAFER_TEST2_TIME,no description available" hexmask.long 0x00 0.--31. 1. "WT2_TIME,WT2_TIME [stored as : hour*10000+minute*100+seconde]" group.long 0x9C++0x03 line.long 0x00 "USBCFG,no description available" bitfld.long 0x00 16. "USB_USE_XO32M_CAPA_BANKS,Enable the use of Crystal 32 MHz internal Capa Banks during the configuration of the High Speed USB for ISP" "0: Disable Crystal 32 MHz CapaBanks,1: Enable Crystal 32 MHz CapaBanks" newline abitfld.long 0x00 8.--15. "USB_SPEED,USB_SPEED[7:0]=" "0x00=0: USB High Speed Module used for ISP,0x01=1: USB Full SPeed Module used for ISP,0x02=2: Neither USB High Speed module nor USB..,0xFF=255: RESERVED" newline hexmask.long.byte 0x00 0.--7. 1. "XO32M_READY_TIME_OUT_MS,no description available" group.long 0xA0++0x03 line.long 0x00 "PERIPHENCFG,no description available" bitfld.long 0x00 31. "CPU1_ENABLE,no description available" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "PERIPHERAL_CONFIGURATION,no description available" group.long 0xA4++0x03 line.long 0x00 "RAMSIZECFG,no description available" hexmask.long 0x00 0.--31. 1. "SRAM_CONFIGURATION,no description available" group.long 0xA8++0x03 line.long 0x00 "FLASHSIZECFG,no description available" hexmask.long 0x00 0.--31. 1. "FLASH_CONFIGURATION,no description available" group.long 0xB0++0x03 line.long 0x00 "RINGO_0,no description available" hexmask.long 0x00 1.--31. 1. "RINGO_0_CTRL,To copy RINGO_0_CTRL = ANACTRL->RINGO0_CTRL[30:0]" newline bitfld.long 0x00 0. "RINGO_0_CTRL_VALID," "0,1" group.long 0xB4++0x03 line.long 0x00 "RINGO_1,no description available" hexmask.long 0x00 1.--31. 1. "RINGO_1_CTRL,To copy RINGO_1_CTRL = ANACTRL->RINGO1_CTRL[30:0]" newline bitfld.long 0x00 0. "RINGO_1_CTRL_VALID," "0,1" group.long 0xB8++0x03 line.long 0x00 "RINGO_2,no description available" hexmask.long 0x00 1.--31. 1. "RINGO_2_CTRL,To copy RINGO_2_CTRL = ANACTRL->RINGO2_CTRL[30:0]" newline bitfld.long 0x00 0. "RINGO_2_CTRL_VALID," "0,1" group.long 0xC0++0x03 line.long 0x00 "FRO_192MHZ,no description available" hexmask.long.byte 0x00 17.--24. 1. "FRO192M_DACTRIM,FRO192M_DACTRIM[7:0]" newline hexmask.long.byte 0x00 8.--14. 1. "FRO192M_TEMPTRIM,FRO192M_TEMPTRIM[6:0]" newline bitfld.long 0x00 1.--6. "FRO192M_BIASTRIM,FRO192M_BIASTRIM[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "FRO192M_TRIM_VALID,no description available" "0,1" group.long 0xC8++0x03 line.long 0x00 "XO_32MHZ,no description available" bitfld.long 0x00 31. "XO32M_XO_AC_BUF_STATUS,no description available" "0,1" newline bitfld.long 0x00 30. "XO32M_XO_SLAVE_STATUS,no description available" "0,1" newline hexmask.long.byte 0x00 23.--29. 1. "XO32M_XOUT_CAPCAL_8PF,no description available" newline hexmask.long.byte 0x00 16.--22. 1. "XO32M_XOUT_CAPCAL_6PF,no description available" newline bitfld.long 0x00 15. "XO32M_XOUT_TRIM_VALID,no description available" "0,1" newline hexmask.long.byte 0x00 8.--14. 1. "XO32M_XIN_CAPCAL_8PF,no description available" newline hexmask.long.byte 0x00 1.--7. 1. "XO32M_XIN_CAPCAL_6PF,no description available" newline bitfld.long 0x00 0. "XO32M_XIN_TRIM_VALID,no description available" "0,1" group.long 0xCC++0x03 line.long 0x00 "XO_32KHZ,no description available" hexmask.long.byte 0x00 23.--29. 1. "XO32K_XOUT_CAPCAL_8PF,no description available" newline hexmask.long.byte 0x00 16.--22. 1. "XO32K_XOUT_CAPCAL_6PF,no description available" newline bitfld.long 0x00 15. "XO32K_XOUT_TRIM_VALID,no description available" "0,1" newline hexmask.long.byte 0x00 8.--14. 1. "XO32K_XIN_CAPCAL_8PF,no description available" newline hexmask.long.byte 0x00 1.--7. 1. "XO32K_XIN_CAPCAL_6PF,no description available" newline bitfld.long 0x00 0. "XO32K_XIN_TRIM_VALID,no description available" "0,1" group.long 0xD0++0x03 line.long 0x00 "FRO_1MHZ,no description available" hexmask.long.byte 0x00 1.--7. 1. "FRO1M_FREQSEL,Frequency trimming bits" newline bitfld.long 0x00 0. "FRO1M_TRIM_VALID,no description available" "0,1" group.long 0xD8++0x03 line.long 0x00 "DCDC_POWER_PROFILE_HIGH_0,no description available" bitfld.long 0x00 24.--27. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 23. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1" newline bitfld.long 0x00 22. "SLICINGENABLE,Enable staggered switching of power switches" "0,1" newline bitfld.long 0x00 18.--21. "VOUT,Set output regulation voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "DISABLEISENSE,Disable Current sensing" "0,1" newline bitfld.long 0x00 12.--16. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 11. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1" newline bitfld.long 0x00 9.--10. "ISEL,Alter Internal biasing currents" "0,1,2,3" newline bitfld.long 0x00 7.--8. "ICOMP,Select the type of ZCD comparator" "0,1,2,3" newline bitfld.long 0x00 1.--6. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "DCDC_TRIM_VALID,DCDC is trimed" "0,1" group.long 0xD8++0x03 line.long 0x00 "DCDC_POWER_PROFILE_HIGH_ARRAY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xDC++0x03 line.long 0x00 "DCDC_POWER_PROFILE_HIGH_1,no description available" bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1" newline bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1" newline bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1" newline bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1" newline bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1" newline bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3" newline bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1" newline bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xDC++0x03 line.long 0x00 "DCDC_POWER_PROFILE_HIGH_ARRAY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xE0++0x03 line.long 0x00 "DCDC_POWER_PROFILE_LOW_0,no description available" bitfld.long 0x00 24.--27. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 23. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1" newline bitfld.long 0x00 22. "SLICINGENABLE,Enable staggered switching of power switches" "0,1" newline bitfld.long 0x00 18.--21. "VOUT,Set output regulation voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "DISABLEISENSE,Disable Current sensing" "0,1" newline bitfld.long 0x00 12.--16. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 11. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1" newline bitfld.long 0x00 9.--10. "ISEL,Alter Internal biasing currents" "0,1,2,3" newline bitfld.long 0x00 7.--8. "ICOMP,Select the type of ZCD comparator" "0,1,2,3" newline bitfld.long 0x00 1.--6. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "DCDC_TRIM_VALID,DCDC is trimed" "0,1" group.long 0xE0++0x03 line.long 0x00 "DCDC_POWER_PROFILE_LOW_ARRAY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xE4++0x03 line.long 0x00 "DCDC_POWER_PROFILE_LOW_1,no description available" bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1" newline bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1" newline bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1" newline bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1" newline bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1" newline bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3" newline bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1" newline bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE4++0x03 line.long 0x00 "DCDC_POWER_PROFILE_LOW_ARRAY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xE8++0x03 line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_0,no description available" bitfld.long 0x00 24.--27. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 23. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1" newline bitfld.long 0x00 22. "SLICINGENABLE,Enable staggered switching of power switches" "0,1" newline bitfld.long 0x00 18.--21. "VOUT,Set output regulation voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "DISABLEISENSE,Disable Current sensing" "0,1" newline bitfld.long 0x00 12.--16. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 11. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1" newline bitfld.long 0x00 9.--10. "ISEL,Alter Internal biasing currents" "0,1,2,3" newline bitfld.long 0x00 7.--8. "ICOMP,Select the type of ZCD comparator" "0,1,2,3" newline bitfld.long 0x00 1.--6. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "DCDC_TRIM_VALID,DCDC is trimed" "0,1" group.long 0xE8++0x03 line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_ARRAY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xEC++0x03 line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_1,no description available" bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1" newline bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1" newline bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1" newline bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1" newline bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1" newline bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3" newline bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1" newline bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEC++0x03 line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_ARRAY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0xF0++0x03 line.long 0x00 "BOD,no description available" bitfld.long 0x00 21.--22. "BOD_CORE_HYST,no description available" "0,1,2,3" newline bitfld.long 0x00 17.--19. "BOD_CORE_TRIGLVL,no description available" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. "BOD_CORE_TRIM_VALID,no description available" "0,1" newline bitfld.long 0x00 6.--7. "BOD_VBAT_HYST,no description available" "0,1,2,3" newline bitfld.long 0x00 1.--5. "BOD_VBAT_TRIGLVL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0. "BOD_VBAT_TRIM_VALID,no description available" "0,1" group.long 0xF4++0x03 line.long 0x00 "LDO_AO,no description available" bitfld.long 0x00 25.--29. "DPDW_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 24. "DPDW_TRIM_VALID,no description available" "0,1" newline bitfld.long 0x00 17.--21. "PDWN_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16. "PDWN_TRIM_VALID,no description available" "0,1" newline bitfld.long 0x00 9.--13. "DSLP_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8. "DSLP_TRIM_VALID,no description available" "0,1" newline bitfld.long 0x00 1.--5. "ACTIVE_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0. "ACTIVE_TRIM_VALID,no description available" "0,1" group.long 0xF8++0x03 line.long 0x00 "SDIO_DELAY,no description available" hexmask.long.word 0x00 1.--10. 1. "SDIO_0_DELAY,SDIO_0_DELAY (unit: 100 ps)" newline bitfld.long 0x00 0. "SDIO_0_VALID,no description available" "0,1" group.long 0x100++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_0,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_1,VREF1VCURVETRIM_1 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_0,VREF1VCURVETRIM_0 (unit: 100uV)" group.long 0x100++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY0,Aux Bias Curve Ambient (30degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x104++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_1,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_3,VREF1VCURVETRIM_3 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_2,VREF1VCURVETRIM_2 (unit: 100uV)" group.long 0x104++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY1,Aux Bias Curve Ambient (30degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x108++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_2,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_5,VREF1VCURVETRIM_5 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_4,VREF1VCURVETRIM_4 (unit: 100uV)" group.long 0x108++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY2,Aux Bias Curve Ambient (30degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x10C++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_3,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_7,VREF1VCURVETRIM_7 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_6,VREF1VCURVETRIM_6 (unit: 100uV)" group.long 0x10C++0x03 line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY3,Aux Bias Curve Ambient (30degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x110++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_0,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_1,VREF1VCURVETRIM_1 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_0,VREF1VCURVETRIM_0 (unit: 100uV)" group.long 0x110++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY0,Aux Bias Curve TEMP (105degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x114++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_1,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_3,VREF1VCURVETRIM_3 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_2,VREF1VCURVETRIM_2 (unit: 100uV)" group.long 0x114++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY1,Aux Bias Curve TEMP (105degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x118++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_2,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_5,VREF1VCURVETRIM_5 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_4,VREF1VCURVETRIM_4 (unit: 100uV)" group.long 0x118++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY2,Aux Bias Curve TEMP (105degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x11C++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_3,no description available" hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_7,VREF1VCURVETRIM_7 (unit: 100uV)" newline hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_6,VREF1VCURVETRIM_6 (unit: 100uV)" group.long 0x11C++0x03 line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY3,Aux Bias Curve TEMP (105degC)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 2. (strings "1" "2" )(list 0x00 0x04 ) group.long ($2+0x120)++0x03 line.long 0x00 "TEMP_SENS_VBE1VBE8_REF_$1,no description available" hexmask.long.word 0x00 16.--31. 1. "VBE8,no description available" newline hexmask.long.word 0x00 0.--15. 1. "VBE1,no description available" repeat.end group.long 0x128++0x03 line.long 0x00 "TEMP_SENS_SLOPE,no description available" hexmask.long 0x00 1.--31. 1. "SLOPE_x1024,SLOPE_x1024[30:0]" newline bitfld.long 0x00 0. "VALID,no description available" "0,1" group.long 0x12C++0x03 line.long 0x00 "TEMP_SENS_OFFSET,no description available" hexmask.long 0x00 1.--31. 1. "OFFSET_x1024,OFFSET_x1024[30:0]" newline bitfld.long 0x00 0. "VALID,no description available" "0,1" group.long 0x130++0x03 line.long 0x00 "PVT_MONITOR_0_ARRAY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x130++0x03 line.long 0x00 "PVT_MONITOR_0_RINGO,no description available" hexmask.long 0x00 1.--31. 1. "RINGO_FREQ_HZ,no description available" newline bitfld.long 0x00 0. "RINGO_VALID,no description available" "0,1" group.long 0x134++0x03 line.long 0x00 "PVT_MONITOR_0_ARRAY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x134++0x03 line.long 0x00 "PVT_MONITOR_0_DELAYS_LSB,no description available" hexmask.long.word 0x00 21.--30. 1. "DELAY_2,Delay in us" newline hexmask.long.word 0x00 11.--20. 1. "DELAY_1,Delay in us" newline hexmask.long.word 0x00 1.--10. 1. "DELAY_0,Delay in us" newline bitfld.long 0x00 0. "DELAY_VALID,no description available" "0,1" group.long 0x138++0x03 line.long 0x00 "PVT_MONITOR_0_ARRAY2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x138++0x03 line.long 0x00 "PVT_MONITOR_0_DELAYS_MSB,no description available" hexmask.long.word 0x00 20.--29. 1. "DELAY_5,Delay in us" newline hexmask.long.word 0x00 10.--19. 1. "DELAY_4,Delay in us" newline hexmask.long.word 0x00 0.--9. 1. "DELAY_3,Delay in us" group.long 0x140++0x03 line.long 0x00 "PVT_MONITOR_1_ARRAY0,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x140++0x03 line.long 0x00 "PVT_MONITOR_1_RINGO,no description available" hexmask.long 0x00 1.--31. 1. "RINGO_FREQ_HZ,no description available" newline bitfld.long 0x00 0. "RINGO_VALID,no description available" "0,1" group.long 0x144++0x03 line.long 0x00 "PVT_MONITOR_1_ARRAY1,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x144++0x03 line.long 0x00 "PVT_MONITOR_1_DELAYS_LSB,no description available" hexmask.long.word 0x00 21.--30. 1. "DELAY_2,Delay in us" newline hexmask.long.word 0x00 11.--20. 1. "DELAY_1,Delay in us" newline hexmask.long.word 0x00 1.--10. 1. "DELAY_0,Delay in us" newline bitfld.long 0x00 0. "DELAY_VALID,no description available" "0,1" group.long 0x148++0x03 line.long 0x00 "PVT_MONITOR_1_ARRAY2,no description available" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x148++0x03 line.long 0x00 "PVT_MONITOR_1_DELAYS_MSB,no description available" hexmask.long.word 0x00 20.--29. 1. "DELAY_5,Delay in us" newline hexmask.long.word 0x00 10.--19. 1. "DELAY_4,Delay in us" newline hexmask.long.word 0x00 0.--9. 1. "DELAY_3,Delay in us" repeat 13. (increment 0 1) (increment 0 0x04) group.long ($2+0x14C)++0x03 line.long 0x00 "NXP_DEVICE_PRIVATE_KEY[$1],no description available $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x180)++0x03 line.long 0x00 "NXP_DEVICE_CERTIFICATE_[$1],NXP Device Certificate (ECDSA_sign - r $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x1A0)++0x03 line.long 0x00 "NXP_DEVICE_CERTIFICATE_[$1],NXP Device Certificate (ECDSA_sign - s $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x1C0)++0x03 line.long 0x00 "SHA256_DIGEST[$1],SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat.end group.long 0x1E0++0x03 line.long 0x00 "ECID_BACKUP_0,no description available" hexmask.long.word 0x00 16.--31. 1. "COORD_X,no description available" newline hexmask.long.word 0x00 0.--15. 1. "COORD_Y,no description available" group.long 0x1E0++0x03 line.long 0x00 "ECID_BACKUP_ARRAY0,ECID backup (the original is in page n-1)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x1E4++0x03 line.long 0x00 "ECID_BACKUP_1,no description available" hexmask.long.byte 0x00 0.--7. 1. "WAFER,no description available" group.long 0x1E4++0x03 line.long 0x00 "ECID_BACKUP_ARRAY1,ECID backup (the original is in page n-1)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x1E8++0x03 line.long 0x00 "ECID_BACKUP_2,no description available" hexmask.long 0x00 0.--31. 1. "LOTID_LSB,no description available" group.long 0x1E8++0x03 line.long 0x00 "ECID_BACKUP_ARRAY2,ECID backup (the original is in page n-1)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" group.long 0x1EC++0x03 line.long 0x00 "ECID_BACKUP_3,no description available" hexmask.long 0x00 0.--31. 1. "LOTID_MSB,no description available" group.long 0x1EC++0x03 line.long 0x00 "ECID_BACKUP_ARRAY3,ECID backup (the original is in page n-1)" hexmask.long 0x00 0.--31. 1. "FIELD,no description available" repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x1F0)++0x03 line.long 0x00 "CHECKSUM[$1],Checksum of the whole page $1" repeat.end group.long 0xCAC++0x03 line.long 0x00 "DIS_ROM_HIDING,no description available" hexmask.long 0x00 0.--31. 1. "DIS_ROM_HIDING,When 0x3CC35AA5 ROM hiding feture is disabled" group.long 0xCBC++0x03 line.long 0x00 "PUF_SRAM,no description available" bitfld.long 0x00 25. "STBP,STBP" "0,1" newline bitfld.long 0x00 23.--24. "WAM,SRAM Write Assist settings" "0,1,2,3" newline bitfld.long 0x00 22. "WAEN,SRAM Write Assist Enable" "0,1" newline bitfld.long 0x00 18.--21. "RAM,SRAM Read Assist settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "RAEN,SRAM Read Assist Enable" "0,1" newline bitfld.long 0x00 16. "WRME,Write read margin enable" "0,1" newline bitfld.long 0x00 13.--15. "WM,Write Margin control settings" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--12. "RM,Read Margin control settings" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--9. "SMB,Source Biasing voltage" "0: Low leakage,1: Medium leakage,2: Highest leakage,3: Disable" newline bitfld.long 0x00 2. "ckgating,PUF SRAM Clock Gating control" "0,1" newline bitfld.long 0x00 1. "mode,PUF SRAM Controller operating mode" "0,1" newline bitfld.long 0x00 0. "PUF_SRAM_VALID," "0,1" tree.end tree "FLASH_ROMPATCH" base ad:0x3EC00 group.long 0x00++0x03 line.long 0x00 "HEADER," hexmask.long.byte 0x00 24.--31. 1. "IDENTIFIER," hexmask.long.byte 0x00 16.--23. 1. "TYPE," hexmask.long.byte 0x00 8.--15. 1. "SUB_TYPE," hexmask.long.byte 0x00 0.--7. 1. "ENTRIES," repeat 255. (increment 0 1) (increment 0 0x4) group.long ($2+0x04)++0x03 line.long 0x00 "PATCH[$1],$1" hexmask.long 0x00 0.--31. 1. "PATCH," repeat.end tree.end endif tree "FLEXCOMM (Flexcomm)" tree "FLEXCOMM0" base ad:0x40086000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM1" base ad:0x40087000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM2" base ad:0x40088000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM3" base ad:0x40089000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM4" base ad:0x4008A000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM5" base ad:0x40096000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM6" base ad:0x40097000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM7" base ad:0x40098000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "FLEXCOMM8" base ad:0x4009F000 group.long 0xFF8++0x03 line.long 0x00 "PSELID,Peripheral Select and Flexcomm module ID" hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID" rbitfld.long 0x00 7. "I2SPRESENT,I2S Present" "0: I2S Not Present,1: I2S Present" newline rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: I2C Not Present,1: I2C Present" rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm module does not include the SPI..,1: This Flexcomm module includes the SPI function" newline rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm module does not include the..,1: This Flexcomm module includes the USART.." bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.." newline bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C,4: I2S_TRANSMIT,5: I2S_RECEIVE,?..." rgroup.long 0xFFC++0x03 line.long 0x00 "PID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "Major_Rev,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "Minor_Rev,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "FLEXSPI (FlexSPI)" base ad:0x400C0000 group.long 0x00++0x03 line.long 0x00 "MCR0,Module Control Register 0" hexmask.long.byte 0x00 24.--31. 1. "AHBGRANTWAIT,Timeout wait cycle for AHB command grant" hexmask.long.byte 0x00 16.--23. 1. "IPGRANTWAIT,Timeout wait cycle for IP command grant" newline bitfld.long 0x00 15. "LEARNEN,This bit is used to enable/disable data learning feature" "0: Disable,1: Enable" bitfld.long 0x00 14. "SCKFREERUNEN,This bit is used to force SCLK output free-running" "0: Disable,1: Enable" newline bitfld.long 0x00 12. "DOZEEN,Doze mode enable bit" "0: Doze mode support disabled,1: Doze mode support enabled" bitfld.long 0x00 11. "HSEN,Half Speed Serial Flash access Enable" "0: Disable divide by 2 of serial flash clock for..,1: Enable divide by 2 of serial flash clock for.." newline bitfld.long 0x00 8.--10. "SERCLKDIV,Serial root clock" "0: Divided by 1,1: Divided by 2,2: Divided by 3,3: Divided by 4,4: Divided by 5,5: Divided by 6,6: Divided by 7,7: Divided by 8" bitfld.long 0x00 4.--5. "RXCLKSRC,Sample Clock source selection for Flash Reading" "0: Dummy Read strobe generated by FlexSPI..,1: Dummy Read strobe generated by FlexSPI..,2: SCLK output clock and loopback from SCLK pad,3: Flash provided Read strobe and input from DQS.." newline bitfld.long 0x00 1. "MDIS,Module Disable" "0,1" bitfld.long 0x00 0. "SWRESET,Software Reset" "0,1" group.long 0x04++0x03 line.long 0x00 "MCR1,Module Control Register 1" hexmask.long.word 0x00 16.--31. 1. "SEQWAIT,Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles" hexmask.long.word 0x00 0.--15. 1. "AHBBUSWAIT,AHB Bus wait" group.long 0x08++0x03 line.long 0x00 "MCR2,Module Control Register 2" hexmask.long.byte 0x00 24.--31. 1. "RESUMEWAIT,Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed" bitfld.long 0x00 15. "SAMEDEVICEEN,All external devices are same devices (both in types and size) for A1/A2/B1/B2" "0: In Individual mode FLSHA1CRx/FLSHA2CRx..,1: FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register.." newline bitfld.long 0x00 14. "CLRLEARNPHASE,The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1" "0,1" bitfld.long 0x00 11. "CLRAHBBUFOPT,Clear AHB buffer" "0: AHB RX/TX Buffer will not be cleaned..,1: AHB RX/TX Buffer will be cleaned.." group.long 0x0C++0x03 line.long 0x00 "AHBCR,AHB Bus Control Register" bitfld.long 0x00 20.--21. "ALIGNMENT,Decides all AHB read/write boundary" "0: No limit,1: 1 KBytes,2: 512 Bytes,3: 256 Bytes" bitfld.long 0x00 10. "READSZALIGN,AHB Read Size Alignment" "0: AHB read size will be decided by other..,1: AHB read size to up size to 8 bytes aligned.." newline bitfld.long 0x00 6. "READADDROPT,AHB Read Address option bit" "0: There is AHB read burst start address..,1: There is no AHB read burst start address.." bitfld.long 0x00 5. "PREFETCHEN,AHB Read Prefetch Enable" "0,1" newline bitfld.long 0x00 4. "BUFFERABLEEN,Enable AHB bus bufferable write access support" "0: Disabled,1: Enabled" bitfld.long 0x00 3. "CACHABLEEN,Enable AHB bus cachable read access support" "0: Disabled,1: Enabled" newline bitfld.long 0x00 2. "CLRAHBTXBUF,Clear the status/pointers of AHB TX Buffer" "0,1" bitfld.long 0x00 1. "CLRAHBRXBUF,Clear the status/pointers of AHB RX Buffer" "0,1" group.long 0x10++0x03 line.long 0x00 "INTEN,Interrupt Enable Register" bitfld.long 0x00 17. "AHBGCMERREN,AHB read gcm error interrupt enable" "0,1" bitfld.long 0x00 16. "IPCMDSECUREVIOEN,IP command security violation interrupt enable" "0,1" newline bitfld.long 0x00 11. "SEQTIMEOUTEN,Sequence execution timeout interrupt enable" "0,1" bitfld.long 0x00 10. "AHBBUSTIMEOUTEN,AHB Bus timeout interrupt" "0,1" newline bitfld.long 0x00 9. "SCKSTOPBYWREN,SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable" "0,1" bitfld.long 0x00 8. "SCKSTOPBYRDEN,SCLK is stopped during command sequence because Async RX FIFO full interrupt enable" "0,1" newline bitfld.long 0x00 7. "DATALEARNFAILEN,Data Learning failed interrupt enable" "0,1" bitfld.long 0x00 6. "IPTXWEEN,IP TX FIFO WaterMark empty interrupt enable" "0,1" newline bitfld.long 0x00 5. "IPRXWAEN,IP RX FIFO WaterMark available interrupt enable" "0,1" bitfld.long 0x00 4. "AHBCMDERREN,AHB triggered Command Sequences Error Detected interrupt enable" "0,1" newline bitfld.long 0x00 3. "IPCMDERREN,IP triggered Command Sequences Error Detected interrupt enable" "0,1" bitfld.long 0x00 2. "AHBCMDGEEN,AHB triggered Command Sequences Grant Timeout interrupt enable" "0,1" newline bitfld.long 0x00 1. "IPCMDGEEN,IP triggered Command Sequences Grant Timeout interrupt enable" "0,1" bitfld.long 0x00 0. "IPCMDDONEEN,IP triggered Command Sequences Execution finished interrupt enable" "0,1" group.long 0x14++0x03 line.long 0x00 "INTR,Interrupt Register" eventfld.long 0x00 17. "AHBGCMERR,AHB read gcm error interrupt" "0,1" eventfld.long 0x00 16. "IPCMDSECUREVIO,IP command security violation interrupt" "0,1" newline eventfld.long 0x00 11. "SEQTIMEOUT,Sequence execution timeout interrupt" "0,1" eventfld.long 0x00 10. "AHBBUSTIMEOUT,AHB Bus timeout interrupt" "0,1" newline eventfld.long 0x00 9. "SCKSTOPBYWR,SCLK is stopped during command sequence because Async TX FIFO empty interrupt" "0,1" eventfld.long 0x00 8. "SCKSTOPBYRD,SCLK is stopped during command sequence because Async RX FIFO full interrupt" "0,1" newline eventfld.long 0x00 7. "DATALEARNFAIL,Data Learning failed interrupt" "0,1" eventfld.long 0x00 6. "IPTXWE,IP TX FIFO watermark empty interrupt" "0,1" newline eventfld.long 0x00 5. "IPRXWA,IP RX FIFO watermark available interrupt" "0,1" eventfld.long 0x00 4. "AHBCMDERR,AHB triggered Command Sequences Error Detected interrupt" "0,1" newline eventfld.long 0x00 3. "IPCMDERR,IP triggered Command Sequences Error Detected interrupt" "0,1" eventfld.long 0x00 2. "AHBCMDGE,AHB triggered Command Sequences Grant Timeout interrupt" "0,1" newline eventfld.long 0x00 1. "IPCMDGE,IP triggered Command Sequences Grant Timeout interrupt" "0,1" eventfld.long 0x00 0. "IPCMDDONE,IP triggered Command Sequences Execution finished interrupt" "0,1" rgroup.long 0x18++0x03 line.long 0x00 "LUTKEY,LUT Key Register" hexmask.long 0x00 0.--31. 1. "KEY,The Key to lock or unlock LUT" group.long 0x1C++0x03 line.long 0x00 "LUTCR,LUT Control Register" bitfld.long 0x00 2. "PROTECT,LUT protection" "0,1" bitfld.long 0x00 1. "UNLOCK,Unlock LUT" "0,1" newline bitfld.long 0x00 0. "LOCK,Lock LUT" "0,1" group.long 0x20++0x03 line.long 0x00 "AHBRXBUF0CR0,AHB RX Buffer 0 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x24++0x03 line.long 0x00 "AHBRXBUF1CR0,AHB RX Buffer 1 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x28++0x03 line.long 0x00 "AHBRXBUF2CR0,AHB RX Buffer 2 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x2C++0x03 line.long 0x00 "AHBRXBUF3CR0,AHB RX Buffer 3 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x30++0x03 line.long 0x00 "AHBRXBUF4CR0,AHB RX Buffer 4 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x34++0x03 line.long 0x00 "AHBRXBUF5CR0,AHB RX Buffer 5 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x38++0x03 line.long 0x00 "AHBRXBUF6CR0,AHB RX Buffer 6 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x3C++0x03 line.long 0x00 "AHBRXBUF7CR0,AHB RX Buffer 7 Control Register 0" bitfld.long 0x00 31. "PREFETCHEN,AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master" "0,1" bitfld.long 0x00 24.--26. "PRIORITY,This priority for AHB Master Read which this AHB RX Buffer is assigned" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "MSTRID,This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "BUFSZ,AHB RX Buffer Size in 64 bits" group.long 0x60++0x03 line.long 0x00 "FLSHA1CR0,Flash Control Register 0" bitfld.long 0x00 31. "SPLITRDEN,AHB read access split function control" "0,1" bitfld.long 0x00 30. "SPLITWREN,AHB write access split function control" "0,1" newline hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte" group.long 0x64++0x03 line.long 0x00 "FLSHA2CR0,Flash Control Register 0" bitfld.long 0x00 31. "SPLITRDEN,AHB read access split function control" "0,1" bitfld.long 0x00 30. "SPLITWREN,AHB write access split function control" "0,1" newline hexmask.long.tbyte 0x00 0.--22. 1. "FLSHSZ,Flash Size in KByte" repeat 2. (strings "1" "2" )(list 0x0 0x4 ) group.long ($2+0x70)++0x03 line.long 0x00 "FLSHCR1A$1,Flash Control Register $1" hexmask.long.word 0x00 16.--31. 1. "CSINTERVAL,This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion" bitfld.long 0x00 15. "CSINTERVALUNIT,CS interval unit" "0: The CS interval unit is 1 serial clock cycle,1: The CS interval unit is 256 serial clock cycle" newline bitfld.long 0x00 11.--14. "CAS,Column Address Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10. "WA,Word Addressable" "0,1" newline bitfld.long 0x00 5.--9. "TCSH,Serial Flash CS Hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "TCSS,Serial Flash CS setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat.end repeat 2. (strings "1" "2" )(list 0x0 0x4 ) group.long ($2+0x80)++0x03 line.long 0x00 "FLSHCR2A$1,Flash Control Register 2" bitfld.long 0x00 31. "CLRINSTRPTR,Clear the instruction pointer which is internally saved pointer by JMP_ON_CS" "0,1" bitfld.long 0x00 28.--30. "AWRWAITUNIT,AWRWAIT unit" "0: The AWRWAIT unit is 2 ahb clock cycle,1: The AWRWAIT unit is 8 ahb clock cycle,2: The AWRWAIT unit is 32 ahb clock cycle,3: The AWRWAIT unit is 128 ahb clock cycle,4: The AWRWAIT unit is 512 ahb clock cycle,5: The AWRWAIT unit is 2048 ahb clock cycle,6: The AWRWAIT unit is 8192 ahb clock cycle,7: The AWRWAIT unit is 32768 ahb clock cycle" newline hexmask.long.word 0x00 16.--27. 1. "AWRWAIT,For certain devices (such as FPGA) it need some time to write data into internal memory after the command sequences finished on FlexSPI interface" bitfld.long 0x00 13.--15. "AWRSEQNUM,Sequence Number for AHB Write triggered Command" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--11. "AWRSEQID,Sequence Index for AHB Write triggered Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--7. "ARDSEQNUM,Sequence Number for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--3. "ARDSEQID,Sequence Index for AHB Read triggered Command in LUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x94++0x03 line.long 0x00 "FLSHCR4,Flash Control Register 4" bitfld.long 0x00 2. "WMENA,Write mask enable bit for flash device on port A" "0: Write mask is disabled DQS(RWDS) pin will not..,1: Write mask is enabled DQS(RWDS) pin will be.." bitfld.long 0x00 0. "WMOPT1,Write mask option bit 1" "0: DQS pin will be used as Write Mask when..,1: DQS pin will not be used as Write Mask when.." group.long 0xA0++0x03 line.long 0x00 "IPCR0,IP Control Register 0" hexmask.long 0x00 0.--31. 1. "SFAR,Serial Flash Address for IP command" group.long 0xA4++0x03 line.long 0x00 "IPCR1,IP Control Register 1" bitfld.long 0x00 24.--26. "ISEQNUM,Sequence Number for IP command: ISEQNUM+1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--19. "ISEQID,Sequence Index in LUT for IP command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--15. 1. "IDATSZ,Flash Read/Program Data Size (in Bytes) for IP command" group.long 0xB0++0x03 line.long 0x00 "IPCMD,IP Command Register" bitfld.long 0x00 0. "TRG,Setting this bit will trigger an IP Command" "0,1" group.long 0xB4++0x03 line.long 0x00 "DLPR,Data Learn Pattern Register" hexmask.long 0x00 0.--31. 1. "DLP,Data Learning Pattern" group.long 0xB8++0x03 line.long 0x00 "IPRXFCR,IP RX FIFO Control Register" hexmask.long.byte 0x00 2.--8. 1. "RXWMRK,Watermark level is (RXWMRK+1)*64 Bits" bitfld.long 0x00 1. "RXDMAEN,IP RX FIFO reading by DMA enabled" "0: IP RX FIFO would be read by processor,1: IP RX FIFO would be read by DMA" newline bitfld.long 0x00 0. "CLRIPRXF,Clear all valid data entries in IP RX FIFO" "0,1" group.long 0xBC++0x03 line.long 0x00 "IPTXFCR,IP TX FIFO Control Register" hexmask.long.byte 0x00 2.--8. 1. "TXWMRK,Watermark level is (TXWMRK+1)*64 Bits" bitfld.long 0x00 1. "TXDMAEN,IP TX FIFO filling by DMA enabled" "0: IP TX FIFO would be filled by processor,1: IP TX FIFO would be filled by DMA" newline bitfld.long 0x00 0. "CLRIPTXF,Clear all valid data entries in IP TX FIFO" "0,1" group.long 0xC0++0x03 line.long 0x00 "DLLCRA,DLL Control Register 0" bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1" newline bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "DLLRESET,DLL reset" "0,1" newline bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1" group.long 0xC4++0x03 line.long 0x00 "DLLCRB,DLL Control Register 0" bitfld.long 0x00 9.--14. "OVRDVAL,Slave clock delay line delay cell number selection override value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8. "OVRDEN,Slave clock delay line delay cell number selection override enable" "0,1" newline bitfld.long 0x00 3.--6. "SLVDLYTARGET,The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz DLLEN set to 0x1 OVRDEN set to =0x0 then SLVDLYTARGET setting of 0xF is recommended" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "DLLRESET,DLL reset" "0,1" newline bitfld.long 0x00 0. "DLLEN,DLL calibration enable" "0,1" rgroup.long 0xE0++0x03 line.long 0x00 "STS0,Status Register 0" bitfld.long 0x00 4.--7. "DATALEARNPHASEA,Indicate the sampling clock phase selection on Port A after Data Learning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2.--3. "ARBCMDSRC,This status field indicates the trigger source of current command sequence granted by arbitrator" "0: Triggered by AHB read command (triggered by..,1: Triggered by AHB write command (triggered by..,2: Triggered by IP command (triggered by setting..,3: Triggered by suspended command (resumed)" newline bitfld.long 0x00 1. "ARBIDLE,This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface" "0,1" bitfld.long 0x00 0. "SEQIDLE,This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface" "0,1" rgroup.long 0xE4++0x03 line.long 0x00 "STS1,Status Register 1" bitfld.long 0x00 24.--27. "IPCMDERRCODE,Indicates the Error Code when IP command Error detected" "0: No error,?,2: IP command with JMP_ON_CS instruction used in..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,6: Flash access start address exceed the whole..,?,?,?,?,?,?,?,14: Sequence execution timeout,15: Flash boundary crossed" bitfld.long 0x00 16.--19. "IPCMDERRID,Indicates the sequence Index when IP command error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "AHBCMDERRCODE,Indicates the Error Code when AHB command Error detected" "0: No error,?,2: AHB Write command with JMP_ON_CS instruction..,3: There is unknown instruction opcode in the..,4: Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in..,5: Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in..,?,?,?,?,?,?,?,?,14: Sequence execution timeout,?..." bitfld.long 0x00 0.--3. "AHBCMDERRID,Indicates the sequence index when an AHB command error is detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xE8++0x03 line.long 0x00 "STS2,Status Register 2" bitfld.long 0x00 8.--13. "AREFSEL,Flash A sample clock reference delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 2.--7. "ASLVSEL,Flash A sample clock slave delay line delay cell number selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 1. "AREFLOCK,Flash A sample clock reference delay line locked" "0,1" bitfld.long 0x00 0. "ASLVLOCK,Flash A sample clock slave delay line locked" "0,1" rgroup.long 0xEC++0x03 line.long 0x00 "AHBSPNDSTS,AHB Suspend Status Register" hexmask.long.word 0x00 16.--31. 1. "DATLFT,Left Data size for suspended command sequence (in byte)" bitfld.long 0x00 1.--3. "BUFID,AHB RX BUF ID for suspended command sequence" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "ACTIVE,Indicates if an AHB read prefetch command sequence has been suspended" "0,1" rgroup.long 0xF0++0x03 line.long 0x00 "IPRXFSTS,IP RX FIFO Status Register" hexmask.long.word 0x00 16.--31. 1. "RDCNTR,Total Read Data Counter: RDCNTR * 64 Bits" hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP RX FIFO" rgroup.long 0xF4++0x03 line.long 0x00 "IPTXFSTS,IP TX FIFO Status Register" hexmask.long.word 0x00 16.--31. 1. "WRCNTR,Total Write Data Counter: WRCNTR * 64 Bits" hexmask.long.byte 0x00 0.--7. 1. "FILL,Fill level of IP TX FIFO" repeat 32. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0x100)++0x03 line.long 0x00 "RFDR[$1],IP RX FIFO Data Register x $1" hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data" repeat.end repeat 32. (increment 0 1) (increment 0 0x04) wgroup.long ($2+0x180)++0x03 line.long 0x00 "TFDR[$1],IP TX FIFO Data Register x $1" hexmask.long 0x00 0.--31. 1. "TXDATA,TX Data" repeat.end repeat 64. (increment 0 1) (increment 0 0x04) group.long ($2+0x200)++0x03 line.long 0x00 "LUT[$1],LUT x $1" bitfld.long 0x00 26.--31. "OPCODE1,OPCODE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. "NUM_PADS1,NUM_PADS1" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. "OPERAND1,OPERAND1" bitfld.long 0x00 10.--15. "OPCODE0,OPCODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--9. "NUM_PADS0,NUM_PADS0" "0,1,2,3" hexmask.long.byte 0x00 0.--7. 1. "OPERAND0,OPERAND0" repeat.end group.long 0x420++0x03 line.long 0x00 "HADDRSTART,HADDR REMAP START ADDR" hexmask.long.tbyte 0x00 12.--31. 1. "ADDRSTART,HADDR start address" bitfld.long 0x00 0. "REMAPEN,AHB Bus address remap function enable" "0: HADDR REMAP Disabled,1: HADDR REMAP Enabled" group.long 0x424++0x03 line.long 0x00 "HADDREND,HADDR REMAP END ADDR" hexmask.long.tbyte 0x00 12.--31. 1. "ENDSTART,HADDR remap range's end addr 4K aligned" group.long 0x428++0x03 line.long 0x00 "HADDROFFSET,HADDR REMAP OFFSET" hexmask.long.tbyte 0x00 12.--31. 1. "ADDROFFSET,HADDR offset field remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFFSET" group.long 0x42C++0x03 line.long 0x00 "IPEDCTRL,IPED function control" bitfld.long 0x00 10. "IPED_SWRESET,Drive IPED interface i_abort" "0,1" bitfld.long 0x00 9. "IPED_PROTECT,when ipedctrl protect = 0 or priviledge access no restriction when ipedctrl protect = 1 only priviledge access can" "0,1" newline bitfld.long 0x00 8. "AHBGCMRD,AHB read IPED GCM mode decryption enable" "0,1" bitfld.long 0x00 7. "AHGCMWR,AHB write IPED GCM mode encryption enable" "0,1" newline bitfld.long 0x00 6. "IPGCMWR,IP write GCM mode enable" "0,1" bitfld.long 0x00 4. "AHBRD_EN,AHB read IPED CTR mode decryption enable" "0,1" newline bitfld.long 0x00 3. "AHBWR_EN,AHB write IPED CTR mode encryption enable" "0,1" bitfld.long 0x00 2. "IPWR_EN,IP write IPED CTR mode encryption enable" "0,1" newline bitfld.long 0x00 1. "IPED_EN,Drive IPED interface i_enable" "0,1" bitfld.long 0x00 0. "CONFIG,Drive IPED interface i_config" "0,1" group.long 0x500++0x03 line.long 0x00 "IPEDCTXCTRL0,IPED context control 0" bitfld.long 0x00 6.--7. "CTX3_FREEZE0,Controls the RW properties of this field and region 3 context registers (CTX3_xxxx)" "0,1,2,3" bitfld.long 0x00 4.--5. "CTX2_FREEZE0,Controls the RW properties of this field and region 2 context registers (CTX2_xxxx)" "0,1,2,3" newline bitfld.long 0x00 2.--3. "CTX1_FREEZE0,Controls the RW properties of this field and region 1 context registers (CTX1_xxxx)" "0,1,2,3" bitfld.long 0x00 0.--1. "CTX0_FREEZE0,Controls the RW properties of this field and region 0 context registers (CTX0_xxxx)" "0,1,2,3" group.long 0x504++0x03 line.long 0x00 "IPEDCTXCTRL1,IPED context control 1" bitfld.long 0x00 6.--7. "CTX3_FREEZE1,Controls the RW properties of this field and region 3 context registers (CTX3_xxxx)" "0,1,2,3" bitfld.long 0x00 4.--5. "CTX2_FREEZE1,Controls the RW properties of this field and region 2 context registers (CTX2_xxxx)" "0,1,2,3" newline bitfld.long 0x00 2.--3. "CTX1_FREEZE1,Controls the RW properties of this field and region 1 context registers (CTX1_xxxx)" "0,1,2,3" bitfld.long 0x00 0.--1. "CTX0_FREEZE1,Controls the RW properties of this field and region 0 context registers (CTX0_xxxx)" "0,1,2,3" group.long 0x520++0x03 line.long 0x00 "IPEDCTX0IV0,IPED context0 IV0" hexmask.long 0x00 0.--31. 1. "CTX0_IV0,Lowest 32 bits of IV for region 0" group.long 0x524++0x03 line.long 0x00 "IPEDCTX0IV1,IPED context0 IV1" hexmask.long 0x00 0.--31. 1. "CTX0_IV1,Highest 32 bits of IV for region 0" group.long 0x528++0x03 line.long 0x00 "IPEDCTX0START,Start address of region 0" hexmask.long.tbyte 0x00 8.--31. 1. "start_address,Start address of region 0" bitfld.long 0x00 1. "ahbbuserror_dis,If this bit is 1 ahb bus error is disable" "0,1" newline bitfld.long 0x00 0. "GCM,If this bit is 1 current region is GCM mode region" "0,1" group.long 0x52C++0x03 line.long 0x00 "IPEDCTX0END,End address of region 0" hexmask.long.tbyte 0x00 8.--31. 1. "end_address,End address of region 0" group.long 0x530++0x03 line.long 0x00 "IPEDCTX0AAD0,IPED context0 AAD0" hexmask.long 0x00 0.--31. 1. "CTX0_AAD0,Lowest 32 bits of AAD for region 0" group.long 0x534++0x03 line.long 0x00 "IPEDCTX0AAD1,IPED context0 AAD1" hexmask.long 0x00 0.--31. 1. "CTX0_AAD1,Highest 32 bits of AAD for region 0" group.long 0x540++0x03 line.long 0x00 "IPEDCTX1IV0,IPED context1 IV0" hexmask.long 0x00 0.--31. 1. "CTX1_IV0,Lowest 32 bits of IV for region 1" group.long 0x544++0x03 line.long 0x00 "IPEDCTX1IV1,IPED context1 IV1" hexmask.long 0x00 0.--31. 1. "CTX1_IV1,Highest 32 bits of IV for region 1" group.long 0x548++0x03 line.long 0x00 "IPEDCTX1START,Start address of region 1" hexmask.long.tbyte 0x00 8.--31. 1. "start_address,Start address of region 1" bitfld.long 0x00 1. "ahbbuserror_dis,If this bit is 1 ahb bus error is disable" "0,1" newline bitfld.long 0x00 0. "GCM,If this bit is 1 current region is GCM mode region" "0,1" group.long 0x54C++0x03 line.long 0x00 "IPEDCTX1END,End address of region 1" hexmask.long.tbyte 0x00 8.--31. 1. "end_address,End address of region 1" group.long 0x550++0x03 line.long 0x00 "IPEDCTX1AAD0,IPED context1 AAD0" hexmask.long 0x00 0.--31. 1. "CTX1_AAD0,Lowest 32 bits of AAD for region 1" group.long 0x554++0x03 line.long 0x00 "IPEDCTX1AAD1,IPED context1 AAD1" hexmask.long 0x00 0.--31. 1. "CTX1_AAD1,Highest 32 bits of AAD for region 1" group.long 0x560++0x03 line.long 0x00 "IPEDCTX2IV0,IPED context2 IV0" hexmask.long 0x00 0.--31. 1. "CTX2_IV0,Lowest 32 bits of IV for region 2" group.long 0x564++0x03 line.long 0x00 "IPEDCTX2IV1,IPED context2 IV1" hexmask.long 0x00 0.--31. 1. "CTX2_IV1,Highest 32 bits of IV for region 2" group.long 0x568++0x03 line.long 0x00 "IPEDCTX2START,Start address of region 2" hexmask.long.tbyte 0x00 8.--31. 1. "start_address,Start address of region 2" bitfld.long 0x00 1. "ahbbuserror_dis,If this bit is 1 ahb bus error is disable" "0,1" newline bitfld.long 0x00 0. "GCM,If this bit is 1 current region is GCM mode region" "0,1" group.long 0x56C++0x03 line.long 0x00 "IPEDCTX2END,End address of region 2" hexmask.long.tbyte 0x00 8.--31. 1. "end_address,End address of region 2" group.long 0x570++0x03 line.long 0x00 "IPEDCTX2AAD0,IPED context2 AAD0" hexmask.long 0x00 0.--31. 1. "CTX2_AAD0,Lowest 32 bits of AAD for region 2" group.long 0x574++0x03 line.long 0x00 "IPEDCTX2AAD1,IPED context2 AAD1" hexmask.long 0x00 0.--31. 1. "CTX2_AAD1,Highest 32 bits of AAD for region 2" group.long 0x580++0x03 line.long 0x00 "IPEDCTX3IV0,IPED context3 IV0" hexmask.long 0x00 0.--31. 1. "CTX3_IV0,Lowest 32 bits of IV for region 3" group.long 0x584++0x03 line.long 0x00 "IPEDCTX3IV1,IPED context3 IV1" hexmask.long 0x00 0.--31. 1. "CTX3_IV1,Highest 32 bits of IV for region 3" group.long 0x588++0x03 line.long 0x00 "IPEDCTX3START,Start address of region 3" hexmask.long.tbyte 0x00 8.--31. 1. "start_address,Start address of region 3" bitfld.long 0x00 1. "ahbbuserror_dis,If this bit is 1 ahb bus error is disable" "0,1" newline bitfld.long 0x00 0. "GCM,If this bit is 1 current region is GCM mode region" "0,1" group.long 0x58C++0x03 line.long 0x00 "IPEDCTX3END,End address of region 3" hexmask.long.tbyte 0x00 8.--31. 1. "end_address,End address of region 3" group.long 0x590++0x03 line.long 0x00 "IPEDCTX3AAD0,IPED context3 AAD0" hexmask.long 0x00 0.--31. 1. "CTX3_AAD0,Lowest 32 bits of AAD for region 3" group.long 0x594++0x03 line.long 0x00 "IPEDCTX3AAD1,IPED context3 AAD1" hexmask.long 0x00 0.--31. 1. "CTX3_AAD1,Highest 32 bits of AAD for region 3" tree.end tree "FREQME (Frequency Measurement)" base ad:0x40013140 rgroup.long 0x00++0x03 line.long 0x00 "FREQMECTRL_R,Frequency Measurement (in Read mode)" bitfld.long 0x00 31. "MEASURE_IN_PROGRESS,Measure in Progress" "0: Process complete,1: In Progress" hexmask.long 0x00 0.--30. 1. "RESULT,Result" wgroup.long 0x00++0x03 line.long 0x00 "FREQMECTRL_W,Frequency Measurement (in Write mode)" bitfld.long 0x00 31. "MEASURE_IN_PROGRESS,Measure in Progress" "0: FORCE_TERMINATE,1: Initiates Measurement Cycle" bitfld.long 0x00 30. "CONTINUOUS_MODE_EN,Continuous Mode Enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 14. "RESULT_READY_INT_EN,Result Ready Interrupt Enable" "0: DISABLE,1: ENABLE" bitfld.long 0x00 13. "GT_MAX_INT_EN,Greater Than Maximum Interrupt Enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 12. "LT_MIN_INT_EN,Less Than Minimum Interrupt Enable" "0: DISABLE,1: ENABLE" bitfld.long 0x00 9. "PULSE_POL,Pulse Polarity" "0: High Period,1: Low Period" newline bitfld.long 0x00 8. "PULSE_MODE,Pulse Width Measurement mode select" "0: Frequency Measurement Mode,1: Pulse Width Measurement mode" bitfld.long 0x00 0.--4. "REF_SCALE,Reference Clock Scaling Factor" "0: Count cycle = 2 ^ 0 = 1,1: Count cycle = 2 ^ 1 = 2,2: Count cycle = 2 ^ 2 = 4,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Count cycle = 2 ^ 31 = 2 147 483 648" group.long 0x04++0x03 line.long 0x00 "FREQMECTRLSTAT,Frequency Measurement Control Status" rbitfld.long 0x00 31. "MEASURE_IN_PROGRESS,Measure in Progress Status" "0,1" rbitfld.long 0x00 30. "CONTINUOUS_MODE_EN,Continuous Mode Enable Status" "0,1" newline eventfld.long 0x00 26. "RESULT_READY_STAT,Result Ready Status" "0,1" eventfld.long 0x00 25. "GT_MAX_STAT,Greater Than Maximum Result Status" "0,1" newline eventfld.long 0x00 24. "LT_MIN_STAT,Less Than Minimum Results Status" "0,1" rbitfld.long 0x00 14. "RESULT_READY_INT_EN,Result Ready Interrupt Enable Status" "0,1" newline rbitfld.long 0x00 13. "GT_MAX_INT_EN,Greater Then Maximum Interrupt Enable Status" "0,1" rbitfld.long 0x00 12. "LT_MIN_INT_EN,Less Than Minimum Interrupt Enable Status" "0,1" newline rbitfld.long 0x00 9. "PULSE_POL,Pulse Polarity Status" "0,1" rbitfld.long 0x00 8. "PULSE_MODE,Pulse Mode Status" "0,1" newline rbitfld.long 0x00 0.--4. "REF_SCALE,Reference Scale Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x08++0x03 line.long 0x00 "FREQMEMIN,Frequency Measurement Minimum" hexmask.long 0x00 0.--30. 1. "MIN_VALUE,Minumum Value" group.long 0x0C++0x03 line.long 0x00 "FREQMEMAX,Frequency Measurement Maximum" hexmask.long 0x00 0.--30. 1. "MAX_VALUE,Maximum Value" tree.end endif tree "GINT (Group GPIO input interrupt (GINT0/1))" repeat 2. (list 0. 1.) (list ad:0x40002000 ad:0x40003000) tree "GINT$1" base $2 group.long 0x00++0x03 line.long 0x00 "CTRL,GPIO grouped interrupt control register" bitfld.long 0x00 2. "TRIG,Group interrupt trigger" "0: Edge-triggered,1: Level-triggered" bitfld.long 0x00 1. "COMB,Combine enabled inputs for group interrupt" "0: Or,1: And" newline bitfld.long 0x00 0. "INT,Group interrupt status" "0: No request,1: Request active" group.long 0x00++0x03 line.long 0x00 "CTRL,GPIO grouped interrupt control" bitfld.long 0x00 2. "TRIG,Group interrupt trigger" "0: EDGE_TRIGGERED,1: LEVEL_TRIGGERED" bitfld.long 0x00 1. "COMB,Combine enabled inputs for group interrupt" "0: OR functionality,1: AND functionality" newline eventfld.long 0x00 0. "INT,Group interrupt status" "0: No interrupt request is pending,1: Interrupt request is pending" group.long 0x20++0x03 line.long 0x00 "PORT_POL[0],GPIO grouped interrupt port 0 polarity register" abitfld.long 0x00 0.--31. "POL,Configure pin polarity of port m pins for group interrupt" "0x00000000=0: the pin is active LOW,0x00000001=1: the pin is active HIGH" group.long 0x20++0x03 line.long 0x00 "PORT_POL[0],Port polarity" bitfld.long 0x00 31. "POL31,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 30. "POL30,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 29. "POL29,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 28. "POL28,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 27. "POL27,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 26. "POL26,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 25. "POL25,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 24. "POL24,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 23. "POL23,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 22. "POL22,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 21. "POL21,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 20. "POL20,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 19. "POL19,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 18. "POL18,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 17. "POL17,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 16. "POL16,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 15. "POL15,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 14. "POL14,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 13. "POL13,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 12. "POL12,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 11. "POL11,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 10. "POL10,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 9. "POL9,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 8. "POL8,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 7. "POL7,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 6. "POL6,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 5. "POL5,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 4. "POL4,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 3. "POL3,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 2. "POL2,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 1. "POL1,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 0. "POL0,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" group.long 0x24++0x03 line.long 0x00 "PORT_POL[1],GPIO grouped interrupt port 0 polarity register" abitfld.long 0x00 0.--31. "POL,Configure pin polarity of port m pins for group interrupt" "0x00000000=0: the pin is active LOW,0x00000001=1: the pin is active HIGH" group.long 0x24++0x03 line.long 0x00 "PORT_POL[1],Port polarity" bitfld.long 0x00 31. "POL31,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 30. "POL30,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 29. "POL29,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 28. "POL28,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 27. "POL27,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 26. "POL26,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 25. "POL25,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 24. "POL24,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 23. "POL23,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 22. "POL22,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 21. "POL21,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 20. "POL20,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 19. "POL19,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 18. "POL18,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 17. "POL17,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 16. "POL16,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 15. "POL15,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 14. "POL14,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 13. "POL13,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 12. "POL12,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 11. "POL11,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 10. "POL10,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 9. "POL9,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 8. "POL8,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 7. "POL7,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 6. "POL6,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 5. "POL5,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 4. "POL4,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 3. "POL3,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 2. "POL2,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" newline bitfld.long 0x00 1. "POL1,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" bitfld.long 0x00 0. "POL0,Polarity of pin n of the port" "0: Pin is active LOW,1: Pin is active HIGH" group.long 0x40++0x03 line.long 0x00 "PORT_ENA[0],GPIO grouped interrupt port 0 enable register" abitfld.long 0x00 0.--31. "ENA,Enable port 0 pin for group interrupt" "0x00000000=0: the port 0 pin is disabled and..,0x00000001=1: the port 0 pin is enabled and.." group.long 0x40++0x03 line.long 0x00 "PORT_ENA[0],GPIO grouped interrupt port 0 enable register" bitfld.long 0x00 31. "ENA31,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 30. "ENA30,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 29. "ENA29,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 28. "ENA28,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 27. "ENA27,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 26. "ENA26,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 25. "ENA25,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 24. "ENA24,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 23. "ENA23,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 22. "ENA22,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 21. "ENA21,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 20. "ENA20,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 19. "ENA19,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 18. "ENA18,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 17. "ENA17,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 16. "ENA16,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 15. "ENA15,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 14. "ENA14,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 13. "ENA13,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 12. "ENA12,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 11. "ENA11,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 10. "ENA10,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 9. "ENA9,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 8. "ENA8,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 7. "ENA7,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 6. "ENA6,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 5. "ENA5,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 4. "ENA4,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 3. "ENA3,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 2. "ENA2,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 1. "ENA1,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 0. "ENA0,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." group.long 0x44++0x03 line.long 0x00 "PORT_ENA[1],GPIO grouped interrupt port 0 enable register" abitfld.long 0x00 0.--31. "ENA,Enable port 0 pin for group interrupt" "0x00000000=0: the port 0 pin is disabled and..,0x00000001=1: the port 0 pin is enabled and.." group.long 0x44++0x03 line.long 0x00 "PORT_ENA[1],GPIO grouped interrupt port 0 enable register" bitfld.long 0x00 31. "ENA31,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 30. "ENA30,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 29. "ENA29,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 28. "ENA28,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 27. "ENA27,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 26. "ENA26,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 25. "ENA25,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 24. "ENA24,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 23. "ENA23,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 22. "ENA22,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 21. "ENA21,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 20. "ENA20,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 19. "ENA19,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 18. "ENA18,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 17. "ENA17,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 16. "ENA16,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 15. "ENA15,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 14. "ENA14,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 13. "ENA13,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 12. "ENA12,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 11. "ENA11,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 10. "ENA10,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 9. "ENA9,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 8. "ENA8,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 7. "ENA7,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 6. "ENA6,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 5. "ENA5,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 4. "ENA4,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 3. "ENA3,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 2. "ENA2,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." newline bitfld.long 0x00 1. "ENA1,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." bitfld.long 0x00 0. "ENA0,Enables port pin n to contribute to the group interrupt" "0: Pin is disabled and does not contribute to..,1: Pin is enabled and contributes to the grouped.." tree.end repeat.end tree.end tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)" tree "GPIO" base ad:0x4008C000 repeat 4. (increment 0 1) (increment 0 0x04) wgroup.long ($2+0x2000)++0x03 line.long 0x00 "DIR[$1],Port direction $1" bitfld.long 0x00 31. "DIRP31,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 30. "DIRP30,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 29. "DIRP29,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 28. "DIRP28,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 27. "DIRP27,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 26. "DIRP26,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 25. "DIRP25,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 24. "DIRP24,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 23. "DIRP23,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 22. "DIRP22,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 21. "DIRP21,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 20. "DIRP20,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 19. "DIRP19,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 18. "DIRP18,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 17. "DIRP17,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 16. "DIRP16,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 15. "DIRP15,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 14. "DIRP14,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 13. "DIRP13,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 12. "DIRP12,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 11. "DIRP11,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 10. "DIRP10,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 9. "DIRP9,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 8. "DIRP8,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 7. "DIRP7,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 6. "DIRP6,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 5. "DIRP5,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 4. "DIRP4,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 3. "DIRP3,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 2. "DIRP2,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 1. "DIRP1,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 0. "DIRP0,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2080)++0x03 line.long 0x00 "MASK[$1],Port mask $1" bitfld.long 0x00 31. "MASKP31,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 30. "MASKP30,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 29. "MASKP29,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 28. "MASKP28,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 27. "MASKP27,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 26. "MASKP26,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 25. "MASKP25,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 24. "MASKP24,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 23. "MASKP23,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 22. "MASKP22,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 21. "MASKP21,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 20. "MASKP20,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 19. "MASKP19,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 18. "MASKP18,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 17. "MASKP17,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 16. "MASKP16,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 15. "MASKP15,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 14. "MASKP14,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 13. "MASKP13,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 12. "MASKP12,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 11. "MASKP11,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 10. "MASKP10,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 9. "MASKP9,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 8. "MASKP8,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 7. "MASKP7,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 6. "MASKP6,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 5. "MASKP5,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 4. "MASKP4,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 3. "MASKP3,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 2. "MASKP2,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 1. "MASKP1,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 0. "MASKP0,Port Mask" "0: Read MPIN,1: Read MPIN" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2100)++0x03 line.long 0x00 "PIN[$1],Port pin $1" bitfld.long 0x00 31. "PORT31,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 30. "PORT30,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 29. "PORT29,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 28. "PORT28,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 27. "PORT27,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 26. "PORT26,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 25. "PORT25,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 24. "PORT24,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 23. "PORT23,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 22. "PORT22,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 21. "PORT21,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 20. "PORT20,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 19. "PORT19,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 18. "PORT18,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 17. "PORT17,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 16. "PORT16,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 15. "PORT15,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 14. "PORT14,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 13. "PORT13,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 12. "PORT12,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 11. "PORT11,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 10. "PORT10,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 9. "PORT9,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 8. "PORT8,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 7. "PORT7,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 6. "PORT6,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 5. "PORT5,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 4. "PORT4,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 3. "PORT3,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 2. "PORT2,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 1. "PORT1,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 0. "PORT0,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2180)++0x03 line.long 0x00 "MPIN[$1],Masked Port Pin $1" bitfld.long 0x00 31. "MPORTP31,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 30. "MPORTP30,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 29. "MPORTP29,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 28. "MPORTP28,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 27. "MPORTP27,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 26. "MPORTP26,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 25. "MPORTP25,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 24. "MPORTP24,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 23. "MPORTP23,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 22. "MPORTP22,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 21. "MPORTP21,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 20. "MPORTP20,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 19. "MPORTP19,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 18. "MPORTP18,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 17. "MPORTP17,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 16. "MPORTP16,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 15. "MPORTP15,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 14. "MPORTP14,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 13. "MPORTP13,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 12. "MPORTP12,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 11. "MPORTP11,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 10. "MPORTP10,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 9. "MPORTP9,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 8. "MPORTP8,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 7. "MPORTP7,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 6. "MPORTP6,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 5. "MPORTP5,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 4. "MPORTP4,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 3. "MPORTP3,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 2. "MPORTP2,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 1. "MPORTP1,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 0. "MPORTP0,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2200)++0x03 line.long 0x00 "SET[$1],Port set $1" hexmask.long 0x00 0.--31. 1. "SETP,Read or set output bits" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2280)++0x03 line.long 0x00 "CLR[$1],Port clear $1" eventfld.long 0x00 31. "CLRP31,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 30. "CLRP30,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 29. "CLRP29,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 28. "CLRP28,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 27. "CLRP27,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 26. "CLRP26,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 25. "CLRP25,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 24. "CLRP24,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 23. "CLRP23,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 22. "CLRP22,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 21. "CLRP21,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 20. "CLRP20,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 19. "CLRP19,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 18. "CLRP18,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 17. "CLRP17,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 16. "CLRP16,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 15. "CLRP15,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 14. "CLRP14,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 13. "CLRP13,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 12. "CLRP12,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 11. "CLRP11,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 10. "CLRP10,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 9. "CLRP9,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 8. "CLRP8,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 7. "CLRP7,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 6. "CLRP6,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 5. "CLRP5,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 4. "CLRP4,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 3. "CLRP3,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 2. "CLRP2,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 1. "CLRP1,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 0. "CLRP0,Clear output bits" "0: No operation,1: Clears output bit" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) wgroup.long ($2+0x2300)++0x03 line.long 0x00 "NOT[$1],Port toggle $1" bitfld.long 0x00 31. "NOTP31,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 30. "NOTP30,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 29. "NOTP29,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 28. "NOTP28,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 27. "NOTP27,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 26. "NOTP26,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 25. "NOTP25,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 24. "NOTP24,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 23. "NOTP23,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 22. "NOTP22,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 21. "NOTP21,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 20. "NOTP20,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 19. "NOTP19,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 18. "NOTP18,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 17. "NOTP17,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 16. "NOTP16,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 15. "NOTP15,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 14. "NOTP14,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 13. "NOTP13,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 12. "NOTP12,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 11. "NOTP11,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 10. "NOTP10,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 9. "NOTP9,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 8. "NOTP8,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 7. "NOTP7,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 6. "NOTP6,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 5. "NOTP5,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 4. "NOTP4,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 3. "NOTP3,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 2. "NOTP2,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 1. "NOTP1,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 0. "NOTP0,Toggle output bits" "0: No operation,1: Toggle output bit" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) wgroup.long ($2+0x2380)++0x03 line.long 0x00 "DIRSET[$1],Port direction set $1" bitfld.long 0x00 31. "DIRSETP31,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 30. "DIRSETP30,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 29. "DIRSETP29,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 28. "DIRSETP28,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 27. "DIRSETP27,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 26. "DIRSETP26,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 25. "DIRSETP25,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 24. "DIRSETP24,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 23. "DIRSETP23,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 22. "DIRSETP22,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 21. "DIRSETP21,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 20. "DIRSETP20,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 19. "DIRSETP19,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 18. "DIRSETP18,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 17. "DIRSETP17,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 16. "DIRSETP16,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 15. "DIRSETP15,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 14. "DIRSETP14,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 13. "DIRSETP13,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 12. "DIRSETP12,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 11. "DIRSETP11,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 10. "DIRSETP10,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 9. "DIRSETP9,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 8. "DIRSETP8,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 7. "DIRSETP7,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 6. "DIRSETP6,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 5. "DIRSETP5,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 4. "DIRSETP4,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 3. "DIRSETP3,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 2. "DIRSETP2,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 1. "DIRSETP1,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 0. "DIRSETP0,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2400)++0x03 line.long 0x00 "DIRCLR[$1],Port direction clear $1" eventfld.long 0x00 31. "DIRCLRP31,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 30. "DIRCLRP30,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 29. "DIRCLRP29,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 28. "DIRCLRP28,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 27. "DIRCLRP27,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 26. "DIRCLRP26,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 25. "DIRCLRP25,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 24. "DIRCLRP24,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 23. "DIRCLRP23,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 22. "DIRCLRP22,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 21. "DIRCLRP21,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 20. "DIRCLRP20,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 19. "DIRCLRP19,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 18. "DIRCLRP18,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 17. "DIRCLRP17,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 16. "DIRCLRP16,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 15. "DIRCLRP15,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 14. "DIRCLRP14,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 13. "DIRCLRP13,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 12. "DIRCLRP12,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 11. "DIRCLRP11,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 10. "DIRCLRP10,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 9. "DIRCLRP9,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 8. "DIRCLRP8,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 7. "DIRCLRP7,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 6. "DIRCLRP6,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 5. "DIRCLRP5,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 4. "DIRCLRP4,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 3. "DIRCLRP3,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 2. "DIRCLRP2,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 1. "DIRCLRP1,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 0. "DIRCLRP0,Clear direction bits" "0: No operation,1: Clears direction bits" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) wgroup.long ($2+0x2480)++0x03 line.long 0x00 "DIRNOT[$1],Port direction toggle $1" hexmask.long 0x00 0.--28. 1. "DIRNOTP,Toggle direction bits" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2500)++0x03 line.long 0x00 "INTENA[$1],Interrupt A enable control $1" bitfld.long 0x00 31. "INT_EN31,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 30. "INT_EN30,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 29. "INT_EN29,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 28. "INT_EN28,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 27. "INT_EN27,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 26. "INT_EN26,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 25. "INT_EN25,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 24. "INT_EN24,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 23. "INT_EN23,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 22. "INT_EN22,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 21. "INT_EN21,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 20. "INT_EN20,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 19. "INT_EN19,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 18. "INT_EN18,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 17. "INT_EN17,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 16. "INT_EN16,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 15. "INT_EN15,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 14. "INT_EN14,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 13. "INT_EN13,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 12. "INT_EN12,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 11. "INT_EN11,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 10. "INT_EN10,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 9. "INT_EN9,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 8. "INT_EN8,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 7. "INT_EN7,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 6. "INT_EN6,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 5. "INT_EN5,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 4. "INT_EN4,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 3. "INT_EN3,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 2. "INT_EN2,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 1. "INT_EN1,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 0. "INT_EN0,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2580)++0x03 line.long 0x00 "INTENB[$1],Interrupt B enable control $1" bitfld.long 0x00 31. "INT_EN31,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 30. "INT_EN30,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 29. "INT_EN29,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 28. "INT_EN28,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 27. "INT_EN27,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 26. "INT_EN26,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 25. "INT_EN25,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 24. "INT_EN24,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 23. "INT_EN23,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 22. "INT_EN22,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 21. "INT_EN21,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 20. "INT_EN20,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 19. "INT_EN19,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 18. "INT_EN18,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 17. "INT_EN17,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 16. "INT_EN16,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 15. "INT_EN15,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 14. "INT_EN14,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 13. "INT_EN13,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 12. "INT_EN12,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 11. "INT_EN11,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 10. "INT_EN10,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 9. "INT_EN9,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 8. "INT_EN8,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 7. "INT_EN7,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 6. "INT_EN6,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 5. "INT_EN5,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 4. "INT_EN4,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 3. "INT_EN3,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 2. "INT_EN2,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 1. "INT_EN1,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 0. "INT_EN0,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2600)++0x03 line.long 0x00 "INTPOL[$1],Interupt polarity control $1" bitfld.long 0x00 31. "POL_CTL31,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 30. "POL_CTL30,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 29. "POL_CTL29,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 28. "POL_CTL28,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 27. "POL_CTL27,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 26. "POL_CTL26,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 25. "POL_CTL25,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 24. "POL_CTL24,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 23. "POL_CTL23,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 22. "POL_CTL22,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 21. "POL_CTL21,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 20. "POL_CTL20,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 19. "POL_CTL19,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 18. "POL_CTL18,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 17. "POL_CTL17,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 16. "POL_CTL16,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 15. "POL_CTL15,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 14. "POL_CTL14,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 13. "POL_CTL13,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 12. "POL_CTL12,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 11. "POL_CTL11,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 10. "POL_CTL10,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 9. "POL_CTL9,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 8. "POL_CTL8,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 7. "POL_CTL7,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 6. "POL_CTL6,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 5. "POL_CTL5,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 4. "POL_CTL4,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 3. "POL_CTL3,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 2. "POL_CTL2,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 1. "POL_CTL1,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 0. "POL_CTL0,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2680)++0x03 line.long 0x00 "INTEDG[$1],Interrupt edge select $1" bitfld.long 0x00 31. "EDGE31,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 30. "EDGE30,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 29. "EDGE29,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 28. "EDGE28,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 27. "EDGE27,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 26. "EDGE26,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 25. "EDGE25,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 24. "EDGE24,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 23. "EDGE23,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 22. "EDGE22,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 21. "EDGE21,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 20. "EDGE20,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 19. "EDGE19,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 18. "EDGE18,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 17. "EDGE17,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 16. "EDGE16,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 15. "EDGE15,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 14. "EDGE14,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 13. "EDGE13,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 12. "EDGE12,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 11. "EDGE11,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 10. "EDGE10,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 9. "EDGE9,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 8. "EDGE8,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 7. "EDGE7,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 6. "EDGE6,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 5. "EDGE5,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 4. "EDGE4,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 3. "EDGE3,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 2. "EDGE2,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 1. "EDGE1,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 0. "EDGE0,Edge or level mode select bits" "0: Level mode,1: Edge mode" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2700)++0x03 line.long 0x00 "INTSTATA[$1],Interrupt status for interrupt A $1" hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2780)++0x03 line.long 0x00 "INTSTATB[$1],Interrupt status for interrupt B $1" hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status" repeat.end repeat 4. (increment 0 1)(increment 0 0x20) tree "Byte_Pin[$1]" group.byte ($2+0x00)++0x00 line.byte 0x00 "B_[0],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x01)++0x00 line.byte 0x00 "B_[1],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x02)++0x00 line.byte 0x00 "B_[2],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x03)++0x00 line.byte 0x00 "B_[3],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x04)++0x00 line.byte 0x00 "B_[4],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x05)++0x00 line.byte 0x00 "B_[5],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x06)++0x00 line.byte 0x00 "B_[6],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x07)++0x00 line.byte 0x00 "B_[7],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x08)++0x00 line.byte 0x00 "B_[8],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x09)++0x00 line.byte 0x00 "B_[9],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x0A)++0x00 line.byte 0x00 "B_[10],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x0B)++0x00 line.byte 0x00 "B_[11],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x0C)++0x00 line.byte 0x00 "B_[12],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x0D)++0x00 line.byte 0x00 "B_[13],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x0E)++0x00 line.byte 0x00 "B_[14],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x0F)++0x00 line.byte 0x00 "B_[15],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x10)++0x00 line.byte 0x00 "B_[16],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x11)++0x00 line.byte 0x00 "B_[17],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x12)++0x00 line.byte 0x00 "B_[18],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x13)++0x00 line.byte 0x00 "B_[19],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x14)++0x00 line.byte 0x00 "B_[20],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x15)++0x00 line.byte 0x00 "B_[21],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x16)++0x00 line.byte 0x00 "B_[22],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x17)++0x00 line.byte 0x00 "B_[23],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x18)++0x00 line.byte 0x00 "B_[24],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x19)++0x00 line.byte 0x00 "B_[25],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x1A)++0x00 line.byte 0x00 "B_[26],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x1B)++0x00 line.byte 0x00 "B_[27],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x1C)++0x00 line.byte 0x00 "B_[28],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x1D)++0x00 line.byte 0x00 "B_[29],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x1E)++0x00 line.byte 0x00 "B_[30],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" group.byte ($2+0x1F)++0x00 line.byte 0x00 "B_[31],Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" tree.end repeat.end repeat 4. (increment 0 1)(increment 0 0x1080) tree "Word_Pin[$1]" group.long ($2+0x1000)++0x03 line.long 0x00 "W_[0],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1004)++0x03 line.long 0x00 "W_[1],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1008)++0x03 line.long 0x00 "W_[2],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x100C)++0x03 line.long 0x00 "W_[3],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1010)++0x03 line.long 0x00 "W_[4],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1014)++0x03 line.long 0x00 "W_[5],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1018)++0x03 line.long 0x00 "W_[6],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x101C)++0x03 line.long 0x00 "W_[7],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1020)++0x03 line.long 0x00 "W_[8],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1024)++0x03 line.long 0x00 "W_[9],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1028)++0x03 line.long 0x00 "W_[10],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x102C)++0x03 line.long 0x00 "W_[11],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1030)++0x03 line.long 0x00 "W_[12],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1034)++0x03 line.long 0x00 "W_[13],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1038)++0x03 line.long 0x00 "W_[14],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x103C)++0x03 line.long 0x00 "W_[15],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1040)++0x03 line.long 0x00 "W_[16],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1044)++0x03 line.long 0x00 "W_[17],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1048)++0x03 line.long 0x00 "W_[18],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x104C)++0x03 line.long 0x00 "W_[19],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1050)++0x03 line.long 0x00 "W_[20],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1054)++0x03 line.long 0x00 "W_[21],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1058)++0x03 line.long 0x00 "W_[22],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x105C)++0x03 line.long 0x00 "W_[23],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1060)++0x03 line.long 0x00 "W_[24],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1064)++0x03 line.long 0x00 "W_[25],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1068)++0x03 line.long 0x00 "W_[26],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x106C)++0x03 line.long 0x00 "W_[27],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1070)++0x03 line.long 0x00 "W_[28],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1074)++0x03 line.long 0x00 "W_[29],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x1078)++0x03 line.long 0x00 "W_[30],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" group.long ($2+0x107C)++0x03 line.long 0x00 "W_[31],Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" tree.end repeat.end tree.end tree "SECGPIO" base ad:0x400A8000 repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF ) group.byte ($2+0x00)++0x00 line.byte 0x00 "B0_$1,Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" repeat.end repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF ) group.byte ($2+0x10)++0x00 line.byte 0x00 "B0_$1,Byte pin registers for all port GPIO pins" bitfld.byte 0x00 0. "PBYTE,Port Byte" "0,1" repeat.end repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x03 line.long 0x00 "W0_$1,Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" repeat.end repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1040)++0x03 line.long 0x00 "W0_$1,Word pin registers for all port GPIO pins" hexmask.long 0x00 0.--31. 1. "PWORD,PWORD" repeat.end wgroup.long 0x2000++0x03 line.long 0x00 "DIR0,Port direction" bitfld.long 0x00 31. "DIRP31,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 30. "DIRP30,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 29. "DIRP29,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 28. "DIRP28,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 27. "DIRP27,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 26. "DIRP26,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 25. "DIRP25,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 24. "DIRP24,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 23. "DIRP23,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 22. "DIRP22,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 21. "DIRP21,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 20. "DIRP20,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 19. "DIRP19,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 18. "DIRP18,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 17. "DIRP17,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 16. "DIRP16,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 15. "DIRP15,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 14. "DIRP14,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 13. "DIRP13,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 12. "DIRP12,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 11. "DIRP11,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 10. "DIRP10,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 9. "DIRP9,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 8. "DIRP8,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 7. "DIRP7,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 6. "DIRP6,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 5. "DIRP5,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 4. "DIRP4,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 3. "DIRP3,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 2. "DIRP2,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" newline bitfld.long 0x00 1. "DIRP1,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" bitfld.long 0x00 0. "DIRP0,Selects pin direction for pin PIOa_b" "0: DIR_0,1: Output" group.long 0x2080++0x03 line.long 0x00 "MASK0,Port mask" bitfld.long 0x00 31. "MASKP31,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 30. "MASKP30,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 29. "MASKP29,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 28. "MASKP28,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 27. "MASKP27,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 26. "MASKP26,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 25. "MASKP25,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 24. "MASKP24,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 23. "MASKP23,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 22. "MASKP22,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 21. "MASKP21,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 20. "MASKP20,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 19. "MASKP19,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 18. "MASKP18,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 17. "MASKP17,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 16. "MASKP16,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 15. "MASKP15,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 14. "MASKP14,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 13. "MASKP13,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 12. "MASKP12,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 11. "MASKP11,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 10. "MASKP10,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 9. "MASKP9,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 8. "MASKP8,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 7. "MASKP7,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 6. "MASKP6,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 5. "MASKP5,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 4. "MASKP4,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 3. "MASKP3,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 2. "MASKP2,Port Mask" "0: Read MPIN,1: Read MPIN" newline bitfld.long 0x00 1. "MASKP1,Port Mask" "0: Read MPIN,1: Read MPIN" bitfld.long 0x00 0. "MASKP0,Port Mask" "0: Read MPIN,1: Read MPIN" group.long 0x2100++0x03 line.long 0x00 "PIN0,Port pin" bitfld.long 0x00 31. "PORT31,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 30. "PORT30,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 29. "PORT29,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 28. "PORT28,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 27. "PORT27,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 26. "PORT26,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 25. "PORT25,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 24. "PORT24,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 23. "PORT23,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 22. "PORT22,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 21. "PORT21,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 20. "PORT20,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 19. "PORT19,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 18. "PORT18,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 17. "PORT17,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 16. "PORT16,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 15. "PORT15,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 14. "PORT14,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 13. "PORT13,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 12. "PORT12,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 11. "PORT11,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 10. "PORT10,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 9. "PORT9,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 8. "PORT8,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 7. "PORT7,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 6. "PORT6,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 5. "PORT5,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 4. "PORT4,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 3. "PORT3,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 2. "PORT2,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" newline bitfld.long 0x00 1. "PORT1,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" bitfld.long 0x00 0. "PORT0,Port pins" "0: Read- pin is low Write- clear output bit,1: Read- pin is high Write- set output bit" group.long 0x2180++0x03 line.long 0x00 "MPIN0,Masked Port Pin" bitfld.long 0x00 31. "MPORTP31,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 30. "MPORTP30,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 29. "MPORTP29,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 28. "MPORTP28,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 27. "MPORTP27,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 26. "MPORTP26,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 25. "MPORTP25,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 24. "MPORTP24,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 23. "MPORTP23,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 22. "MPORTP22,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 21. "MPORTP21,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 20. "MPORTP20,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 19. "MPORTP19,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 18. "MPORTP18,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 17. "MPORTP17,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 16. "MPORTP16,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 15. "MPORTP15,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 14. "MPORTP14,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 13. "MPORTP13,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 12. "MPORTP12,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 11. "MPORTP11,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 10. "MPORTP10,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 9. "MPORTP9,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 8. "MPORTP8,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 7. "MPORTP7,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 6. "MPORTP6,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 5. "MPORTP5,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 4. "MPORTP4,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 3. "MPORTP3,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 2. "MPORTP2,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." newline bitfld.long 0x00 1. "MPORTP1,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." bitfld.long 0x00 0. "MPORTP0,Mask bits for port pins" "0: Read- pin is LOW and/or the corresponding bit..,1: Read- pin is HIGH and the corresponding bit.." group.long 0x2200++0x03 line.long 0x00 "SET0,Port set" hexmask.long 0x00 0.--31. 1. "SETP,Read or set output bits" group.long 0x2280++0x03 line.long 0x00 "CLR0,Port clear" eventfld.long 0x00 31. "CLRP31,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 30. "CLRP30,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 29. "CLRP29,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 28. "CLRP28,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 27. "CLRP27,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 26. "CLRP26,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 25. "CLRP25,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 24. "CLRP24,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 23. "CLRP23,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 22. "CLRP22,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 21. "CLRP21,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 20. "CLRP20,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 19. "CLRP19,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 18. "CLRP18,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 17. "CLRP17,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 16. "CLRP16,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 15. "CLRP15,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 14. "CLRP14,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 13. "CLRP13,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 12. "CLRP12,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 11. "CLRP11,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 10. "CLRP10,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 9. "CLRP9,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 8. "CLRP8,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 7. "CLRP7,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 6. "CLRP6,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 5. "CLRP5,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 4. "CLRP4,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 3. "CLRP3,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 2. "CLRP2,Clear output bits" "0: No operation,1: Clears output bit" newline eventfld.long 0x00 1. "CLRP1,Clear output bits" "0: No operation,1: Clears output bit" eventfld.long 0x00 0. "CLRP0,Clear output bits" "0: No operation,1: Clears output bit" wgroup.long 0x2300++0x03 line.long 0x00 "NOT0,Port toggle" bitfld.long 0x00 31. "NOTP31,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 30. "NOTP30,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 29. "NOTP29,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 28. "NOTP28,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 27. "NOTP27,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 26. "NOTP26,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 25. "NOTP25,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 24. "NOTP24,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 23. "NOTP23,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 22. "NOTP22,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 21. "NOTP21,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 20. "NOTP20,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 19. "NOTP19,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 18. "NOTP18,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 17. "NOTP17,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 16. "NOTP16,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 15. "NOTP15,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 14. "NOTP14,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 13. "NOTP13,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 12. "NOTP12,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 11. "NOTP11,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 10. "NOTP10,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 9. "NOTP9,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 8. "NOTP8,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 7. "NOTP7,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 6. "NOTP6,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 5. "NOTP5,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 4. "NOTP4,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 3. "NOTP3,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 2. "NOTP2,Toggle output bits" "0: No operation,1: Toggle output bit" newline bitfld.long 0x00 1. "NOTP1,Toggle output bits" "0: No operation,1: Toggle output bit" bitfld.long 0x00 0. "NOTP0,Toggle output bits" "0: No operation,1: Toggle output bit" wgroup.long 0x2380++0x03 line.long 0x00 "DIRSET0,Port direction set" bitfld.long 0x00 31. "DIRSETP31,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 30. "DIRSETP30,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 29. "DIRSETP29,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 28. "DIRSETP28,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 27. "DIRSETP27,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 26. "DIRSETP26,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 25. "DIRSETP25,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 24. "DIRSETP24,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 23. "DIRSETP23,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 22. "DIRSETP22,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 21. "DIRSETP21,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 20. "DIRSETP20,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 19. "DIRSETP19,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 18. "DIRSETP18,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 17. "DIRSETP17,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 16. "DIRSETP16,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 15. "DIRSETP15,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 14. "DIRSETP14,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 13. "DIRSETP13,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 12. "DIRSETP12,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 11. "DIRSETP11,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 10. "DIRSETP10,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 9. "DIRSETP9,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 8. "DIRSETP8,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 7. "DIRSETP7,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 6. "DIRSETP6,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 5. "DIRSETP5,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 4. "DIRSETP4,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 3. "DIRSETP3,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 2. "DIRSETP2,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" newline bitfld.long 0x00 1. "DIRSETP1,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" bitfld.long 0x00 0. "DIRSETP0,Direction set bits for Port pins" "0: No operation,1: Sets direction bit" group.long 0x2400++0x03 line.long 0x00 "DIRCLR0,Port direction clear" eventfld.long 0x00 31. "DIRCLRP31,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 30. "DIRCLRP30,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 29. "DIRCLRP29,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 28. "DIRCLRP28,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 27. "DIRCLRP27,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 26. "DIRCLRP26,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 25. "DIRCLRP25,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 24. "DIRCLRP24,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 23. "DIRCLRP23,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 22. "DIRCLRP22,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 21. "DIRCLRP21,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 20. "DIRCLRP20,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 19. "DIRCLRP19,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 18. "DIRCLRP18,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 17. "DIRCLRP17,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 16. "DIRCLRP16,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 15. "DIRCLRP15,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 14. "DIRCLRP14,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 13. "DIRCLRP13,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 12. "DIRCLRP12,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 11. "DIRCLRP11,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 10. "DIRCLRP10,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 9. "DIRCLRP9,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 8. "DIRCLRP8,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 7. "DIRCLRP7,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 6. "DIRCLRP6,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 5. "DIRCLRP5,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 4. "DIRCLRP4,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 3. "DIRCLRP3,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 2. "DIRCLRP2,Clear direction bits" "0: No operation,1: Clears direction bits" newline eventfld.long 0x00 1. "DIRCLRP1,Clear direction bits" "0: No operation,1: Clears direction bits" eventfld.long 0x00 0. "DIRCLRP0,Clear direction bits" "0: No operation,1: Clears direction bits" wgroup.long 0x2480++0x03 line.long 0x00 "DIRNOT0,Port direction toggle" hexmask.long 0x00 0.--28. 1. "DIRNOTP,Toggle direction bits" group.long 0x2500++0x03 line.long 0x00 "INTENA0,Interrupt A enable control" bitfld.long 0x00 31. "INT_EN31,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 30. "INT_EN30,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 29. "INT_EN29,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 28. "INT_EN28,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 27. "INT_EN27,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 26. "INT_EN26,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 25. "INT_EN25,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 24. "INT_EN24,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 23. "INT_EN23,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 22. "INT_EN22,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 21. "INT_EN21,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 20. "INT_EN20,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 19. "INT_EN19,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 18. "INT_EN18,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 17. "INT_EN17,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 16. "INT_EN16,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 15. "INT_EN15,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 14. "INT_EN14,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 13. "INT_EN13,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 12. "INT_EN12,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 11. "INT_EN11,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 10. "INT_EN10,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 9. "INT_EN9,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 8. "INT_EN8,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 7. "INT_EN7,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 6. "INT_EN6,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 5. "INT_EN5,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 4. "INT_EN4,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 3. "INT_EN3,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 2. "INT_EN2,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" newline bitfld.long 0x00 1. "INT_EN1,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" bitfld.long 0x00 0. "INT_EN0,Interrupt A enable bits" "0: Pin does not contribute to GPIO interrupt A,1: Pin contributes to GPIO interrupt A" group.long 0x2580++0x03 line.long 0x00 "INTENB0,Interrupt B enable control" bitfld.long 0x00 31. "INT_EN31,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 30. "INT_EN30,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 29. "INT_EN29,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 28. "INT_EN28,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 27. "INT_EN27,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 26. "INT_EN26,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 25. "INT_EN25,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 24. "INT_EN24,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 23. "INT_EN23,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 22. "INT_EN22,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 21. "INT_EN21,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 20. "INT_EN20,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 19. "INT_EN19,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 18. "INT_EN18,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 17. "INT_EN17,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 16. "INT_EN16,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 15. "INT_EN15,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 14. "INT_EN14,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 13. "INT_EN13,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 12. "INT_EN12,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 11. "INT_EN11,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 10. "INT_EN10,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 9. "INT_EN9,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 8. "INT_EN8,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 7. "INT_EN7,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 6. "INT_EN6,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 5. "INT_EN5,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 4. "INT_EN4,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 3. "INT_EN3,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 2. "INT_EN2,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" newline bitfld.long 0x00 1. "INT_EN1,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" bitfld.long 0x00 0. "INT_EN0,Interrupt B enable bits" "0: Pin does not contribute to GPIO interrupt B,1: Pin contributes to GPIO interrupt B" group.long 0x2600++0x03 line.long 0x00 "INTPOL0,Interupt polarity control" bitfld.long 0x00 31. "POL_CTL31,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 30. "POL_CTL30,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 29. "POL_CTL29,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 28. "POL_CTL28,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 27. "POL_CTL27,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 26. "POL_CTL26,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 25. "POL_CTL25,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 24. "POL_CTL24,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 23. "POL_CTL23,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 22. "POL_CTL22,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 21. "POL_CTL21,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 20. "POL_CTL20,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 19. "POL_CTL19,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 18. "POL_CTL18,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 17. "POL_CTL17,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 16. "POL_CTL16,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 15. "POL_CTL15,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 14. "POL_CTL14,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 13. "POL_CTL13,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 12. "POL_CTL12,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 11. "POL_CTL11,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 10. "POL_CTL10,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 9. "POL_CTL9,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 8. "POL_CTL8,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 7. "POL_CTL7,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 6. "POL_CTL6,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 5. "POL_CTL5,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 4. "POL_CTL4,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 3. "POL_CTL3,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 2. "POL_CTL2,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" newline bitfld.long 0x00 1. "POL_CTL1,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" bitfld.long 0x00 0. "POL_CTL0,Polarity control for each pin" "0: High level or rising edge triggered,1: Low level or falling edge triggered" group.long 0x2680++0x03 line.long 0x00 "INTEDG0,Interrupt edge select" bitfld.long 0x00 31. "EDGE31,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 30. "EDGE30,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 29. "EDGE29,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 28. "EDGE28,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 27. "EDGE27,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 26. "EDGE26,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 25. "EDGE25,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 24. "EDGE24,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 23. "EDGE23,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 22. "EDGE22,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 21. "EDGE21,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 20. "EDGE20,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 19. "EDGE19,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 18. "EDGE18,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 17. "EDGE17,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 16. "EDGE16,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 15. "EDGE15,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 14. "EDGE14,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 13. "EDGE13,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 12. "EDGE12,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 11. "EDGE11,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 10. "EDGE10,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 9. "EDGE9,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 8. "EDGE8,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 7. "EDGE7,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 6. "EDGE6,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 5. "EDGE5,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 4. "EDGE4,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 3. "EDGE3,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 2. "EDGE2,Edge or level mode select bits" "0: Level mode,1: Edge mode" newline bitfld.long 0x00 1. "EDGE1,Edge or level mode select bits" "0: Level mode,1: Edge mode" bitfld.long 0x00 0. "EDGE0,Edge or level mode select bits" "0: Level mode,1: Edge mode" group.long 0x2700++0x03 line.long 0x00 "INTSTATA0,Interrupt status for interrupt A" hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status" group.long 0x2780++0x03 line.long 0x00 "INTSTATB0,Interrupt status for interrupt B" hexmask.long 0x00 0.--31. 1. "STATUS,Interrupt status" tree.end tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "HSCMP" repeat 3. (list 0. 1. 2.) (list ad:0x400B3000 ad:0x400B7000 ad:0x400BA000) tree "HSCMP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number" newline hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number" rgroup.long 0x04++0x03 line.long 0x00 "PARAM,Parameter Register" bitfld.long 0x00 0.--3. "DAC_RES,DAC Resolution" "0: 4 bit DAC,1: 6 bit DAC,2: 8 bit DAC,3: 10 bit DAC,4: 12 bit DAC,5: 14 bit DAC,6: 16 bit DAC,?..." group.long 0x08++0x03 line.long 0x00 "CCR0,Comparator Control Register 0" bitfld.long 0x00 2. "LINKEN,CMP-to-DAC Link Enable" "0: Disable the CMP-to-DAC link,1: Enable the CMP-to-DAC link" bitfld.long 0x00 1. "CMP_STOP_EN,Comparator STOP Mode Enable" "0: Disable the analog comparator regardless of..,1: Allow the analog comparator to be enabled by.." newline bitfld.long 0x00 0. "CMP_EN,Comparator Enable" "0: Disable (The analog logic remains off and..,1: ENABLE" group.long 0x0C++0x03 line.long 0x00 "CCR1,Comparator Control Register 1" hexmask.long.byte 0x00 24.--31. 1. "FILT_PER,Filter Sample Period" bitfld.long 0x00 16.--18. "FILT_CNT,Filter Sample Count" "0: Filter is bypassed,1: 1 consecutive sample (Comparator output is..,2: 2 consecutive samples,3: 3 consecutive samples,4: 4 consecutive samples,5: 5 consecutive samples,6: 6 consecutive samples,7: 7 consecutive samples" newline bitfld.long 0x00 10.--11. "EVT_SEL,COUT Event Select" "0: Rising edge,1: Falling edge,2: Both edges,3: Both edges" bitfld.long 0x00 9. "WINDOW_CLS,COUT Event Window Close" "0: COUT event cannot close the window,1: COUT event can close the window" newline bitfld.long 0x00 8. "WINDOW_INV,WINDOW/SAMPLE Signal Invert" "0: Do not invert,1: INVERT" bitfld.long 0x00 7. "COUTA_OW,COUTA Output Level for Closed Window" "0: COUTA is 0,1: COUTA is 1" newline bitfld.long 0x00 6. "COUTA_OWEN,COUTA_OW Enable" "0: COUTA holds the last sampled value,1: COUTA is defined by the COUTA_OW bit" bitfld.long 0x00 5. "COUT_PEN,Comparator Output Pin Enable" "0: Not available,1: AVAILABLE" newline bitfld.long 0x00 4. "COUT_SEL,Comparator Output Select" "0: Use COUT (filtered),1: Use COUTA (unfiltered)" bitfld.long 0x00 3. "COUT_INV,Comparator Invert" "0: Do not invert,1: INVERT" newline bitfld.long 0x00 2. "DMA_EN,DMA Enable" "0: DISABLE,1: ENABLE" bitfld.long 0x00 1. "SAMPLE_EN,Sampling Enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 0. "WINDOW_EN,Windowing Enable" "0: DISABLE,1: ENABLE" group.long 0x10++0x03 line.long 0x00 "CCR2,Comparator Control Register 2" bitfld.long 0x00 28.--29. "INMSEL,Input Minus Select" "0: IN0,1: IN1,?..." bitfld.long 0x00 24.--25. "INPSEL,Input Plus Select" "0: IN0,1: IN1,?..." newline bitfld.long 0x00 20.--22. "MSEL,Minus Input MUX Select" "0: Input 0m,1: Input 1m,2: Input 2m,3: Input 3m,4: Input 4m,5: Input 5m,?,7: Internal DAC output" bitfld.long 0x00 16.--18. "PSEL,Plus Input MUX Select" "0: Input 0p,1: Input 1p,2: Input 2p,3: Input 3p,4: Input 4p,5: Input 5p,?,7: Internal DAC output" newline bitfld.long 0x00 4.--5. "HYSTCTR,Comparator Hysteresis Control" "0: LEVEL_0,1: LEVEL_1,2: LEVEL_2,3: LEVEL_3" bitfld.long 0x00 2. "OFFSET,Comparator Offset Control" "0: Level 0,1: Level 1" newline bitfld.long 0x00 1. "CMP_NPMD,CMP Nano Power Mode Select" "0: Disable (Mode is determined by CMP_HPMD.),1: Enable" bitfld.long 0x00 0. "CMP_HPMD,CMP High Power Mode Select" "0: Low power(speed) comparison mode,1: High power(speed) comparison mode" group.long 0x18++0x03 line.long 0x00 "DCR,DAC Control Register" hexmask.long.byte 0x00 16.--23. 1. "DAC_DATA,DAC Output Voltage Select" bitfld.long 0x00 15. "DACOE,DAC Output Enable" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 8. "VRSEL,DAC Reference High Voltage Source Select" "0: vrefh0,1: vrefh1" bitfld.long 0x00 1. "DAC_HPMD,DAC High Power Mode Select" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 0. "DAC_EN,DAC Enable" "0: DISABLE,1: ENABLE" group.long 0x1C++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 2. "RRF_IE,Round-Robin Flag Interrupt Enable" "0: DISABLE,1: Enable" bitfld.long 0x00 1. "CFF_IE,Comparator Flag Falling Interrupt Enable" "0: DISABLE,1: Enable" newline bitfld.long 0x00 0. "CFR_IE,Comparator Flag Rising Interrupt Enable" "0: DISABLE,1: Enable" group.long 0x20++0x03 line.long 0x00 "CSR,Comparator Status Register" rbitfld.long 0x00 8. "COUT,Analog Comparator Output" "0,1" eventfld.long 0x00 2. "RRF,Round-Robin Flag" "0: NOT_DETECTED,1: DETECTED" newline eventfld.long 0x00 1. "CFF,Analog Comparator Flag Falling" "0: NOT_DETECTED,1: DETECTED" eventfld.long 0x00 0. "CFR,Analog Comparator Flag Rising" "0: NOT_DETECTED,1: DETECTED" group.long 0x24++0x03 line.long 0x00 "RRCR0,Round Robin Control Register 0" bitfld.long 0x00 16.--21. "RR_INITMOD,Initialization Delay Modulus" "0: 63 cycles (same as 111111b),1: 1 to 63 cycles,2: 1 to 63 cycles,3: 1 to 63 cycles,4: 1 to 63 cycles,5: 1 to 63 cycles,6: 1 to 63 cycles,7: 1 to 63 cycles,8: 1 to 63 cycles,9: 1 to 63 cycles,?..." bitfld.long 0x00 8.--9. "RR_NSAM,Number of Sample Clocks" "0: 0 clocks,1: 1 clocks,2: 2 clocks,3: 3 clocks" newline bitfld.long 0x00 0. "RR_EN,Round-Robin Enable" "0: DISABLE,1: ENABLE" group.long 0x28++0x03 line.long 0x00 "RRCR1,Round Robin Control Register 1" bitfld.long 0x00 20.--22. "FIXCH,Fixed Channel Select" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3,4: Channel 4,5: Channel 5,6: Channel 6,7: Channel 7" bitfld.long 0x00 16. "FIXP,Fixed Port" "0: Fix the Plus port,1: Fix the Minus port" newline bitfld.long 0x00 7. "RR_CH7EN,Channel 7 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" bitfld.long 0x00 6. "RR_CH6EN,Channel 6 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 5. "RR_CH5EN,Channel 5 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" bitfld.long 0x00 4. "RR_CH4EN,Channel 4 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 3. "RR_CH3EN,Channel 3 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" bitfld.long 0x00 2. "RR_CH2EN,Channel 2 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "RR_CH1EN,Channel 1 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" bitfld.long 0x00 0. "RR_CH0EN,Channel 0 Input Enable in Trigger Mode" "0: DISABLE,1: ENABLE" group.long 0x2C++0x03 line.long 0x00 "RRCSR,Round Robin Control and Status Register" bitfld.long 0x00 7. "RR_CH7OUT,Comparison Result for Channel 7" "0,1" bitfld.long 0x00 6. "RR_CH6OUT,Comparison Result for Channel 6" "0,1" newline bitfld.long 0x00 5. "RR_CH5OUT,Comparison Result for Channel 5" "0,1" bitfld.long 0x00 4. "RR_CH4OUT,Comparison Result for Channel 4" "0,1" newline bitfld.long 0x00 3. "RR_CH3OUT,Comparison Result for Channel 3" "0,1" bitfld.long 0x00 2. "RR_CH2OUT,Comparison Result for Channel 2" "0,1" newline bitfld.long 0x00 1. "RR_CH1OUT,Comparison Result for Channel 1" "0,1" bitfld.long 0x00 0. "RR_CH0OUT,Comparison Result for Channel 0" "0,1" group.long 0x30++0x03 line.long 0x00 "RRSR,Round Robin Status Register" eventfld.long 0x00 7. "RR_CH7F,Channel 7 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" eventfld.long 0x00 6. "RR_CH6F,Channel 6 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" newline eventfld.long 0x00 5. "RR_CH5F,Channel 5 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" eventfld.long 0x00 4. "RR_CH4F,Channel 4 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" newline eventfld.long 0x00 3. "RR_CH3F,Channel 3 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" eventfld.long 0x00 2. "RR_CH2F,Channel 2 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" newline eventfld.long 0x00 1. "RR_CH1F,Channel 1 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" eventfld.long 0x00 0. "RR_CH0F,Channel 0 Input Changed Flag" "0: NOT_DIFFERENT,1: DIFFERENT" group.long 0x38++0x03 line.long 0x00 "RRCR2,Round Robin Control Register 2" bitfld.long 0x00 31. "RR_TIMER_EN,Round-Robin internal timer enable" "0: Round-Robin internal timer is disabled,1: Round-Robin internal timer is enabled" hexmask.long 0x00 0.--27. 1. "RR_TIMER_RELOAD,Number of sample clocks" tree.end repeat.end tree.end endif tree "I2C (Inter-Integrated Circuit)" tree "I2C0" base ad:0x40086000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2C1" base ad:0x40087000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2C2" base ad:0x40088000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2C3" base ad:0x40089000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2C4" base ad:0x4008A000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2C5" base ad:0x40096000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2C6" base ad:0x40097000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2C7" base ad:0x40098000 group.long 0x800++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 5. "HSCAPABLE,High Speed mode Capable enable" "0: Fast mode Plus enable,1: High Speed mode enable" bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled" group.long 0x804++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle" rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active" newline bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun" rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting" newline bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected" rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected" newline rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index T" "0: Address 0,1: Address 1,2: Address 2,3: Address 3" rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching" newline rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State" "0: Slave address,1: Slave receive,2: Slave transmit,?..." rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.." bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss" newline rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..." rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending" group.long 0x808++0x03 line.long 0x00 "INTENSET,Interrupt Enable Set Register" bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL Time-out interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event Time-out interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled" wgroup.long 0x80C++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" newline bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0: No effect on interrupt,1: Clears the interrupt bit in INTENSET register" group.long 0x810++0x03 line.long 0x00 "TIMEOUT,Time-out Register" hexmask.long.word 0x00 4.--15. 1. "TO,Time-out time value" bitfld.long 0x00 0.--3. "TOMIN,Time-out time value the bottom 4 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CLKDIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Divider Value" rgroup.long 0x818++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: SCLTIMEOUT_ISNOTACTIVE,1: SCLTIMEOUT_ISACTIVE" bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: EVENTTIMEOUT_ISNOTACTIVE,1: EVENTTIMEOUT_ISACTIVE" newline bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: MONIDLE_ISNOTACTIVE,1: MONIDLE_ISACTIVE" bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: MONOV_ISNOTACTIVE,1: MONOV_ISACTIVE" newline bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: MONRDY_ISNOTACTIVE,1: MONRDY_ISACTIVE" bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: SLVDESEL_ISNOTACTIVE,1: SLVDESEL_ISACTIVE" newline bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0: SLVNOTSTR_ISNOTACTIVE,1: SLVNOTSTR_ISACTIVE" bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: SLVPENDING_ISNOTACTIVE,1: SLVPENDING_ISACTIVE" newline bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: MSTSTSTPERR_ISNOTACTIVE,1: MSTSTSTPERR_ISACTIVE" bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: MSTARBLOSS_ISNOTACTIVE,1: MSTARBLOSS_ISACTIVE" newline bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: MSTPENDING_ISNOTACTIVE,1: MSTPENDING_ISACTIVE" group.long 0x820++0x03 line.long 0x00 "MSTCTL,Master Control Register" bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable" bitfld.long 0x00 2. "MSTSTOP,Master Stop control(write-only)" "0: NO_EFFECT,1: Stop" newline bitfld.long 0x00 1. "MSTSTART,Master Start control(write-only)" "0: NO_EFFECT,1: Start" bitfld.long 0x00 0. "MSTCONTINUE,Master Continue(write-only)" "0: NO_EFFECT,1: Continue" group.long 0x824++0x03 line.long 0x00 "MSTTIME,Master Timing Register" bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks" group.long 0x828++0x03 line.long 0x00 "MSTDAT,Master Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register" group.long 0x840++0x03 line.long 0x00 "SLVCTL,Slave Control Register" bitfld.long 0x00 9. "AUTOMATCHREAD,Automatic Match" "0: In Automatic Mode the expected next operation..,1: In Automatic Mode the expected next operation.." bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.." newline bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: NO_EFFECT,1: NACK" newline bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: NO_EFFECT,1: Continue" group.long 0x844++0x03 line.long 0x00 "SLVDAT,Slave Data Register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register" repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x848)++0x03 line.long 0x00 "SLVADR$1,Slave Address Register" bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode" hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address" newline bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored" repeat.end group.long 0x858++0x03 line.long 0x00 "SLVQUAL0,Slave Qualification for Address 0 Register" hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0" bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend" rgroup.long 0x880++0x03 line.long 0x00 "MONRXDAT,Monitor Receiver Data Register" bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged" bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected" newline bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected" hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree.end tree "I2S (Inter-Integrated Sound Bus Controller)" tree "I2S0" base ad:0x40086000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2S1" base ad:0x40087000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2S2" base ad:0x40088000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2S3" base ad:0x40089000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2S4" base ad:0x4008A000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2S5" base ad:0x40096000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2S6" base ad:0x40097000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "I2S7" base ad:0x40098000 group.long 0xC00++0x03 line.long 0x00 "CFG1,Configuration Register 1 for the Primary Channel Pair" bitfld.long 0x00 16.--20. "DATALEN,Data Length" "?,?,?,3: Data is 4 bits in length,4: Data is 5 bits in length,?,?,7: Data is 8 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Data is 31 bits in length,31: Data is 32 bits in length" newline bitfld.long 0x00 13. "WS_POL,WS Polarity" "0: NOT_INVERTED,1: INVERTED" newline bitfld.long 0x00 12. "SCK_POL,SCK Polarity" "0: FALLING_EDGE,1: RISING_EDGE" newline bitfld.long 0x00 11. "PDMDATA,PDM Data Selection" "0: Normal Operation,1: DMIC_SUBSYSTEM" newline bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 9. "LEFTJUST,Left-Justify Data" "0: RIGHT_JUSTIFIED,1: LEFT_JUSTIFIED" newline bitfld.long 0x00 8. "RIGHTLOW,Right Channel Low" "0: RIGHT_HIGH,1: RIGHT_LOW" newline bitfld.long 0x00 6.--7. "MODE,Mode" "0: CLASSIC_MODE,1: DSP mode WS 50% duty cycle,2: DSP_MODE_WS_1_CLOCK,3: DSP_MODE_WS_1_DATA" newline bitfld.long 0x00 4.--5. "MSTSLVCFG,Master/Slave Configuration Selection" "0: NORMAL_SLAVE_MODE,1: WS Synchronized Master Mode,2: Master Using an Existing SCK Mode,3: Normal Master Mode" newline bitfld.long 0x00 2.--3. "PAIRCOUNT,Pair Count" "0: One Pair,1: Two Pairs,2: Three Pairs,3: Four Pairs" newline bitfld.long 0x00 1. "DATAPAUSE,Data Flow Pause" "0: Normal operation,1: PAUSE" newline bitfld.long 0x00 0. "MAINENABLE,Main Enable" "0: DISABLED,1: ENABLED" group.long 0xC04++0x03 line.long 0x00 "CFG2,Configuration Register 2 for the Primary Channel Pair" hexmask.long.word 0x00 16.--26. 1. "POSITION,Data Position" newline hexmask.long.word 0x00 0.--10. 1. "FRAMELEN,Frame Length" group.long 0xC08++0x03 line.long 0x00 "STAT,Status Register for the Primary Channel Pair" rbitfld.long 0x00 3. "DATAPAUSED,Data Paused" "0: NOT_PAUSED,1: PAUSED" newline rbitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline eventfld.long 0x00 1. "SLVFRMERR,Slave Frame Error" "0: NO_ERROR,1: ERROR" newline rbitfld.long 0x00 0. "BUSY,Busy Status" "0: IDLE,1: BUSY" group.long 0xC1C++0x03 line.long 0x00 "DIV,Clock Divider" hexmask.long.word 0x00 0.--11. 1. "DIV,Divider" group.long 0xC20++0x03 line.long 0x00 "P1CFG1,Configuration Register 1 for Channel Pair 1" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC24++0x03 line.long 0x00 "P2CFG1,Configuration Register 2 for Channel Pair 1" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC28++0x03 line.long 0x00 "PSTAT1,Status Register for Channel Pair 1" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC40++0x03 line.long 0x00 "P1CFG2,Configuration Register 1 for Channel Pair 2" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC44++0x03 line.long 0x00 "P2CFG2,Configuration Register 2 for Channel Pair 2" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC48++0x03 line.long 0x00 "PSTAT2,Status Register for Channel Pair 2" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xC60++0x03 line.long 0x00 "P1CFG3,Configuration Register 1 for Channel Pair 3" bitfld.long 0x00 10. "ONECHANNEL,Single Channel Mode" "0: DUAL_CHANNEL,1: SINGLE_CHANNEL" newline bitfld.long 0x00 0. "PAIRENABLE,Pair Enable" "0: DISABLED,1: ENABLED" group.long 0xC64++0x03 line.long 0x00 "P2CFG3,Configuration Register 2 for Channel Pair 3" hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position" rgroup.long 0xC68++0x03 line.long 0x00 "PSTAT3,Status Register for Channel Pair 3" bitfld.long 0x00 3. "DATAPAUSED,Data Paused Status Flag" "0: Data Not Paused,1: Data Paused" newline bitfld.long 0x00 2. "LR,Left/Right Indication" "0: LEFT_CHANNEL,1: RIGHT_CHANNEL" newline bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error Flag" "0: NO_ERROR,1: ERROR" newline bitfld.long 0x00 0. "BUSY,Busy Status for Channel Pair" "0: Idle,1: Busy" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration and Enable" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read causes the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts wake up the device..,1: A device wake-up for DMA occurs if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 13. "DMARX,DMA Receive" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 12. "DMATX,DMA Transmit" "0: DISABLED,1: ENABLED" newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "?,?,2: Size 32 Bits,3: Size 48 Bits" newline bitfld.long 0x00 3. "PACK48,Packing Format 48-bit data" "0: Bits_24,1: Bits_32_16" newline bitfld.long 0x00 2. "TXI2SE0,Transmit I2S Empty 0" "0: LAST_VALUE,1: ZERO" newline bitfld.long 0x00 1. "ENABLERX,Enable Receive FIFO" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable Transmit FIFO" "0: Disabled Transmit,1: Enabled transmit" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0: RX FIFO is empty,?..." newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0: TX FIFO is empty,?..." newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO Not Empty" "0: Receive FIFO is empty,1: Receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO Not Full" "0: Transmit FIFO is full and another write would..,1: Transmit FIFO is not full so more data can be.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty however the peripheral.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: NOT_ASSERTED,1: Interrupt" newline eventfld.long 0x00 1. "RXERR,RX FIFO Error" "0: No receive FIFO error occured,1: Receive FIFO error occured" newline eventfld.long 0x00 0. "TXERR,TX FIFO Error" "0: No transmit FIFO error occured,1: Transmit FIFO error occured" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger generates if the receive FIFO.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger generates if the transmit FIFO.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Set and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt" "0: Disabled,1: Enabled" group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear and Read" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 2. "TXLVL,Transmit Level Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Clear" "0: Interrupt is not cleared,1: Interrupt is cleared" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit Data to the FIFO" wgroup.long 0xE24++0x03 line.long 0x00 "FIFOWR48H,FIFO Write Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE34++0x03 line.long 0x00 "FIFORD48H,FIFO Read Data for Upper Data Bits" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" hexmask.long 0x00 0.--31. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE44++0x03 line.long 0x00 "FIFORD48HNOPOP,FIFO Data Read for Upper Data Bits with No FIFO Pop" hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,I2S Module Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module Identifier" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "I3C" base ad:0x40016000 group.long 0x00++0x03 line.long 0x00 "MCONFIG,Master Configuration" bitfld.long 0x00 28.--31. "I2CBAUD,I2C baud rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 25.--27. "SKEW,Skew" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24. "ODHPP,Open Drain High Push-Pull" "0,1" hexmask.long.byte 0x00 16.--23. 1. "ODBAUD,Open drain baud rate" newline bitfld.long 0x00 12.--15. "PPLOW,Push-Pull low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "PPBAUD,Push-pull baud rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. "ODSTOP,Open drain stop" "0,1" bitfld.long 0x00 4.--5. "HKEEP,High-Keeper" "0: NONE,1: WIRED_IN,2: PASSIVE_SDA,3: PASSIVE_ON_SDA_SCL" newline bitfld.long 0x00 3. "DISTO,Disable Timeout" "0,1" bitfld.long 0x00 0.--1. "MSTENA,Master enable" "0: MASTER_OFF,1: MASTER_ON,2: MASTER_CAPABLE,3: I2C_MASTER_MODE" group.long 0x04++0x03 line.long 0x00 "SCONFIG,Slave Configuration" hexmask.long.byte 0x00 25.--31. 1. "SADDR,Static address" hexmask.long.byte 0x00 16.--23. 1. "BAMATCH,Bus available match" newline bitfld.long 0x00 9. "OFFLINE,Offline" "0,1" bitfld.long 0x00 8. "IDRAND,ID random" "0,1" newline bitfld.long 0x00 4. "DDROK,DDR OK" "0,1" bitfld.long 0x00 3. "S0IGNORE,S0/S1 errors ignore" "0,1" newline bitfld.long 0x00 2. "MATCHSS,Match START or STOP" "0,1" bitfld.long 0x00 1. "NACK,Not acknowledge" "0,1" newline bitfld.long 0x00 0. "SLVENA,Slave enable" "0,1" group.long 0x08++0x03 line.long 0x00 "SSTATUS,Slave Status" rbitfld.long 0x00 30.--31. "TIMECTRL,Time control" "0: NO_TIME_CONTROL,?,2: ASYNC_MODE,?..." rbitfld.long 0x00 28.--29. "ACTSTATE,Activity state from Common Command Codes (CCC)" "0: NO_LATENCY,1: LATENCY_1MS,2: LATENCY_100MS,3: LATENCY_10S" newline rbitfld.long 0x00 27. "HJDIS,Hot-Join is disabled" "0,1" rbitfld.long 0x00 25. "MRDIS,Master requests are disabled" "0,1" newline rbitfld.long 0x00 24. "IBIDIS,In-Band Interrupts are disabled" "0,1" rbitfld.long 0x00 20.--21. "EVDET,Event details" "0: NONE,1: NO_REQUEST,2: NACKED,3: ACKED" newline eventfld.long 0x00 18. "EVENT,Event" "0,1" eventfld.long 0x00 17. "CHANDLED,Common Command Code handled" "0,1" newline eventfld.long 0x00 16. "HDRMATCH,High Data Rate command match" "0,1" rbitfld.long 0x00 15. "ERRWARN,Error warning" "0,1" newline eventfld.long 0x00 14. "CCC,Common Command Code" "0,1" eventfld.long 0x00 13. "DACHG,DACHG" "0,1" newline rbitfld.long 0x00 12. "TXNOTFULL,Transmit buffer is not full" "0,1" rbitfld.long 0x00 11. "RX_PEND,Received message pending" "0,1" newline eventfld.long 0x00 10. "STOP,Stop" "0,1" eventfld.long 0x00 9. "MATCHED,Matched" "0,1" newline eventfld.long 0x00 8. "START,Start" "0,1" rbitfld.long 0x00 6. "STHDR,Status High Data Rate" "0,1" newline rbitfld.long 0x00 5. "STDAA,Status Dynamic Address Assignment" "0,1" rbitfld.long 0x00 4. "STREQWR,Status request" "0,1" newline rbitfld.long 0x00 3. "STREQRD,Status request" "0,1" rbitfld.long 0x00 2. "STCCCH,Status Common Command Code Handler" "0,1" newline rbitfld.long 0x00 1. "STMSG,Status message" "0,1" rbitfld.long 0x00 0. "STNOTSTOP,Status not stop" "0,1" group.long 0x0C++0x03 line.long 0x00 "SCTRL,Slave Control" hexmask.long.byte 0x00 24.--31. 1. "VENDINFO,Vendor information" bitfld.long 0x00 20.--21. "ACTSTATE,Activity state (of slave)" "0,1,2,3" newline bitfld.long 0x00 16.--19. "PENDINT,Pending interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. "IBIDATA,In-Band Interrupt data" newline bitfld.long 0x00 3. "EXTDATA,Extended Data" "0,1" bitfld.long 0x00 0.--1. "EVENT,EVENT" "0: NORMAL_MODE,1: IBI,2: MASTER_REQUEST,3: HOT_JOIN_REQUEST" group.long 0x10++0x03 line.long 0x00 "SINTSET,Slave Interrupt Set" bitfld.long 0x00 18. "EVENT,Event interrupt enable" "0,1" bitfld.long 0x00 17. "CHANDLED,Common Command Code (CCC) (that was handled by I3C module) interrupt enable" "0,1" newline bitfld.long 0x00 16. "DDRMATCHED,Double Data Rate (DDR) interrupt enable" "0,1" bitfld.long 0x00 15. "ERRWARN,Error/warning interrupt enable" "0,1" newline bitfld.long 0x00 14. "CCC,Common Command Code (CCC) (that was not handled by I3C module) interrupt enable" "0,1" bitfld.long 0x00 13. "DACHG,Dynamic address change interrupt enable" "0,1" newline bitfld.long 0x00 12. "TXSEND,Transmit interrupt enable" "0,1" bitfld.long 0x00 11. "RXPEND,Receive interrupt enable" "0,1" newline bitfld.long 0x00 10. "STOP,Stop interrupt enable" "0,1" bitfld.long 0x00 9. "MATCHED,Match interrupt enable" "0,1" newline bitfld.long 0x00 8. "START,Start interrupt enable" "0,1" group.long 0x14++0x03 line.long 0x00 "SINTCLR,Slave Interrupt Clear" eventfld.long 0x00 18. "EVENT,EVENT interrupt enable clear" "0,1" eventfld.long 0x00 17. "CHANDLED,CHANDLED interrupt enable clear" "0,1" newline eventfld.long 0x00 16. "DDRMATCHED,DDRMATCHED interrupt enable clear" "0,1" eventfld.long 0x00 15. "ERRWARN,ERRWARN interrupt enable clear" "0,1" newline eventfld.long 0x00 14. "CCC,CCC interrupt enable clear" "0,1" eventfld.long 0x00 13. "DACHG,DACHG interrupt enable clear" "0,1" newline eventfld.long 0x00 12. "TXSEND,TXSEND interrupt enable clear" "0,1" eventfld.long 0x00 11. "RXPEND,RXPEND interrupt enable clear" "0,1" newline eventfld.long 0x00 10. "STOP,STOP interrupt enable clear" "0,1" eventfld.long 0x00 9. "MATCHED,MATCHED interrupt enable clear" "0,1" newline eventfld.long 0x00 8. "START,START interrupt enable clear" "0,1" rgroup.long 0x18++0x03 line.long 0x00 "SINTMASKED,Slave Interrupt Mask" bitfld.long 0x00 18. "EVENT,EVENT interrupt mask" "0,1" bitfld.long 0x00 17. "CHANDLED,CHANDLED interrupt mask" "0,1" newline bitfld.long 0x00 16. "DDRMATCHED,DDRMATCHED interrupt mask" "0,1" bitfld.long 0x00 15. "ERRWARN,ERRWARN interrupt mask" "0,1" newline bitfld.long 0x00 14. "CCC,CCC interrupt mask" "0,1" bitfld.long 0x00 13. "DACHG,DACHG interrupt mask" "0,1" newline bitfld.long 0x00 12. "TXSEND,TXSEND interrupt mask" "0,1" bitfld.long 0x00 11. "RXPEND,RXPEND interrupt mask" "0,1" newline bitfld.long 0x00 10. "STOP,STOP interrupt mask" "0,1" bitfld.long 0x00 9. "MATCHED,MATCHED interrupt mask" "0,1" newline bitfld.long 0x00 8. "START,START interrupt mask" "0,1" group.long 0x1C++0x03 line.long 0x00 "SERRWARN,Slave Errors and Warnings" eventfld.long 0x00 17. "OWRITE,Over-write error" "0,1" eventfld.long 0x00 16. "OREAD,Over-read error" "0,1" newline eventfld.long 0x00 11. "S0S1,S0 or S1 error" "0,1" eventfld.long 0x00 10. "HCRC,HDR-DDR CRC error" "0,1" newline eventfld.long 0x00 9. "HPAR,HDR parity error" "0,1" eventfld.long 0x00 8. "SPAR,SDR parity error" "0,1" newline eventfld.long 0x00 4. "INVSTART,Invalid start error" "0,1" eventfld.long 0x00 3. "TERM,Terminated error" "0,1" newline eventfld.long 0x00 2. "URUNNACK,Underrun and Not Acknowledged (NACKed) error" "0,1" eventfld.long 0x00 1. "URUN,Underrun error" "0,1" newline eventfld.long 0x00 0. "ORUN,Overrun error" "0,1" group.long 0x20++0x03 line.long 0x00 "SDMACTRL,Slave DMA Control" bitfld.long 0x00 4.--5. "DMAWIDTH,Width of DMA operations" "0: BYTE Default = 1,1: BYTE Default = 1,2: HALF_WORD,?..." bitfld.long 0x00 2.--3. "DMATB,DMA Write (To-bus) trigger" "0: NOT_USED,1: ENABLE_ONE_FRAME,2: ENABLE,?..." newline bitfld.long 0x00 0.--1. "DMAFB,DMA Read (From-bus) trigger" "0: DMA not used,1: DMA is enabled for 1 frame,2: DMA enable,?..." group.long 0x2C++0x03 line.long 0x00 "SDATACTRL,Slave Data Control" rbitfld.long 0x00 31. "RXEMPTY,RX is empty" "0: RX is not empty,1: RX is empty" rbitfld.long 0x00 30. "TXFULL,TX is full" "0: TX is not full,1: TX is full" newline rbitfld.long 0x00 24.--28. "RXCOUNT,Count of bytes in RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. "TXCOUNT,Count of bytes in TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "RXTRIG,Trigger level for RX FIFO fullness" "0: Trigger on not empty,1: Trigger on or more full,2: Trigger on .5 or more full,3: Trigger on 3/4 or more full" bitfld.long 0x00 4.--5. "TXTRIG,Trigger level for TX FIFO emptiness" "0: Trigger on empty,1: Trigger on full or less,2: Trigger on .5 full or less,3: Trigger on 1 less than full or less (Default)" newline bitfld.long 0x00 3. "UNLOCK,Unlock" "0,1" bitfld.long 0x00 1. "FLUSHFB,Flushes the from-bus buffer/FIFO" "0,1" newline bitfld.long 0x00 0. "FLUSHTB,Flush the to-bus buffer/FIFO" "0,1" wgroup.long 0x30++0x03 line.long 0x00 "SWDATAB,Slave Write Data Byte" bitfld.long 0x00 16. "END_ALSO,End also" "0,1" bitfld.long 0x00 8. "END,End" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "DATA,The data byte to send to the master" wgroup.long 0x34++0x03 line.long 0x00 "SWDATABE,Slave Write Data Byte End" hexmask.long.byte 0x00 0.--7. 1. "DATA,The data byte to send to the master" wgroup.long 0x38++0x03 line.long 0x00 "SWDATAH,Slave Write Data Half-word" bitfld.long 0x00 16. "END,End of message" "0,1" hexmask.long.byte 0x00 8.--15. 1. "DATA1,The 2nd byte to send to the master" newline hexmask.long.byte 0x00 0.--7. 1. "DATA0,The 1st byte to send to the master" wgroup.long 0x3C++0x03 line.long 0x00 "SWDATAHE,Slave Write Data Half-word End" hexmask.long.byte 0x00 8.--15. 1. "DATA1,The 2nd byte to send to the master" hexmask.long.byte 0x00 0.--7. 1. "DATA0,The 1st byte to send to the master" rgroup.long 0x40++0x03 line.long 0x00 "SRDATAB,Slave Read Data Byte" hexmask.long.byte 0x00 0.--7. 1. "DATA0,Byte read from the master" rgroup.long 0x48++0x03 line.long 0x00 "SRDATAH,Slave Read Data Half-word" hexmask.long.byte 0x00 8.--15. 1. "MSB,The 2nd byte read from the slave" hexmask.long.byte 0x00 0.--7. 1. "LSB,The 1st byte read from the slave" rgroup.long 0x5C++0x03 line.long 0x00 "SCAPABILITIES2,Slave Capabilities 2" bitfld.long 0x00 23. "SSTWR,Slave-Slave(s)-Tunnel write capable" "0,1" bitfld.long 0x00 22. "SSTSUB,Slave-Slave(s)-Tunnel subscriber capable" "0,1" newline bitfld.long 0x00 21. "AASA,Supports SETAASA" "0,1" bitfld.long 0x00 18.--19. "GROUP,GROUP" "0: Does not supports v1.1 Group addressing,1: Supports one group,2: Supports two groups,3: Supports three groups" newline bitfld.long 0x00 17. "SLVRST,Slave Reset" "0: Does not support Slave Reset,1: Supports Slave Reset" bitfld.long 0x00 9. "IBIXREG,In-Band Interrupt Extended Register" "0: Does not support IBIXREG,1: Supports IBIXREG" newline bitfld.long 0x00 8. "IBIEXT,In-Band Interrupt EXTDATA" "0: Does not support IBIEXT,1: Supports IBIEXT" bitfld.long 0x00 6. "I2CDEVID,I2C Device ID" "0: Does not support I2CDEVID,1: Supports I2CDEVID" newline bitfld.long 0x00 5. "I2CRST,I2C SW Reset" "0: Does not support I2CRST,1: Supports I2CRST" bitfld.long 0x00 4. "I2C10B,I2C 10-bit Address" "0: Does not support I2C10B,1: Supports I2C10B" newline bitfld.long 0x00 0.--3. "MAPCNT,Map Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SCAPABILITIES,Slave Capabilities" bitfld.long 0x00 31. "DMA,DMA" "0: DMA is not supported,1: DMA is supported" bitfld.long 0x00 30. "INT,INT" "0: Interrupts are not supported,1: Interrupts are supported" newline bitfld.long 0x00 28.--29. "FIFORX,FIFO receive" "0: FIFO_2BYTE,1: FIFO_4BYTE,2: FIFO_8BYTE,3: FIFO_16BYTE" bitfld.long 0x00 26.--27. "FIFOTX,FIFO transmit" "0: FIFO_2BYTE,1: FIFO_4BYTE,2: FIFO_8BYTE,3: FIFO_16BYTE" newline bitfld.long 0x00 23.--25. "EXTFIFO,External FIFO" "0: NO_EXT_FIFO,1: STD_EXT_FIFO,2: REQUEST_EXT_FIFO,?..." bitfld.long 0x00 21. "TIMECTRL,Time control" "0: NO_TIME_CONTROL_TYPE,1: ATLEAST1_TIME_CONTROL" newline bitfld.long 0x00 16.--20. "IBI_MR_HJ,In-Band Interrupts Master Requests Hot Join events" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--15. "CCCHANDLE,Common Command Codes (CCC) handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. "SADDR,Static address" "0: NO_STATIC,1: STATIC,2: HW_CONTROL,3: CONFIG" bitfld.long 0x00 9. "MASTER,Master" "0: MASTERNOTSUPPORTED,1: MASTERSUPPORTED" newline bitfld.long 0x00 6.--7. "HDRSUPP,HDR support" "0,1,2,3" bitfld.long 0x00 2.--5. "IDREG,ID register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--1. "IDENA,ID 48b handler" "0: APPLICATION,1: HW,2: HW_BUT,3: PARTNO" group.long 0x64++0x03 line.long 0x00 "SDYNADDR,Slave Dynamic Address" hexmask.long.word 0x00 16.--31. 1. "KEY,Key" bitfld.long 0x00 13.--15. "SA10B,10bit Static Address" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "MAPSA,Map a Static Address" "0,1" hexmask.long.byte 0x00 1.--7. 1. "DADDR,Dynamic address" newline bitfld.long 0x00 0. "DAVALID,DAVALID" "0: DANOTASSIGNED,1: DAASSIGNED" group.long 0x68++0x03 line.long 0x00 "SMAXLIMITS,Slave Maximum Limits" hexmask.long.word 0x00 16.--27. 1. "MAXWR,Maximum write length" hexmask.long.word 0x00 0.--11. 1. "MAXRD,Maximum read length" group.long 0x6C++0x03 line.long 0x00 "SIDPARTNO,Slave ID Part Number" hexmask.long 0x00 0.--31. 1. "PARTNO,Part number" group.long 0x70++0x03 line.long 0x00 "SIDEXT,Slave ID Extension" hexmask.long.byte 0x00 16.--23. 1. "BCR,Bus Characteristics Register" hexmask.long.byte 0x00 8.--15. 1. "DCR,Device Characteristic Register" group.long 0x74++0x03 line.long 0x00 "SVENDORID,Slave Vendor ID" hexmask.long.word 0x00 0.--14. 1. "VID,Vendor ID" group.long 0x78++0x03 line.long 0x00 "STCCLOCK,Slave Time Control Clock" hexmask.long.byte 0x00 8.--15. 1. "FREQ,Clock frequency" hexmask.long.byte 0x00 0.--7. 1. "ACCURACY,Clock accuracy" rgroup.long 0x7C++0x03 line.long 0x00 "SMSGMAPADDR,Slave Message Map Address" bitfld.long 0x00 16.--19. "MAPLASTM2,Matched Previous Index 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "MAPLASTM1,Matched Previous Address Index 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "LASTSTATIC,Last Static Address Matched" "0,1" bitfld.long 0x00 0.--3. "MAPLAST,Matched Address Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x84++0x03 line.long 0x00 "MCTRL,Master Main Control" hexmask.long.byte 0x00 16.--23. 1. "RDTERM,Read terminate" hexmask.long.byte 0x00 9.--15. 1. "ADDR,Address" newline bitfld.long 0x00 8. "DIR,DIR" "0: DIR,1: DIRREAD" bitfld.long 0x00 6.--7. "IBIRESP,In-Band Interrupt (IBI) response" "0: ACK,1: NACK,2: ACK_WITH_MANDATORY,3: MANUAL" newline bitfld.long 0x00 4.--5. "TYPE,Bus type with EmitStartAddr" "0: I3C,1: I2C,2: DDR,?..." bitfld.long 0x00 0.--2. "REQUEST,Request" "0: NONE,1: EMITSTARTADDR,2: EMITSTOP,3: IBIACKNACK,4: PROCESSDAA,?,6: FORCEEXIT and SLAVERESET,7: AUTOIBI" group.long 0x88++0x03 line.long 0x00 "MSTATUS,Master Status" hexmask.long.byte 0x00 24.--30. 1. "IBIADDR,IBI address" eventfld.long 0x00 19. "NOWMASTER,Now master (now this module is a master)" "0,1" newline rbitfld.long 0x00 15. "ERRWARN,Error or warning" "0,1" eventfld.long 0x00 13. "IBIWON,In-Band Interrupt (IBI) won" "0,1" newline rbitfld.long 0x00 12. "TXNOTFULL,TX buffer/FIFO not yet full" "0,1" rbitfld.long 0x00 11. "RXPEND,RXPEND" "0,1" newline eventfld.long 0x00 10. "COMPLETE,COMPLETE" "0,1" eventfld.long 0x00 9. "MCTRLDONE,Master control done" "0,1" newline eventfld.long 0x00 8. "SLVSTART,Slave start" "0,1" rbitfld.long 0x00 6.--7. "IBITYPE,In-Band Interrupt (IBI) type" "0: NONE,1: IBI,2: MR,3: HJ" newline rbitfld.long 0x00 5. "NACKED,Not acknowledged" "0,1" rbitfld.long 0x00 4. "BETWEEN,Between" "0: INACTIVE,1: ACTIVE" newline rbitfld.long 0x00 0.--2. "STATE,State of the master" "0: IDLE,1: SLVREQ,2: MSGSDR,3: NORMACT,4: MSGDDR,5: DAA,6: IBIACK,7: IBIRCV" group.long 0x8C++0x03 line.long 0x00 "MIBIRULES,Master In-band Interrupt Registry and Rules" bitfld.long 0x00 31. "NOBYTE,No IBI byte" "0,1" bitfld.long 0x00 30. "MSB0,Set Most Significant address Bit to 0" "0,1" newline bitfld.long 0x00 24.--29. "ADDR4,ADDR4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. "ADDR3,ADDR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 12.--17. "ADDR2,ADDR2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. "ADDR1,ADDR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. "ADDR0,ADDR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x90++0x03 line.long 0x00 "MINTSET,Master Interrupt Set" bitfld.long 0x00 19. "NOWMASTER,Now master (now this I3C module is a master) interrupt enable" "0,1" bitfld.long 0x00 15. "ERRWARN,Error or warning (ERRWARN) interrupt enable" "0,1" newline bitfld.long 0x00 13. "IBIWON,In-Band Interrupt (IBI) won interrupt enable" "0,1" bitfld.long 0x00 12. "TXNOTFULL,TX buffer/FIFO is not full interrupt enable" "0,1" newline bitfld.long 0x00 11. "RXPEND,RX pending interrupt enable" "0,1" bitfld.long 0x00 10. "COMPLETE,Completed message interrupt enable" "0,1" newline bitfld.long 0x00 9. "MCTRLDONE,Master control done interrupt enable" "0,1" bitfld.long 0x00 8. "SLVSTART,Slave start interrupt enable" "0,1" group.long 0x94++0x03 line.long 0x00 "MINTCLR,Master Interrupt Clear" eventfld.long 0x00 19. "NOWMASTER,NOWMASTER interrupt enable clear" "0,1" eventfld.long 0x00 15. "ERRWARN,ERRWARN interrupt enable clear" "0,1" newline eventfld.long 0x00 13. "IBIWON,IBIWON interrupt enable clear" "0,1" eventfld.long 0x00 12. "TXNOTFULL,TXNOTFULL interrupt enable clear" "0,1" newline eventfld.long 0x00 11. "RXPEND,RXPEND interrupt enable clear" "0,1" eventfld.long 0x00 10. "COMPLETE,COMPLETE interrupt enable clear" "0,1" newline eventfld.long 0x00 9. "MCTRLDONE,MCTRLDONE interrupt enable clear" "0,1" eventfld.long 0x00 8. "SLVSTART,SLVSTART interrupt enable clear" "0,1" rgroup.long 0x98++0x03 line.long 0x00 "MINTMASKED,Master Interrupt Mask" bitfld.long 0x00 19. "NOWMASTER,NOWMASTER interrupt mask" "0,1" bitfld.long 0x00 15. "ERRWARN,ERRWARN interrupt mask" "0,1" newline bitfld.long 0x00 13. "IBIWON,IBIWON interrupt mask" "0,1" bitfld.long 0x00 12. "TXNOTFULL,TXNOTFULL interrupt mask" "0,1" newline bitfld.long 0x00 11. "RXPEND,RXPEND interrupt mask" "0,1" bitfld.long 0x00 10. "COMPLETE,COMPLETE interrupt mask" "0,1" newline bitfld.long 0x00 9. "MCTRLDONE,MCTRLDONE interrupt mask" "0,1" bitfld.long 0x00 8. "SLVSTART,SLVSTART interrupt mask" "0,1" group.long 0x9C++0x03 line.long 0x00 "MERRWARN,Master Errors and Warnings" eventfld.long 0x00 20. "TIMEOUT,TIMEOUT error" "0,1" eventfld.long 0x00 19. "INVREQ,Invalid request error" "0,1" newline eventfld.long 0x00 18. "MSGERR,Message error" "0,1" eventfld.long 0x00 17. "OWRITE,Over-write error" "0,1" newline eventfld.long 0x00 16. "OREAD,Over-read error" "0,1" eventfld.long 0x00 10. "HCRC,High data rate CRC error" "0,1" newline eventfld.long 0x00 9. "HPAR,High data rate parity" "0,1" eventfld.long 0x00 3. "WRABT,WRABT (Write abort) error" "0,1" newline eventfld.long 0x00 2. "NACK,Not acknowledge (NACK) error" "0,1" group.long 0xA0++0x03 line.long 0x00 "MDMACTRL,Master DMA Control" bitfld.long 0x00 4.--5. "DMAWIDTH,DMA width" "0: BYTE,1: BYTE,2: HALF_WORD,?..." bitfld.long 0x00 2.--3. "DMATB,DMA to bus" "0: NOT_USED,1: ENABLE_ONE_FRAME,2: ENABLE,?..." newline bitfld.long 0x00 0.--1. "DMAFB,DMA from bus" "0: NOT_USED,1: ENABLE_ONE_FRAME,2: ENABLE,?..." group.long 0xAC++0x03 line.long 0x00 "MDATACTRL,Master Data Control" rbitfld.long 0x00 31. "RXEMPTY,RX is empty" "0: RX is not yet empty,1: RX is empty" rbitfld.long 0x00 30. "TXFULL,TX is full" "0: TX is not yet full,1: TX is full" newline rbitfld.long 0x00 24.--28. "RXCOUNT,RX byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--20. "TXCOUNT,TX byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--7. "RXTRIG,RX trigger level" "0: Trigger on not empty,1: Trigger on 1/4 full or more,2: Trigger on 1/2 full or more,3: Trigger on 3/4 full or more" bitfld.long 0x00 4.--5. "TXTRIG,TX trigger level" "0: Trigger on empty,1: Trigger on 1/4 full or less,2: Trigger on 1/2 full or less,3: Default" newline bitfld.long 0x00 3. "UNLOCK,Unlock" "0,1" bitfld.long 0x00 1. "FLUSHFB,Flush from-bus buffer/FIFO" "0,1" newline bitfld.long 0x00 0. "FLUSHTB,Flush to-bus buffer/FIFO" "0,1" wgroup.long 0xB0++0x03 line.long 0x00 "MWDATAB,Master Write Data Byte" bitfld.long 0x00 16. "END_ALSO,End of message also" "0,1" bitfld.long 0x00 8. "END,End of message" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "VALUE,Data byte" wgroup.long 0xB4++0x03 line.long 0x00 "MWDATABE,Master Write Data Byte End" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Data" wgroup.long 0xB8++0x03 line.long 0x00 "MWDATAH,Master Write Data Half-word" bitfld.long 0x00 16. "END,End of message" "0,1" hexmask.long.byte 0x00 8.--15. 1. "DATA1,Data byte 1" newline hexmask.long.byte 0x00 0.--7. 1. "DATA0,Data byte 0" wgroup.long 0xBC++0x03 line.long 0x00 "MWDATAHE,Master Write Data Byte End" hexmask.long.byte 0x00 8.--15. 1. "DATA1,DATA 1" hexmask.long.byte 0x00 0.--7. 1. "DATA0,DATA 0" rgroup.long 0xC0++0x03 line.long 0x00 "MRDATAB,Master Read Data Byte" hexmask.long.byte 0x00 0.--7. 1. "VALUE,VALUE" rgroup.long 0xC8++0x03 line.long 0x00 "MRDATAH,Master Read Data Half-word" hexmask.long.byte 0x00 8.--15. 1. "MSB,MSB" hexmask.long.byte 0x00 0.--7. 1. "LSB,LSB" wgroup.long 0xCC++0x03 line.long 0x00 "MWDATAB1,Byte-only Write Byte Data (to bus)" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Value" wgroup.long 0xD0++0x03 line.long 0x00 "MWMSG_SDR_CONTROL,Master Write Message in SDR mode" bitfld.long 0x00 11.--15. "LEN,Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "I2C,I2C" "0: I3C message,1: I2C message" newline bitfld.long 0x00 8. "END,End of SDR message" "0,1" hexmask.long.byte 0x00 1.--7. 1. "ADDR,Address to be written to" newline bitfld.long 0x00 0. "DIR,Direction" "0: ,1: " wgroup.long 0xD0++0x03 line.long 0x00 "MWMSG_SDR_DATA,Master Write Message Data in SDR mode" hexmask.long.word 0x00 0.--15. 1. "DATA16B,Data" rgroup.long 0xD4++0x03 line.long 0x00 "MRMSG_SDR,Master Read Message in SDR mode" hexmask.long.word 0x00 0.--15. 1. "DATA,Data" wgroup.long 0xD8++0x03 line.long 0x00 "MWMSG_DDR_CONTROL,Master Write Message in DDR mode" bitfld.long 0x00 14. "END,End of message" "0,1" hexmask.long.word 0x00 0.--9. 1. "LEN,Length of message" wgroup.long 0xD8++0x03 line.long 0x00 "MWMSG_DDR_DATA,Master Write Message Data in DDR mode" hexmask.long.word 0x00 0.--15. 1. "DATA16B,Data" rgroup.long 0xDC++0x03 line.long 0x00 "MRMSG_DDR,Master Read Message in DDR mode" hexmask.long.word 0x00 0.--15. 1. "DATA,Data" group.long 0xE4++0x03 line.long 0x00 "MDYNADDR,Master Dynamic Address" hexmask.long.byte 0x00 1.--7. 1. "DADDR,Dynamic address" bitfld.long 0x00 0. "DAVALID,Dynamic address valid" "0,1" rgroup.long 0x11C++0x03 line.long 0x00 "SMAPCTRL0,Map Feature Control 0" bitfld.long 0x00 8.--10. "CAUSE,Cause" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 1.--7. 1. "DA,Dynamic Address" newline bitfld.long 0x00 0. "ENA,Enable" "0,1" group.long 0x140++0x03 line.long 0x00 "IBIEXT1,Extended IBI Data 1" hexmask.long.byte 0x00 24.--31. 1. "EXT3,Extra byte 3" hexmask.long.byte 0x00 16.--23. 1. "EXT2,Extra byte 2" newline hexmask.long.byte 0x00 8.--15. 1. "EXT1,Extra byte 1" rbitfld.long 0x00 4.--6. "MAX,Maximum" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "CNT,Count" "0,1,2,3,4,5,6,7" group.long 0x144++0x03 line.long 0x00 "IBIEXT2,Extended IBI Data 2" hexmask.long.byte 0x00 24.--31. 1. "EXT7,Extra byte 7" hexmask.long.byte 0x00 16.--23. 1. "EXT6,Extra byte 6" newline hexmask.long.byte 0x00 8.--15. 1. "EXT5,Extra byte 5" hexmask.long.byte 0x00 0.--7. 1. "EXT4,Extra byte 4" rgroup.long 0xFFC++0x03 line.long 0x00 "SID,Slave Module ID" hexmask.long 0x00 0.--31. 1. "ID,ID" tree.end endif tree "INPUTMUX (Input multiplexing (INPUTMUX))" base ad:0x40006000 repeat 7. (increment 0 1) (increment 0 0x4) group.long ($2+0x00)++0x03 line.long 0x00 "SCT0_INMUX[$1],Inputmux register for SCT0 input $1" bitfld.long 0x00 0.--5. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPIO_IN_A function selected from IOCON..,1: SCT_GPIO_IN_B function selected from IOCON..,2: SCT_GPIO_IN_C function selected from IOCON..,3: SCT_GPIO_IN_D function selected from IOCON..,4: SCT_GPIO_IN_E function selected from IOCON..,5: SCT_GPIO_IN_F function selected from IOCON..,6: SCT_GPIO_IN_G function selected from IOCON..,7: SCT_GPIO_IN_H function selected from IOCON..,8: T0_MAT0 ctimer 0 match[0] output,9: T1_MAT0 ctimer 1 match[0] output,10: T2_MAT0 ctimer 2 match[0] output,11: T3_MAT0 ctimer 3 match[0] output,12: T4_MAT0 ctimer 4 match[0] output,13: ADC0_IRQ interrupt request from ADC0,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,?,17: ACMP0_OUT from analog comparator,18: SHARED_I2S_SCLK0 output from I2S pin sharing,19: SHARED_I2S_SCLK1 output from I2S pin sharing,20: SHARED_I2S_WS0 output from I2S pin sharing,21: SHARED_I2S_WS1 output from I2S pin sharing,22: ARM_TXEV interrupt event from CPU0,23: DEBUG_HALTED from CPU0,24: ADC1_IRQ interrupt request from ADC1,25: ADC0_tcomp[0],26: ADC0_tcomp[1],27: ADC0_tcomp[2],28: ADC0_tcomp[3],29: ADC1_tcomp[0],30: ADC1_tcomp[1],31: ADC1_tcomp[2],32: ADC1_tcomp[3],33: HSCMP0_OUT,34: HSCMP1_OUT,35: HSCMP2_OUT,36: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,37: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,38: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,39: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,40: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,41: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,42: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,43: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,44: ENC0_CMP/POS_MATCH,45: ENC1_CMP/POS_MATCH,46: AOI0_OUT0,47: AOI0_OUT1,48: AOI0_OUT2,49: AOI0_OUT3,50: AOI1_OUT0,51: AOI1_OUT1,52: AOI1_OUT2,53: AOI1_OUT3,54: FC3_SCK,55: FC3_RXD_SDA_MOSI_DATA,56: FC3_TXD_SCL_MISO_WS,57: FC3_CTS_DSA_SSEL0,58: TMPR_OUT,59: val59,60: val59,61: val59,62: val59,63: val59" repeat.end repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x20)++0x03 line.long 0x00 "TIMER0CAP[$1],Capture select register for TIMER0 inputs $1" bitfld.long 0x00 0.--5. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 5" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat.end group.long 0x30++0x03 line.long 0x00 "TIMER0TRIG,Trigger register for TIMER0" bitfld.long 0x00 0.--5. "TRIGIN,Input number to TIMER0 trigger inputs" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x40)++0x03 line.long 0x00 "TIMER1CAP[$1],Capture select register for TIMER1 inputs $1" bitfld.long 0x00 0.--5. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 5" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat.end group.long 0x50++0x03 line.long 0x00 "TIMER1TRIG,Trigger register for TIMER1" bitfld.long 0x00 0.--5. "TRIGIN,Input number to TIMER1 trigger inputs" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x60)++0x03 line.long 0x00 "TIMER2CAP[$1],Capture select register for TIMER2 inputs $1" bitfld.long 0x00 0.--5. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 5" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat.end group.long 0x70++0x03 line.long 0x00 "TIMER2TRIG,Trigger register for TIMER2" bitfld.long 0x00 0.--5. "TRIGIN,Input number to TIMER2 trigger inputs" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat 8. (increment 0 1) (increment 0 0x4) group.long ($2+0xA0)++0x03 line.long 0x00 "EZHARCHB_INMUX[$1],Inputmux register for EZH arch B inputs $1" hexmask.long.byte 0x00 0.--6. 1. "INP,Input number select to EZHARCHB input" repeat.end repeat 8. (increment 0 1) (increment 0 0x4) group.long ($2+0xC0)++0x03 line.long 0x00 "PINTSEL[$1],Pin interrupt select $1" hexmask.long.byte 0x00 0.--6. 1. "INTPIN,Pin number select for pin interrupt or pattern match engine input" repeat.end repeat 32. (increment 0 1) (increment 0 0x4) group.long ($2+0xE0)++0x03 line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select for DMA0 channel $1" bitfld.long 0x00 0.--5. "INP,Trigger input number (binary value) for DMA channel n (n = 0 to 31)" "0: FlexSPI_RX,1: FlexSPI_TX,2: GPIO_INT0,3: GPIO_INT1,4: GPIO_INT2,5: GPIO_INT3,6: T0_DMAREQ_M0,7: T0_DMAREQ_M1,8: T1_DMAREQ_M0,9: T1_DMAREQ_M1,10: T2_DMAREQ_M0,11: T2_DMAREQ_M1,12: T3_DMAREQ_M0,13: T3_DMAREQ_M1,14: T4_DMAREQ_M0,15: T4_DMAREQ_M1,16: ACMP0_OUT,17: SDMA0_TRIGOUT_A,18: SDMA0_TRIGOUT_B,19: SDMA0_TRIGOUT_C,20: SDMA0_TRIGOUT_D,21: SCT_DMA0,22: SCT_DMA1,23: ADC0_tcomp[0],24: ADC1_tcomp[0],25: HSCMP0,26: HSCMP1,27: HSCMP2,28: AOI0_OUT0,29: AOI0_OUT1,30: AOI0_OUT2,31: AOI0_OUT3,32: AOI1_OUT0,33: AOI1_OUT1,34: AOI1_OUT2,35: AOI1_OUT3,36: FlexPWM0_req_capt0,37: FlexPWM0_req_capt1,38: FlexPWM0_req_capt2,39: FlexPWM0_req_capt3,40: FlexPWM0_req_val0,41: FlexPWM0_req_val1,42: FlexPWM0_req_val2,43: FlexPWM0_req_val3,44: FlexPWM1_req_capt0,45: FlexPWM1_req_capt1,46: FlexPWM1_req_capt2,47: FlexPWM1_req_capt3,48: FlexPWM1_req_val0,49: FlexPWM1_req_val1,50: FlexPWM1_req_val2,51: FlexPWM1_req_val3,52: TMPR_OUT,?..." repeat.end repeat 7. (increment 0 1) (increment 0 0x04) group.long ($2+0x160)++0x03 line.long 0x00 "DMA0_OTRIG_INMUX[$1],DMA0 output trigger selection for DMA0 input trigger $1" bitfld.long 0x00 0.--5. "INP,DMA trigger output number (binary value) for DMA channel n (n = 0 to 52)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" repeat.end group.long 0x180++0x03 line.long 0x00 "FREQMEAS_REF,Selection for frequency measurement reference clock" bitfld.long 0x00 0.--4. "CLKIN,Clock source number (binary value) for frequency measure function target clock" "0: XTAL32MHz,1: FRO_OSC_12M,2: FRO_OSC_96M,3: WDOSC (FRO1M),4: 32KHZ_OSC,5: MAIN_SYS_CLOCK,6: FREQME_GPIO_CLK_A,7: FREQME_GPIO_CLK_B,8: AOI0_OUT2,9: AOI1_OUT2,?..." group.long 0x184++0x03 line.long 0x00 "FREQMEAS_TAR,Selection for frequency measurement target clock" bitfld.long 0x00 0.--4. "CLKIN,Clock source number (binary value) for frequency measure function target clock" "0: XTAL32MHz,1: FRO_OSC_12M,2: FRO_OSC_96M,3: WDOSC (FRO1M),4: 32KHZ_OSC,5: MAIN_SYS_CLOCK,6: FREQME_GPIO_CLK_A,7: FREQME_GPIO_CLK_B,8: AOI0_OUT2,9: AOI1_OUT2,?..." repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x1A0)++0x03 line.long 0x00 "TIMER3CAP[$1],Capture select register for TIMER3 inputs $1" bitfld.long 0x00 0.--5. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 5" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat.end group.long 0x1B0++0x03 line.long 0x00 "TIMER3TRIG,Trigger register for TIMER3" bitfld.long 0x00 0.--5. "TRIGIN,Input number to TIMER3 trigger inputs" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x1C0)++0x03 line.long 0x00 "TIMER4CAP[$1],Capture select register for TIMER4 inputs $1" bitfld.long 0x00 0.--5. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 5" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat.end group.long 0x1D0++0x03 line.long 0x00 "TIMER4TRIG,Trigger register for TIMER4" bitfld.long 0x00 0.--5. "TRIGIN,Input number to TIMER4 trigger inputs" "0: CTIMER_INP0 function selected from IOCON..,1: CTIMER_INP1 function selected from IOCON..,2: CTIMER_INP2 function selected from IOCON..,3: CTIMER_INP3 function selected from IOCON..,4: CTIMER_INP4 function selected from IOCON..,5: CTIMER_INP5 function selected from IOCON..,6: CTIMER_INP6 function selected from IOCON..,7: CTIMER_INP7 function selected from IOCON..,8: CTIMER_INP8 function selected from IOCON..,9: CTIMER_INP9 function selected from IOCON..,10: CTIMER_INP10 function selected from IOCON..,11: CTIMER_INP11 function selected from IOCON..,12: CTIMER_INP12 function selected from IOCON..,13: CTIMER_INP13 function selected from IOCON..,14: CTIMER_INP14 function selected from IOCON..,15: CTIMER_INP15 function selected from IOCON..,16: CTIMER_INP16 function selected from IOCON..,17: CTIMER_INP17 function selected from IOCON..,18: CTIMER_INP18 function selected from IOCON..,19: CTIMER_INP19 function selected from IOCON..,20: USB0_FRAME_TOGGLE,?,22: ACMP0_OUT from analog comparator,23: SHARED_I2S_WS0 output from I2S pin sharing,24: SHARED_I2S_WS1 output from I2S pin sharing,25: ADC0_IRQ,26: ADC1_IRQ,27: HSCMP0_OUT,28: HSCMP1_OUT,29: HSCMP2_OUT,30: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,31: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,32: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,34: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,35: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,37: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,38: ENC0_CMP/POS_MATCH,39: ENC1_CMP/POS_MATCH,40: AOI0_OUT0,41: AOI0_OUT1,42: AOI0_OUT2,43: AOI0_OUT3,44: AOI1_OUT0,45: AOI1_OUT1,46: AOI1_OUT2,47: AOI1_OUT3,48: TMPR_OUT,49: val49,50: val49,51: val49,52: val49,53: val49,54: val49,55: val49,56: val49,57: val49,58: val49,59: val49,60: val49,61: val49,62: val49,63: val49" repeat 2. (increment 0 1) (increment 0 0x04) group.long ($2+0x1E0)++0x03 line.long 0x00 "PINTSECSEL[$1],Pin interrupt secure select $1" bitfld.long 0x00 0.--5. "INTPIN,Pin number select for pin interrupt secure or pattern match engine input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" repeat.end repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x200)++0x03 line.long 0x00 "DMA1_ITRIG_INMUX[$1],Trigger select for DMA1 channel $1" bitfld.long 0x00 0.--4. "INP,Trigger input number (binary value) for DMA channel n (n = 0 to 14)" "0: Pin interrupt 0 (GPIO_INT0),1: Pin interrupt 1 (GPIO_INT1),2: Pin interrupt 2 (GPIO_INT2),3: Pin interrupt 3 (GPIO_INT3),4: Timer CTIMER0 Match 0 (T0_DMAREQ_M0),5: Timer CTIMER0 Match 1 (T0_DMAREQ_M1),6: Timer CTIMER2 Match 0 (T2_DMAREQ_M0),7: Timer CTIMER4 Match 0 (T4_DMAREQ_M0),8: SDMA1_TRIGOUT_A,9: SDMA1_TRIGOUT_B,10: SDMA1_TRIGOUT_C,11: SDMA1_TRIGOUT_D,12: SCT_DMA_REQ0,13: SCT_DMA_REQ1,14: FlexSPI_RX,15: FlexSPI_TX,16: AOI0_OUT0,17: AOI0_OUT1,18: AOI0_OUT2,19: AOI0_OUT3,20: AOI1_OUT0,21: AOI1_OUT1,22: AOI1_OUT2,23: AOI1_OUT3,24: TMPR_OUT,?..." repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x240)++0x03 line.long 0x00 "DMA1_OTRIG_INMUX[$1],DMA1 output trigger selection for DMA1 input trigger $1" bitfld.long 0x00 0.--3. "SDMA1_CH_TRIGOUT,DMA trigger output number (binary value) for DMA channel n (n = 0 to 15)" "0: SDMA1_CH0_TRIGOUT,1: SDMA1_CH1_TRIGOUT,2: SDMA1_CH2_TRIGOUT,3: SDMA1_CH3_TRIGOUT,4: SDMA1_CH4_TRIGOUT,5: SDMA1_CH5_TRIGOUT,6: SDMA1_CH6_TRIGOUT,7: SDMA1_CH7_TRIGOUT,8: SDMA1_CH8_TRIGOUT,9: SDMA1_CH9_TRIGOUT,10: SDMA1_CH10_TRIGOUT,11: SDMA1_CH11_TRIGOUT,12: SDMA1_CH12_TRIGOUT,13: SDMA1_CH13_TRIGOUT,?..." repeat.end group.long 0x260++0x03 line.long 0x00 "HSCMP0_TRIG,Input connections for HSCMP0" bitfld.long 0x00 0.--5. "TRIGIN,CMP0 input trigger" "0: PIN_INT0,1: PIN_INT6,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT6,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T0_MAT0,9: T4_MAT0,?,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC1_tcomp[0],?,?,17: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,18: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,19: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,20: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,21: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,22: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,23: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,24: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,25: ENC0_CMP/POS_MATCH,26: ENC1_CMP/POS_MATCH,27: AOI0_OUT0,28: AOI0_OUT1,29: AOI0_OUT2,30: AOI0_OUT3,31: AOI1_OUT0,32: AOI1_OUT1,33: AOI1_OUT2,34: AOI1_OUT3,35: DMA0_TRIGOUT0,36: DMA0_TRIGOUT1,37: DMA0_TRIGOUT2,?..." repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x280)++0x03 line.long 0x00 "ADC0_TRIG[$1],ADC0 Trigger input connections $1" bitfld.long 0x00 0.--5. "TRIGIN,ADC0 trigger inputs" "0: PIN_INT0,1: PIN_INT1,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT9,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T3_MAT3,9: T4_MAT3,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM0_SM0_MUX_TRIG0,25: PWM0_SM0_MUX_TRIG1,26: PWM0_SM1_MUX_TRIG0,27: PWM0_SM1_MUX_TRIG1,28: PWM0_SM2_MUX_TRIG0,29: PWM0_SM2_MUX_TRIG1,30: PWM0_SM3_MUX_TRIG0,31: PWM0_SM3_MUX_TRIG1,32: PWM1_SM0_MUX_TRIG0,33: PWM1_SM0_MUX_TRIG1,34: PWM1_SM1_MUX_TRIG0,35: PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0,37: PWM1_SM2_MUX_TRIG1,38: PWM1_SM3_MUX_TRIG0,39: PWM1_SM3_MUX_TRIG1,40: ENC0_CMP/POS_MATCH,41: ENC1_CMP/POS_MATCH,42: AOI0_OUT0,43: AOI0_OUT1,44: AOI0_OUT2,45: AOI0_OUT3,46: AOI1_OUT0,47: AOI1_OUT1,48: AOI1_OUT2,49: AOI1_OUT3,50: DMA0_TRIGOUT0,51: DMA0_TRIGOUT1,52: DMA0_TRIGOUT2,53: val53,54: val53,55: val53,56: val53,57: val53,58: val53,59: val53,60: val53,61: val53,62: val53,63: val53" repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x2C0)++0x03 line.long 0x00 "ADC1_TRIG[$1],ADC1 Trigger input connections $1" bitfld.long 0x00 0.--5. "TRIGIN,ADC1 trigger inputs" "0: PIN_INT0,1: PIN_INT2,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT3,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T3_MAT2,9: T4_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM0_SM0_MUX_TRIG0,25: PWM0_SM0_MUX_TRIG1,26: PWM0_SM1_MUX_TRIG0,27: PWM0_SM1_MUX_TRIG1,28: PWM0_SM2_MUX_TRIG0,29: PWM0_SM2_MUX_TRIG1,30: PWM0_SM3_MUX_TRIG0,31: PWM0_SM3_MUX_TRIG1,32: PWM1_SM0_MUX_TRIG0,33: PWM1_SM0_MUX_TRIG1,34: PWM1_SM1_MUX_TRIG0,35: PWM1_SM1_MUX_TRIG1,36: PWM1_SM2_MUX_TRIG0,37: PWM1_SM2_MUX_TRIG1,38: PWM1_SM3_MUX_TRIG0,39: PWM1_SM3_MUX_TRIG1,40: ENC0_CMP/POS_MATCH,41: ENC1_CMP/POS_MATCH,42: AOI0_OUT0,43: AOI0_OUT1,44: AOI0_OUT2,45: AOI0_OUT3,46: AOI1_OUT0,47: AOI1_OUT1,48: AOI1_OUT2,49: AOI1_OUT3,50: DMA0_TRIGOUT0,51: DMA0_TRIGOUT1,52: DMA0_TRIGOUT2,53: val53,54: val53,55: val53,56: val53,57: val53,58: val53,59: val53,60: val53,61: val53,62: val53,63: val53" repeat.end group.long 0x300++0x03 line.long 0x00 "DAC0_TRIG,DAC0 Trigger Inputs" bitfld.long 0x00 0.--4. "TRIGIN,DAC0 trigger input" "0: PIN_INT0,1: PIN_INT3,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT0,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT0,9: T3_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC1_tcomp[0],15: HSCMP0_OUT,16: HSCMP1_OUT,17: HSCMP2_OUT,18: AOI0_OUT0,19: AOI0_OUT1,20: AOI0_OUT2,21: AOI0_OUT3,22: AOI1_OUT0,23: AOI1_OUT1,24: AOI1_OUT2,25: AOI1_OUT3,26: DMA0_TRIGOUT0,27: DMA0_TRIGOUT1,28: DMA0_TRIGOUT2,?..." group.long 0x320++0x03 line.long 0x00 "DAC1_TRIG,DAC1 Trigger Inputs" bitfld.long 0x00 0.--4. "TRIGIN,DAC1 trigger input" "0: PIN_INT0,1: PIN_INT4,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT1,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT1,9: T3_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[1],14: ADC1_tcomp[1],15: HSCMP0_OUT,16: HSCMP1_OUT,17: HSCMP2_OUT,18: AOI0_OUT0,19: AOI0_OUT1,20: AOI0_OUT2,21: AOI0_OUT3,22: AOI1_OUT0,23: AOI1_OUT1,24: AOI1_OUT2,25: AOI1_OUT3,26: DMA0_TRIGOUT0,27: DMA0_TRIGOUT1,28: DMA0_TRIGOUT2,?..." group.long 0x340++0x03 line.long 0x00 "DAC2_TRIG,DAC2 Trigger Inputs" bitfld.long 0x00 0.--4. "TRIGIN,DAC2 trigger input" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT2,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT2,9: T3_MAT2,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[2],14: ADC1_tcomp[2],15: HSCMP0_OUT,16: HSCMP1_OUT,17: HSCMP2_OUT,18: AOI0_OUT0,19: AOI0_OUT1,20: AOI0_OUT2,21: AOI0_OUT3,22: AOI1_OUT0,23: AOI1_OUT1,24: AOI1_OUT2,25: AOI1_OUT3,26: DMA0_TRIGOUT0,27: DMA0_TRIGOUT1,28: DMA0_TRIGOUT2,?..." group.long 0x360++0x03 line.long 0x00 "ENC0_TRIG,ENC0 Trigger Input Connections" bitfld.long 0x00 0.--5. "TRIGIN,ENC0 input trigger" "0: PIN_INT0,1: PIN_INT4,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT1,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT0,9: T3_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x364++0x03 line.long 0x00 "ENC0_HOME,ENC0 Input Connections" bitfld.long 0x00 0.--5. "ENC0_HOME,ENC0 Input Connections" "0: PIN_INT0,1: PIN_INT4,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT1,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT0,9: T3_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM0_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x368++0x03 line.long 0x00 "ENC0_INDEX,ENC0 Input Connections" bitfld.long 0x00 0.--5. "ENC0_INDEX,ENC0 Input Connections" "0: PIN_INT0,1: PIN_INT4,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT1,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT0,9: T3_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x36C++0x03 line.long 0x00 "ENC0_PHASEB,ENC0 Input Connections" bitfld.long 0x00 0.--5. "ENC0_PHASEB,ENC0 Input Connections" "0: PIN_INT0,1: PIN_INT4,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT1,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT0,9: T3_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x370++0x03 line.long 0x00 "ENC0_PHASEA,ENC0 Input Connections" bitfld.long 0x00 0.--5. "ENC0_PHASEA,ENC0 Input Connections" "0: PIN_INT0,1: PIN_INT4,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT1,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT0,9: T3_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x380++0x03 line.long 0x00 "ENC1_TRIG,ENC1 Trigger Input Connections" bitfld.long 0x00 0.--5. "TRIGIN,ENC1 input trigger" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT7,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT1,9: T3_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x384++0x03 line.long 0x00 "ENC1_HOME,ENC1 Input Connections" bitfld.long 0x00 0.--5. "ENC1_HOME,ENC1 input trigger" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT7,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT1,9: T3_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x388++0x03 line.long 0x00 "ENC1_INDEX,ENC1 Input Connections" bitfld.long 0x00 0.--5. "ENC1_INDEX,ENC1 input trigger" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT7,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT1,9: T3_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x38C++0x03 line.long 0x00 "ENC1_PHASEB,ENC1 Input Connections" bitfld.long 0x00 0.--5. "ENC1_PHASEB,ENC1 input trigger" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT7,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT1,9: T3_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x390++0x03 line.long 0x00 "ENC1_PHASEA,ENC1 Input Connections" bitfld.long 0x00 0.--5. "ENC1_PHASEA,ENC1 input trigger" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT7,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T1_MAT1,9: T3_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x3A0)++0x03 line.long 0x00 "PWM0_EXTSYNC[$1],PWM0 external synchronization $1" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM0" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT2,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT0,9: T4_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x3B0)++0x03 line.long 0x00 "PWM0_EXTA[$1],PWM0 input trigger connections $1" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM0" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT2,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT0,9: T4_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat.end group.long 0x3C0++0x03 line.long 0x00 "PWM0_EXTFORCE,PWM0 external force trigger connections" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM0" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT2,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT0,9: T4_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x3C4)++0x03 line.long 0x00 "PWM0_FAULT[$1],PWM0 fault input trigger connections $1" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM0" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT2,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT0,9: T4_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x3E0)++0x03 line.long 0x00 "PWM1_EXTSYNC[$1],PWM1 external synchronization $1" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM1" "0: PIN_INT0,1: PIN_INT2,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT3,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT1,9: T4_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM0_SM0_MUX_TRIG0,25: PWM0_SM0_MUX_TRIG1,26: PWM0_SM1_MUX_TRIG0,27: PWM0_SM1_MUX_TRIG1,28: PWM0_SM2_MUX_TRIG0,29: PWM0_SM2_MUX_TRIG1,30: PWM0_SM3_MUX_TRIG0,31: PWM0_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat.end repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x3F0)++0x03 line.long 0x00 "PWM1_EXTA[$1],PWM1 input trigger connections $1" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM1" "0: PIN_INT0,1: PIN_INT2,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT3,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT1,9: T4_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM0_SM0_MUX_TRIG0,25: PWM0_SM0_MUX_TRIG1,26: PWM0_SM1_MUX_TRIG0,27: PWM0_SM1_MUX_TRIG1,28: PWM0_SM2_MUX_TRIG0,29: PWM0_SM2_MUX_TRIG1,30: PWM0_SM3_MUX_TRIG0,31: PWM0_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat.end group.long 0x400++0x03 line.long 0x00 "PWM1_EXTFORCE,PWM1 external force trigger connections" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM1" "0: PIN_INT0,1: PIN_INT2,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT3,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT1,9: T4_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM0_SM0_MUX_TRIG0,25: PWM0_SM0_MUX_TRIG1,26: PWM0_SM1_MUX_TRIG0,27: PWM0_SM1_MUX_TRIG1,28: PWM0_SM2_MUX_TRIG0,29: PWM0_SM2_MUX_TRIG1,30: PWM0_SM3_MUX_TRIG0,31: PWM0_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat 4. (increment 0 1) (increment 0 0x04) group.long ($2+0x404)++0x03 line.long 0x00 "PWM1_FAULT[$1],PWM1 fault input trigger connections $1" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM1" "0: PIN_INT0,1: PIN_INT2,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT3,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT1,9: T4_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM0_SM0_MUX_TRIG0,25: PWM0_SM0_MUX_TRIG1,26: PWM0_SM1_MUX_TRIG0,27: PWM0_SM1_MUX_TRIG1,28: PWM0_SM2_MUX_TRIG0,29: PWM0_SM2_MUX_TRIG1,30: PWM0_SM3_MUX_TRIG0,31: PWM0_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat.end group.long 0x420++0x03 line.long 0x00 "PWM0_EXTCLK,PWM0 external clock trigger connections" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM0" "0: PIN_INT0,1: PIN_INT5,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT2,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT0,9: T4_MAT0,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM1_SM0_MUX_TRIG0,25: PWM1_SM0_MUX_TRIG1,26: PWM1_SM1_MUX_TRIG0,27: PWM1_SM1_MUX_TRIG1,28: PWM1_SM2_MUX_TRIG0,29: PWM1_SM2_MUX_TRIG1,30: PWM1_SM3_MUX_TRIG0,31: PWM1_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." group.long 0x424++0x03 line.long 0x00 "PWM1_EXTCLK,PWM1 external clock trigger connections" bitfld.long 0x00 0.--5. "TRIGIN,Trigger input connections for PWM1" "0: PIN_INT0,1: PIN_INT2,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT3,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T2_MAT1,9: T4_MAT1,10: ACMP0_OUT,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[0],14: ADC0_tcomp[1],15: ADC0_tcomp[2],16: ADC0_tcomp[3],17: ADC1_tcomp[0],18: ADC1_tcomp[1],19: ADC1_tcomp[2],20: ADC1_tcomp[3],21: HSCMP0_OUT,22: HSCMP1_OUT,23: HSCMP2_OUT,24: PWM0_SM0_MUX_TRIG0,25: PWM0_SM0_MUX_TRIG1,26: PWM0_SM1_MUX_TRIG0,27: PWM0_SM1_MUX_TRIG1,28: PWM0_SM2_MUX_TRIG0,29: PWM0_SM2_MUX_TRIG1,30: PWM0_SM3_MUX_TRIG0,31: PWM0_SM3_MUX_TRIG1,32: ENC0_CMP/POS_MATCH,33: ENC1_CMP/POS_MATCH,34: AOI0_OUT0,35: AOI0_OUT1,36: AOI0_OUT2,37: AOI0_OUT3,38: AOI1_OUT0,39: AOI1_OUT1,40: AOI1_OUT2,41: AOI1_OUT3,42: EXTTRIG_IN0,43: EXTTRIG_IN1,44: EXTTRIG_IN2,45: EXTTRIG_IN3,46: EXTTRIG_IN4,47: EXTTRIG_IN5,48: EXTTRIG_IN6,49: EXTTRIG_IN7,50: EXTTRIG_IN8,51: EXTTRIG_IN9,52: DMA0_TRIGOUT0,53: DMA0_TRIGOUT1,54: DMA0_TRIGOUT2,?..." repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x440)++0x03 line.long 0x00 "AOI0_IN[$1],AOI0 trigger inputs $1" bitfld.long 0x00 0.--5. "IN,Input trigger assignments" "0: PIN_INT0,1: PIN_INT1,2: SCT_OUT0,3: SCT_OUT1,4: SCT_OUT2,5: SCT_OUT3,6: T0_MAT3,7: T1_MAT3,8: T2_MAT3,9: T2_MAT2,10: T3_MAT2,11: T4_MAT2,12: ACMP0_OUT,13: GPIOINT_BMATCH,14: ADC0_IRQ,15: ADC1_IRQ,16: ADC0_tcomp[0],17: ADC0_tcomp[1],18: ADC0_tcomp[2],19: ADC0_tcomp[3],20: ADC1_tcomp[0],21: ADC1_tcomp[1],22: ADC1_tcomp[2],23: ADC1_tcomp[3],24: HSCMP0_OUT,25: HSCMP1_OUT,26: HSCMP2_OUT,27: PWM0_SM0_MUX_TRIG0,28: PWM0_SM0_MUX_TRIG1,29: PWM0_SM1_MUX_TRIG0,30: PWM0_SM1_MUX_TRIG1,31: PWM0_SM2_MUX_TRIG0,32: PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0,34: PWM0_SM3_MUX_TRIG1,35: PWM1_SM0_MUX_TRIG0,36: PWM1_SM0_MUX_TRIG1,37: PWM1_SM1_MUX_TRIG0,38: PWM1_SM1_MUX_TRIG1,39: PWM1_SM2_MUX_TRIG0,40: PWM1_SM2_MUX_TRIG1,41: PWM1_SM3_MUX_TRIG0,42: PWM1_SM3_MUX_TRIG1,43: ENC0_CMP/POS_MATCH,44: ENC1_CMP/POS_MATCH,45: EXTTRIG_IN0,46: EXTTRIG_IN1,47: EXTTRIG_IN2,48: EXTTRIG_IN3,?,?,51: DMA0_TRIGOUT0,52: DMA0_TRIGOUT1,53: DMA0_TRIGOUT2,54: DMA0_TRIGOUT3,55: DMA0_TRIGOUT4,56: DMA0_TRIGOUT5,57: DMA0_TRIGOUT6,58: DMA1_TRIGOUT0,59: DMA1_TRIGOUT1,60: DMA1_TRIGOUT2,?..." repeat.end repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x480)++0x03 line.long 0x00 "AOI1_IN[$1],AOI1 trigger inputs $1" bitfld.long 0x00 0.--5. "IN,Input trigger assignments" "0: PIN_INT0,1: PIN_INT1,2: SCT_OUT0,3: SCT_OUT1,4: SCT_OUT2,5: SCT_OUT3,6: T0_MAT3,7: T1_MAT3,8: T2_MAT3,9: T2_MAT2,10: T3_MAT2,11: T4_MAT2,12: ACMP0_OUT,13: GPIOINT_BMATCH,14: ADC0_IRQ,15: ADC1_IRQ,16: ADC0_tcomp[0],17: ADC0_tcomp[1],18: ADC0_tcomp[2],19: ADC0_tcomp[3],20: ADC1_tcomp[0],21: ADC1_tcomp[1],22: ADC1_tcomp[2],23: ADC1_tcomp[3],24: HSCMP0_OUT,25: HSCMP1_OUT,26: HSCMP2_OUT,27: PWM0_SM0_MUX_TRIG0,28: PWM0_SM0_MUX_TRIG1,29: PWM0_SM1_MUX_TRIG0,30: PWM0_SM1_MUX_TRIG1,31: PWM0_SM2_MUX_TRIG0,32: PWM0_SM2_MUX_TRIG1,33: PWM0_SM3_MUX_TRIG0,34: PWM0_SM3_MUX_TRIG1,35: PWM1_SM0_MUX_TRIG0,36: PWM1_SM0_MUX_TRIG1,37: PWM1_SM1_MUX_TRIG0,38: PWM1_SM1_MUX_TRIG1,39: PWM1_SM2_MUX_TRIG0,40: PWM1_SM2_MUX_TRIG1,41: PWM1_SM3_MUX_TRIG0,42: PWM1_SM3_MUX_TRIG1,43: ENC0_CMP/POS_MATCH,44: ENC1_CMP/POS_MATCH,45: EXTTRIG_IN0,46: EXTTRIG_IN1,47: EXTTRIG_IN2,48: EXTTRIG_IN3,?,?,51: DMA0_TRIGOUT0,52: DMA0_TRIGOUT1,53: DMA0_TRIGOUT2,54: DMA0_TRIGOUT3,55: DMA0_TRIGOUT4,56: DMA0_TRIGOUT5,57: DMA0_TRIGOUT6,58: DMA1_TRIGOUT0,59: DMA1_TRIGOUT1,60: DMA1_TRIGOUT2,?..." repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x4C0)++0x03 line.long 0x00 "AOI_EXT_TRIG[$1],AOI External Trigger Inputs $1" bitfld.long 0x00 0.--4. "TRIGIN,AOI external trigger inputs from 0 to 4" "0: PIN_INT0,1: PIN_INT1,2: ADC0_IRQ,3: ADC1_IRQ,4: ADC0_tcomp[0],5: ADC1_tcomp[0],6: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,7: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,8: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,9: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,10: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,11: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,12: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,13: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,14: ENC0_CMP/POS_MATCH,15: ENC1_CMP/POS_MATCH,16: AOI0_OUT0,17: AOI0_OUT1,18: AOI0_OUT2,19: AOI0_OUT3,20: AOI1_OUT0,21: AOI1_OUT1,22: AOI1_OUT2,23: AOI1_OUT3,24: TMPR_OUT,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25" repeat.end group.long 0x4E0++0x03 line.long 0x00 "HSCMP1_TRIG,Input connections for HSCMP1" bitfld.long 0x00 0.--5. "TRIGIN,CMP1 input trigger" "0: PIN_INT0,1: PIN_INT7,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT7,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T0_MAT1,9: T4_MAT1,?,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[1],14: ADC1_tcomp[1],?,?,17: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,18: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,19: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,20: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,21: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,22: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,23: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,24: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,25: ENC0_CMP/POS_MATCH,26: ENC1_CMP/POS_MATCH,27: AOI0_OUT0,28: AOI0_OUT1,29: AOI0_OUT2,30: AOI0_OUT3,31: AOI1_OUT0,32: AOI1_OUT1,33: AOI1_OUT2,34: AOI1_OUT3,35: DMA0_TRIGOUT0,36: DMA0_TRIGOUT1,37: DMA0_TRIGOUT2,?..." group.long 0x500++0x03 line.long 0x00 "HSCMP2_TRIG,Input connections for HSCMP2" bitfld.long 0x00 0.--5. "TRIGIN,CMP2 input trigger" "0: PIN_INT0,1: PIN_INT4,2: SCT_OUT4,3: SCT_OUT5,4: SCT_OUT8,5: T0_MAT3,6: T1_MAT3,7: T2_MAT3,8: T0_MAT2,9: T4_MAT2,?,11: ARM_TXEV,12: GPIOINT_BMATCH,13: ADC0_tcomp[2],14: ADC1_tcomp[2],?,?,17: PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1,18: PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1,19: PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1,20: PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1,21: PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1,22: PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1,23: PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1,24: PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1,25: ENC0_CMP/POS_MATCH,26: ENC1_CMP/POS_MATCH,27: AOI0_OUT0,28: AOI0_OUT1,29: AOI0_OUT2,30: AOI0_OUT3,31: AOI1_OUT0,32: AOI1_OUT1,33: AOI1_OUT2,34: AOI1_OUT3,35: DMA0_TRIGOUT0,36: DMA0_TRIGOUT1,37: DMA0_TRIGOUT2,?..." repeat 16. (strings "3232" "3233" "3234" "3235" "3236" "3237" "3238" "3239" "3240" "3241" "3242" "3243" "3244" "3245" "3246" "3247" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x520)++0x03 line.long 0x00 "DMA0_ITRIG_INMUX$1,Trigger select for DMA0 channel" bitfld.long 0x00 0.--5. "INP,Trigger input number (binary value) for DMA channel n (n = 32 to 51)" "0: FlexSPI_RX,1: FlexSPI_TX,2: GPIO_INT0,3: GPIO_INT1,4: GPIO_INT2,5: GPIO_INT3,6: T0_DMAREQ_M0,7: T0_DMAREQ_M1,8: T1_DMAREQ_M0,9: T1_DMAREQ_M1,10: T2_DMAREQ_M0,11: T2_DMAREQ_M1,12: T3_DMAREQ_M0,13: T3_DMAREQ_M1,14: T4_DMAREQ_M0,15: T4_DMAREQ_M1,16: ACMP0_OUT,17: SDMA0_TRIGOUT_A,18: SDMA0_TRIGOUT_B,19: SDMA0_TRIGOUT_C,20: SDMA0_TRIGOUT_D,21: SCT_DMA0,22: SCT_DMA1,23: ADC0_tcomp[0],24: ADC1_tcomp[0],25: HSCMP0,26: HSCMP1,27: HSCMP2,28: AOI0_OUT0,29: AOI0_OUT1,30: AOI0_OUT2,31: AOI0_OUT3,32: AOI1_OUT0,33: AOI1_OUT1,34: AOI1_OUT2,35: AOI1_OUT3,36: FlexPWM0_req_capt0,37: FlexPWM0_req_capt1,38: FlexPWM0_req_capt2,39: FlexPWM0_req_capt3,40: FlexPWM0_req_val0,41: FlexPWM0_req_val1,42: FlexPWM0_req_val2,43: FlexPWM0_req_val3,44: FlexPWM1_req_capt0,45: FlexPWM1_req_capt1,46: FlexPWM1_req_capt2,47: FlexPWM1_req_capt3,48: FlexPWM1_req_val0,49: FlexPWM1_req_val1,50: FlexPWM1_req_val2,51: FlexPWM1_req_val3,52: TMPR_OUT,?..." repeat.end repeat 4. (strings "3248" "3249" "3250" "3251" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x560)++0x03 line.long 0x00 "DMA0_ITRIG_INMUX$1,Trigger select for DMA0 channel" bitfld.long 0x00 0.--5. "INP,Trigger input number (binary value) for DMA channel n (n = 32 to 51)" "0: FlexSPI_RX,1: FlexSPI_TX,2: GPIO_INT0,3: GPIO_INT1,4: GPIO_INT2,5: GPIO_INT3,6: T0_DMAREQ_M0,7: T0_DMAREQ_M1,8: T1_DMAREQ_M0,9: T1_DMAREQ_M1,10: T2_DMAREQ_M0,11: T2_DMAREQ_M1,12: T3_DMAREQ_M0,13: T3_DMAREQ_M1,14: T4_DMAREQ_M0,15: T4_DMAREQ_M1,16: ACMP0_OUT,17: SDMA0_TRIGOUT_A,18: SDMA0_TRIGOUT_B,19: SDMA0_TRIGOUT_C,20: SDMA0_TRIGOUT_D,21: SCT_DMA0,22: SCT_DMA1,23: ADC0_tcomp[0],24: ADC1_tcomp[0],25: HSCMP0,26: HSCMP1,27: HSCMP2,28: AOI0_OUT0,29: AOI0_OUT1,30: AOI0_OUT2,31: AOI0_OUT3,32: AOI1_OUT0,33: AOI1_OUT1,34: AOI1_OUT2,35: AOI1_OUT3,36: FlexPWM0_req_capt0,37: FlexPWM0_req_capt1,38: FlexPWM0_req_capt2,39: FlexPWM0_req_capt3,40: FlexPWM0_req_val0,41: FlexPWM0_req_val1,42: FlexPWM0_req_val2,43: FlexPWM0_req_val3,44: FlexPWM1_req_capt0,45: FlexPWM1_req_capt1,46: FlexPWM1_req_capt2,47: FlexPWM1_req_capt3,48: FlexPWM1_req_val0,49: FlexPWM1_req_val1,50: FlexPWM1_req_val2,51: FlexPWM1_req_val3,52: TMPR_OUT,?..." repeat.end group.long 0x740++0x03 line.long 0x00 "DMA0_REQEN0,Enable DMA0 requests" bitfld.long 0x00 31. "REQ_ENA31,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 30. "REQ_ENA30,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 29. "REQ_ENA29,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 28. "REQ_ENA28,Controls the first 32 request inputs of DMA0" "0,1" newline bitfld.long 0x00 27. "REQ_ENA27,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 26. "REQ_ENA26,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 25. "REQ_ENA25,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 24. "REQ_ENA24,Controls the first 32 request inputs of DMA0" "0,1" newline bitfld.long 0x00 23. "REQ_ENA23,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 22. "REQ_ENA22,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 21. "REQ_ENA21,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 20. "REQ_ENA20,Controls the first 32 request inputs of DMA0" "0,1" newline bitfld.long 0x00 19. "REQ_ENA19,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 18. "REQ_ENA18,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 17. "REQ_ENA17,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 16. "REQ_ENA16,Controls the first 32 request inputs of DMA0" "0,1" newline bitfld.long 0x00 15. "REQ_ENA15,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 14. "REQ_ENA14,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 13. "REQ_ENA13,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 12. "REQ_ENA12,Controls the first 32 request inputs of DMA0" "0,1" newline bitfld.long 0x00 11. "REQ_ENA11,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 10. "REQ_ENA10,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 9. "REQ_ENA9,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 8. "REQ_ENA8,Controls the first 32 request inputs of DMA0" "0,1" newline bitfld.long 0x00 7. "REQ_ENA7,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 6. "REQ_ENA6,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 5. "REQ_ENA5,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 4. "REQ_ENA4,Controls the first 32 request inputs of DMA0" "0,1" newline bitfld.long 0x00 3. "REQ_ENA3,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 2. "REQ_ENA2,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 1. "REQ_ENA1,Controls the first 32 request inputs of DMA0" "0,1" bitfld.long 0x00 0. "REQ_ENA0,Controls the first 32 request inputs of DMA0" "0,1" group.long 0x744++0x03 line.long 0x00 "DMA0_REQEN1,Enable DMA0 requests" bitfld.long 0x00 19. "REQ_ENA19,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 18. "REQ_ENA18,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 17. "REQ_ENA17,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 16. "REQ_ENA16,Controls the remaining 20 request inputs of DMA0" "0,1" newline bitfld.long 0x00 15. "REQ_ENA15,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 14. "REQ_ENA14,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 13. "REQ_ENA13,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 12. "REQ_ENA12,Controls the remaining 20 request inputs of DMA0" "0,1" newline bitfld.long 0x00 11. "REQ_ENA11,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 10. "REQ_ENA10,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 9. "REQ_ENA9,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 8. "REQ_ENA8,Controls the remaining 20 request inputs of DMA0" "0,1" newline bitfld.long 0x00 7. "REQ_ENA7,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 6. "REQ_ENA6,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 5. "REQ_ENA5,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 4. "REQ_ENA4,Controls the remaining 20 request inputs of DMA0" "0,1" newline bitfld.long 0x00 3. "REQ_ENA3,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 2. "REQ_ENA2,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 1. "REQ_ENA1,Controls the remaining 20 request inputs of DMA0" "0,1" bitfld.long 0x00 0. "REQ_ENA0,Controls the remaining 20 request inputs of DMA0" "0,1" wgroup.long 0x748++0x03 line.long 0x00 "DMA0_REQEN0_SET,Set bits in DMA0_REQEN0 register" bitfld.long 0x00 31. "SET31,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 30. "SET30,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 29. "SET29,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 28. "SET28,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 27. "SET27,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 26. "SET26,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 25. "SET25,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 24. "SET24,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 23. "SET23,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 22. "SET22,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 21. "SET21,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 20. "SET20,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 19. "SET19,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 18. "SET18,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 17. "SET17,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 16. "SET16,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 15. "SET15,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 14. "SET14,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 13. "SET13,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 12. "SET12,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 11. "SET11,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 10. "SET10,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 9. "SET9,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 8. "SET8,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 7. "SET7,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 6. "SET6,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 5. "SET5,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 4. "SET4,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 3. "SET3,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 2. "SET2,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 1. "SET1,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 0. "SET0,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is set to 1 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" wgroup.long 0x74C++0x03 line.long 0x00 "DMA0_REQEN1_SET,Set bits in DMA0_REQEN1 register" bitfld.long 0x00 19. "REQ_ENA19,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 18. "REQ_ENA18,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 17. "REQ_ENA17,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 16. "REQ_ENA16,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 15. "REQ_ENA15,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 14. "REQ_ENA14,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 13. "REQ_ENA13,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 12. "REQ_ENA12,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 11. "REQ_ENA11,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 10. "REQ_ENA10,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 9. "REQ_ENA9,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 8. "REQ_ENA8,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 7. "REQ_ENA7,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 6. "REQ_ENA6,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 5. "REQ_ENA5,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 4. "REQ_ENA4,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 3. "REQ_ENA3,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 2. "REQ_ENA2,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 1. "REQ_ENA1,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 0. "REQ_ENA0,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is set to 1 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" wgroup.long 0x750++0x03 line.long 0x00 "DMA0_REQEN0_CLR,Clear bits in DMA0_REQEN0 register" bitfld.long 0x00 31. "CLR31,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 30. "CLR30,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 29. "CLR29,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 28. "CLR28,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 27. "CLR27,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 26. "CLR26,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 25. "CLR25,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 24. "CLR24,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 23. "CLR23,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 22. "CLR22,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 21. "CLR21,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 20. "CLR20,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 19. "CLR19,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 18. "CLR18,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 17. "CLR17,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 16. "CLR16,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 15. "CLR15,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 14. "CLR14,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 13. "CLR13,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 12. "CLR12,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 11. "CLR11,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 10. "CLR10,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 9. "CLR9,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 8. "CLR8,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 7. "CLR7,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 6. "CLR6,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 5. "CLR5,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 4. "CLR4,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" newline bitfld.long 0x00 3. "CLR3,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 2. "CLR2,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 1. "CLR1,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" bitfld.long 0x00 0. "CLR0,Write : If bit #i = 1 bit #i in DMA0_REQEN0 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN0 register" "0,1" wgroup.long 0x754++0x03 line.long 0x00 "DMA0_REQEN1_CLR,Clear bits in DMA0_REQEN1 register" bitfld.long 0x00 19. "REQ_ENA19,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 18. "REQ_ENA18,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 17. "REQ_ENA17,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 16. "REQ_ENA16,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 15. "REQ_ENA15,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 14. "REQ_ENA14,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 13. "REQ_ENA13,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 12. "REQ_ENA12,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 11. "REQ_ENA11,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 10. "REQ_ENA10,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 9. "REQ_ENA9,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 8. "REQ_ENA8,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 7. "REQ_ENA7,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 6. "REQ_ENA6,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 5. "REQ_ENA5,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 4. "REQ_ENA4,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" newline bitfld.long 0x00 3. "REQ_ENA3,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 2. "REQ_ENA2,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 1. "REQ_ENA1,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" bitfld.long 0x00 0. "REQ_ENA0,Write : If bit #i = 1 bit #i in DMA0_REQEN1 register is reset to 0 if bit #i = 0 no change in DMA0_REQEN1 register" "0,1" group.long 0x760++0x03 line.long 0x00 "DMA1_REQEN,Enable DMA1 requests" bitfld.long 0x00 15. "REQ_ENA15,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 14. "REQ_ENA14,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 13. "REQ_ENA13,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 12. "REQ_ENA12,Controls the 16 request inputs of DMA1" "0,1" newline bitfld.long 0x00 11. "REQ_ENA11,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 10. "REQ_ENA10,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 9. "REQ_ENA9,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 8. "REQ_ENA8,Controls the 16 request inputs of DMA1" "0,1" newline bitfld.long 0x00 7. "REQ_ENA7,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 6. "REQ_ENA6,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 5. "REQ_ENA5,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 4. "REQ_ENA4,Controls the 16 request inputs of DMA1" "0,1" newline bitfld.long 0x00 3. "REQ_ENA3,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 2. "REQ_ENA2,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 1. "REQ_ENA1,Controls the 16 request inputs of DMA1" "0,1" bitfld.long 0x00 0. "REQ_ENA0,Controls the 16 request inputs of DMA1" "0,1" wgroup.long 0x768++0x03 line.long 0x00 "DMA1_REQEN_SET,Set bits in DMA1_REQEN register" bitfld.long 0x00 15. "SET15,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 14. "SET14,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 13. "SET13,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 12. "SET12,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" newline bitfld.long 0x00 11. "SET11,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 10. "SET10,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 9. "SET9,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 8. "SET8,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" newline bitfld.long 0x00 7. "SET7,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 6. "SET6,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 5. "SET5,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 4. "SET4,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" newline bitfld.long 0x00 3. "SET3,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 2. "SET2,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 1. "SET1,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 0. "SET0,Write : If bit #i = 1 bit #i in DMA1_REQEN register is set to 1 if bit #i = 0 no change in DMA1_REQEN register" "0,1" wgroup.long 0x770++0x03 line.long 0x00 "DMA1_REQEN_CLR,Clear bits in DMA1_REQEN register" bitfld.long 0x00 15. "CLR15,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 14. "CLR14,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 13. "CLR13,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 12. "CLR12,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" newline bitfld.long 0x00 11. "CLR11,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 10. "CLR10,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 9. "CLR9,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 8. "CLR8,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" newline bitfld.long 0x00 7. "CLR7,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 6. "CLR6,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 5. "CLR5,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 4. "CLR4,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" newline bitfld.long 0x00 3. "CLR3,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 2. "CLR2,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 1. "CLR1,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" bitfld.long 0x00 0. "CLR0,Write : If bit #i = 1 bit #i in DMA1_REQEN register is reset to 0 if bit #i = 0 no change in DMA1_REQEN register" "0,1" group.long 0x780++0x03 line.long 0x00 "DMA0_ITRIGEN0,Enable DMA0 triggers" bitfld.long 0x00 31. "ITRIGEN31,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 30. "ITRIGEN30,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 29. "ITRIGEN29,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 28. "ITRIGEN28,Controls the 32 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 27. "ITRIGEN27,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 26. "ITRIGEN26,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 25. "ITRIGEN25,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 24. "ITRIGEN24,Controls the 32 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 23. "ITRIGEN23,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 22. "ITRIGEN22,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 21. "ITRIGEN21,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 20. "ITRIGEN20,Controls the 32 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 19. "ITRIGEN19,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 18. "ITRIGEN18,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 17. "ITRIGEN17,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 16. "ITRIGEN16,Controls the 32 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 15. "ITRIGEN15,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 14. "ITRIGEN14,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 13. "ITRIGEN13,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 12. "ITRIGEN12,Controls the 32 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 11. "ITRIGEN11,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 10. "ITRIGEN10,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 9. "ITRIGEN9,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 8. "ITRIGEN8,Controls the 32 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 7. "ITRIGEN7,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 6. "ITRIGEN6,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 5. "ITRIGEN5,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 4. "ITRIGEN4,Controls the 32 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 3. "ITRIGEN3,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 2. "ITRIGEN2,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 1. "ITRIGEN1,Controls the 32 trigger inputs of DMA0" "0,1" bitfld.long 0x00 0. "ITRIGEN0,Controls the 32 trigger inputs of DMA0" "0,1" group.long 0x784++0x03 line.long 0x00 "DMA0_ITRIGEN1,Enable DMA0 triggers" bitfld.long 0x00 19. "ITRIGEN19,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 18. "ITRIGEN18,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 17. "ITRIGEN17,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 16. "ITRIGEN16,Controls the remaining 20 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 15. "ITRIGEN15,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 14. "ITRIGEN14,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 13. "ITRIGEN13,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 12. "ITRIGEN12,Controls the remaining 20 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 11. "ITRIGEN11,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 10. "ITRIGEN10,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 9. "ITRIGEN9,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 8. "ITRIGEN8,Controls the remaining 20 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 7. "ITRIGEN7,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 6. "ITRIGEN6,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 5. "ITRIGEN5,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 4. "ITRIGEN4,Controls the remaining 20 trigger inputs of DMA0" "0,1" newline bitfld.long 0x00 3. "ITRIGEN3,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 2. "ITRIGEN2,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 1. "ITRIGEN1,Controls the remaining 20 trigger inputs of DMA0" "0,1" bitfld.long 0x00 0. "ITRIGEN0,Controls the remaining 20 trigger inputs of DMA0" "0,1" wgroup.long 0x788++0x03 line.long 0x00 "DMA0_ITRIGEN0_SET,Set bits in DMA0_ITRIGEN0 register" bitfld.long 0x00 31. "SET31,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 30. "SET30,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 29. "SET29,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 28. "SET28,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 27. "SET27,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 26. "SET26,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 25. "SET25,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 24. "SET24,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 23. "SET23,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 22. "SET22,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 21. "SET21,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 20. "SET20,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 19. "SET19,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 18. "SET18,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 17. "SET17,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 16. "SET16,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 15. "SET15,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 14. "SET14,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 13. "SET13,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 12. "SET12,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 11. "SET11,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 10. "SET10,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 9. "SET9,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 8. "SET8,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 7. "SET7,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 6. "SET6,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 5. "SET5,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 4. "SET4,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 3. "SET3,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 2. "SET2,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 1. "SET1,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 0. "SET0,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" wgroup.long 0x78C++0x03 line.long 0x00 "DMA0_ITRIGEN1_SET,Set bits in DMA0_ITRIGEN1 register" bitfld.long 0x00 19. "SET19,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 18. "SET18,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 17. "SET17,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 16. "SET16,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 15. "SET15,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 14. "SET14,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 13. "SET13,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 12. "SET12,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 11. "SET11,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 10. "SET10,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 9. "SET9,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 8. "SET8,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 7. "SET7,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 6. "SET6,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 5. "SET5,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 4. "SET4,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 3. "SET3,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 2. "SET2,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 1. "SET1,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 0. "SET0,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is set to 1 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" wgroup.long 0x790++0x03 line.long 0x00 "DMA0_ITRIGEN0_CLR,Clear bits in DMA0_ITRIGEN0 register" bitfld.long 0x00 31. "CLR31,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 30. "CLR30,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 29. "CLR29,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 28. "CLR28,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 27. "CLR27,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 26. "CLR26,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 25. "CLR25,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 24. "CLR24,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 23. "CLR23,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 22. "CLR22,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 21. "CLR21,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 20. "CLR20,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 19. "CLR19,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 18. "CLR18,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 17. "CLR17,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 16. "CLR16,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 15. "CLR15,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 14. "CLR14,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 13. "CLR13,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 12. "CLR12,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 11. "CLR11,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 10. "CLR10,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 9. "CLR9,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 8. "CLR8,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 7. "CLR7,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 6. "CLR6,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 5. "CLR5,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 4. "CLR4,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" newline bitfld.long 0x00 3. "CLR3,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 2. "CLR2,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 1. "CLR1,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" bitfld.long 0x00 0. "CLR0,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN0 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN0 register" "0,1" wgroup.long 0x794++0x03 line.long 0x00 "DMA0_ITRIGEN1_CLR,Clear bits in DMA0_ITRIGEN1 register" bitfld.long 0x00 19. "CLR19,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 18. "CLR18,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 17. "CLR17,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 16. "CLR16,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 15. "CLR15,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 14. "CLR14,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 13. "CLR13,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 12. "CLR12,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 11. "CLR11,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 10. "CLR10,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 9. "CLR9,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 8. "CLR8,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 7. "CLR7,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 6. "CLR6,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 5. "CLR5,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 4. "CLR4,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" newline bitfld.long 0x00 3. "CLR3,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 2. "CLR2,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 1. "CLR1,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" bitfld.long 0x00 0. "CLR0,Write : If bit #i = 1 bit #i in DMA0_ITRIGEN1 register is reset to 0 if bit #i = 0 no change in DMA0_ITRIGEN1 register" "0,1" group.long 0x7A0++0x03 line.long 0x00 "DMA1_ITRIGEN,Enable DMA1 triggers" bitfld.long 0x00 15. "ITRIGEN15,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 14. "ITRIGEN14,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 13. "ITRIGEN13,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 12. "ITRIGEN12,Controls the 16 trigger inputs of DMA1" "0,1" newline bitfld.long 0x00 11. "ITRIGEN11,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 10. "ITRIGEN10,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 9. "ITRIGEN9,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 8. "ITRIGEN8,Controls the 16 trigger inputs of DMA1" "0,1" newline bitfld.long 0x00 7. "ITRIGEN7,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 6. "ITRIGEN6,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 5. "ITRIGEN5,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 4. "ITRIGEN4,Controls the 16 trigger inputs of DMA1" "0,1" newline bitfld.long 0x00 3. "ITRIGEN3,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 2. "ITRIGEN2,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 1. "ITRIGEN1,Controls the 16 trigger inputs of DMA1" "0,1" bitfld.long 0x00 0. "ITRIGEN0,Controls the 16 trigger inputs of DMA1" "0,1" wgroup.long 0x7A8++0x03 line.long 0x00 "DMA1_ITRIGEN_SET,Set bits in DMA1_ITRIGEN register" bitfld.long 0x00 15. "SET15,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 14. "SET14,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 13. "SET13,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 12. "SET12,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" newline bitfld.long 0x00 11. "SET11,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 10. "SET10,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 9. "SET9,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 8. "SET8,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" newline bitfld.long 0x00 7. "SET7,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 6. "SET6,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 5. "SET5,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 4. "SET4,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" newline bitfld.long 0x00 3. "SET3,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 2. "SET2,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 1. "SET1,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 0. "SET0,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is set to 1 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" wgroup.long 0x7B0++0x03 line.long 0x00 "DMA1_ITRIGEN_CLR,Clear bits in DMA1_ITRIGEN register" bitfld.long 0x00 15. "CLR15,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 14. "CLR14,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 13. "CLR13,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 12. "CLR12,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" newline bitfld.long 0x00 11. "CLR11,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 10. "CLR10,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 9. "CLR9,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 8. "CLR8,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" newline bitfld.long 0x00 7. "CLR7,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 6. "CLR6,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 5. "CLR5,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 4. "CLR4,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" newline bitfld.long 0x00 3. "CLR3,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 2. "CLR2,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 1. "CLR1,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" bitfld.long 0x00 0. "CLR0,Write : If bit #i = 1 bit #i in DMA1_ITRIGEN register is reset to 0 if bit #i = 0 no change in DMA1_ITRIGEN register" "0,1" tree.end tree "IOCON" base ad:0x40001000 group.long 0x00++0x03 line.long 0x00 "PIO0_0,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x03 line.long 0x00 "PIO0_1,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 5. (strings "2" "3" "4" "5" "6" )(list 0x0 0x4 0x8 0xC 0x10 ) group.long ($2+0x08)++0x03 line.long 0x00 "PIO0_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x1C++0x03 line.long 0x00 "PIO0_7,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x03 line.long 0x00 "PIO0_8,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x03 line.long 0x00 "PIO0_9,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 3. (strings "10" "11" "12" )(list 0x0 0x4 0x8 ) group.long ($2+0x28)++0x03 line.long 0x00 "PIO0_$1,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "13" "14" )(list 0x0 0x4 ) group.long ($2+0x34)++0x03 line.long 0x00 "PIO0_$1,I2C control for port" bitfld.long 0x00 15. "I2CFILTER,Configures I2C features for standard mode fast mode and Fast Mode Plus operation and High-Speed mode operation" "0: I2C 50 ns glitch filter enabled,1: I2C 10 ns glitch filter enabled" bitfld.long 0x00 14. "EGP,Switch between GPIO mode and I2C mode" "0: I2C_MODE,1: GPIO mode" newline bitfld.long 0x00 13. "ECS,Pull-up current source enable in I2C mode" "0: Disabled,1: Enabled" bitfld.long 0x00 12. "FILTEROFF,Controls input glitch filter" "0: Filter enabled,1: Filter disabled" newline bitfld.long 0x00 11. "SSEL,Supply Selection bit" "0: 3V3 Signaling in I2C Mode,1: 1V8 Signaling in I2C Mode" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "15" "16" )(list 0x0 0x4 ) group.long ($2+0x3C)++0x03 line.long 0x00 "PIO0_$1,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "17" "18" )(list 0x0 0x4 ) group.long ($2+0x44)++0x03 line.long 0x00 "PIO0_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 4. (strings "19" "20" "21" "22" )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x4C)++0x03 line.long 0x00 "PIO0_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "23" "24" )(list 0x0 0x4 ) group.long ($2+0x5C)++0x03 line.long 0x00 "PIO0_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "25" "26" )(list 0x0 0x4 ) group.long ($2+0x64)++0x03 line.long 0x00 "PIO0_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x6C++0x03 line.long 0x00 "PIO0_27,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 3. (strings "28" "29" "30" )(list 0x0 0x4 0x8 ) group.long ($2+0x70)++0x03 line.long 0x00 "PIO0_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x7C++0x03 line.long 0x00 "PIO0_31,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC 0x10 ) group.long ($2+0x80)++0x03 line.long 0x00 "PIO1_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x94++0x03 line.long 0x00 "PIO1_5,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98++0x03 line.long 0x00 "PIO1_6,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9C++0x03 line.long 0x00 "PIO1_7,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x03 line.long 0x00 "PIO1_8,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 2. (strings "9" "10" )(list 0x0 0x4 ) group.long ($2+0xA4)++0x03 line.long 0x00 "PIO1_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0xAC++0x03 line.long 0x00 "PIO1_11,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 3. (strings "12" "13" "14" )(list 0x0 0x4 0x8 ) group.long ($2+0xB0)++0x03 line.long 0x00 "PIO1_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 4. (strings "15" "16" "17" "18" )(list 0x0 0x4 0x8 0xC ) group.long ($2+0xBC)++0x03 line.long 0x00 "PIO1_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0xCC++0x03 line.long 0x00 "PIO1_19,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD0++0x03 line.long 0x00 "PIO1_20,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD4++0x03 line.long 0x00 "PIO1_21,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD8++0x03 line.long 0x00 "PIO1_22,Analog/Digital I/O control for port" bitfld.long 0x00 11. "ASW1,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" newline bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 2. (strings "23" "24" )(list 0x0 0x4 ) group.long ($2+0xDC)++0x03 line.long 0x00 "PIO1_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 7. (strings "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 ) group.long ($2+0xE4)++0x03 line.long 0x00 "PIO1_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x100++0x03 line.long 0x00 "PIO2_0,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x104++0x03 line.long 0x00 "PIO2_1,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x108++0x03 line.long 0x00 "PIO2_2,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10C++0x03 line.long 0x00 "PIO2_3,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "PIO2_4,Analog/Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 2. (strings "5" "6" )(list 0x00 0x04 ) group.long ($2+0x114)++0x03 line.long 0x00 "PIO2_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x11C++0x03 line.long 0x00 "PIO2_7,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "PIO2_8,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 2. (strings "9" "10" )(list 0x00 0x04 ) group.long ($2+0x124)++0x03 line.long 0x00 "PIO2_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 4. (strings "11" "12" "13" "14" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x12C)++0x03 line.long 0x00 "PIO2_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 4. (strings "15" "16" "17" "18" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x13C)++0x03 line.long 0x00 "PIO2_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "19" "20" )(list 0x00 0x04 ) group.long ($2+0x14C)++0x03 line.long 0x00 "PIO2_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "21" "22" )(list 0x00 0x04 ) group.long ($2+0x154)++0x03 line.long 0x00 "PIO2_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 2. (strings "23" "24" )(list 0x00 0x04 ) group.long ($2+0x15C)++0x03 line.long 0x00 "PIO2_$1,Analog/Digital I/O control for port" bitfld.long 0x00 10. "ASW0,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" newline bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" newline bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 7. (strings "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 ) group.long ($2+0x164)++0x03 line.long 0x00 "PIO2_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x180)++0x03 line.long 0x00 "PIO3_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C0)++0x03 line.long 0x00 "PIO3_$1,Digital I/O control for port" bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain" bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode" newline bitfld.long 0x00 7. "INVERT,Invert polarity of input signal" "0: Don't invert the signal,1: Invert the signal" bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster" newline bitfld.long 0x00 4.--5. "MODE,Mode select (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" bitfld.long 0x00 0.--3. "FUNC,Signal(function) select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end tree.end sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") tree "MPU (Memory Protection Unit)" base ad:0xE000ED90 rgroup.long 0x00++0x03 line.long 0x00 "TYPE,The MPU Type Register indicates how many regions the MPU support" hexmask.long.byte 0x00 8.--15. 1. "DREGION,Number of regions supported by the MPU" bitfld.long 0x00 0. "SEPARATE,Indicates support for separate instruction and data address maps" "0,1" group.long 0x04++0x03 line.long 0x00 "CTRL,MPU Control Register" bitfld.long 0x00 2. "PRIVDEFENA,no description available" "0: Disables the default memory map,1: Enables the default memory map as a.." bitfld.long 0x00 1. "HFNMIENA,Enables the operation of MPU during HardFault and NMI handlers" "0: MPU is disabled during HardFault and NMI..,1: The MPU is enabled during HardFault and NMI.." newline bitfld.long 0x00 0. "ENABLE,Enables the MPU" "0: The MPU is disabled,1: The MPU is enabled" group.long 0x08++0x03 line.long 0x00 "RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. "REGION,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" group.long 0x0C++0x03 line.long 0x00 "RBAR,MPU Region Base Address Register" hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region" bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable" newline bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level" bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted" group.long 0x10++0x03 line.long 0x00 "RLAR,MPU Region Limit Address Register" hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address" bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled" group.long 0x14++0x03 line.long 0x00 "RBAR_A1,MPU Region Base Address Register" hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region" bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable" newline bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level" bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted" group.long 0x18++0x03 line.long 0x00 "RLAR_A1,MPU Region Limit Address Register" hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address" bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled" group.long 0x1C++0x03 line.long 0x00 "RBAR_A2,MPU Region Base Address Register" hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region" bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable" newline bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level" bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted" group.long 0x20++0x03 line.long 0x00 "RLAR_A2,MPU Region Limit Address Register" hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address" bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled" group.long 0x24++0x03 line.long 0x00 "RBAR_A3,MPU Region Base Address Register" hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region" bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable" newline bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level" bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted" group.long 0x28++0x03 line.long 0x00 "RLAR_A3,MPU Region Limit Address Register" hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address" bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled" group.long 0x30++0x03 line.long 0x00 "MAIR0,MPU Memory Attribute Indirection Registers 0" hexmask.long.byte 0x00 24.--31. 1. "ATTR3,Memory attribute encoding for MPU regions with an AttrIndex of 3" hexmask.long.byte 0x00 16.--23. 1. "ATTR2,Memory attribute encoding for MPU regions with an AttrIndex of 2" newline hexmask.long.byte 0x00 8.--15. 1. "ATTR1,Memory attribute encoding for MPU regions with an AttrIndex of 1" hexmask.long.byte 0x00 0.--7. 1. "ATTR0,Memory attribute encoding for MPU regions with an AttrIndex of 0" group.long 0x3C++0x03 line.long 0x00 "MAIR1,MPU Memory Attribute Indirection Registers 1" hexmask.long.byte 0x00 24.--31. 1. "ATTR7,Memory attribute encoding for MPU regions with an AttrIndex of 7" hexmask.long.byte 0x00 16.--23. 1. "ATTR6,Memory attribute encoding for MPU regions with an AttrIndex of 6" newline hexmask.long.byte 0x00 8.--15. 1. "ATTR5,Memory attribute encoding for MPU regions with an AttrIndex of 5" hexmask.long.byte 0x00 0.--7. 1. "ATTR4,Memory attribute encoding for MPU regions with an AttrIndex of 4" tree.end endif tree "MRT (Multi-Rate Timer (MRT))" base ad:0x4000D000 group.long 0xF0++0x03 line.long 0x00 "MODCFG,Module Configuration" bitfld.long 0x00 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register" "0: Hardware status mode,1: MULTI_TASK_MODE" bitfld.long 0x00 4.--8. "NOB,Number Of Bits: identifies the number of timer bits in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. "NOC,Number Of Channels: identifies the number of channels in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xF4++0x03 line.long 0x00 "IDLE_CH,Idle Channel" bitfld.long 0x00 4.--7. "CHAN,Idle channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF8++0x03 line.long 0x00 "IRQ_FLAG,Global Interrupt Flag" bitfld.long 0x00 3. "GFLAG3,Monitors the interrupt flag of TIMER3 and acts similarly to channel 0" "0,1" bitfld.long 0x00 2. "GFLAG2,Monitors the interrupt flag of TIMER2 and acts similarly to channel 0" "0,1" bitfld.long 0x00 1. "GFLAG1,Monitors the interrupt flag of TIMER1 and acts similarly to channel 0" "0,1" bitfld.long 0x00 0. "GFLAG0,Monitors the interrupt flag of TIMER0" "0: No pending interrupt,1: PENDING_INTERRUPT" rgroup.long 0xFC++0x03 line.long 0x00 "ID_CODE,Multi-Rate Timer ID code" hexmask.long 0x00 0.--31. 1. "ID_CODE,Multi-Rate Timer ID code" repeat 4. (increment 0 1)(increment 0 0x10) tree "CHANNEL[$1]" group.long ($2+0x00)++0x03 line.long 0x00 "INTVAL,Time Interval Value" bitfld.long 0x00 31. "LOAD,Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n register" "0: No force load,1: Force load" hexmask.long.tbyte 0x00 0.--23. 1. "IVALUE,Time interval load value" rgroup.long ($2+0x04)++0x03 line.long 0x00 "TIMER,Timer" hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Holds the current timer value of the down-counter" group.long ($2+0x08)++0x03 line.long 0x00 "CTRL,Control" bitfld.long 0x00 1.--2. "MODE,Selects the timer mode" "0: REPEAT_INTERRUPT_MODE,1: ONE_SHOT_INTERRUPT_MODE,2: ONE_SHOT_STALL_MODE,?..." bitfld.long 0x00 0. "INTEN,Enable the TIMER n interrupt" "0: Disabled,1: Enabled" group.long ($2+0x0C)++0x03 line.long 0x00 "STAT,Status" eventfld.long 0x00 2. "INUSE,Channel-In-Use flag" "0: This timer channel is not in use,1: This timer channel is in use" rbitfld.long 0x00 1. "RUN,Indicates the state of TIMER n" "0: Idle state,1: Running" bitfld.long 0x00 0. "INTFLAG,Monitors the interrupt flag" "0: No pending interrupt,1: Pending interrupt" tree.end repeat.end tree.end tree "NVIC" base ad:0xE000E100 repeat 16. (increment 0 1) (increment 0 0x4) group.long ($2+0x00)++0x03 line.long 0x00 "ISER[$1],Interrupt Set Enable Register $1" bitfld.long 0x00 31. "SETENA31,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 30. "SETENA30,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 29. "SETENA29,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 28. "SETENA28,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 27. "SETENA27,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 26. "SETENA26,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 25. "SETENA25,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 24. "SETENA24,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 23. "SETENA23,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 22. "SETENA22,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 21. "SETENA21,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 20. "SETENA20,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 19. "SETENA19,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 18. "SETENA18,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 17. "SETENA17,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 16. "SETENA16,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 15. "SETENA15,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 14. "SETENA14,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 13. "SETENA13,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 12. "SETENA12,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 11. "SETENA11,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 10. "SETENA10,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 9. "SETENA9,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 8. "SETENA8,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 7. "SETENA7,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 6. "SETENA6,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 5. "SETENA5,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 4. "SETENA4,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 3. "SETENA3,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 2. "SETENA2,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 1. "SETENA1,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 0. "SETENA0,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." repeat.end repeat 16. (increment 0 1) (increment 0 0x4) group.long ($2+0x80)++0x03 line.long 0x00 "ICER[$1],Interrupt Clear Enable Register $1" bitfld.long 0x00 31. "CLRENA31,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 30. "CLRENA30,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 29. "CLRENA29,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 28. "CLRENA28,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 27. "CLRENA27,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 26. "CLRENA26,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 25. "CLRENA25,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 24. "CLRENA24,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 23. "CLRENA23,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 22. "CLRENA22,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 21. "CLRENA21,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 20. "CLRENA20,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 19. "CLRENA19,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 18. "CLRENA18,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 17. "CLRENA17,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 16. "CLRENA16,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 15. "CLRENA15,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 14. "CLRENA14,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 13. "CLRENA13,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 12. "CLRENA12,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 11. "CLRENA11,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 10. "CLRENA10,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 9. "CLRENA9,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 8. "CLRENA8,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 7. "CLRENA7,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 6. "CLRENA6,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 5. "CLRENA5,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 4. "CLRENA4,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 3. "CLRENA3,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 2. "CLRENA2,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 1. "CLRENA1,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 0. "CLRENA0,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.." repeat.end repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x100)++0x03 line.long 0x00 "ISPR[$1],Interrupt Set Pending Register $1" bitfld.long 0x00 31. "SETPEND31,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 30. "SETPEND30,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 29. "SETPEND29,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 28. "SETPEND28,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 27. "SETPEND27,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 26. "SETPEND26,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 25. "SETPEND25,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 24. "SETPEND24,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 23. "SETPEND23,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 22. "SETPEND22,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 21. "SETPEND21,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 20. "SETPEND20,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 19. "SETPEND19,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 18. "SETPEND18,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 17. "SETPEND17,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 16. "SETPEND16,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 15. "SETPEND15,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 14. "SETPEND14,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 13. "SETPEND13,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 12. "SETPEND12,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 11. "SETPEND11,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 10. "SETPEND10,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 9. "SETPEND9,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 8. "SETPEND8,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 7. "SETPEND7,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 6. "SETPEND6,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 5. "SETPEND5,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 4. "SETPEND4,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 3. "SETPEND3,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 2. "SETPEND2,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." newline bitfld.long 0x00 1. "SETPEND1,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." bitfld.long 0x00 0. "SETPEND0,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.." repeat.end repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x180)++0x03 line.long 0x00 "ICPR[$1],Interrupt Clear Pending Register $1" bitfld.long 0x00 31. "CLRPEND31,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 30. "CLRPEND30,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 29. "CLRPEND29,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 28. "CLRPEND28,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 27. "CLRPEND27,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 26. "CLRPEND26,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 25. "CLRPEND25,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 24. "CLRPEND24,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 23. "CLRPEND23,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 22. "CLRPEND22,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 21. "CLRPEND21,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 20. "CLRPEND20,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 19. "CLRPEND19,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 18. "CLRPEND18,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 17. "CLRPEND17,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 16. "CLRPEND16,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 15. "CLRPEND15,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 14. "CLRPEND14,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 13. "CLRPEND13,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 12. "CLRPEND12,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 11. "CLRPEND11,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 10. "CLRPEND10,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 9. "CLRPEND9,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 8. "CLRPEND8,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 7. "CLRPEND7,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 6. "CLRPEND6,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 5. "CLRPEND5,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 4. "CLRPEND4,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 3. "CLRPEND3,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 2. "CLRPEND2,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." newline bitfld.long 0x00 1. "CLRPEND1,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." bitfld.long 0x00 0. "CLRPEND0,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.." repeat.end repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x200)++0x03 line.long 0x00 "IABR[$1],Interrupt Active Bit Register $1" bitfld.long 0x00 31. "ACTIVE31,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 30. "ACTIVE30,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 29. "ACTIVE29,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 28. "ACTIVE28,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 27. "ACTIVE27,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 26. "ACTIVE26,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 25. "ACTIVE25,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 24. "ACTIVE24,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 23. "ACTIVE23,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 22. "ACTIVE22,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 21. "ACTIVE21,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 20. "ACTIVE20,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 19. "ACTIVE19,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 18. "ACTIVE18,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 17. "ACTIVE17,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 16. "ACTIVE16,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 15. "ACTIVE15,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 14. "ACTIVE14,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 13. "ACTIVE13,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 12. "ACTIVE12,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 11. "ACTIVE11,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 10. "ACTIVE10,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 9. "ACTIVE9,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 8. "ACTIVE8,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 7. "ACTIVE7,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 6. "ACTIVE6,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 5. "ACTIVE5,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 4. "ACTIVE4,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 3. "ACTIVE3,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 2. "ACTIVE2,Active state bits" "0: The interrupt is not active,1: The interrupt is active" newline bitfld.long 0x00 1. "ACTIVE1,Active state bits" "0: The interrupt is not active,1: The interrupt is active" bitfld.long 0x00 0. "ACTIVE0,Active state bits" "0: The interrupt is not active,1: The interrupt is active" repeat.end repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x280)++0x03 line.long 0x00 "ITNS[$1],Interrupt Target Non-secure Register $1" bitfld.long 0x00 31. "INTS31,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 30. "INTS30,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 29. "INTS29,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 28. "INTS28,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 27. "INTS27,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 26. "INTS26,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 25. "INTS25,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 24. "INTS24,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 23. "INTS23,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 22. "INTS22,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 21. "INTS21,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 20. "INTS20,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 19. "INTS19,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 18. "INTS18,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 17. "INTS17,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 16. "INTS16,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 15. "INTS15,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 14. "INTS14,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 13. "INTS13,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 12. "INTS12,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 11. "INTS11,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 10. "INTS10,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 9. "INTS9,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 8. "INTS8,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 7. "INTS7,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 6. "INTS6,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 5. "INTS5,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 4. "INTS4,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 3. "INTS3,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 2. "INTS2,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" newline bitfld.long 0x00 1. "INTS1,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" bitfld.long 0x00 0. "INTS0,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state" repeat.end repeat 120. (increment 0 1) (increment 0 0x04) group.long ($2+0x300)++0x03 line.long 0x00 "IPR[$1],Interrupt Priority Register $1" hexmask.long.byte 0x00 24.--31. 1. "PRI_3,no description available" hexmask.long.byte 0x00 16.--23. 1. "PRI_2,no description available" newline hexmask.long.byte 0x00 8.--15. 1. "PRI_1,no description available" hexmask.long.byte 0x00 0.--7. 1. "PRI_0,no description available" repeat.end wgroup.long 0xE00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger in the range 0-479" tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "OPAMP" repeat 3. (list 0. 1. 2.) (list ad:0x400B4000 ad:0x400B8000 ad:0x400BB000) tree "OPAMP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "VERID,Version ID Register" hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number" hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number" hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number" rgroup.long 0x04++0x03 line.long 0x00 "PARAM,Parameter Register" bitfld.long 0x00 0. "PGA_FUNCTION,PGA Function Option" "0: Core amplifier is enabled,1: PGA function is enabled" group.long 0x08++0x03 line.long 0x00 "OPAMP_CTR,OPAMP control register" bitfld.long 0x00 24.--26. "NGAIN,Negative PGA selection" "0: NGAIN_0,1: Inverting gain application -1X,2: Inverting gain application -2X,3: Inverting gain application -4X,4: Inverting gain application -8X,5: Inverting gain application -16X,6: Inverting gain application -33X,7: Inverting gain application -64X" bitfld.long 0x00 20.--22. "PGAIN,Positive PGA Selection" "?,1: Inverting gain application 2X,2: Inverting gain application 3X,3: Inverting gain application 5X,4: Inverting gain application 9X,5: Inverting gain application 17X,6: Inverting gain application 34X,7: Inverting gain application 65X" bitfld.long 0x00 17.--18. "PREF,Positive Reference Voltage Selection" "0: Select vrefh3,1: Select vrefh0,2: Select vrefh1,?..." newline bitfld.long 0x00 16. "ADCSW,ADC Channel Switch" "0,1" bitfld.long 0x00 4.--5. "INTREF,Internal Reference Voltage Selection" "0: Select vdda/2,1: Select vdda_3v,2: Select vssa_3v,3: Not allowed" bitfld.long 0x00 2.--3. "BIASC,Bias Current Trim Selection" "0: Default,1: Increase current,2: Decrease current,3: Further decrease current" newline bitfld.long 0x00 1. "MODE,Mode Selection" "0: Low noise mode,1: High speed mode" bitfld.long 0x00 0. "EN,OPAMP Enable" "0: OPAMP is disabled,1: OPAMP is enabled" tree.end repeat.end tree.end endif tree "OSTIMER (Synchronous OS/Event timer with Wakeup Timer)" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") base ad:0x4002D000 rgroup.long 0x00++0x03 line.long 0x00 "EVTIMERL,EVTIMER Low Register" hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER" rgroup.long 0x00++0x03 line.long 0x00 "EVTIMERL,EVTIMER Low Register" hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER" group.long 0x04++0x03 line.long 0x00 "EVTIMERH,EVTIMER High Register" hexmask.long.word 0x00 0.--9. 1. "EVTIMER_COUNT_VALUE,A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER" rgroup.long 0x08++0x03 line.long 0x00 "CAPTURE_L,Capture Low Register" hexmask.long 0x00 0.--31. 1. "CAPTURE_VALUE,A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function __SEV() )" group.long 0x0C++0x03 line.long 0x00 "CAPTURE_H,Capture High Register" hexmask.long.word 0x00 0.--9. 1. "CAPTURE_VALUE,A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function __SEV() )" group.long 0x10++0x03 line.long 0x00 "MATCH_L,Match Low Register" hexmask.long 0x00 0.--31. 1. "MATCH_VALUE,The value written to the MATCH (L/H) register pair is compared against the central EVTIMER" group.long 0x14++0x03 line.long 0x00 "MATCH_H,Match High Register" hexmask.long.word 0x00 0.--9. 1. "MATCH_VALUE,The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER" group.long 0x1C++0x03 line.long 0x00 "OSEVENT_CTRL,OS_EVENT TIMER Control Register" rbitfld.long 0x00 2. "MATCH_WR_RDY,This bit will be low when it is safe to write to reload the Match Registers" "0,1" bitfld.long 0x00 1. "OSTIMER_INTENA,When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set" "0,1" bitfld.long 0x00 0. "OSTIMER_INTRFLAG,This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair" "0,1" endif sif cpuis("LPC5534*")||cpuis("LPC5536*") base ad:0x4002D000 rgroup.long 0x00++0x03 line.long 0x00 "EVTIMERL,EVTIMER Low Register" hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,EVTimer Count value" rgroup.long 0x04++0x03 line.long 0x00 "EVTIMERH,EVTIMER High Register" hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,EVTimer Count value" rgroup.long 0x08++0x03 line.long 0x00 "CAPTURE_L,Local Capture Low Register for CPU" hexmask.long 0x00 0.--31. 1. "CAPTURE_VALUE,EVTimer Capture value" rgroup.long 0x0C++0x03 line.long 0x00 "CAPTURE_H,Local Capture High Register for CPU" hexmask.long 0x00 0.--31. 1. "CAPTURE_VALUE,EVTimer Capture value" group.long 0x10++0x03 line.long 0x00 "MATCH_L,Local Match Low Register for CPU" hexmask.long 0x00 0.--31. 1. "MATCH_VALUE,EVTimer Match value" group.long 0x14++0x03 line.long 0x00 "MATCH_H,Local Match High Register for CPU" hexmask.long 0x00 0.--31. 1. "MATCH_VALUE,EVTimer Match value" group.long 0x1C++0x03 line.long 0x00 "OSEVENT_CTRL,OS Event Timer Control Register for CPU" bitfld.long 0x00 2. "MATCH_WR_RDY,EVTimer Match Write Ready" "0,1" bitfld.long 0x00 1. "OSTIMER_INTENA,Interrupt/Wake-up Request" "0: Interrupt/wake-up requests due to the..,1: An interrupt/wake-up request to the domain.." bitfld.long 0x00 0. "OSTIMER_INTRFLAG,Interrupt Flag" "0,1" endif tree.end tree "PINT (Pin Interrupts and Pattern Match)" tree "PINT" base ad:0x40004000 group.long 0x00++0x03 line.long 0x00 "ISEL,Pin Interrupt Mode" hexmask.long.byte 0x00 0.--7. 1. "PMODE,Interrupt mode" group.long 0x04++0x03 line.long 0x00 "IENR,Pin Interrupt Level or Rising Edge Interrupt Enable" hexmask.long.byte 0x00 0.--7. 1. "ENRL,Enable Interrupt" wgroup.long 0x08++0x03 line.long 0x00 "SIENR,Pin Interrupt Level or Rising Edge Interrupt Set" hexmask.long.byte 0x00 0.--7. 1. "SETENRL,Set bits in the IENR" group.long 0x0C++0x03 line.long 0x00 "CIENR,Pin Interrupt Level (Rising Edge Interrupt) Clear" hexmask.long.byte 0x00 0.--7. 1. "CENRL,Clear bits in the IENR" group.long 0x10++0x03 line.long 0x00 "IENF,Pin Interrupt Active Level or Falling Edge Interrupt Enable" hexmask.long.byte 0x00 0.--7. 1. "ENAF,Enable Interrupt" wgroup.long 0x14++0x03 line.long 0x00 "SIENF,Pin Interrupt Active Level or Falling Edge Interrupt Set" hexmask.long.byte 0x00 0.--7. 1. "SETENAF,Set bits in the IENF" wgroup.long 0x18++0x03 line.long 0x00 "CIENF,Pin Interrupt Active Level or Falling Edge Interrupt Clear" hexmask.long.byte 0x00 0.--7. 1. "CENAF,Clear bits in the IENF" group.long 0x1C++0x03 line.long 0x00 "RISE,Pin Interrupt Rising Edge" hexmask.long.byte 0x00 0.--7. 1. "RDET,Rising edge detect" group.long 0x20++0x03 line.long 0x00 "FALL,Pin Interrupt Falling Edge" hexmask.long.byte 0x00 0.--7. 1. "FDET,Falling edge detect" group.long 0x24++0x03 line.long 0x00 "IST,Pin Interrupt Status" hexmask.long.byte 0x00 0.--7. 1. "PSTAT,Pin interrupt status" group.long 0x28++0x03 line.long 0x00 "PMCTRL,Pattern Match Interrupt Control" hexmask.long.byte 0x00 24.--31. 1. "PMAT,Pattern Matches" bitfld.long 0x00 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true" "0: Disabled- RXEV output to the CPU is disabled,1: Enabled- RXEV output to the CPU is enabled" newline bitfld.long 0x00 0. "SEL_PMATCH,Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function" "0: Pin interrupt- interrupts are driven in..,1: Pattern match- interrupts are driven in.." group.long 0x2C++0x03 line.long 0x00 "PMSRC,Pattern Match Interrupt Bit-Slice Source" bitfld.long 0x00 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" newline bitfld.long 0x00 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" newline bitfld.long 0x00 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" newline bitfld.long 0x00 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" group.long 0x30++0x03 line.long 0x00 "PMCFG,Pattern Match Interrupt Bit Slice Configuration" bitfld.long 0x00 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint" "0: No effect,1: Endpoint" bitfld.long 0x00 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint" "0: No effect,1: Endpoint" newline bitfld.long 0x00 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint" "0: No effect,1: Endpoint" bitfld.long 0x00 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint" "0: No effect,1: Endpoint" newline bitfld.long 0x00 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint" "0: No effect,1: Endpoint" bitfld.long 0x00 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint" "0: No effect,1: Endpoint" newline bitfld.long 0x00 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint" "0: No effect,1: Endpoint" tree.end tree "SECPINT" base ad:0x40005000 group.long 0x00++0x03 line.long 0x00 "ISEL,Pin Interrupt Mode" hexmask.long.byte 0x00 0.--7. 1. "PMODE,Interrupt mode" group.long 0x04++0x03 line.long 0x00 "IENR,Pin Interrupt Level or Rising Edge Interrupt Enable" hexmask.long.byte 0x00 0.--7. 1. "ENRL,Enable Interrupt" wgroup.long 0x08++0x03 line.long 0x00 "SIENR,Pin Interrupt Level or Rising Edge Interrupt Set" hexmask.long.byte 0x00 0.--7. 1. "SETENRL,Set bits in the IENR" group.long 0x0C++0x03 line.long 0x00 "CIENR,Pin Interrupt Level (Rising Edge Interrupt) Clear" hexmask.long.byte 0x00 0.--7. 1. "CENRL,Clear bits in the IENR" group.long 0x10++0x03 line.long 0x00 "IENF,Pin Interrupt Active Level or Falling Edge Interrupt Enable" hexmask.long.byte 0x00 0.--7. 1. "ENAF,Enable Interrupt" wgroup.long 0x14++0x03 line.long 0x00 "SIENF,Pin Interrupt Active Level or Falling Edge Interrupt Set" hexmask.long.byte 0x00 0.--7. 1. "SETENAF,Set bits in the IENF" wgroup.long 0x18++0x03 line.long 0x00 "CIENF,Pin Interrupt Active Level or Falling Edge Interrupt Clear" hexmask.long.byte 0x00 0.--7. 1. "CENAF,Clear bits in the IENF" group.long 0x1C++0x03 line.long 0x00 "RISE,Pin Interrupt Rising Edge" hexmask.long.byte 0x00 0.--7. 1. "RDET,Rising edge detect" group.long 0x20++0x03 line.long 0x00 "FALL,Pin Interrupt Falling Edge" hexmask.long.byte 0x00 0.--7. 1. "FDET,Falling edge detect" group.long 0x24++0x03 line.long 0x00 "IST,Pin Interrupt Status" hexmask.long.byte 0x00 0.--7. 1. "PSTAT,Pin interrupt status" group.long 0x28++0x03 line.long 0x00 "PMCTRL,Pattern Match Interrupt Control" hexmask.long.byte 0x00 24.--31. 1. "PMAT,Pattern Matches" bitfld.long 0x00 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true" "0: Disabled- RXEV output to the CPU is disabled,1: Enabled- RXEV output to the CPU is enabled" newline bitfld.long 0x00 0. "SEL_PMATCH,Specifies whether the pin interrupts are controlled by the pin interrupt function or by the pattern match function" "0: Pin interrupt- interrupts are driven in..,1: Pattern match- interrupts are driven in.." group.long 0x2C++0x03 line.long 0x00 "PMSRC,Pattern Match Interrupt Bit-Slice Source" bitfld.long 0x00 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" newline bitfld.long 0x00 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" newline bitfld.long 0x00 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" newline bitfld.long 0x00 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" bitfld.long 0x00 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7" group.long 0x30++0x03 line.long 0x00 "PMCFG,Pattern Match Interrupt Bit Slice Configuration" bitfld.long 0x00 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" bitfld.long 0x00 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0" "0: CONSTANT_HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event" newline bitfld.long 0x00 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint" "0: No effect,1: Endpoint" bitfld.long 0x00 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint" "0: No effect,1: Endpoint" newline bitfld.long 0x00 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint" "0: No effect,1: Endpoint" bitfld.long 0x00 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint" "0: No effect,1: Endpoint" newline bitfld.long 0x00 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint" "0: No effect,1: Endpoint" bitfld.long 0x00 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint" "0: No effect,1: Endpoint" newline bitfld.long 0x00 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint" "0: No effect,1: Endpoint" tree.end tree.end sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "PLU (LPC80X Programmable Logic Unit (PLU))" base ad:0x4003D000 repeat 26. (increment 0 1) (increment 0 0x04) group.long ($2+0x800)++0x03 line.long 0x00 "LUT_TRUTH[$1],Specifies the Truth Table contents for LUTLUTn $1" hexmask.long 0x00 0.--31. 1. "LUTn_TRUTH,Specifies the Truth Table contents for LUT0" repeat.end group.long 0x900++0x03 line.long 0x00 "OUTPUTS,Provides the current state of the 8 designated PLU Outputs" hexmask.long.byte 0x00 0.--7. 1. "OUTPUT_STATE,Provides the current state of the 8 designated PLU Outputs" group.long 0x904++0x03 line.long 0x00 "WAKEINT_CTRL,Wakeup interrupt control for PLU" eventfld.long 0x00 13. "INTR_CLEAR,Write to clear wakeint_latched" "0,1" bitfld.long 0x00 12. "LATCH_ENABLE,latch the interrupt then can be cleared with next bit INTR_CLEAR" "0,1" bitfld.long 0x00 10.--11. "FILTER_CLKSEL,hclk is divided by 2**filter_clksel" "0: Selects the 1 MHz low-power oscillator as the..,1: Selects the 12 Mhz FRO as the filter clock,2: Selects a third filter clock source if provided,?..." newline bitfld.long 0x00 8.--9. "FILTER_MODE,control input of the PLU add filtering for glitch" "0: Bypass mode,1: Filter 1 clock period,2: Filter 2 clock period,3: Filter 3 clock period" hexmask.long.byte 0x00 0.--7. 1. "MASK,Interrupt mask (which of the 8 PLU Outputs contribute to interrupt)" repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0xC00)++0x03 line.long 0x00 "OUTPUT_MUX[$1],Selects the source to be connected to PLU Output OUTPUT_n $1" bitfld.long 0x00 0.--4. "OUTPUTn,Selects the source to be connected to PLU Output 0" "0: The PLU output 0,1: The PLU output 1,2: The PLU output 2,3: The PLU output 3,4: The PLU output 4,5: The PLU output 5,6: The PLU output 6,7: The PLU output 7,8: The PLU output 8,9: The PLU output 9,10: The PLU output 10,11: The PLU output 11,12: The PLU output 12,13: The PLU output 13,14: The PLU output 14,15: The PLU output 15,16: The PLU output 16,17: The PLU output 17,18: The PLU output 18,19: The PLU output 19,20: The PLU output 20,21: The PLU output 21,22: The PLU output 22,23: The PLU output 23,24: The PLU output 24,25: The PLU output 25,26: state(0),27: state(1),28: state(2),29: state(3),?..." repeat.end repeat 26. (increment 0 1)(increment 0 0x20) tree "LUT[$1]" group.long ($2+0x00)++0x03 line.long 0x00 "LUT_INP_MUX0,LUTn input x MUX" bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..." group.long ($2+0x04)++0x03 line.long 0x00 "LUT_INP_MUX1,LUTn input x MUX" bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..." group.long ($2+0x08)++0x03 line.long 0x00 "LUT_INP_MUX2,LUTn input x MUX" bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..." group.long ($2+0x0C)++0x03 line.long 0x00 "LUT_INP_MUX3,LUTn input x MUX" bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..." group.long ($2+0x10)++0x03 line.long 0x00 "LUT_INP_MUX4,LUTn input x MUX" bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..." tree.end repeat.end tree.end endif tree "PMC" base ad:0x40020000 group.long 0x00++0x03 line.long 0x00 "CTRL,Power Management Control [Reset by: PoR Pin Reset Software Reset and BoDs reset]" bitfld.long 0x00 5.--6. "DEEPSLEEPCORESUPPLY,Select Core Logic supply source during DEEP-SLEEP low power mode" "0: LDO CORE in Low Power Mode,1: LDO CORE in High Power Mode,2: DCDC Converter,?..." newline bitfld.long 0x00 4. "SELCORESUPPLYWK,Select Core Logic supply source when waking up from DEEP-SLEEP and POWER-DOWN low power modes" "0: Core Logic is supplied by DCDC Converter,1: Core Logic is supplied by LDO CORE.." newline bitfld.long 0x00 3. "SELMEMSUPPLY,Select Memories supply source in DEEP-SLEEP low power mode: Note: in POWER-DOWN and DEEP-POWER-DOWN memories are always supplied by LDO_MEM" "0: Memories are supplied by LDO_MEM in..,1: Memories are supplied by DCDC/LDO_CORE in.." newline bitfld.long 0x00 2. "SELCLOCK,Select the Power Management Controller (PMC) functional clock" "0: 1 MHz Free Running Oscillator,1: 12 MHz Free Running Oscillator" newline bitfld.long 0x00 0.--1. "LPMODE,Power Mode Control" "0: ACTIVE power mode,1: DEEP-SLEEP low power mode,2: POWER-DOWN low power mode,3: DEEP-POWER-DOWN low power mode" group.long 0x04++0x03 line.long 0x00 "STATUS,Power Management Controller FSM (Finite State Machines) status" rbitfld.long 0x00 28.--31. "WAFERTESTDONEVECT,Indicates cuurent status of wafer test level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 18.--19. "BOOTMODE,Latest IC Boot cause" "0: Latest IC boot was a Full power cycle boot..,1: Latest IC boot was from DEEP SLEEP low power..,2: Latest IC boot was from POWER DOWN low power..,3: Latest IC boot was from DEEP POWER DOWN low.." newline rbitfld.long 0x00 15.--17. "FSMDPWD,DEEP POWER DOWN Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11.--14. "FSMPWDN,POWER DOWN Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 7.--10. "FSMDSLP,DEEP SLEEP Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 3.--6. "FSMPWUP,POWER UP Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--2. "FSMMAIN,Power Management Controller Main Finite State Machine (FSM) status" "0: POWER UP,1: ACTIVE,2: POWER DOWN,3: DEEP SLEEP,?,?,6: DEEP POWER DOWN,7: IC Structural TEST Mode" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Power Management Controller FSM (Finite State Machines) status" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 23. "FSMLDOCOREEXPTMRENABLE,Indicates the status of the LDO CORE Exponential Timer (enabled or disabled) as driven by the Hardware Finite State Machines (FSM)" "0,1" newline bitfld.long 0x00 22. "FSMLDOCORELPENABLE,Indicates the power status of the LDO CORE Low Power Mode (enabled or disabled) as driven by the Hardware Finite State Machines (FSM)" "0: LDO CORE Low Power Mode is currently disabled..,1: LDO CORE Low Power Mode is currently enabled.." newline bitfld.long 0x00 21. "FSMLDOCOREHPENABLE,Indicates the power status of the LDO CORE High Power Mode (enabled or disabled) as driven by the Hardware Finite State Machines (FSM)" "0: LDO CORE High Power Mode is currently..,1: LDO CORE High Power Mode is currently enabled.." newline bitfld.long 0x00 20. "FSMDCDCENABLE,Indicates the power status of the DCDC (enabled or disabled) as driven by the Hardware Finite State Machines (FSM)" "0: DCDC is currently disabled by the Hardware..,1: DCDC is currently enabled by the Hardware.." newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18.--19. "BOOTMODE,Latest IC Boot cause" "0: Latest IC boot was a Full power cycle boot..,1: Latest IC boot was from DEEP SLEEP low power..,2: Latest IC boot was from POWER DOWN low power..,3: Latest IC boot was from DEEP POWER DOWN low.." endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 18.--19. "BOOTMODE,Latest IC Boot cause" "0: Latest IC boot was a Full power cycle boot..,1: Latest IC boot was from DEEP-SLEEP low power..,2: Latest IC boot was from POWER-DOWN low power..,3: Latest IC boot was from DEEP-POWER-DOWN low.." endif endif group.long 0x08++0x03 line.long 0x00 "RESETCTRL,Reset Control [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 30.--31. "BODCORERESETENA_SECURE_DP,BOD Core reset enable" "?,1: Any other value than b10 BOD Core reset is..,2: BOD Core reset is disable,?..." newline bitfld.long 0x00 28.--29. "BODVBATRESETENA_SECURE_DP,BOD VBAT reset enable" "?,1: Any other value than b10 BOD VBAT reset is..,2: BOD VBAT reset is disable,?..." newline bitfld.long 0x00 6.--7. "BODCORERESETENA_SECURE,BOD Core reset enable" "?,1: Any other value than b10 BOD Core reset is..,2: BOD Core reset is disable,?..." newline bitfld.long 0x00 4.--5. "BODVBATRESETENA_SECURE,BOD VBAT reset enable" "?,1: Any other value than b10 BOD VBAT reset is..,2: BOD VBAT reset is disable,?..." newline endif bitfld.long 0x00 3. "SWRRESETENABLE,Software reset enable" "0: Software reset is disable,1: Software reset is enable" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 2. "BODCORERESETENABLE,BOD CORE reset enable" "0: BOD CORE reset is disable,1: BOD CORE reset is enable" newline bitfld.long 0x00 1. "BODVBATRESETENABLE,BOD VBAT reset enable" "0: BOD VBAT reset is disable,1: BOD VBAT reset is enable" newline endif bitfld.long 0x00 0. "DPDWAKEUPRESETENABLE,Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer)" "0: Reset event from DEEP POWER DOWN mode is..,1: Reset event from DEEP POWER DOWN mode is enable" group.long 0x08++0x03 line.long 0x00 "RESETCTRL,Reset Control" bitfld.long 0x00 30.--31. "BODCORERESETENA_SECURE_DP,BOD_CORE reset enable" "?,1: And any other value than b10,2: BOD_CORE reset is disabled,?..." newline bitfld.long 0x00 28.--29. "BODVDDMAINRESETENA_SECURE_DP,BOD_VDDMAIN reset enabled" "?,1: And any other value than b10,2: BOD_VDDMAIN reset is disabled,?..." newline bitfld.long 0x00 6.--7. "BODCORERESETENA_SECURE,BOD_CORE reset enabled" "?,1: And any other value than b10,2: BODCORE reset is disabled,?..." newline bitfld.long 0x00 4.--5. "BODVDDMAINRESETENA_SECURE,BOD_VDDMAIN reset enabled" "?,1: And any other value than b10,2: BOD_VDDMAIN reset is disabled,?..." newline bitfld.long 0x00 3. "SWRRESETENABLE,Software reset enable" "0: Software reset is disabled,1: Software reset is enabled" newline bitfld.long 0x00 0. "DPDWAKEUPRESETENABLE,Wake-up from DEEP-POWER-DOWN reset event (either from wake up I/O or RTC or OS Event Timer)" "0: Reset event from DEEP-POWER-DOWN mode is..,1: Reset event from DEEP-POWER-DOWN mode is.." group.long 0x0C++0x03 line.long 0x00 "RESETCAUSE,Reset Cause" bitfld.long 0x00 10.--12. "DPD_EVENTS_ORDER,In DEEP-POWER-DOWN mode indicates which reset event occured first between DPDRESET_WAKEUPIO DPDRESET_RTC and DPDRESET_OSTIMER" "0: No event,1: WAKEUPIO,2: RTC,3: Both WAKEUPIO and RTC events occured at the..,4: OSTIMER,5: Both WAKEUPIO and OSTIMER events occured at..,6: Both RTC and OSTIMER events occured at the..,7: WAKEUPIO RTC and OSTIMER events occured at.." newline bitfld.long 0x00 9. "CDOGRESET," "0,1" newline bitfld.long 0x00 8. "DPDRESET_OSTIMER," "0,1" newline bitfld.long 0x00 7. "DPDRESET_RTC," "0,1" newline bitfld.long 0x00 6. "DPDRESET_WAKEUPIO," "0,1" newline bitfld.long 0x00 5. "SWRRESET," "0,1" newline bitfld.long 0x00 4. "WDTRESET," "0,1" newline bitfld.long 0x00 3. "SYSTEMRESET," "0,1" newline bitfld.long 0x00 2. "BODRESET," "0,1" newline bitfld.long 0x00 1. "PADRESET," "0,1" newline eventfld.long 0x00 0. "POR," "0,1" group.long 0x10++0x03 line.long 0x00 "DCDC0,DCDC (first) control" bitfld.long 0x00 23.--26. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 22. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1" newline bitfld.long 0x00 21. "SLICINGENABLE,Enable staggered switching of power switches" "0,1" newline bitfld.long 0x00 17.--20. "VOUT,Set output regulation voltage" "0: V_DCDC_0P950,1: V_DCDC_0P975,2: V_DCDC_1P000,3: V_DCDC_1P025,4: V_DCDC_1P050,5: V_DCDC_1P075,6: V_DCDC_1P100,7: V_DCDC_1P125,8: V_DCDC_1P150,9: V_DCDC_1P175,10: V_DCDC_1P200,?..." newline bitfld.long 0x00 16. "DISABLEISENSE,Disable Current sensing" "0,1" newline bitfld.long 0x00 11.--15. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1" newline bitfld.long 0x00 8.--9. "ISEL,Alter Internal biasing currents" "0,1,2,3" newline bitfld.long 0x00 6.--7. "ICOMP,Select the type of ZCD comparator" "0,1,2,3" newline bitfld.long 0x00 0.--5. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DCDC0,DCDC (first) control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 23.--26. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 21.--26. "CONFIG1,DCDC configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 22. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1" newline bitfld.long 0x00 21. "SLICINGENABLE,Enable staggered switching of power switches" "0,1" newline endif bitfld.long 0x00 17.--20. "VOUT,Set output regulation voltage" "0: V_DCDC_0P950,1: V_DCDC_0P975,2: V_DCDC_1P000,3: V_DCDC_1P025,4: V_DCDC_1P050,5: V_DCDC_1P075,6: V_DCDC_1P100,7: V_DCDC_1P125,8: V_DCDC_1P150,9: V_DCDC_1P175,10: V_DCDC_1P200,?..." newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") hexmask.long.tbyte 0x00 0.--16. 1. "CONFIG0,DCDC configuration" endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 16. "DISABLEISENSE,Disable Current sensing" "0,1" newline bitfld.long 0x00 11.--15. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1" newline bitfld.long 0x00 8.--9. "ISEL,Alter Internal biasing currents" "0,1,2,3" newline bitfld.long 0x00 6.--7. "ICOMP,Select the type of ZCD comparator" "0,1,2,3" newline bitfld.long 0x00 0.--5. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.long 0x14++0x03 line.long 0x00 "DCDC1,DCDC (second) control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") hexmask.long 0x00 0.--31. 1. "CONFIG2,DCDC configuration" endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1" newline bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1" newline bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1" newline bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1" newline bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3" newline bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1" newline bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x1C++0x03 line.long 0x00 "LDOPMU,Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 25. "BOOST_ENA_PWD,Control the LDO AO boost mode in the different low power modes (DEEP SLEEP POWERDOWN and DEEP POWER DOWN)" "0: LDO AO Boost Mode is disable,1: LDO AO Boost Mode is enable" newline bitfld.long 0x00 24. "BOOST_ENA,Control the LDO AO boost mode in ACTIVE mode" "0: LDO AO Boost Mode is disable,1: LDO AO Boost Mode is enable" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 20. "BLEED,Controls LDOMEM bleed current" "0: Bleed current is disable,1: Bleed current is enable" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 15.--19. "VADJ_BOOST_PWD,Sets the Always-On domain LDO Boost output level in all power down modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline endif bitfld.long 0x00 10.--14. "VADJ_BOOST,Sets the Always-On domain LDO Boost output level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 5.--9. "VADJ_PWD,Sets the Always-On domain LDO output level in all power down modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline endif bitfld.long 0x00 0.--4. "VADJ,Sets the Always-On domain LDO output level" "0: V_1P220,1: V_0P700,2: 0.725 V,3: V_0P750,4: 0.775 V,5: V_0P800,6: 0.825 V,7: V_0P850,8: 0.875 V,9: V_0P900,10: V_0P960,11: V_0P970,12: V_0P980,13: V_0P990,14: V_1P000,15: V_1P010,16: V_1P020,17: V_1P030,18: V_1P040,19: V_1P050,20: V_1P060,21: V_1P070,22: V_1P080,23: V_1P090,24: V_1P100,25: V_1P110,26: V_1P120,27: V_1P130,28: V_1P140,29: V_1P150,30: V_1P160,31: V_1P220_1" group.long 0x20++0x03 line.long 0x00 "LDOMEM,Memories LDO control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" bitfld.long 0x00 15.--19. "VADJ_BOOST_PWD,Sets the Memories LDO Boost output level in all power down modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. "VADJ_BOOST,Sets the Memories LDO Boost output level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. "VADJ_PWD,Sets the Memories LDO output level in all power down modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "VADJ,Sets the Memories LDO output level" "0: V_1P220,1: V_0P700,2: 0.725 V,3: V_0P750,4: 0.775 V,5: V_0P800,6: 0.825 V,7: V_0P850,8: 0.875 V,9: V_0P900,10: V_0P960,11: V_0P970,12: V_0P980,13: V_0P990,14: V_1P000,15: V_1P010,16: V_1P020,17: V_1P030,18: V_1P040,19: V_1P050,20: V_1P060,21: V_1P070,22: V_1P080,23: V_1P090,24: V_1P100,25: V_1P110,26: V_1P120,27: V_1P130,28: V_1P140,29: V_1P150,30: V_1P160,31: V_1P220_1" group.long 0x24++0x03 line.long 0x00 "LDOCORE0,LDO CORE (first) control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" hexmask.long.byte 0x00 24.--30. 1. "REGREFTRIM,High Power regulation point select" newline bitfld.long 0x00 17.--18. "LPREGREFSEL,Low Power regulation point select" "0: V_0P900,1: V_0P850,2: V_0P800,3: V_0P750" group.long 0x28++0x03 line.long 0x00 "LDOFLASHNV,Flash High Voltage LDO control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" bitfld.long 0x00 0.--2. "VADJ,Sets the LDO output level" "0: 1.650 V,1: 1.700 V,2: 1.750 V,3: 1.800 V,4: 1.850 V,5: 1.900 V,6: 1.950 V,7: V_2P000" group.long 0x2C++0x03 line.long 0x00 "LDOEFUSEPROG,eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" bitfld.long 0x00 0.--2. "VADJ,Sets the LDO output level" "0: 1.650 V,1: 1.700 V,2: 1.750 V,3: 1.800 V,4: 1.850 V,5: 1.900 V,6: 1.950 V,7: V_2P000" group.long 0x30++0x03 line.long 0x00 "BODVDDMAIN,VDDMAIN Brown Out Dectector control" bitfld.long 0x00 5.--6. "HYST,BoD Hysteresis control" "0: HYST_25MV,1: HYST_50MV,2: HYST_75MV,3: HYST_100MV" newline bitfld.long 0x00 0.--4. "TRIGLVL,BoD trigger level" "0: 1.00 V,1: 1.10 V,2: 1.20 V,3: 1.30 V,4: 1.40 V,5: 1.50 V,6: 1.60 V,7: 1.65 V,8: 1.70 V,9: 1.75 V,10: 1.80 V,11: 1.90 V,12: 2.00 V,13: 2.10 V,14: 2.20 V,15: 2.30 V,16: 2.40 V,17: 2.50 V,18: 2.60 V,19: 2.70 V,20: 2.80 V,21: 2.90 V,22: 3.00 V,23: 3.10 V,24: 3.20 V,25: V_3P30_2,26: V_3P30_3,27: V_3P30_4,28: V_3P30_5,29: V_3P30_6,30: V_3P30_7,31: V_3P30_8" group.long 0x30++0x03 line.long 0x00 "BODVBAT,VBAT Brown Out Dectector (BoD) control register [Reset by: PoR Pin Reset Software Reset]" bitfld.long 0x00 5.--6. "HYST,BoD Hysteresis control" "0: HYST_25MV,1: HYST_50MV,2: HYST_75MV,3: HYST_100MV" newline bitfld.long 0x00 0.--4. "TRIGLVL,BoD trigger level" "0: 1.00 V,1: 1.10 V,2: 1.20 V,3: 1.30 V,4: 1.40 V,5: 1.50 V,6: 1.60 V,7: 1.65 V,8: 1.70 V,9: 1.75 V,10: 1.80 V,11: 1.90 V,12: 2.00 V,13: 2.10 V,14: 2.20 V,15: 2.30 V,16: 2.40 V,17: 2.50 V,18: 2.60 V,19: 2.70 V,20: 2.806 V,21: 2.90 V,22: 3.00 V,23: 3.10 V,24: 3.20 V,25: V_3P30_2,26: V_3P30_3,27: V_3P30_4,28: V_3P30_5,29: V_3P30_6,30: V_3P30_7,31: V_3P30_8" group.long 0x38++0x03 line.long 0x00 "BODCORE,Digital Core logic Brown Out Dectector control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" bitfld.long 0x00 4.--5. "HYST,BOD_CORE Hysteresis control" "0: HYST_25MV,1: HYST_50MV,2: HYST_75MV,3: HYST_100MV" newline bitfld.long 0x00 0.--2. "TRIGLVL,BoD trigger level" "0: 0.60 V,1: 0.65 V,2: 0.70 V,3: 0.75 V,4: 0.80 V,5: 0.85 V,6: 0.90 V,7: 0.95 V" group.long 0x40++0x03 line.long 0x00 "REFFASTWKUP,Analog References fast wake-up Control register [Reset by: PoR]" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 1. "HWWKUP,Analog References fast wake-up in case of Hardware Pin reset" "0: Analog References fast wake-up feature is..,1: Analog References fast wake-up feature is.." newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 1. "HWWKUP,Analog References fast wake-up in case of Hardware Pin reset" "0: Analog References fast wake-up feature is..,1: Analog References fast wake-up feature is.." newline bitfld.long 0x00 0. "LPWKUP,Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP POWER DOWN and DEEP POWER DOWN)" "0: Analog References fast wake-up feature is..,1: Analog References fast wake-up feature is.." endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0. "LPWKUP,Analog References fast wake-up in case of wake-up from a low power mode (DEEP-SLEEP POWER-DOWN and DEEP-POWER-DOWN)" "0: Analog References fast wake-up feature is..,1: Analog References fast wake-up feature is.." endif group.long 0x4C++0x03 line.long 0x00 "XTAL32K,32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR Brown Out Detectors Reset]" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 25. "CAPTESTOSCINSEL,Select the input for test" "0: Oscillator output pin (osc_out),1: Oscillator input pin (osc_in)" newline bitfld.long 0x00 24. "CAPTESTENABLE,Enable signal for cap test" "0,1" newline bitfld.long 0x00 23. "CAPTESTSTART,Start test" "0,1" newline bitfld.long 0x00 22. "CAPTESTSTARTSRCSEL,Source selection for xo32k_captest_start_ao_set" "0: Sourced from CAPTESTSTART,1: Sourced from calibration" newline endif hexmask.long.byte 0x00 15.--21. 1. "CAPBANKOUT,Capa bank setting output" newline hexmask.long.byte 0x00 8.--14. 1. "CAPBANKIN,Capa bank setting input" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6.--7. "AMPL,oscillator amplitude selection inputs" "0,1,2,3" newline bitfld.long 0x00 4.--5. "IBIAS,bias current selection inputs" "0,1,2,3" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 3. "TEST,Oscillator Bypass Test Mode control" "0: Oscillation mode,1: Bypass test mode is enabled" endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 3. "TEST,Oscillator Test Mode" "0,1" newline bitfld.long 0x00 1.--2. "IREF,reference output current selection inputs" "0,1,2,3" endif group.long 0x50++0x03 line.long 0x00 "COMP,Analog Comparator control" bitfld.long 0x00 18.--20. "FILTERCGF_CLKDIV,Filter Clock divider" "0: Filter clock period duration equals 1 Analog..,1: Filter clock period duration equals 2 Analog..,2: Filter clock period duration equals 4 Analog..,3: Filter clock period duration equals 8 Analog..,4: Filter clock period duration equals 16 Analog..,5: Filter clock period duration equals 32 Analog..,6: Filter clock period duration equals 64 Analog..,7: Filter clock period duration equals 128.." newline bitfld.long 0x00 16.--17. "FILTERCGF_SAMPLEMODE,Control the filtering of the Analog Comparator output" "0: Bypass mode,1: Filter 1 clock period,2: Filter 2 clock period,3: Filter 3 clock period" newline bitfld.long 0x00 10.--14. "VREF,Control reference voltage step per steps of (VREFINPUT/31)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--9. "NMUX,Control word for N multiplexer" "0: VREF (See field VREFINPUT),1: Pin P0_0,2: Pin P0_9,3: Pin P0_18,4: Pin P1_14,5: Pin P2_23,?..." newline bitfld.long 0x00 4.--6. "PMUX,Control word for P multiplexer" "0: VREF (See field VREFINPUT),1: Pin P0_0,2: Pin P0_9,3: Pin P0_18,4: Pin P1_14,5: Pin P2_23,?..." newline bitfld.long 0x00 3. "LOWPOWER,Low power mode" "0: High speed mode,1: Low power mode (Low speed)" newline bitfld.long 0x00 2. "VREFINPUT,Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder)" "0: Select internal VREF,1: Select VDDA" newline bitfld.long 0x00 1. "HYST,Hysteris when hyst = '1'" "0: Hysteresis is disabled,1: Hysteresis is enabled" group.long 0x50++0x03 line.long 0x00 "COMP,Analog Comparator control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" bitfld.long 0x00 18.--20. "FILTERCGF_CLKDIV,Filter Clock divider" "0: Filter clock period duration equals 1 Analog..,1: Filter clock period duration equals 2 Analog..,2: Filter clock period duration equals 4 Analog..,3: Filter clock period duration equals 8 Analog..,4: Filter clock period duration equals 16 Analog..,5: Filter clock period duration equals 32 Analog..,6: Filter clock period duration equals 64 Analog..,7: Filter clock period duration equals 128.." newline bitfld.long 0x00 16.--17. "FILTERCGF_SAMPLEMODE,Control the filtering of the Analog Comparator output" "0: Bypass mode,1: Filter 1 clock period,2: Filter 2 clock period,3: Filter 3 clock period" newline bitfld.long 0x00 10.--14. "VREF,Control reference voltage step per steps of (VREFINPUT/31)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7.--9. "NMUX,Control word for N multiplexer" "0: VREF (See field VREFINPUT),1: Pin P0_0,2: Pin P0_9,3: Pin P0_18,4: Pin P1_14,5: Pin P2_23,?..." newline bitfld.long 0x00 4.--6. "PMUX,Control word for P multiplexer" "0: VREF (See fiedl VREFINPUT),1: Pin P0_0,2: Pin P0_9,3: Pin P0_18,4: Pin P1_14,5: Pin P2_23,?..." newline bitfld.long 0x00 3. "LOWPOWER,Low power mode" "0: High speed mode,1: Low power mode (Low speed)" newline bitfld.long 0x00 2. "VREFINPUT,Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder)" "0: Select internal VREF,1: Select VDDA" newline bitfld.long 0x00 1. "HYST,Hysteris when hyst = '1'" "0: Hysteresis is disable,1: Hysteresis is enable" wgroup.long 0x60++0x03 line.long 0x00 "CMD,DCDC and LDOCORE power state (enable/disable) control" bitfld.long 0x00 5. "LDOCORELOWPWRDISABLE,Disable LDO CORE Low Power Mode (self clearing bit)" "0: No effect,1: Disable LDO CORE Low Power Mode" newline bitfld.long 0x00 4. "LDOCORELOWPWRENABLE,Enable LDO CORE Low Power Mode (self clearing bit)" "0: No effect,1: Enable LDO CORE Low Power Mode" newline bitfld.long 0x00 3. "LDOCOREHIGHPWRDISABLE,Disable LDO CORE High Power Mode (self clearing bit)" "0: No effect,1: Disable LDO CORE High Power Mode" newline bitfld.long 0x00 2. "LDOCOREHIGHPWRENABLE,Enable LDO CORE High Power Mode (self clearing bit)" "0: No effect,1: Enable LDO CORE High Power Mode" newline bitfld.long 0x00 1. "DCDCDISABLE,Disable DCDC (self clearing bit)" "0: No effect,1: Disbale DCDC" newline bitfld.long 0x00 0. "DCDCENABLE,Enable DCDC (self clearing bit)" "0: No effect,1: Enable DCDC" group.long 0x64++0x03 line.long 0x00 "WAKEUPIOCTRL,Deep Power Down wake-up source [Reset by: PoR Pin Reset Software Reset]" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 21. "WAKEUPIO_RSTN,WAKEUP IO event detector reset control" "0: Bloc is reset,1: Bloc is not reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 20. "WAKEUPIO_ENABLE_CTRL,Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 12 to 19)" "0: WAKEUP IO PAD mode control comes from IOCON,1: WAKEUP IO PAD mode control comes from.." newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 20. "WAKEUPIO_ENABLE_CTRL,Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 10 to 19)" "0: WAKEUP IO PAD mode control comes from IOCON,1: WAKEUP IO PAD mode control comes from.." newline bitfld.long 0x00 18.--19. "MODEWAKEUPIOPAD4,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 18.--19. "MODEWAKEUPIOPAD3,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 16.--17. "MODEWAKEUPIOPAD2,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 16.--17. "MODEWAKEUPIOPAD3,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 14.--15. "MODEWAKEUPIOPAD2,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 14.--15. "MODEWAKEUPIOPAD1,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 12.--13. "MODEWAKEUPIOPAD0,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 12.--13. "MODEWAKEUPIOPAD1,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline bitfld.long 0x00 10.--11. "MODEWAKEUPIOPAD0,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 11. "MODEWAKEUP3,Configure wake up I/O 3 in Deep Power Down mode" "0,1" newline bitfld.long 0x00 10. "MODEWAKEUP2,Configure wake up I/O 2 in Deep Power Down mode" "0,1" newline bitfld.long 0x00 9. "MODEWAKEUP1,Configure wake up I/O 1 in Deep Power Down mode" "0,1" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 9. "FALLINGEDGEWAKEUP4,Enable / disable detection of falling edge events on Wake Up 4 pin in Deep Power Down modes" "0: Falling edge detection is disabled,1: Falling edge detection is enabled" newline bitfld.long 0x00 8. "RISINGEDGEWAKEUP4,Enable / disable detection of rising edge events on Wake Up 4 pin in Deep Power Down modes" "0: Rising edge detection is disabled,1: Rising edge detection is enabled" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 8. "MODEWAKEUP0,Configure wake up I/O 0 in Deep Power Down mode" "0,1" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 7. "FALLINGEDGEWAKEUP3,Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 7. "FALLINGEDGEWAKEUP3,Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes" "0: Falling edge detection is disabled,1: Falling edge detection is enabled" newline bitfld.long 0x00 6. "RISINGEDGEWAKEUP3,Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes" "0: Rising edge detection is disabled,1: Rising edge detection is enabled" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6. "RISINGEDGEWAKEUP3,Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable" newline bitfld.long 0x00 5. "FALLINGEDGEWAKEUP2,Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 5. "FALLINGEDGEWAKEUP2,Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes" "0: Falling edge detection is disabled,1: Falling edge detection is enabled" newline bitfld.long 0x00 4. "RISINGEDGEWAKEUP2,Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes" "0: Rising edge detection is disabled,1: Rising edge detection is enabled" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 4. "RISINGEDGEWAKEUP2,Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable" newline bitfld.long 0x00 3. "FALLINGEDGEWAKEUP1,Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 3. "FALLINGEDGEWAKEUP1,Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes" "0: Falling edge detection is disabled,1: Falling edge detection is enabled" newline bitfld.long 0x00 2. "RISINGEDGEWAKEUP1,Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes" "0: Rising edge detection is disabled,1: Rising edge detection is enabled" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 2. "RISINGEDGEWAKEUP1,Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable" newline bitfld.long 0x00 1. "FALLINGEDGEWAKEUP0,Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 1. "FALLINGEDGEWAKEUP0,Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes" "0: Falling edge detection is disabled,1: Falling edge detection is enabled" newline bitfld.long 0x00 0. "RISINGEDGEWAKEUP0,Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes" "0: Rising edge detection is disabled,1: Rising edge detection is enabled" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0. "RISINGEDGEWAKEUP0,Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable" endif group.long 0x68++0x03 line.long 0x00 "WAKEIOCAUSE,Wake-up I/O source" bitfld.long 0x00 5.--9. "WAKEUPIO_EVENTS_ORDER,In DEEP-POWER-DOWN mode indicates which wake up I/O event occured first when several wake up I/Os are enabled" "0: NONE,1: Wake up I/O 0,2: Wake up I/O 1,?,4: Wake up I/O 2,?,?,?,8: Wake up I/O 3,?,?,?,?,?,?,?,16: Wake up I/O 4,?..." newline bitfld.long 0x00 4. "WAKEUP4,Allows to identify Wake up I/O 4 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." newline bitfld.long 0x00 3. "WAKEUP3,Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." newline bitfld.long 0x00 2. "WAKEUP2,Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." newline bitfld.long 0x00 1. "WAKEUP1,Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." newline rbitfld.long 0x00 0. "WAKEUP0,Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." group.long 0x68++0x03 line.long 0x00 "WAKEIOCAUSE,Allows to identify the Wake-up I/O source from Deep Power Down mode" bitfld.long 0x00 3. "WAKEUP3,Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." newline bitfld.long 0x00 2. "WAKEUP2,Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." newline bitfld.long 0x00 1. "WAKEUP1,Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." newline rbitfld.long 0x00 0. "WAKEUP0,Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.." group.long 0x6C++0x03 line.long 0x00 "LIFECYCLESTATE,Life Cycle State as configured in the OTP" hexmask.long.byte 0x00 0.--7. 1. "LC,Life Cycle state" rgroup.long 0x70++0x03 line.long 0x00 "STATUSPWR,Power status from various analog modules (DCDC LDO etc)" bitfld.long 0x00 4. "LDOCOREPWROK,CORE LDO power OK" "0,1" newline bitfld.long 0x00 0. "DCDCPWROK,DCDC converter power OK" "0,1" group.long 0x74++0x03 line.long 0x00 "STATUSCLK,FRO and XTAL status register [Reset by: PoR Brown Out Detectors Reset]" bitfld.long 0x00 2. "XTAL32KOSCFAILURE,XTAL32 KHZ oscillator oscillation failure detection indicator" "0: No oscillation failure has been detetced..,1: At least one oscillation failure has been.." newline rbitfld.long 0x00 0. "XTAL32KOK,XTAL oscillator 32 K OK signal" "0,1" group.long 0x74++0x03 line.long 0x00 "STATUSCLK,Clock status" bitfld.long 0x00 2. "XTAL32KOSCFAILURE,XTAL32 KHZ oscillator oscillation failure detection indicator" "0: No oscillation failure has been detetced..,1: At least one oscillation failure has been.." newline rbitfld.long 0x00 0. "XTAL32KOK,XTAL oscillator 32 K OK signal" "0,1" group.long 0x80++0x03 line.long 0x00 "AOREG0,Always-on 0" hexmask.long.word 0x00 0.--15. 1. "DATA_15_0,General purpose always on domain data storage" group.long 0x84++0x03 line.long 0x00 "AOREG1,General purpose always on domain data storage [Reset by: PoR Brown Out Detectors Reset]" bitfld.long 0x00 16.--19. "BOOTERRORCOUNTER,ROM Boot Fatal Error Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 13. "CDOGRESET,The last chip reset was caused by the code Watchdog" "0,1" newline endif bitfld.long 0x00 12. "DPDRESET_OSTIMER,The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode" "0,1" newline bitfld.long 0x00 11. "DPDRESET_RTC,The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode" "0,1" newline bitfld.long 0x00 10. "DPDRESET_WAKEUPIO,The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode" "0,1" newline bitfld.long 0x00 9. "SWRRESET,The last chip reset was caused by a Software event" "0,1" newline bitfld.long 0x00 8. "WDTRESET,The last chip reset was caused by the Watchdog Timer" "0,1" newline bitfld.long 0x00 7. "SYSTEMRESET,The last chip reset was caused by a System Reset requested by the ARM CPU" "0,1" newline bitfld.long 0x00 6. "BODRESET,The last chip reset was caused by a Brown Out Detector (BoD) either VBAT BoD or Core Logic BoD" "0,1" newline bitfld.long 0x00 5. "PADRESET,The last chip reset was caused by a Pin Reset" "0,1" newline bitfld.long 0x00 4. "POR,The last chip reset was caused by a Power On Reset" "0,1" group.long 0x84++0x03 line.long 0x00 "AOREG1,Always-on 1" bitfld.long 0x00 24.--27. "BOOTERRORCOUNTER,ROM Boot Fatal Error Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--16. "DPD_EVENTS_ORDER,In DEEP-POWER-DOWN mode indicates which reset event occured first between a wake up I/O event (in DEEP-POWER-DOWN) a RTC event (in DEEP-POWER-DOWN) and a OS Timer event (in DEEP-POWER-DOWN)" "0: No event,1: WAKEUPIO,2: RTC,3: Both WAKEUPIO and RTC events occured at the..,4: OSTIMER,5: Both WAKEUPIO and OSTIMER events occured at..,6: Both RTC and OSTIMER events occured at the..,7: WAKEUPIO RTC and OSTIMER events occured at.." newline bitfld.long 0x00 13. "CDOGRESET,The last chip reset was caused by the code Watchdog" "0,1" newline bitfld.long 0x00 12. "DPDRESET_OSTIMER,An OS Timer event occured during a DEEP-POWER-DOWN mode" "0,1" newline bitfld.long 0x00 11. "DPDRESET_RTC,A RTC event occured during DEEP-POWER-DOWN mode" "0,1" newline bitfld.long 0x00 10. "DPDRESET_WAKEUPIO,A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode" "0,1" newline bitfld.long 0x00 9. "SWRRESET,The last chip reset was caused by a Software event" "0,1" newline bitfld.long 0x00 8. "WDTRESET,The last chip reset was caused by the Watchdog Timer" "0,1" newline bitfld.long 0x00 7. "SYSTEMRESET,The last chip reset was caused by a System Reset requested by the ARM CPU" "0,1" newline bitfld.long 0x00 6. "BODRESET,The last chip reset was caused by a Brown Out Detector (BoD) either BOD_VDDMAIN or BOD_CORE" "0,1" newline bitfld.long 0x00 5. "PADRESET,The last chip reset was caused by a Pin Reset" "0,1" newline bitfld.long 0x00 4. "POR,The last chip reset was caused by a Power On Reset" "0,1" group.long 0x90++0x03 line.long 0x00 "MISCCTRL,Dummy Control bus to PMU [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 15. "WAKUPIO_RST,WAKEUP IO event detector reset control" "0: Wakeup IO is not reset,1: Wakeup IO is reset" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 13.--15. "MISCCTRL_13_15,Reserved" "0,1,2,3,4,5,6,7" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 13.--14. "MISCCTRL_13_14,Reserved" "0,1,2,3" newline endif bitfld.long 0x00 12. "DISABLE_BLEED,Controls LDO MEM bleed current" "0: LDO_MEM bleed current is enabled,1: LDO_MEM bleed current is disabled" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 11. "MODEWAKEUP3,Configure wake up I/O 3 in Deep Power Down mode" "0,1" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") hexmask.long.word 0x00 3.--11. 1. "MISCCTRL_3_11,Reserved" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 10. "MODEWAKEUP2,Configure wake up I/O 2 in Deep Power Down mode" "0,1" newline bitfld.long 0x00 9. "MODEWAKEUP1,Configure wake up I/O 1 in Deep Power Down mode" "0,1" newline bitfld.long 0x00 8. "MODEWAKEUP0,Configure wake up I/O 0 in Deep Power Down mode" "0,1" newline bitfld.long 0x00 3.--7. "MISCCTRL_3_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 2. "LOWPWR_FLASH_BUF,no description available" "0,1" newline endif bitfld.long 0x00 1. "LDOMEMHIGHZMODE,Control the activation of LDO MEM High Z mode" "0: LDO MEM High Z mode is disabled,1: LDO MEM High Z mode is enabled" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0. "LDODEEPSLEEPREF,Select LDO Deep Sleep reference source" "0: LDO DEEP Sleep uses Flash buffer biasing as..,1: LDO DEEP Sleep uses Band Gap 0.8V as reference" endif group.long 0x90++0x03 line.long 0x00 "MISCCTRL,Miscellaneous Control Register for PMU [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" bitfld.long 0x00 16. "VREF_ISO,VREF isolation control" "0: VREF module isolation is disabled,1: VREF module isolation is enabled" group.long 0x98++0x03 line.long 0x00 "RTCOSC32K,RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR Brown Out Detectors Reset]" bitfld.long 0x00 31. "CLK1HZDIVUPDATEREQ,RTC 1Hz Divider status flag" "0,1" newline bitfld.long 0x00 30. "CLK1HZDIVHALT,Halts the divider counter" "0,1" newline hexmask.long.word 0x00 16.--26. 1. "CLK1HZDIV,Actual division ratio is : 31744 + CLK1HZDIV" newline bitfld.long 0x00 15. "CLK1KHZDIVUPDATEREQ,RTC 1KHz clock Divider status flag" "0,1" newline bitfld.long 0x00 1.--3. "CLK1KHZDIV,Actual division ratio is : 28 + CLK1KHZDIV" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "SEL,Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz)" "0: FRO 32 KHz,1: XTAL 32KHz" group.long 0x98++0x03 line.long 0x00 "RTCOSC32K,32 KHz clocks source control" bitfld.long 0x00 0. "SEL,Select the 32K oscillator to be used in for the RTC the OS Event Timer and the rest of the SoC (either XTAL32KHz or FRO32KHz)" "0: FRO 32 KHz,1: XTAL 32KHz" group.long 0x9C++0x03 line.long 0x00 "OSTIMER,OS Timer control register [Reset by: PoR Brown Out Detectors Reset]" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 4.--5. "OSTIMERCLKSEL,OS event timer clock select" "0: Oscillator 32 kHz clock,1: FRO 1MHz clock,2: Main clock for OS timer,3: No clock" newline endif bitfld.long 0x00 3. "OSC32KPD,Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K" "0,1" newline bitfld.long 0x00 2. "DPDWAKEUPENABLE,Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode)" "0,1" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 1. "CLOCKENABLE,Enable OS event timer clock" "0,1" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 1. "CLOCKENABLE,Enable OSTIMER 32 KHz clock" "0,1" newline endif bitfld.long 0x00 0. "SOFTRESET,Active high reset" "0,1" group.long 0x9C++0x03 line.long 0x00 "OSEVENTTIMER,OS Event Timer control" bitfld.long 0x00 3.--4. "SELCLOCK,Select OS Event Timer Clock source" "0: 32-KHz Free Running Oscillator (FRO),1: 32-KHz Crystal Oscillator (XTAL),2: 1-MHz FRO,3: System Bus clock" newline bitfld.long 0x00 2. "DPDWAKEUPENABLE,Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode)" "0,1" newline bitfld.long 0x00 1. "CLOCKENABLE,Enable OSTIMER 32 KHz clock" "0,1" newline bitfld.long 0x00 0. "SOFTRESET,Active high reset" "0,1" group.long 0xA0++0x03 line.long 0x00 "PDSLEEPCFG1,Controls the power to various modules during Low Power modes - DEEP-SLEEP POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR Pin Reset Brown Out Detectors Reset Software Reset]" bitfld.long 0x00 9. "STOPEN_DAC2,Controls DAC2 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN)" "0: DAC Stop Mode is disabled,1: DAC Stop Mode is enabled" newline bitfld.long 0x00 8. "STOPEN_DAC1,Controls DAC1 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN)" "0: DAC Stop Mode is disabled,1: DAC Stop Mode is enabled" newline bitfld.long 0x00 7. "STOPEN_DAC0,Controls DAC0 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always disabled in DEEP-POWER-DOWN)" "0: DAC Stop Mode is disabled,1: DAC Stop Mode is enabled" newline bitfld.long 0x00 6. "PDEN_DAC2,Controls DAC2 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN)" "0: DAC2 is powered on during low power mode,1: DAC2 is powered off during low power mode" newline bitfld.long 0x00 5. "PDEN_DAC1,Controls DAC1 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN)" "0: DAC1 is powered on during low power mode,1: DAC1 is powered off during low power mode" newline bitfld.long 0x00 4. "PDEN_DAC0,Controls DAC0 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-POWER-DOWN)" "0: DAC0 is powered on during low power mode,1: DAC0 is powered off during low power mode" newline bitfld.long 0x00 3. "PDEN_HSCMP2_DAC,Controls High Speed Comparator2 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN)" "0: High Speed Comparator2 DAC is powered on..,1: High Speed Comparator2 DAC is powered off.." newline bitfld.long 0x00 2. "PDEN_HSCMP1_DAC,Controls High Speed Comparator1 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN)" "0: High Speed Comparator1 DAC is powered on..,1: High Speed Comparator1 DAC is powered off.." newline bitfld.long 0x00 1. "PDEN_HSCMP0_DAC,Controls High Speed Comparator0 DAC power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN)" "0: High Speed Comparator0 DAC is powered on..,1: High Speed Comparator0 DAC is powered off.." newline bitfld.long 0x00 0. "PDEN_CMPBIAS,Controls Comparators 1/2/3 Bias power during DEEP-SLEEP (always shut down during POWER-DOWN & DEEP-POWER-DOWN)" "0: Analog Bias is powered on during low power mode,1: Analog Bias is powered off during low power.." group.long 0xA4++0x03 line.long 0x00 "TIMEOUTEVENTS,Record time-out errors that might occur at different stages during IC power up" bitfld.long 0x00 12. "PDWN_FLASHINIT_DONE," "0,1" newline bitfld.long 0x00 11. "PDWN_SRAM_WAKEUP," "0,1" newline bitfld.long 0x00 10. "PDWN_LDOFLASHNV_OK," "0,1" newline bitfld.long 0x00 9. "PDWN_DCDC_BODVDDMAIN_OK," "0,1" newline bitfld.long 0x00 8. "PDWN_LDOFLASH_SRAM_OFF," "0,1" newline bitfld.long 0x00 7. "DSLP_SRAM_WAKEUP," "0,1" newline bitfld.long 0x00 6. "DSLP_LDOFLASHNV_OK," "0,1" newline bitfld.long 0x00 5. "DSLP_DCDC_OK," "0,1" newline bitfld.long 0x00 4. "DSLP_LDOFLASH_SRAM_OFF," "0,1" newline bitfld.long 0x00 3. "PWUP_FLASHINIT_DONE," "0,1" newline bitfld.long 0x00 2. "PWUP_SRAM_WAKEUP," "0,1" newline bitfld.long 0x00 1. "PWUP_LDOFLASHNV_OK," "0,1" newline bitfld.long 0x00 0. "PWUP_DCDC_OK," "0,1" group.long 0xB0++0x03 line.long 0x00 "PDSLEEPCFG0,Controls the power to various modules during Low Power modes - DEEP-SLEEP POWER-DOWN and DEEP-POWER-DOWN [Reset by: PoR Pin Reset Brown Out Detectors Reset Software Reset]" bitfld.long 0x00 31. "PDEN_VREF,Controls VREF power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: VREF is powered on during low power mode,1: VREF is powered off during low power mode" newline bitfld.long 0x00 30. "PDEN_OPAMP2,Controls Operational Amplifier2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: Operational Amplifier is powered on during..,1: Operational Amplifier is powered off during.." newline bitfld.long 0x00 29. "PDEN_OPAMP1,Controls Operational Amplifier1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: Operational Amplifier is powered on during..,1: Operational Amplifier is powered off during.." newline bitfld.long 0x00 28. "PDEN_OPAMP0,Controls Operational Amplifier0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: Operational Amplifier is powered on during..,1: Operational Amplifier is powered off during.." newline bitfld.long 0x00 27. "PDEN_HSCMP2,Controls High Speed Comparator2 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: High Speed Comparator is powered on during..,1: High Speed Comparator is powered off during.." newline bitfld.long 0x00 26. "PDEN_HSCMP1,Controls High Speed Comparator1 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: High Speed Comparator is powered on during..,1: High Speed Comparator is powered off during.." newline bitfld.long 0x00 25. "PDEN_HSCMP0,Controls High Speed Comparator0 power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: High Speed Comparator is powered on during..,1: High Speed Comparator is powered off during.." newline bitfld.long 0x00 24. "PDEN_ROM,Controls ROM power during DEEP-SLEEP (ROM is always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: ROM is powered on during low power mode,1: ROM is powered off during low power mode" newline bitfld.long 0x00 23. "PDEN_PLL0_SSCG,Controls PLL0 Spread Sprectrum module power during DEEP-SLEEP (PLL0 Spread Spectrum is always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: PLL0 Spread Sprectrum module is powered on..,1: PLL0 Spread Sprectrum module is powered off.." newline bitfld.long 0x00 21. "PDEN_LDOFLASHNV,Controls Flash NV (high voltage) LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: Flash NV (high voltage) is powered on during..,1: Flash NV (high voltage) is powered off during.." newline bitfld.long 0x00 20. "PDEN_LDOXTALHF,Controls High speed crystal LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: High speed crystal LDO is powered on during..,1: High speed crystal LDO is powered off during.." newline bitfld.long 0x00 18. "PDEN_LDOEFUSEPROG,Controls USB high speed LDO power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: USB high speed LDO is powered on during low..,1: USB high speed LDO is powered off during low.." newline bitfld.long 0x00 16. "PDEN_LDOMEM,Controls Memories LDO power during DEEP-SLEEP POWER-DOWN and DEEP-POWER-DOWN" "0: Memories LDO is powered on during low power..,1: Memories LDO is powered off during low power.." newline bitfld.long 0x00 13. "PDEN_COMP,Controls Analog Comparator power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN)" "0: Analog Comparator is powered on during low..,1: Analog Comparator is powered off during low.." newline bitfld.long 0x00 11. "PDEN_USBFSPHY,Controls USB Full Speed phy power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: USB Full Speed phy is powered on during low..,1: USB Full Speed phy is powered off during low.." newline bitfld.long 0x00 10. "PDEN_PLL1,Controls USB PLL (also refered as PLL1) power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: USB PLL (also refered as PLL1) is powered on..,1: USB PLL (also refered as PLL1) is powered off.." newline bitfld.long 0x00 9. "PDEN_PLL0,Controls System PLL (also refered as PLL0) power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: System PLL (also refered as PLL0) is powered..,1: System PLL (also refered as PLL0) is powered.." newline bitfld.long 0x00 8. "PDEN_XTALHF,Controls high speed crystal power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: High speed crystal is powered on during low..,1: High speed crystal is powered off during low.." newline bitfld.long 0x00 7. "PDEN_XTAL32K,Controls crystal 32 KHz power during DEEP-SLEEP POWER-DOWN and DEEP-POWER-DOWN" "0: crystal 32 KHz is powered on during low power..,1: crystal 32 KHz is powered off during low.." newline bitfld.long 0x00 6. "PDEN_FRO32K,Controls power during DEEP-SLEEP POWER-DOWN and DEEP-POWER-DOWN" "0: FRO 32 KHz is powered on during low power mode,1: FRO 32 KHz is powered off during low power mode" newline bitfld.long 0x00 5. "PDEN_FRO192M,Controls 192MHz Free Running Oscillator power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-POWER-DOWN)" "0: FRO 192 MHz is powered on during low power mode,1: FRO 192 MHz is powered off during low power.." newline bitfld.long 0x00 4. "PDEN_FRO1M,Controls 1 MHz Free Running Oscillator power during DEEP-SLEEP POWER-DOWN and DEEP-POWER-DOWN" "0: FRO 1MHz is powered on during low power mode,1: FRO 1MHz is powered off during low power mode" newline bitfld.long 0x00 3. "PDEN_BODVDDMAIN,Controls BOD_VDDMAIN power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN)" "0: BOD_VDDMAIN is powered on during low power mode,1: BOD_VDDMAIN is powered off during low power.." newline bitfld.long 0x00 2. "PDEN_BODCORE,Controls Core Logic BoD power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN)" "0: BOD_CORE is powered on during low power mode,1: BOD_CORE is powered off during low power mode" newline bitfld.long 0x00 1. "PDEN_BIAS,Controls Analog Bias power during DEEP-SLEEP and POWER-DOWN (always shut down during DEEP-POWER-DOWN)" "0: Analog Bias is powered on during low power mode,1: Analog Bias is powered off during low power.." group.long 0xB4++0x03 line.long 0x00 "SRAMRETCTRL,Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR Pin Reset Brown Out Detectors Reset Software Reset]" bitfld.long 0x00 14. "RETEN_H2PREG_FLEXSPI,Controls FlexSPI Dual Port Register Files power down modes during deep sleep" "0: DEEP-SLEEP,1: DEEP-SLEEP" newline bitfld.long 0x00 13. "RETEN_RAM_FLEXSPILPCACHE,Controls FlexSPI Cache SRAM power down modes during low power modes" "0,1" newline bitfld.long 0x00 12. "RETEN_RAM_FLASHLPCACHE,Controls Embedded Flash Cache SRAM power down modes during low power modes" "0,1" newline bitfld.long 0x00 11. "RETEN_RAM_43,Controls RAM_43 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 10. "RETEN_RAM_42,Controls RAM_42 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 9. "RETEN_RAM_41,Controls RAM_41 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 8. "RETEN_RAM_40,Controls RAM_40 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 7. "RETEN_RAM_30,Controls RAM_30 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 6. "RETEN_RAM_20,Controls RAM_20 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 5. "RETEN_RAM_10,Controls RAM_10 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 4. "RETEN_RAM_03,Controls RAM_03 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 3. "RETEN_RAM_02,Controls RAM_02 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 2. "RETEN_RAM_01,Controls RAM_01 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 1. "RETEN_RAM_00,Controls RAM_00 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." newline bitfld.long 0x00 0. "RETEN_RAM_X0,Controls RAM_X0 power down modes during low power modes" "0: DEEP-SLEEP,1: The SRAM is in 'Deep Sleep' mode (In this.." group.long 0xB8++0x03 line.long 0x00 "PDRUNCFG0,Controls the power to various analog blocks [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" bitfld.long 0x00 23. "PDEN_PLL0_SSCG,Controls power to System PLL (PLL0) Spread Spectrum module" "0: PLL0 Sread spectrum module is powered,1: PLL0 Sread spectrum module is powered down" newline bitfld.long 0x00 22. "PDEN_RNG,Controls power to all True Random Number Genetaor (TRNG) clock sources" "0: TRNG clocks are powered,1: TRNG clocks are powered down" newline bitfld.long 0x00 20. "PDEN_LDOXO32M,Controls power to high speed crystal LDO" "0: High speed crystal LDO is powered,1: High speed crystal LDO is powered down" newline bitfld.long 0x00 19. "PDEN_AUXBIAS,Controls power to auxiliary biasing (AUXBIAS)" "0: auxiliary biasing is powered,1: auxiliary biasing is powered down" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18. "PDEN_LDOUSBHS,Controls power to USB high speed LDO" "0: USB high speed LDO is powered,1: USB high speed LDO is powered down" newline endif bitfld.long 0x00 13. "PDEN_COMP,Controls power to Analog Comparator" "0: Analog Comparator is powered,1: Analog Comparator is powered down" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 12. "PDEN_USBHSPHY,Controls power to USB High Speed Phy" "0: USB HS phy is powered,1: USB HS phy is powered down" newline bitfld.long 0x00 11. "PDEN_USBFSPHY,Controls power to USB Full Speed phy" "0: USB Full Speed phy is powered,1: USB Full Speed phy is powered down" newline bitfld.long 0x00 10. "PDEN_PLL1,Controls power to USB PLL (also refered as PLL1)" "0: PLL1 is powered,1: PLL1 is powered down" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 10. "PDEN_PLL1,Controls power to PLL1" "0: PLL1 is powered,1: PLL1 is powered down" newline endif bitfld.long 0x00 9. "PDEN_PLL0,Controls power to System PLL (also refered as PLL0)" "0: PLL0 is powered,1: PLL0 is powered down" newline bitfld.long 0x00 8. "PDEN_XTAL32M,Controls power to high speed crystal" "0: High speed crystal is powered,1: High speed crystal is powered down" newline bitfld.long 0x00 7. "PDEN_XTAL32K,Controls power to crystal 32 KHz" "0: Crystal 32KHz is powered,1: Crystal 32KHz is powered down" newline bitfld.long 0x00 6. "PDEN_FRO32K,Controls power to the Free Running Oscillator (FRO) 32 KHz" "0: FRO32KHz is powered,1: FRO32KHz is powered down" newline bitfld.long 0x00 3. "PDEN_BODVBAT,Controls power to VBAT Brown Out Detector (BOD)" "0: BOD VBAT is powered,1: BOD VBAT is powered down" group.long 0xB8++0x03 line.long 0x00 "PDRUNCFG0,Power configuration 0" bitfld.long 0x00 31. "PDEN_VREF,Controls power to VREF module" "0: VREF is powered on,1: VREF is powered down" newline bitfld.long 0x00 30. "PDEN_OPAMP2,Controls power to Operational Amplifier2" "0: Operational Amplifier2 is powered on,1: Operational Amplifier2 is powered down" newline bitfld.long 0x00 29. "PDEN_OPAMP1,Controls power to Operational Amplifier1" "0: Operational Amplifier1 is powered on,1: Operational Amplifier1 is powered down" newline bitfld.long 0x00 28. "PDEN_OPAMP0,Controls power to Operational Amplifier0" "0: Operational Amplifier0 is powered on,1: Operational Amplifier0 is powered down" newline bitfld.long 0x00 27. "PDEN_HSCMP2,Controls power to High Speed Comparator2" "0: High Speed Comparator2 is powered on,1: High Speed Comparator2 is powered down" newline bitfld.long 0x00 26. "PDEN_HSCMP1,Controls power to High Speed Comparator1" "0: High Speed Comparator1 is powered on,1: High Speed Comparator1 is powered down" newline bitfld.long 0x00 25. "PDEN_HSCMP0,Controls power to High Speed Comparator0" "0: High Speed Comparator0 is powered on,1: High Speed Comparator0 is powered down" newline bitfld.long 0x00 23. "PDEN_PLL0_SSCG,Controls power to System PLL (PLL0) Spread Spectrum module" "0: PLL0 Sread spectrum module is powered,1: PLL0 Sread spectrum module is powered down" newline bitfld.long 0x00 21. "PDEN_LDOFLASHNV,Controls power to Flasn NV (high voltage) LDO" "0: Flash NV LDO is powered,1: Flash NV LDO is powered down" newline bitfld.long 0x00 20. "PDEN_LDOXTALHF,Controls power to high speed crystal LDO" "0: High speed crystal LDO is powered,1: High speed crystal LDO is powered down" newline bitfld.long 0x00 18. "PDEN_LDOEFUSEPROG,Controls power to eFUSE Programming LDO" "0: USB high speed LDO is powered,1: USB high speed LDO is powered down" newline bitfld.long 0x00 16. "PDEN_LDOMEM,Controls power to Memories LDO" "0: Memories LDO is powered,1: Memories LDO is powered down" newline bitfld.long 0x00 13. "PDEN_COMP,Controls power to Analog Comparator" "0: Analog Comparator is powered,1: Analog Comparator is powered down" newline bitfld.long 0x00 11. "PDEN_USBFSPHY,Controls power to USB Full Speed phy" "0: USB Full Speed phy is powered,1: USB Full Speed phy is powered down" newline bitfld.long 0x00 10. "PDEN_PLL1,Controls power to USB PLL (also refered as PLL1)" "0: PLL1 is powered,1: PLL1 is powered down" newline bitfld.long 0x00 9. "PDEN_PLL0,Controls power to System PLL (also refered as PLL0)" "0: PLL0 is powered,1: PLL0 is powered down" newline bitfld.long 0x00 8. "PDEN_XTALHF,Controls power to high speed crystal" "0: High speed crystal is powered,1: High speed crystal is powered down" newline bitfld.long 0x00 7. "PDEN_XTAL32K,Controls power to crystal 32 KHz" "0: Crystal 32KHz is powered,1: Crystal 32KHz is powered down" newline bitfld.long 0x00 6. "PDEN_FRO32K,Controls power to the Free Running Oscillator (FRO) 32 KHz" "0: FRO32KHz is powered,1: FRO32KHz is powered down" newline bitfld.long 0x00 5. "PDEN_FRO192M,Controls power to the Free Running Oscillator (FRO) 192 MHz The 12MHz 48 MHz and 96 MHz clocks are derived from this FRO" "0: FRO 192MHz is powered,1: FRO 192MHz is powered down" newline bitfld.long 0x00 3. "PDEN_BODVDDMAIN,Controls power to VDDMAIN Brown Out Detector (BOD_VDDMAIN)" "0: BOD_VDDMAIN is powered,1: BOD_VDDMAIN is powered down" newline bitfld.long 0x00 2. "PDEN_BODCORE,Controls power to Core Brown Out Detector (BOD_CORE)" "0: BOD_CORE is powered,1: BOD_CORE is powered down" newline bitfld.long 0x00 1. "PDEN_BIAS,Controls power to" "0: Analog Bias is powered,1: Analog Bias is powered down" newline bitfld.long 0x00 0. "PDEN_DCDC,Controls power to Bulk DCDC Converter" "0: DCDC is powered,1: DCDC is powered down" group.long 0xBC++0x03 line.long 0x00 "PDRUNCFG1,Power configuration 1" bitfld.long 0x00 9. "STOPEN_DAC2,Controls DAC2 Stop mode" "0: DAC2 Stop mode is disabled,1: DAC2 Stop mode is enabled" newline bitfld.long 0x00 8. "STOPEN_DAC1,Controls DAC1 Stop mode" "0: DAC1 Stop mode is disabled,1: DAC1 Stop mode is enabled" newline bitfld.long 0x00 7. "STOPEN_DAC0,Controls DAC0 Stop mode" "0: DAC0 Stop mode is disabled,1: DAC0 Stop mode is enabled" newline bitfld.long 0x00 6. "PDEN_DAC2,Controls power to DAC2" "0: DAC2 is powered,1: DAC2 is powered down" newline bitfld.long 0x00 5. "PDEN_DAC1,Controls power to DAC1" "0: DAC1 is powered,1: DAC1 is powered down" newline bitfld.long 0x00 4. "PDEN_DAC0,Controls power to DAC0" "0: DAC0 is powered,1: DAC0 is powered down" newline bitfld.long 0x00 3. "PDEN_HSCMP2_DAC,Controls power to High Speed Comparator2 DAC" "0: High Speed Comparator2 DAC is powered,1: High Speed Comparator2 DAC is powered down" newline bitfld.long 0x00 2. "PDEN_HSCMP1_DAC,Controls power to High Speed Comparator1 DAC" "0: High Speed Comparator1 DAC is powered,1: High Speed Comparator1 DAC is powered down" newline bitfld.long 0x00 1. "PDEN_HSCMP0_DAC,Controls power to High Speed Comparator0 DAC" "0: High Speed Comparator0 DAC is powered,1: High Speed Comparator0 DAC is powered down" newline bitfld.long 0x00 0. "PDEN_CMPBIAS,Controls power of Comparators 1/2/3 bias" "0: Comparators 1/2/3 bias is powered,1: Comparators 1/2/3 bias is powered down" wgroup.long 0xC0++0x03 line.long 0x00 "PDRUNCFGSET0,Controls the power to various analog blocks [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" hexmask.long 0x00 0.--31. 1. "PDRUNCFGSET0,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register if they are implemented" wgroup.long 0xC0++0x03 line.long 0x00 "PDRUNCFGSET0,Power configuration set 0" hexmask.long 0x00 0.--31. 1. "PDRUNCFGSET0,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register if they are implemented" wgroup.long 0xC4++0x03 line.long 0x00 "PDRUNCFGSET1,Power configuration set 1" hexmask.long.word 0x00 0.--9. 1. "PDRUNCFGSET1,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register if they are implemented" wgroup.long 0xC8++0x03 line.long 0x00 "PDRUNCFGCLR0,Controls the power to various analog blocks [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]" hexmask.long 0x00 0.--31. 1. "PDRUNCFGCLR0,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register if they are implemented" wgroup.long 0xC8++0x03 line.long 0x00 "PDRUNCFGCLR0,Power configuration clear 0" hexmask.long 0x00 0.--31. 1. "PDRUNCFGCLR0,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register if they are implemented" wgroup.long 0xCC++0x03 line.long 0x00 "PDRUNCFGCLR1,Power configuration clear 1" hexmask.long.word 0x00 0.--9. 1. "PDRUNCFGCLR1,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register if they are implemented" group.long 0xD4++0x03 line.long 0x00 "SRAMCTRL,All SRAMs common control signals [Reset by: PoR Pin Reset Brown Out Detectors Reset Software Reset]" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 8. "WRME,Write read margin enable" "0,1" newline bitfld.long 0x00 5.--7. "WM,Write Margin control settings" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2.--4. "RM,Read Margin control settings" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x00 0.--1. "SMB,Source Biasing voltage" "0: Low leakage,1: Medium leakage,2: Highest leakage,3: Disable" group.long 0xD8++0x03 line.long 0x00 "SRAMCTRL0,RAM_X0 and RAM_00 to RAM_30 power modes controls [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset] When [LS LSDEL DSB DSBDEL] is" bitfld.long 0x00 31. "RAM_30_LSDEL,RAM_30 Light Sleep mode delayed" "0,1" newline bitfld.long 0x00 30. "RAM_30_DSBDEL,RAM_30 Deep sleep delayed" "0,1" newline bitfld.long 0x00 29. "RAM_30_DSB,RAM_30 Deep sleep mode" "0,1" newline bitfld.long 0x00 28. "RAM_30_LS,RAM_30 Light Sleep mode" "0,1" newline bitfld.long 0x00 27. "RAM_20_LSDEL,RAM_20 Sleep mode disable" "0,1" newline bitfld.long 0x00 26. "RAM_20_DSBDEL,RAM_20 Deep sleep delayed" "0,1" newline bitfld.long 0x00 25. "RAM_20_DSB,RAM_20 Deep sleep mode" "0,1" newline bitfld.long 0x00 24. "RAM_20_LS,RAM_20 Light Sleep mode" "0,1" newline bitfld.long 0x00 23. "RAM_10_LSDEL,RAM_10 Sleep mode disable" "0,1" newline bitfld.long 0x00 22. "RAM_10_DSBDEL,RAM_10 Deep sleep delayed" "0,1" newline bitfld.long 0x00 21. "RAM_10_DSB,RAM_10 Deep sleep mode" "0,1" newline bitfld.long 0x00 20. "RAM_10_LS,RAM_10 Light Sleep mode" "0,1" newline bitfld.long 0x00 19. "RAM_03_LSDEL,RAM_03 Sleep mode disable" "0,1" newline bitfld.long 0x00 18. "RAM_03_DSBDEL,RAM_03 Deep sleep delayed" "0,1" newline bitfld.long 0x00 17. "RAM_03_DSB,RAM_03 Deep sleep mode" "0,1" newline bitfld.long 0x00 16. "RAM_03_LS,RAM_03 Light Sleep mode" "0,1" newline bitfld.long 0x00 15. "RAM_02_LSDEL,RAM_02 Sleep mode disable" "0,1" newline bitfld.long 0x00 14. "RAM_02_DSBDEL,RAM_02 Deep sleep delayed" "0,1" newline bitfld.long 0x00 13. "RAM_02_DSB,RAM_02 Deep sleep mode" "0,1" newline bitfld.long 0x00 12. "RAM_02_LS,RAM_02 Light Sleep mode" "0,1" newline bitfld.long 0x00 11. "RAM_01_LSDEL,RAM_01 Sleep mode disable" "0,1" newline bitfld.long 0x00 10. "RAM_01_DSBDEL,RAM_01 Deep sleep delayed" "0,1" newline bitfld.long 0x00 9. "RAM_01_DSB,RAM_01 Deep sleep mode" "0,1" newline bitfld.long 0x00 8. "RAM_01_LS,RAM_01 Light Sleep mode" "0,1" newline bitfld.long 0x00 7. "RAM_00_LSDEL,RAM_00 Sleep mode disable" "0,1" newline bitfld.long 0x00 6. "RAM_00_DSBDEL,RAM_00 Deep sleep delayed" "0,1" newline bitfld.long 0x00 5. "RAM_00_DSB,RAM_00 Deep sleep mode" "0,1" newline bitfld.long 0x00 4. "RAM_00_LS,RAM_00 Light Sleep mode" "0,1" newline bitfld.long 0x00 3. "RAM_X0_LSDEL,RAM_X0 Sleep mode disable" "0,1" newline bitfld.long 0x00 2. "RAM_X0_DSBDEL,RAM_X0 Deep sleep delayed" "0,1" newline bitfld.long 0x00 1. "RAM_X0_DSB,RAM_X0 Deep sleep mode" "0,1" newline bitfld.long 0x00 0. "RAM_X0_LS,RAM_X0 Light Sleep mode" "0,1" group.long 0xDC++0x03 line.long 0x00 "SRAMCTRL1,RAM_40 to RAM_43 power modes controls [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset] When [LS LSDEL DSB DSBDEL] is" bitfld.long 0x00 23. "RAM_FLEXSPILPCACHE_LSDEL,Flex SPI Cache RAM Sleep mode disable" "0,1" newline bitfld.long 0x00 22. "RAM_FLEXSPILPCACHE_DSBDEL,Flex SPI Cache RAM Deep sleep delayed" "0,1" newline bitfld.long 0x00 21. "RAM_FLEXSPILPCACHE_DSB,Flex SPI Cache RAM Deep sleep mode" "0,1" newline bitfld.long 0x00 20. "RAM_FLEXSPILPCACHE_LS,Flex SPI Cache RAM Light Sleep mode" "0,1" newline bitfld.long 0x00 19. "RAM_FLASHLPCACHE_LSDEL,Flash Cache RAM Sleep mode disable" "0,1" newline bitfld.long 0x00 18. "RAM_FLASHLPCACHE_DSBDEL,Flash Cache RAM Deep sleep delayed" "0,1" newline bitfld.long 0x00 17. "RAM_FLASHLPCACHE_DSB,Flash Cache RAM Deep sleep mode" "0,1" newline bitfld.long 0x00 16. "RAM_FLASHLPCACHE_LS,Flash Cache RAM Light Sleep mode" "0,1" newline bitfld.long 0x00 15. "RAM_43_LSDEL,RAM_43 Sleep mode disable" "0,1" newline bitfld.long 0x00 14. "RAM_43_DSBDEL,RAM_43 Deep sleep delayed" "0,1" newline bitfld.long 0x00 13. "RAM_43_DSB,RAM_43 Deep sleep mode" "0,1" newline bitfld.long 0x00 12. "RAM_43_LS,RAM_43 Light Sleep mode" "0,1" newline bitfld.long 0x00 11. "RAM_42_LSDEL,RAM_42 Sleep mode disable" "0,1" newline bitfld.long 0x00 10. "RAM_42_DSBDEL,RAM_42 Deep sleep delayed" "0,1" newline bitfld.long 0x00 9. "RAM_42_DSB,RAM_42 Deep sleep mode" "0,1" newline bitfld.long 0x00 8. "RAM_42_LS,RAM_42 Light Sleep mode" "0,1" newline bitfld.long 0x00 7. "RAM_41_LSDEL,RAM_41 Sleep mode disable" "0,1" newline bitfld.long 0x00 6. "RAM_41_DSBDEL,RAM_41 Deep sleep delayed" "0,1" newline bitfld.long 0x00 5. "RAM_41_DSB,RAM_41 Deep sleep mode" "0,1" newline bitfld.long 0x00 4. "RAM_41_LS,RAM_41 Light Sleep mode" "0,1" newline bitfld.long 0x00 3. "RAM_40_LSDEL,RAM_40 Sleep mode disable" "0,1" newline bitfld.long 0x00 2. "RAM_40_DSBDEL,RAM_40 Deep sleep delayed" "0,1" newline bitfld.long 0x00 1. "RAM_40_DSB,RAM_40 Deep sleep mode" "0,1" newline bitfld.long 0x00 0. "RAM_40_LS,RAM_40 Light Sleep mode" "0,1" tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "POWERQUAD (PowerQuad)" base ad:0x400A6000 group.long 0x00++0x03 line.long 0x00 "OUTBASE,Output Base" hexmask.long 0x00 0.--31. 1. "OUTBASE,Base address register for the output region" group.long 0x04++0x03 line.long 0x00 "OUTFORMAT,Output Format" hexmask.long.byte 0x00 8.--15. 1. "OUT_SCALER,Output Scaler Value" bitfld.long 0x00 4.--5. "OUT_FORMATEXT,Output External Format" "0,1,2,3" newline bitfld.long 0x00 0.--1. "OUT_FORMATINT,Output Internal Format" "0,1,2,3" group.long 0x08++0x03 line.long 0x00 "TMPBASE,Temporary Base" hexmask.long 0x00 0.--31. 1. "TMPBASE,Base address register for the temporary region" group.long 0x0C++0x03 line.long 0x00 "TMPFORMAT,Temporary Format" hexmask.long.byte 0x00 8.--15. 1. "TMP_SCALER,Temporary Scaler Value" bitfld.long 0x00 4.--5. "TMP_FORMATEXT,Temporary External Format" "0,1,2,3" newline bitfld.long 0x00 0.--1. "TMP_FORMATINT,Temporary Internal Format" "0,1,2,3" group.long 0x10++0x03 line.long 0x00 "INABASE,Input A Base" hexmask.long 0x00 0.--31. 1. "INABASE,Input A Base" group.long 0x14++0x03 line.long 0x00 "INAFORMAT,Input A Format" hexmask.long.byte 0x00 8.--15. 1. "INA_SCALER,Input A Scaler Value" bitfld.long 0x00 4.--5. "INA_FORMATEXT,Input A External Format" "0,1,2,3" newline bitfld.long 0x00 0.--1. "INA_FORMATINT,Input A Internal Format" "0,1,2,3" group.long 0x18++0x03 line.long 0x00 "INBBASE,Input B Base" hexmask.long 0x00 0.--31. 1. "INBBASE,Input B Base" group.long 0x1C++0x03 line.long 0x00 "INBFORMAT,Input B Format" hexmask.long.byte 0x00 8.--15. 1. "INB_SCALER,Input B Scaler Value" bitfld.long 0x00 4.--5. "INB_FORMATEXT,Input B External Format" "0,1,2,3" newline bitfld.long 0x00 0.--1. "INB_FORMATINT,Input B Internal Format" "0,1,2,3" group.long 0x100++0x03 line.long 0x00 "CONTROL,Control" rbitfld.long 0x00 31. "INST_BUSY,Instruction Busy" "0,1" bitfld.long 0x00 4.--7. "DECODE_MACHINE,Decode Machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DECODE_OPCODE,Decode Opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x104++0x03 line.long 0x00 "LENGTH,Length" hexmask.long 0x00 0.--31. 1. "INST_LENGTH,Instruction Length" group.long 0x108++0x03 line.long 0x00 "CPPRE,Coprocessor Pre-scale" bitfld.long 0x00 17. "CPPRE_SAT8,Saturation 8" "0: SAT_8_BITS,1: SAT_16_BITS" bitfld.long 0x00 16. "CPPRE_SAT,Saturation" "0: No saturation,1: Forces sub-32 bit saturation" newline hexmask.long.byte 0x00 8.--15. 1. "CPPRE_OUT,Output" hexmask.long.byte 0x00 0.--7. 1. "CPPRE_IN,Input" group.long 0x10C++0x03 line.long 0x00 "MISC,Miscellaneous" hexmask.long 0x00 0.--31. 1. "INST_MISC,For Matrix : Used for scaling factor" group.long 0x110++0x03 line.long 0x00 "CURSORY,Cursory" bitfld.long 0x00 0. "CURSORY,Cursory Mode" "0: Disable Cursory mode,1: Enable Cursory Mode" group.long 0x180++0x03 line.long 0x00 "CORDIC_X,Cordic input X" hexmask.long 0x00 0.--31. 1. "CORDIC_X,Cordic Input x" group.long 0x184++0x03 line.long 0x00 "CORDIC_Y,Cordic Input Y" hexmask.long 0x00 0.--31. 1. "CORDIC_Y,Cordic Input y" group.long 0x188++0x03 line.long 0x00 "CORDIC_Z,Cordic Input Z" hexmask.long 0x00 0.--31. 1. "CORDIC_Z,Cordic Input z" group.long 0x18C++0x03 line.long 0x00 "ERRSTAT,Error Status" bitfld.long 0x00 4. "BUSERROR,Bus Error" "0: NO_ERROR,1: Error on Bus" bitfld.long 0x00 3. "UNDERFLOW,Underflow" "0: NO_ERROR,1: Error on Underflow" newline bitfld.long 0x00 2. "FIXEDOVERFLOW,Fixed Point Overflow" "0: NO_ERROR,1: Error on Fixed Point Overflow" bitfld.long 0x00 1. "NAN,Floating Point NaN" "0: NO_ERROR,1: Error on Floating Point NaN" newline bitfld.long 0x00 0. "OVERFLOW,Floating Point Overflow" "0: NO_ERROR,1: Error on Floating Point Overflow" group.long 0x190++0x03 line.long 0x00 "INTREN,Interrupt Enable" bitfld.long 0x00 7. "INTR_COMP,Interrupt on Instruction Completion" "0: DISABLE,1: Enable interrupt on instruction completion" bitfld.long 0x00 4. "INTR_BERR,Interrupt on AHBM Bus Error" "0: DISABLE,1: Enable interrupt on AHBM Bus Error" newline bitfld.long 0x00 3. "INTR_UFLOW,Interrupt on Subnormal Truncation" "0: DISABLE,1: Enable interrupt on subnormal truncation" bitfld.long 0x00 2. "INTR_FIXED,Interrupt on Fixed Point Overflow" "0: DISABLE,1: Enable interrupt on fixed point overflow" newline bitfld.long 0x00 1. "INTR_NAN,Interrupt Floating Point NaN" "0: DISABLE,1: Enable interrupt on floating point NaN" bitfld.long 0x00 0. "INTR_OFLOW,Interrupt Floating Point Overflow" "0: DISABLE,1: Enable interrupt on floating point overflow" group.long 0x194++0x03 line.long 0x00 "EVENTEN,Event Enable" bitfld.long 0x00 7. "EVENT_COMP,Event Trigger on Instruction Completion" "0: DISABLE,1: Enable event trigger on instruction completion" bitfld.long 0x00 4. "EVENT_BERR,Event Trigger on AHBM Bus Error" "0: DISABLE,1: Enable event trigger on AHBM bus error" newline bitfld.long 0x00 3. "EVENT_UFLOW,Event Trigger on Subnormal Truncation" "0: DISABLE,1: Enable event trigger on subnormal truncation" bitfld.long 0x00 2. "EVENT_FIXED,Event Trigger on Fixed Point Overflow" "0: DISABLE,1: Enable event trigger on fixed point overflow" newline bitfld.long 0x00 1. "EVENT_NAN,Event Trigger on Floating Point NaN" "0: DISABLE,1: Enable event trigger on floating point NaN" bitfld.long 0x00 0. "EVENT_OFLOW,Event Trigger on Floating Point Overflow" "0: DISABLE,1: Enable event trigger on Floating point overflow" group.long 0x198++0x03 line.long 0x00 "INTRSTAT,Interrupt Status" bitfld.long 0x00 0. "INTR_STAT,Interrupt Status" "0: No new interrupt,1: Interrupt captured" repeat 16. (increment 0 1) (increment 0 0x04) group.long ($2+0x200)++0x03 line.long 0x00 "GPREG[$1],General Purpose Register Bank n $1" hexmask.long 0x00 0.--31. 1. "GPREG,General Purpose Register Bank" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x240)++0x03 line.long 0x00 "COMPREG[$1],Compute Register Bank n $1" hexmask.long 0x00 0.--31. 1. "COMPREG,Compute Register Bank" repeat.end tree.end endif sif cpuis("LPC5526*")||cpuis("LPC5528*") tree "PRINCE" base ad:0x40035000 group.long 0x00++0x03 line.long 0x00 "ENC_ENABLE,Encryption Enable register" bitfld.long 0x00 0. "EN,Encryption Enable" "0: Encryption of writes to the flash controller..,1: Encryption of writes to the flash controller.." wgroup.long 0x04++0x03 line.long 0x00 "MASK_LSB,Data Mask register 32 Least Significant Bits" hexmask.long 0x00 0.--31. 1. "MASKVAL,Value of the 32 Least Significant Bits of the 64-bit data mask" wgroup.long 0x08++0x03 line.long 0x00 "MASK_MSB,Data Mask register 32 Most Significant Bits" hexmask.long 0x00 0.--31. 1. "MASKVAL,Value of the 32 Most Significant Bits of the 64-bit data mask" group.long 0x0C++0x03 line.long 0x00 "LOCK,Lock register" bitfld.long 0x00 8. "LOCKMASK,Lock the Mask registers" "0: Disabled,1: Enabled" bitfld.long 0x00 2. "LOCKREG2,Lock Region 2 registers" "0: Disabled,1: Enabled" bitfld.long 0x00 1. "LOCKREG1,Lock Region 1 registers" "0: Disabled,1: Enabled" bitfld.long 0x00 0. "LOCKREG0,Lock Region 0 registers" "0: Disabled,1: Enabled" wgroup.long 0x10++0x03 line.long 0x00 "IV_LSB0,Initial Vector register for region 0 Least Significant Bits" hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector" wgroup.long 0x14++0x03 line.long 0x00 "IV_MSB0,Initial Vector register for region 0 Most Significant Bits" hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector" group.long 0x18++0x03 line.long 0x00 "BASE_ADDR0,Base Address for region 0 register" bitfld.long 0x00 18.--19. "ADDR_PRG,Programmable portion of the base address of region 0" "0,1,2,3" hexmask.long.tbyte 0x00 0.--17. 1. "ADDR_FIXED,Fixed portion of the base address of region 0" group.long 0x1C++0x03 line.long 0x00 "SR_ENABLE0,Sub-Region Enable register for region 0" hexmask.long 0x00 0.--31. 1. "EN,Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0" wgroup.long 0x20++0x03 line.long 0x00 "IV_LSB1,Initial Vector register for region 1 Least Significant Bits" hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector" wgroup.long 0x24++0x03 line.long 0x00 "IV_MSB1,Initial Vector register for region 1 Most Significant Bits" hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector" group.long 0x28++0x03 line.long 0x00 "BASE_ADDR1,Base Address for region 1 register" bitfld.long 0x00 18.--19. "ADDR_PRG,Programmable portion of the base address of region 1" "0,1,2,3" hexmask.long.tbyte 0x00 0.--17. 1. "ADDR_FIXED,Fixed portion of the base address of region 1" group.long 0x2C++0x03 line.long 0x00 "SR_ENABLE1,Sub-Region Enable register for region 1" hexmask.long 0x00 0.--31. 1. "EN,Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1" wgroup.long 0x30++0x03 line.long 0x00 "IV_LSB2,Initial Vector register for region 2 Least Significant Bits" hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector" wgroup.long 0x34++0x03 line.long 0x00 "IV_MSB2,Initial Vector register for region 2 Most Significant Bits" hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector" group.long 0x38++0x03 line.long 0x00 "BASE_ADDR2,Base Address for region 2 register" bitfld.long 0x00 18.--19. "ADDR_PRG,Programmable portion of the base address of region 2" "0,1,2,3" hexmask.long.tbyte 0x00 0.--17. 1. "ADDR_FIXED,Fixed portion of the base address of region 2" group.long 0x3C++0x03 line.long 0x00 "SR_ENABLE2,Sub-Region Enable register for region 2" hexmask.long 0x00 0.--31. 1. "EN,Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2" tree.end endif sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "PWM (Pulse-Width Modulator)" repeat 2. (list 0. 1.) (list ad:0x400C3000 ad:0x400C5000) tree "PWM$1" base $2 rgroup.word 0x00++0x01 line.word 0x00 "SM0CNT,Counter Register" hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits" group.word 0x02++0x01 line.word 0x00 "SM0INIT,Initial Count Register" hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits" group.word 0x04++0x01 line.word 0x00 "SM0CTRL2,Control 2 Register" bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1" bitfld.word 0x00 14. "WAITEN,Sleep Enable" "0,1" newline bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs" bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1" newline bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1" bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1" newline bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization" bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled" newline bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1" bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.." newline bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).." bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..." group.word 0x06++0x01 line.word 0x00 "SM0CTRL,Control Register" bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities" bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled" newline bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled" rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3" newline bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.." bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: Prescaler 1,1: Prescaler 2,2: Prescaler 4,3: Prescaler 8,4: Prescaler 16,5: Prescaler 32,6: Prescaler 64,7: HUNDREDTWENTYEIGHT" newline bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB" bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.." newline bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled" bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled" group.word 0x0A++0x01 line.word 0x00 "SM0VAL0,Value Register 0" hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0" group.word 0x0C++0x01 line.word 0x00 "SM0FRACVAL1,Fractional Value Register 1" bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x0E++0x01 line.word 0x00 "SM0VAL1,Value Register 1" hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1" group.word 0x10++0x01 line.word 0x00 "SM0FRACVAL2,Fractional Value Register 2" bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x12++0x01 line.word 0x00 "SM0VAL2,Value Register 2" hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2" group.word 0x14++0x01 line.word 0x00 "SM0FRACVAL3,Fractional Value Register 3" bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x16++0x01 line.word 0x00 "SM0VAL3,Value Register 3" hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3" group.word 0x18++0x01 line.word 0x00 "SM0FRACVAL4,Fractional Value Register 4" bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x1A++0x01 line.word 0x00 "SM0VAL4,Value Register 4" hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4" group.word 0x1C++0x01 line.word 0x00 "SM0FRACVAL5,Fractional Value Register 5" bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x1E++0x01 line.word 0x00 "SM0VAL5,Value Register 5" hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5" group.word 0x20++0x01 line.word 0x00 "SM0FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1" bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B" newline bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A" bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.." group.word 0x22++0x01 line.word 0x00 "SM0OCTRL,Output Control Register" rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1" rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1" newline rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1" bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted" newline bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted" bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted" newline bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" newline bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" group.word 0x24++0x01 line.word 0x00 "SM0STS,Status Register" rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.." eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.." newline eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing" eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1" newline eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1" eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1" newline eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1" eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1" newline eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1" eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..." group.word 0x26++0x01 line.word 0x00 "SM0INTEN,Interrupt Enable Register" bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled" bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled" newline bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]" bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]" newline bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]" bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]" newline bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]" bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]" newline bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..." group.word 0x28++0x01 line.word 0x00 "SM0DMAEN,DMA Enable Register" bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: ENABLED" bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together" newline bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.." bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1" bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1" bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1" group.word 0x2A++0x01 line.word 0x00 "SM0TCTRL,Output Trigger Control Register" bitfld.word 0x00 15. "PWAOT0,Mux Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_MUX_TRIG0 port" bitfld.word 0x00 14. "PWBOT1,Mux Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_MUX_TRIG1 port" newline bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.." bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "?,1: PWM_OUT_TRIG0 will set when the counter value..,?,3: PWM_OUT_TRIG0 will set when the counter value..,?,5: PWM_OUT_TRIG0 will set when the counter value..,?,7: PWM_OUT_TRIG0 will set when the counter value..,?,9: PWM_OUT_TRIG0 will set when the counter value..,?,11: PWM_OUT_TRIG0 will set when the counter..,?,13: PWM_OUT_TRIG0 will set when the counter..,?,15: PWM_OUT_TRIG0 will set when the counter..,?,17: PWM_OUT_TRIG0 will set when the counter..,?,19: PWM_OUT_TRIG0 will set when the counter..,?,21: PWM_OUT_TRIG0 will set when the counter..,?,23: PWM_OUT_TRIG0 will set when the counter..,?,25: PWM_OUT_TRIG0 will set when the counter..,?,27: PWM_OUT_TRIG0 will set when the counter..,?,29: PWM_OUT_TRIG0 will set when the counter..,?,31: PWM_OUT_TRIG0 will set when the counter..,?,33: PWM_OUT_TRIG0 will set when the counter..,?,35: PWM_OUT_TRIG0 will set when the counter..,?,37: PWM_OUT_TRIG0 will set when the counter..,?,39: PWM_OUT_TRIG0 will set when the counter..,?,41: PWM_OUT_TRIG0 will set when the counter..,?,43: PWM_OUT_TRIG0 will set when the counter..,?,45: PWM_OUT_TRIG0 will set when the counter..,?,47: PWM_OUT_TRIG0 will set when the counter..,?,49: PWM_OUT_TRIG0 will set when the counter..,?,51: PWM_OUT_TRIG0 will set when the counter..,?,53: PWM_OUT_TRIG0 will set when the counter..,?,55: PWM_OUT_TRIG0 will set when the counter..,?,57: PWM_OUT_TRIG0 will set when the counter..,?,59: PWM_OUT_TRIG0 will set when the counter..,?,61: PWM_OUT_TRIG0 will set when the counter..,?,63: PWM_OUT_TRIG0 will set when the counter.." group.word 0x2C++0x01 line.word 0x00 "SM0DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x30++0x01 line.word 0x00 "SM0DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. "DTCNT0,Deadtime Count Register 0" group.word 0x32++0x01 line.word 0x00 "SM0DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. "DTCNT1,Deadtime Count Register 1" group.word 0x34++0x01 line.word 0x00 "SM0CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x36++0x01 line.word 0x00 "SM0CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A" group.word 0x38++0x01 line.word 0x00 "SM0CAPTCTRLB,Capture Control B Register" rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x3A++0x01 line.word 0x00 "SM0CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B" group.word 0x3C++0x01 line.word 0x00 "SM0CAPTCTRLX,Capture Control X Register" rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x3E++0x01 line.word 0x00 "SM0CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X" rgroup.word 0x40++0x01 line.word 0x00 "SM0CVAL0,Capture Value 0 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0" rgroup.word 0x42++0x01 line.word 0x00 "SM0CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x44++0x01 line.word 0x00 "SM0CVAL1,Capture Value 1 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1" rgroup.word 0x46++0x01 line.word 0x00 "SM0CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x48++0x01 line.word 0x00 "SM0CVAL2,Capture Value 2 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2" rgroup.word 0x4A++0x01 line.word 0x00 "SM0CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x4C++0x01 line.word 0x00 "SM0CVAL3,Capture Value 3 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3" rgroup.word 0x4E++0x01 line.word 0x00 "SM0CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x50++0x01 line.word 0x00 "SM0CVAL4,Capture Value 4 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4" rgroup.word 0x52++0x01 line.word 0x00 "SM0CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x54++0x01 line.word 0x00 "SM0CVAL5,Capture Value 5 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5" rgroup.word 0x56++0x01 line.word 0x00 "SM0CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x5A++0x01 line.word 0x00 "SM0CAPTFILTA,Capture PWMA Input Filter Register" bitfld.word 0x00 8.--10. "CAPTA_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTA_FILT_PER,Fault Filter Period" group.word 0x5C++0x01 line.word 0x00 "SM0CAPTFILTB,Capture PWMB Input Filter Register" bitfld.word 0x00 8.--10. "CAPTB_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTB_FILT_PER,Fault Filter Period" group.word 0x5E++0x01 line.word 0x00 "SM0CAPTFILTX,Capture PWMX Input Filter Register" bitfld.word 0x00 8.--10. "CAPTX_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTX_FILT_PER,Fault Filter Period" rgroup.word 0x60++0x01 line.word 0x00 "SM1CNT,Counter Register" hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits" group.word 0x62++0x01 line.word 0x00 "SM1INIT,Initial Count Register" hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits" group.word 0x64++0x01 line.word 0x00 "SM1CTRL2,Control 2 Register" bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1" bitfld.word 0x00 14. "WAITEN,Sleep Enable" "0,1" newline bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs" bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1" newline bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1" bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1" newline bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization" bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled" newline bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1" bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.." newline bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).." bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..." group.word 0x66++0x01 line.word 0x00 "SM1CTRL,Control Register" bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities" bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled" newline bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled" rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3" newline bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.." bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: Prescaler 1,1: Prescaler 2,2: Prescaler 4,3: Prescaler 8,4: Prescaler 16,5: Prescaler 32,6: Prescaler 64,7: HUNDREDTWENTYEIGHT" newline bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB" bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.." newline bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled" bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled" group.word 0x6A++0x01 line.word 0x00 "SM1VAL0,Value Register 0" hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0" group.word 0x6C++0x01 line.word 0x00 "SM1FRACVAL1,Fractional Value Register 1" bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x6E++0x01 line.word 0x00 "SM1VAL1,Value Register 1" hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1" group.word 0x70++0x01 line.word 0x00 "SM1FRACVAL2,Fractional Value Register 2" bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x72++0x01 line.word 0x00 "SM1VAL2,Value Register 2" hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2" group.word 0x74++0x01 line.word 0x00 "SM1FRACVAL3,Fractional Value Register 3" bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x76++0x01 line.word 0x00 "SM1VAL3,Value Register 3" hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3" group.word 0x78++0x01 line.word 0x00 "SM1FRACVAL4,Fractional Value Register 4" bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x7A++0x01 line.word 0x00 "SM1VAL4,Value Register 4" hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4" group.word 0x7C++0x01 line.word 0x00 "SM1FRACVAL5,Fractional Value Register 5" bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x7E++0x01 line.word 0x00 "SM1VAL5,Value Register 5" hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5" group.word 0x80++0x01 line.word 0x00 "SM1FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1" bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B" newline bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A" bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.." group.word 0x82++0x01 line.word 0x00 "SM1OCTRL,Output Control Register" rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1" rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1" newline rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1" bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted" newline bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted" bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted" newline bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" newline bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" group.word 0x84++0x01 line.word 0x00 "SM1STS,Status Register" rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.." eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.." newline eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing" eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1" newline eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1" eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1" newline eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1" eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1" newline eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1" eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..." group.word 0x86++0x01 line.word 0x00 "SM1INTEN,Interrupt Enable Register" bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled" bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled" newline bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]" bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]" newline bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]" bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]" newline bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]" bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]" newline bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..." group.word 0x88++0x01 line.word 0x00 "SM1DMAEN,DMA Enable Register" bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: ENABLED" bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together" newline bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.." bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1" bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1" bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1" group.word 0x8A++0x01 line.word 0x00 "SM1TCTRL,Output Trigger Control Register" bitfld.word 0x00 15. "PWAOT0,Mux Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_MUX_TRIG0 port" bitfld.word 0x00 14. "PWBOT1,Mux Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_MUX_TRIG1 port" newline bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.." bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "?,1: PWM_OUT_TRIG0 will set when the counter value..,?,3: PWM_OUT_TRIG0 will set when the counter value..,?,5: PWM_OUT_TRIG0 will set when the counter value..,?,7: PWM_OUT_TRIG0 will set when the counter value..,?,9: PWM_OUT_TRIG0 will set when the counter value..,?,11: PWM_OUT_TRIG0 will set when the counter..,?,13: PWM_OUT_TRIG0 will set when the counter..,?,15: PWM_OUT_TRIG0 will set when the counter..,?,17: PWM_OUT_TRIG0 will set when the counter..,?,19: PWM_OUT_TRIG0 will set when the counter..,?,21: PWM_OUT_TRIG0 will set when the counter..,?,23: PWM_OUT_TRIG0 will set when the counter..,?,25: PWM_OUT_TRIG0 will set when the counter..,?,27: PWM_OUT_TRIG0 will set when the counter..,?,29: PWM_OUT_TRIG0 will set when the counter..,?,31: PWM_OUT_TRIG0 will set when the counter..,?,33: PWM_OUT_TRIG0 will set when the counter..,?,35: PWM_OUT_TRIG0 will set when the counter..,?,37: PWM_OUT_TRIG0 will set when the counter..,?,39: PWM_OUT_TRIG0 will set when the counter..,?,41: PWM_OUT_TRIG0 will set when the counter..,?,43: PWM_OUT_TRIG0 will set when the counter..,?,45: PWM_OUT_TRIG0 will set when the counter..,?,47: PWM_OUT_TRIG0 will set when the counter..,?,49: PWM_OUT_TRIG0 will set when the counter..,?,51: PWM_OUT_TRIG0 will set when the counter..,?,53: PWM_OUT_TRIG0 will set when the counter..,?,55: PWM_OUT_TRIG0 will set when the counter..,?,57: PWM_OUT_TRIG0 will set when the counter..,?,59: PWM_OUT_TRIG0 will set when the counter..,?,61: PWM_OUT_TRIG0 will set when the counter..,?,63: PWM_OUT_TRIG0 will set when the counter.." group.word 0x8C++0x01 line.word 0x00 "SM1DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x90++0x01 line.word 0x00 "SM1DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. "DTCNT0,Deadtime Count Register 0" group.word 0x92++0x01 line.word 0x00 "SM1DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. "DTCNT1,Deadtime Count Register 1" group.word 0x94++0x01 line.word 0x00 "SM1CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x96++0x01 line.word 0x00 "SM1CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A" group.word 0x98++0x01 line.word 0x00 "SM1CAPTCTRLB,Capture Control B Register" rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x9A++0x01 line.word 0x00 "SM1CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B" group.word 0x9C++0x01 line.word 0x00 "SM1CAPTCTRLX,Capture Control X Register" rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x9E++0x01 line.word 0x00 "SM1CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X" rgroup.word 0xA0++0x01 line.word 0x00 "SM1CVAL0,Capture Value 0 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0" rgroup.word 0xA2++0x01 line.word 0x00 "SM1CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA4++0x01 line.word 0x00 "SM1CVAL1,Capture Value 1 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1" rgroup.word 0xA6++0x01 line.word 0x00 "SM1CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xA8++0x01 line.word 0x00 "SM1CVAL2,Capture Value 2 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2" rgroup.word 0xAA++0x01 line.word 0x00 "SM1CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xAC++0x01 line.word 0x00 "SM1CVAL3,Capture Value 3 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3" rgroup.word 0xAE++0x01 line.word 0x00 "SM1CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xB0++0x01 line.word 0x00 "SM1CVAL4,Capture Value 4 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4" rgroup.word 0xB2++0x01 line.word 0x00 "SM1CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0xB4++0x01 line.word 0x00 "SM1CVAL5,Capture Value 5 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5" rgroup.word 0xB6++0x01 line.word 0x00 "SM1CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xB8++0x01 line.word 0x00 "SM1PHASEDLY,Phase Delay Register" hexmask.word 0x00 0.--15. 1. "PHASEDLY,Initial Count Register Bits" group.word 0xBA++0x01 line.word 0x00 "SM1CAPTFILTA,Capture PWMA Input Filter Register" bitfld.word 0x00 8.--10. "CAPTA_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTA_FILT_PER,Fault Filter Period" group.word 0xBC++0x01 line.word 0x00 "SM1CAPTFILTB,Capture PWMB Input Filter Register" bitfld.word 0x00 8.--10. "CAPTB_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTB_FILT_PER,Fault Filter Period" group.word 0xBE++0x01 line.word 0x00 "SM1CAPTFILTX,Capture PWMX Input Filter Register" bitfld.word 0x00 8.--10. "CAPTX_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTX_FILT_PER,Fault Filter Period" rgroup.word 0xC0++0x01 line.word 0x00 "SM2CNT,Counter Register" hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits" group.word 0xC2++0x01 line.word 0x00 "SM2INIT,Initial Count Register" hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits" group.word 0xC4++0x01 line.word 0x00 "SM2CTRL2,Control 2 Register" bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1" bitfld.word 0x00 14. "WAITEN,Sleep Enable" "0,1" newline bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs" bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1" newline bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1" bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1" newline bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization" bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled" newline bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1" bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.." newline bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).." bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..." group.word 0xC6++0x01 line.word 0x00 "SM2CTRL,Control Register" bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities" bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled" newline bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled" rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3" newline bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.." bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: Prescaler 1,1: Prescaler 2,2: Prescaler 4,3: Prescaler 8,4: Prescaler 16,5: Prescaler 32,6: Prescaler 64,7: HUNDREDTWENTYEIGHT" newline bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB" bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.." newline bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled" bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled" group.word 0xCA++0x01 line.word 0x00 "SM2VAL0,Value Register 0" hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0" group.word 0xCC++0x01 line.word 0x00 "SM2FRACVAL1,Fractional Value Register 1" bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0xCE++0x01 line.word 0x00 "SM2VAL1,Value Register 1" hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1" group.word 0xD0++0x01 line.word 0x00 "SM2FRACVAL2,Fractional Value Register 2" bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0xD2++0x01 line.word 0x00 "SM2VAL2,Value Register 2" hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2" group.word 0xD4++0x01 line.word 0x00 "SM2FRACVAL3,Fractional Value Register 3" bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0xD6++0x01 line.word 0x00 "SM2VAL3,Value Register 3" hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3" group.word 0xD8++0x01 line.word 0x00 "SM2FRACVAL4,Fractional Value Register 4" bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0xDA++0x01 line.word 0x00 "SM2VAL4,Value Register 4" hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4" group.word 0xDC++0x01 line.word 0x00 "SM2FRACVAL5,Fractional Value Register 5" bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0xDE++0x01 line.word 0x00 "SM2VAL5,Value Register 5" hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5" group.word 0xE0++0x01 line.word 0x00 "SM2FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1" bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B" newline bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A" bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.." group.word 0xE2++0x01 line.word 0x00 "SM2OCTRL,Output Control Register" rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1" rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1" newline rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1" bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted" newline bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted" bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted" newline bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" newline bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" group.word 0xE4++0x01 line.word 0x00 "SM2STS,Status Register" rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.." eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.." newline eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing" eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1" newline eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1" eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1" newline eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1" eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1" newline eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1" eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..." group.word 0xE6++0x01 line.word 0x00 "SM2INTEN,Interrupt Enable Register" bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled" bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled" newline bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]" bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]" newline bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]" bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]" newline bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]" bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]" newline bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..." group.word 0xE8++0x01 line.word 0x00 "SM2DMAEN,DMA Enable Register" bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: ENABLED" bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together" newline bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.." bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1" bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1" bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1" group.word 0xEA++0x01 line.word 0x00 "SM2TCTRL,Output Trigger Control Register" bitfld.word 0x00 15. "PWAOT0,Mux Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_MUX_TRIG0 port" bitfld.word 0x00 14. "PWBOT1,Mux Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_MUX_TRIG1 port" newline bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.." bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "?,1: PWM_OUT_TRIG0 will set when the counter value..,?,3: PWM_OUT_TRIG0 will set when the counter value..,?,5: PWM_OUT_TRIG0 will set when the counter value..,?,7: PWM_OUT_TRIG0 will set when the counter value..,?,9: PWM_OUT_TRIG0 will set when the counter value..,?,11: PWM_OUT_TRIG0 will set when the counter..,?,13: PWM_OUT_TRIG0 will set when the counter..,?,15: PWM_OUT_TRIG0 will set when the counter..,?,17: PWM_OUT_TRIG0 will set when the counter..,?,19: PWM_OUT_TRIG0 will set when the counter..,?,21: PWM_OUT_TRIG0 will set when the counter..,?,23: PWM_OUT_TRIG0 will set when the counter..,?,25: PWM_OUT_TRIG0 will set when the counter..,?,27: PWM_OUT_TRIG0 will set when the counter..,?,29: PWM_OUT_TRIG0 will set when the counter..,?,31: PWM_OUT_TRIG0 will set when the counter..,?,33: PWM_OUT_TRIG0 will set when the counter..,?,35: PWM_OUT_TRIG0 will set when the counter..,?,37: PWM_OUT_TRIG0 will set when the counter..,?,39: PWM_OUT_TRIG0 will set when the counter..,?,41: PWM_OUT_TRIG0 will set when the counter..,?,43: PWM_OUT_TRIG0 will set when the counter..,?,45: PWM_OUT_TRIG0 will set when the counter..,?,47: PWM_OUT_TRIG0 will set when the counter..,?,49: PWM_OUT_TRIG0 will set when the counter..,?,51: PWM_OUT_TRIG0 will set when the counter..,?,53: PWM_OUT_TRIG0 will set when the counter..,?,55: PWM_OUT_TRIG0 will set when the counter..,?,57: PWM_OUT_TRIG0 will set when the counter..,?,59: PWM_OUT_TRIG0 will set when the counter..,?,61: PWM_OUT_TRIG0 will set when the counter..,?,63: PWM_OUT_TRIG0 will set when the counter.." group.word 0xEC++0x01 line.word 0x00 "SM2DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xF0++0x01 line.word 0x00 "SM2DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. "DTCNT0,Deadtime Count Register 0" group.word 0xF2++0x01 line.word 0x00 "SM2DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. "DTCNT1,Deadtime Count Register 1" group.word 0xF4++0x01 line.word 0x00 "SM2CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0xF6++0x01 line.word 0x00 "SM2CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A" group.word 0xF8++0x01 line.word 0x00 "SM2CAPTCTRLB,Capture Control B Register" rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0xFA++0x01 line.word 0x00 "SM2CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B" group.word 0xFC++0x01 line.word 0x00 "SM2CAPTCTRLX,Capture Control X Register" rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0xFE++0x01 line.word 0x00 "SM2CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X" rgroup.word 0x100++0x01 line.word 0x00 "SM2CVAL0,Capture Value 0 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0" rgroup.word 0x102++0x01 line.word 0x00 "SM2CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x104++0x01 line.word 0x00 "SM2CVAL1,Capture Value 1 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1" rgroup.word 0x106++0x01 line.word 0x00 "SM2CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x108++0x01 line.word 0x00 "SM2CVAL2,Capture Value 2 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2" rgroup.word 0x10A++0x01 line.word 0x00 "SM2CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x10C++0x01 line.word 0x00 "SM2CVAL3,Capture Value 3 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3" rgroup.word 0x10E++0x01 line.word 0x00 "SM2CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x110++0x01 line.word 0x00 "SM2CVAL4,Capture Value 4 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4" rgroup.word 0x112++0x01 line.word 0x00 "SM2CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x114++0x01 line.word 0x00 "SM2CVAL5,Capture Value 5 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5" rgroup.word 0x116++0x01 line.word 0x00 "SM2CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x118++0x01 line.word 0x00 "SM2PHASEDLY,Phase Delay Register" hexmask.word 0x00 0.--15. 1. "PHASEDLY,Initial Count Register Bits" group.word 0x11A++0x01 line.word 0x00 "SM2CAPTFILTA,Capture PWMA Input Filter Register" bitfld.word 0x00 8.--10. "CAPTA_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTA_FILT_PER,Fault Filter Period" group.word 0x11C++0x01 line.word 0x00 "SM2CAPTFILTB,Capture PWMB Input Filter Register" bitfld.word 0x00 8.--10. "CAPTB_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTB_FILT_PER,Fault Filter Period" group.word 0x11E++0x01 line.word 0x00 "SM2CAPTFILTX,Capture PWMX Input Filter Register" bitfld.word 0x00 8.--10. "CAPTX_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTX_FILT_PER,Fault Filter Period" rgroup.word 0x120++0x01 line.word 0x00 "SM3CNT,Counter Register" hexmask.word 0x00 0.--15. 1. "CNT,Counter Register Bits" group.word 0x122++0x01 line.word 0x00 "SM3INIT,Initial Count Register" hexmask.word 0x00 0.--15. 1. "INIT,Initial Count Register Bits" group.word 0x124++0x01 line.word 0x00 "SM3CTRL2,Control 2 Register" bitfld.word 0x00 15. "DBGEN,Debug Enable" "0,1" bitfld.word 0x00 14. "WAITEN,Sleep Enable" "0,1" newline bitfld.word 0x00 13. "INDEP,Independent or Complementary Pair Operation" "0: PWM_A and PWM_B form a complementary PWM pair,1: PWM_A and PWM_B outputs are independent PWMs" bitfld.word 0x00 12. "PWM23_INIT,PWM23 Initial Value" "0,1" newline bitfld.word 0x00 11. "PWM45_INIT,PWM45 Initial Value" "0,1" bitfld.word 0x00 10. "PWMX_INIT,PWM_X Initial Value" "0,1" newline bitfld.word 0x00 8.--9. "INIT_SEL,Initialization Control Select" "0: Local sync (PWM_X) causes initialization,1: Master reload from submodule 0 causes..,2: Master sync from submodule 0 causes..,3: EXT_SYNC causes initialization" bitfld.word 0x00 7. "FRCEN,FRCEN" "0: Initialization from a FORCE_OUT is disabled,1: Initialization from a FORCE_OUT is enabled" newline bitfld.word 0x00 6. "FORCE,Force Initialization" "0,1" bitfld.word 0x00 3.--5. "FORCE_SEL,This read/write bit determines the source of the FORCE OUTPUT signal for this submodule" "0: The local force signal CTRL2[FORCE] from this..,1: The master force signal from submodule 0 is..,2: The local reload signal from this submodule..,3: The master reload signal from submodule0 is..,4: The local sync signal from this submodule is..,5: The master sync signal from submodule0 is..,6: The external force signal EXT_FORCE from..,7: The external sync signal EXT_SYNC from.." newline bitfld.word 0x00 2. "RELOAD_SEL,Reload Source Select" "0: The local RELOAD signal is used to reload..,1: The master RELOAD signal (from submodule 0).." bitfld.word 0x00 0.--1. "CLK_SEL,Clock Source Select" "0: The IPBus clock is used as the clock for the..,1: EXT_CLK is used as the clock for the local..,2: Submodule 0's clock (AUX_CLK) is used as the..,?..." group.word 0x126++0x01 line.word 0x00 "SM3CTRL,Control Register" bitfld.word 0x00 12.--15. "LDFQ,Load Frequency" "0: Every PWM opportunity,1: Every 2 PWM opportunities,2: Every 3 PWM opportunities,3: Every 4 PWM opportunities,4: Every 5 PWM opportunities,5: Every 6 PWM opportunities,6: Every 7 PWM opportunities,7: Every 8 PWM opportunities,8: Every 9 PWM opportunities,9: Every 10 PWM opportunities,10: Every 11 PWM opportunities,11: Every 12 PWM opportunities,12: Every 13 PWM opportunities,13: Every 14 PWM opportunities,14: Every 15 PWM opportunities,15: Every 16 PWM opportunities" bitfld.word 0x00 11. "HALF,Half Cycle Reload" "0: Half-cycle reloads disabled,1: Half-cycle reloads enabled" newline bitfld.word 0x00 10. "FULL,Full Cycle Reload" "0: Full-cycle reloads disabled,1: Full-cycle reloads enabled" rbitfld.word 0x00 8.--9. "DT,Deadtime" "0,1,2,3" newline bitfld.word 0x00 7. "COMPMODE,Compare Mode" "0: The VAL* registers and the PWM counter are..,1: The VAL* registers and the PWM counter are.." bitfld.word 0x00 4.--6. "PRSC,Prescaler" "0: Prescaler 1,1: Prescaler 2,2: Prescaler 4,3: Prescaler 8,4: Prescaler 16,5: Prescaler 32,6: Prescaler 64,7: HUNDREDTWENTYEIGHT" newline bitfld.word 0x00 3. "SPLIT,Split the DBLPWM signal to PWMA and PWMB" "0: DBLPWM is not split,1: DBLPWM is split to PWMA and PWMB" bitfld.word 0x00 2. "LDMOD,Load Mode Select" "0: Buffered registers of this submodule are..,1: Buffered registers of this submodule are.." newline bitfld.word 0x00 1. "DBLX,PWMX Double Switching Enable" "0: PWMX double pulse disabled,1: PWMX double pulse enabled" bitfld.word 0x00 0. "DBLEN,Double Switching Enable" "0: Double switching disabled,1: Double switching enabled" group.word 0x12A++0x01 line.word 0x00 "SM3VAL0,Value Register 0" hexmask.word 0x00 0.--15. 1. "VAL0,Value Register 0" group.word 0x12C++0x01 line.word 0x00 "SM3FRACVAL1,Fractional Value Register 1" bitfld.word 0x00 11.--15. "FRACVAL1,Fractional Value 1 Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x12E++0x01 line.word 0x00 "SM3VAL1,Value Register 1" hexmask.word 0x00 0.--15. 1. "VAL1,Value Register 1" group.word 0x130++0x01 line.word 0x00 "SM3FRACVAL2,Fractional Value Register 2" bitfld.word 0x00 11.--15. "FRACVAL2,Fractional Value 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x132++0x01 line.word 0x00 "SM3VAL2,Value Register 2" hexmask.word 0x00 0.--15. 1. "VAL2,Value Register 2" group.word 0x134++0x01 line.word 0x00 "SM3FRACVAL3,Fractional Value Register 3" bitfld.word 0x00 11.--15. "FRACVAL3,Fractional Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x136++0x01 line.word 0x00 "SM3VAL3,Value Register 3" hexmask.word 0x00 0.--15. 1. "VAL3,Value Register 3" group.word 0x138++0x01 line.word 0x00 "SM3FRACVAL4,Fractional Value Register 4" bitfld.word 0x00 11.--15. "FRACVAL4,Fractional Value 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x13A++0x01 line.word 0x00 "SM3VAL4,Value Register 4" hexmask.word 0x00 0.--15. 1. "VAL4,Value Register 4" group.word 0x13C++0x01 line.word 0x00 "SM3FRACVAL5,Fractional Value Register 5" bitfld.word 0x00 11.--15. "FRACVAL5,Fractional Value 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x13E++0x01 line.word 0x00 "SM3VAL5,Value Register 5" hexmask.word 0x00 0.--15. 1. "VAL5,Value Register 5" group.word 0x140++0x01 line.word 0x00 "SM3FRCTRL,Fractional Control Register" rbitfld.word 0x00 15. "TEST,Test Status Bit" "0,1" bitfld.word 0x00 4. "FRAC45_EN,Fractional Cycle Placement Enable for PWM_B" "0: Disable fractional cycle placement for PWM_B,1: Enable fractional cycle placement for PWM_B" newline bitfld.word 0x00 2. "FRAC23_EN,Fractional Cycle Placement Enable for PWM_A" "0: Disable fractional cycle placement for PWM_A,1: Enable fractional cycle placement for PWM_A" bitfld.word 0x00 1. "FRAC1_EN,Fractional Cycle PWM Period Enable" "0: Disable fractional cycle length for the PWM..,1: Enable fractional cycle length for the PWM.." group.word 0x142++0x01 line.word 0x00 "SM3OCTRL,Output Control Register" rbitfld.word 0x00 15. "PWMA_IN,PWM_A Input" "0,1" rbitfld.word 0x00 14. "PWMB_IN,PWM_B Input" "0,1" newline rbitfld.word 0x00 13. "PWMX_IN,PWM_X Input" "0,1" bitfld.word 0x00 10. "POLA,PWM_A Output Polarity" "0: PWM_A output not inverted,1: PWM_A output inverted" newline bitfld.word 0x00 9. "POLB,PWM_B Output Polarity" "0: PWM_B output not inverted,1: PWM_B output inverted" bitfld.word 0x00 8. "POLX,PWM_X Output Polarity" "0: PWM_X output not inverted,1: PWM_X output inverted" newline bitfld.word 0x00 4.--5. "PWMAFS,PWM_A Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" bitfld.word 0x00 2.--3. "PWMBFS,PWM_B Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" newline bitfld.word 0x00 0.--1. "PWMXFS,PWM_X Fault State" "0: Output is forced to logic 0 state prior to..,1: Output is forced to logic 1 state prior to..,2: Output is tristated,3: Output is tristated" group.word 0x144++0x01 line.word 0x00 "SM3STS,Status Register" rbitfld.word 0x00 14. "RUF,Registers Updated Flag" "0: No register update has occurred since last..,1: At least one of the double buffered registers.." eventfld.word 0x00 13. "REF,Reload Error Flag" "0: No reload error occurred,1: Reload signal occurred with non-coherent data.." newline eventfld.word 0x00 12. "RF,Reload Flag" "0: No new reload cycle since last STS[RF] clearing,1: New reload cycle since last STS[RF] clearing" eventfld.word 0x00 11. "CFA1,Capture Flag A1" "0,1" newline eventfld.word 0x00 10. "CFA0,Capture Flag A0" "0,1" eventfld.word 0x00 9. "CFB1,Capture Flag B1" "0,1" newline eventfld.word 0x00 8. "CFB0,Capture Flag B0" "0,1" eventfld.word 0x00 7. "CFX1,Capture Flag X1" "0,1" newline eventfld.word 0x00 6. "CFX0,Capture Flag X0" "0,1" eventfld.word 0x00 0.--5. "CMPF,Compare Flags" "0: No compare event has occurred for a..,1: A compare event has occurred for a particular..,?..." group.word 0x146++0x01 line.word 0x00 "SM3INTEN,Interrupt Enable Register" bitfld.word 0x00 13. "REIE,Reload Error Interrupt Enable" "0: STS[REF] CPU interrupt requests disabled,1: STS[REF] CPU interrupt requests enabled" bitfld.word 0x00 12. "RIE,Reload Interrupt Enable" "0: STS[RF] CPU interrupt requests disabled,1: STS[RF] CPU interrupt requests enabled" newline bitfld.word 0x00 11. "CA1IE,Capture A 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFA1],1: Interrupt request enabled for STS[CFA1]" bitfld.word 0x00 10. "CA0IE,Capture A 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFA0],1: Interrupt request enabled for STS[CFA0]" newline bitfld.word 0x00 9. "CB1IE,Capture B 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFB1],1: Interrupt request enabled for STS[CFB1]" bitfld.word 0x00 8. "CB0IE,Capture B 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFB0],1: Interrupt request enabled for STS[CFB0]" newline bitfld.word 0x00 7. "CX1IE,Capture X 1 Interrupt Enable" "0: Interrupt request disabled for STS[CFX1],1: Interrupt request enabled for STS[CFX1]" bitfld.word 0x00 6. "CX0IE,Capture X 0 Interrupt Enable" "0: Interrupt request disabled for STS[CFX0],1: Interrupt request enabled for STS[CFX0]" newline bitfld.word 0x00 0.--5. "CMPIE,Compare Interrupt Enables" "0: The corresponding STS[CMPF] bit will not..,1: The corresponding STS[CMPF] bit will cause an..,?..." group.word 0x148++0x01 line.word 0x00 "SM3DMAEN,DMA Enable Register" bitfld.word 0x00 9. "VALDE,Value Registers DMA Enable" "0: DMA write requests disabled,1: ENABLED" bitfld.word 0x00 8. "FAND,FIFO Watermark AND Control" "0: Selected FIFO watermarks are OR'ed together,1: Selected FIFO watermarks are AND'ed together" newline bitfld.word 0x00 6.--7. "CAPTDE,Capture DMA Enable Source Select" "0: Read DMA requests disabled,1: Exceeding a FIFO watermark sets the DMA read..,2: A local sync (VAL1 matches counter) sets the..,3: A local reload (STS[RF] being set) sets the.." bitfld.word 0x00 5. "CA1DE,Capture A1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 4. "CA0DE,Capture A0 FIFO DMA Enable" "0,1" bitfld.word 0x00 3. "CB1DE,Capture B1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 2. "CB0DE,Capture B0 FIFO DMA Enable" "0,1" bitfld.word 0x00 1. "CX1DE,Capture X1 FIFO DMA Enable" "0,1" newline bitfld.word 0x00 0. "CX0DE,Capture X0 FIFO DMA Enable" "0,1" group.word 0x14A++0x01 line.word 0x00 "SM3TCTRL,Output Trigger Control Register" bitfld.word 0x00 15. "PWAOT0,Mux Output Trigger 0 Source Select" "0: Route the PWM_OUT_TRIG0 signal to..,1: Route the PWMA output to the PWM_MUX_TRIG0 port" bitfld.word 0x00 14. "PWBOT1,Mux Output Trigger 1 Source Select" "0: Route the PWM_OUT_TRIG1 signal to..,1: Route the PWMB output to the PWM_MUX_TRIG1 port" newline bitfld.word 0x00 12. "TRGFRQ,Trigger frequency" "0: Trigger outputs are generated during every..,1: Trigger outputs are generated only during the.." bitfld.word 0x00 0.--5. "OUT_TRIG_EN,Output Trigger Enables" "?,1: PWM_OUT_TRIG0 will set when the counter value..,?,3: PWM_OUT_TRIG0 will set when the counter value..,?,5: PWM_OUT_TRIG0 will set when the counter value..,?,7: PWM_OUT_TRIG0 will set when the counter value..,?,9: PWM_OUT_TRIG0 will set when the counter value..,?,11: PWM_OUT_TRIG0 will set when the counter..,?,13: PWM_OUT_TRIG0 will set when the counter..,?,15: PWM_OUT_TRIG0 will set when the counter..,?,17: PWM_OUT_TRIG0 will set when the counter..,?,19: PWM_OUT_TRIG0 will set when the counter..,?,21: PWM_OUT_TRIG0 will set when the counter..,?,23: PWM_OUT_TRIG0 will set when the counter..,?,25: PWM_OUT_TRIG0 will set when the counter..,?,27: PWM_OUT_TRIG0 will set when the counter..,?,29: PWM_OUT_TRIG0 will set when the counter..,?,31: PWM_OUT_TRIG0 will set when the counter..,?,33: PWM_OUT_TRIG0 will set when the counter..,?,35: PWM_OUT_TRIG0 will set when the counter..,?,37: PWM_OUT_TRIG0 will set when the counter..,?,39: PWM_OUT_TRIG0 will set when the counter..,?,41: PWM_OUT_TRIG0 will set when the counter..,?,43: PWM_OUT_TRIG0 will set when the counter..,?,45: PWM_OUT_TRIG0 will set when the counter..,?,47: PWM_OUT_TRIG0 will set when the counter..,?,49: PWM_OUT_TRIG0 will set when the counter..,?,51: PWM_OUT_TRIG0 will set when the counter..,?,53: PWM_OUT_TRIG0 will set when the counter..,?,55: PWM_OUT_TRIG0 will set when the counter..,?,57: PWM_OUT_TRIG0 will set when the counter..,?,59: PWM_OUT_TRIG0 will set when the counter..,?,61: PWM_OUT_TRIG0 will set when the counter..,?,63: PWM_OUT_TRIG0 will set when the counter.." group.word 0x14C++0x01 line.word 0x00 "SM3DISMAP0,Fault Disable Mapping Register 0" bitfld.word 0x00 8.--11. "DIS0X,PWM_X Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. "DIS0B,PWM_B Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 0.--3. "DIS0A,PWM_A Fault Disable Mask 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x150++0x01 line.word 0x00 "SM3DTCNT0,Deadtime Count Register 0" hexmask.word 0x00 0.--10. 1. "DTCNT0,Deadtime Count Register 0" group.word 0x152++0x01 line.word 0x00 "SM3DTCNT1,Deadtime Count Register 1" hexmask.word 0x00 0.--10. 1. "DTCNT1,Deadtime Count Register 1" group.word 0x154++0x01 line.word 0x00 "SM3CAPTCTRLA,Capture Control A Register" rbitfld.word 0x00 13.--15. "CA1CNT,Capture A1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CA0CNT,Capture A0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFAWM,Capture A FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTA_EN,Edge Counter A Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELA,Input Select A" "0: Raw PWM_A input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGA1,Edge A 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGA0,Edge A 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTA,One Shot Mode A" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMA,Arm A" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x156++0x01 line.word 0x00 "SM3CAPTCOMPA,Capture Compare A Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTA,Edge Counter A" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPA,Edge Compare A" group.word 0x158++0x01 line.word 0x00 "SM3CAPTCTRLB,Capture Control B Register" rbitfld.word 0x00 13.--15. "CB1CNT,Capture B1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CB0CNT,Capture B0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFBWM,Capture B FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTB_EN,Edge Counter B Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELB,Input Select B" "0: Raw PWM_B input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGB1,Edge B 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGB0,Edge B 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTB,One Shot Mode B" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMB,Arm B" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x15A++0x01 line.word 0x00 "SM3CAPTCOMPB,Capture Compare B Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTB,Edge Counter B" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPB,Edge Compare B" group.word 0x15C++0x01 line.word 0x00 "SM3CAPTCTRLX,Capture Control X Register" rbitfld.word 0x00 13.--15. "CX1CNT,Capture X1 FIFO Word Count" "0,1,2,3,4,5,6,7" rbitfld.word 0x00 10.--12. "CX0CNT,Capture X0 FIFO Word Count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x00 8.--9. "CFXWM,Capture X FIFOs Water Mark" "0,1,2,3" bitfld.word 0x00 7. "EDGCNTX_EN,Edge Counter X Enable" "0: Edge counter disabled and held in reset,1: Edge counter enabled" newline bitfld.word 0x00 6. "INP_SELX,Input Select X" "0: Raw PWM_X input signal selected as source,1: EDGE_COUNTER" bitfld.word 0x00 4.--5. "EDGX1,Edge X 1" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" newline bitfld.word 0x00 2.--3. "EDGX0,Edge X 0" "0: DISABLED,1: Capture falling edges,2: Capture rising edges,3: Capture any edge" bitfld.word 0x00 1. "ONESHOTX,One Shot Mode Aux" "0: FREE_RUNNING,1: ONE_SHOT" newline bitfld.word 0x00 0. "ARMX,Arm X" "0: Input capture operation is disabled,1: Input capture operation as specified by.." group.word 0x15E++0x01 line.word 0x00 "SM3CAPTCOMPX,Capture Compare X Register" hexmask.word.byte 0x00 8.--15. 1. "EDGCNTX,Edge Counter X" hexmask.word.byte 0x00 0.--7. 1. "EDGCMPX,Edge Compare X" rgroup.word 0x160++0x01 line.word 0x00 "SM3CVAL0,Capture Value 0 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL0,CAPTVAL0" rgroup.word 0x162++0x01 line.word 0x00 "SM3CVAL0CYC,Capture Value 0 Cycle Register" bitfld.word 0x00 0.--3. "CVAL0CYC,CVAL0CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x164++0x01 line.word 0x00 "SM3CVAL1,Capture Value 1 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL1,CAPTVAL1" rgroup.word 0x166++0x01 line.word 0x00 "SM3CVAL1CYC,Capture Value 1 Cycle Register" bitfld.word 0x00 0.--3. "CVAL1CYC,CVAL1CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x168++0x01 line.word 0x00 "SM3CVAL2,Capture Value 2 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL2,CAPTVAL2" rgroup.word 0x16A++0x01 line.word 0x00 "SM3CVAL2CYC,Capture Value 2 Cycle Register" bitfld.word 0x00 0.--3. "CVAL2CYC,CVAL2CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x16C++0x01 line.word 0x00 "SM3CVAL3,Capture Value 3 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL3,CAPTVAL3" rgroup.word 0x16E++0x01 line.word 0x00 "SM3CVAL3CYC,Capture Value 3 Cycle Register" bitfld.word 0x00 0.--3. "CVAL3CYC,CVAL3CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x170++0x01 line.word 0x00 "SM3CVAL4,Capture Value 4 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL4,CAPTVAL4" rgroup.word 0x172++0x01 line.word 0x00 "SM3CVAL4CYC,Capture Value 4 Cycle Register" bitfld.word 0x00 0.--3. "CVAL4CYC,CVAL4CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x174++0x01 line.word 0x00 "SM3CVAL5,Capture Value 5 Register" hexmask.word 0x00 0.--15. 1. "CAPTVAL5,CAPTVAL5" rgroup.word 0x176++0x01 line.word 0x00 "SM3CVAL5CYC,Capture Value 5 Cycle Register" bitfld.word 0x00 0.--3. "CVAL5CYC,CVAL5CYC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x178++0x01 line.word 0x00 "SM3PHASEDLY,Phase Delay Register" hexmask.word 0x00 0.--15. 1. "PHASEDLY,Initial Count Register Bits" group.word 0x17A++0x01 line.word 0x00 "SM3CAPTFILTA,Capture PWMA Input Filter Register" bitfld.word 0x00 8.--10. "CAPTA_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTA_FILT_PER,Fault Filter Period" group.word 0x17C++0x01 line.word 0x00 "SM3CAPTFILTB,Capture PWMB Input Filter Register" bitfld.word 0x00 8.--10. "CAPTB_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTB_FILT_PER,Fault Filter Period" group.word 0x17E++0x01 line.word 0x00 "SM3CAPTFILTX,Capture PWMX Input Filter Register" bitfld.word 0x00 8.--10. "CAPTX_FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x00 0.--7. 1. "CAPTX_FILT_PER,Fault Filter Period" group.word 0x180++0x01 line.word 0x00 "OUTEN,Output Enable Register" bitfld.word 0x00 8.--11. "PWMA_EN,PWM_A Output Enables" "0: PWM_A output disabled,1: PWM_A output enabled,?..." bitfld.word 0x00 4.--7. "PWMB_EN,PWM_B Output Enables" "0: PWM_B output disabled,1: PWM_B output enabled,?..." newline bitfld.word 0x00 0.--3. "PWMX_EN,PWM_X Output Enables" "0: PWM_X output disabled,1: PWM_X output enabled,?..." group.word 0x182++0x01 line.word 0x00 "MASK,Mask Register" bitfld.word 0x00 12.--15. "UPDATE_MASK,Update Mask Bits Immediately" "0: Normal operation,1: Immediate operation,?..." bitfld.word 0x00 8.--11. "MASKA,PWM_A Masks" "0: PWM_A output normal,1: PWM_A output masked,?..." newline bitfld.word 0x00 4.--7. "MASKB,PWM_B Masks" "0: PWM_B output normal,1: PWM_B output masked,?..." bitfld.word 0x00 0.--3. "MASKX,PWM_X Masks" "0: PWM_X output normal,1: PWM_X output masked,?..." group.word 0x184++0x01 line.word 0x00 "SWCOUT,Software Controlled Output Register" bitfld.word 0x00 7. "SM3OUT23,Submodule 3 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." bitfld.word 0x00 6. "SM3OUT45,Submodule 3 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." newline bitfld.word 0x00 5. "SM2OUT23,Submodule 2 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." bitfld.word 0x00 4. "SM2OUT45,Submodule 2 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." newline bitfld.word 0x00 3. "SM1OUT23,Submodule 1 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." bitfld.word 0x00 2. "SM1OUT45,Submodule 1 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." newline bitfld.word 0x00 1. "SM0OUT23,Submodule 0 Software Controlled Output 23" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." bitfld.word 0x00 0. "SM0OUT45,Submodule 0 Software Controlled Output 45" "0: A logic 0 is supplied to the deadtime..,1: A logic 1 is supplied to the deadtime.." group.word 0x186++0x01 line.word 0x00 "DTSRCSEL,PWM Source Select Register" bitfld.word 0x00 14.--15. "SM3SEL23,Submodule 3 PWM23 Control Select" "0: Generated SM3PWM23 signal is used by the..,1: Inverted generated SM3PWM23 signal is used by..,2: SWCOUT[SM3OUT23] is used by the deadtime logic,3: PWM3_EXTA signal is used by the deadtime logic" bitfld.word 0x00 12.--13. "SM3SEL45,Submodule 3 PWM45 Control Select" "0: Generated SM3PWM45 signal is used by the..,1: Inverted generated SM3PWM45 signal is used by..,2: SWCOUT[SM3OUT45] is used by the deadtime logic,3: PWM3_EXTB signal is used by the deadtime logic" newline bitfld.word 0x00 10.--11. "SM2SEL23,Submodule 2 PWM23 Control Select" "0: Generated SM2PWM23 signal is used by the..,1: Inverted generated SM2PWM23 signal is used by..,2: SWCOUT[SM2OUT23] is used by the deadtime logic,3: PWM2_EXTA signal is used by the deadtime logic" bitfld.word 0x00 8.--9. "SM2SEL45,Submodule 2 PWM45 Control Select" "0: Generated SM2PWM45 signal is used by the..,1: Inverted generated SM2PWM45 signal is used by..,2: SWCOUT[SM2OUT45] is used by the deadtime logic,3: PWM2_EXTB signal is used by the deadtime logic" newline bitfld.word 0x00 6.--7. "SM1SEL23,Submodule 1 PWM23 Control Select" "0: Generated SM1PWM23 signal is used by the..,1: Inverted generated SM1PWM23 signal is used by..,2: SWCOUT[SM1OUT23] is used by the deadtime logic,3: PWM1_EXTA signal is used by the deadtime logic" bitfld.word 0x00 4.--5. "SM1SEL45,Submodule 1 PWM45 Control Select" "0: Generated SM1PWM45 signal is used by the..,1: Inverted generated SM1PWM45 signal is used by..,2: SWCOUT[SM1OUT45] is used by the deadtime logic,3: PWM1_EXTB signal is used by the deadtime logic" newline bitfld.word 0x00 2.--3. "SM0SEL23,Submodule 0 PWM23 Control Select" "0: Generated SM0PWM23 signal is used by the..,1: Inverted generated SM0PWM23 signal is used by..,2: SWCOUT[SM0OUT23] is used by the deadtime logic,3: PWM0_EXTA signal is used by the deadtime logic" bitfld.word 0x00 0.--1. "SM0SEL45,Submodule 0 PWM45 Control Select" "0: Generated SM0PWM45 signal is used by the..,1: Inverted generated SM0PWM45 signal is used by..,2: SWCOUT[SM0OUT45] is used by the deadtime logic,3: PWM0_EXTB signal is used by the deadtime logic" group.word 0x188++0x01 line.word 0x00 "MCTRL,Master Control Register" bitfld.word 0x00 12.--15. "IPOL,Current Polarity" "0: PWM23 is used to generate complementary PWM..,1: PWM45 is used to generate complementary PWM..,?..." bitfld.word 0x00 8.--11. "RUN,Run" "0: PWM counter is stopped but PWM outputs will..,1: PWM counter is started in the corresponding..,?..." newline bitfld.word 0x00 4.--7. "CLDOK,Clear Load Okay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. "LDOK,Load Okay" "0: Do not load new values,1: Load prescaler modulus and PWM values of the..,?..." group.word 0x18A++0x01 line.word 0x00 "MCTRL2,Master Control 2 Register" bitfld.word 0x00 0.--1. "MONPLL,Monitor PLL State" "0: Not locked,1: Not locked,2: Locked,3: Locked" group.word 0x18C++0x01 line.word 0x00 "FCTRL0,Fault Control Register" bitfld.word 0x00 12.--15. "FLVL,Fault Level" "0: A logic 0 on the fault input indicates a..,1: A logic 1 on the fault input indicates a..,?..." bitfld.word 0x00 8.--11. "FAUTO,Automatic Fault Clearing" "0: Manual fault clearing,1: Automatic fault clearing,?..." newline bitfld.word 0x00 4.--7. "FSAFE,Fault Safety Mode" "0: Normal mode,1: Safe mode,?..." bitfld.word 0x00 0.--3. "FIE,Fault Interrupt Enables" "0: FAULTx CPU interrupt requests disabled,1: FAULTx CPU interrupt requests enabled,?..." group.word 0x18E++0x01 line.word 0x00 "FSTS0,Fault Status Register" bitfld.word 0x00 12.--15. "FHALF,Half Cycle Fault Recovery" "0: PWM outputs are not re-enabled at the start..,1: PWM outputs are re-enabled at the start of a..,?..." rbitfld.word 0x00 8.--11. "FFPIN,Filtered Fault Pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.word 0x00 4.--7. "FFULL,Full Cycle" "0: PWM outputs are not re-enabled at the start..,1: PWM outputs are re-enabled at the start of a..,?..." bitfld.word 0x00 0.--3. "FFLAG,Fault Flags" "0: No fault on the FAULTx pin,1: Fault on the FAULTx pin,?..." group.word 0x190++0x01 line.word 0x00 "FFILT0,Fault Filter Register" bitfld.word 0x00 15. "GSTR,Fault Glitch Stretch Enable" "0: Fault input glitch stretching is disabled,1: Input fault signals will be stretched to at.." bitfld.word 0x00 8.--10. "FILT_CNT,Fault Filter Count" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x00 0.--7. 1. "FILT_PER,Fault Filter Period" group.word 0x192++0x01 line.word 0x00 "FTST0,Fault Test Register" bitfld.word 0x00 0. "FTEST,Fault Test" "0: NO_FAULT,1: Cause a simulated fault" group.word 0x194++0x01 line.word 0x00 "FCTRL20,Fault Control 2 Register" bitfld.word 0x00 0.--3. "NOCOMB,No Combinational Path From Fault Input To PWM Output" "0: There is a combinational link from the fault..,1: The direct combinational path from the fault..,?..." tree.end repeat.end tree.end endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "RNG (Random Number Generator)" base ad:0x4003A000 rgroup.long 0x00++0x03 line.long 0x00 "RANDOM_NUMBER,This register contains a random 32 bit number which is computed on demand at each time it is" hexmask.long 0x00 0.--31. 1. "RANDOM_NUMBER,This register contains a random 32 bit number which is computed on demand at each time it is" group.long 0x04++0x03 line.long 0x00 "ENCRYPTED_NUMBER,This register contains a random 32 bit number which is pre-computed" hexmask.long 0x00 0.--31. 1. "ENCRYPTED_NUMBER,This register contains a random 32 bit number which is pre-computed" group.long 0x08++0x03 line.long 0x00 "COUNTER_VAL,no description available" rbitfld.long 0x00 8.--12. "REFRESH_CNT,Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. "CLK_RATIO,Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes" group.long 0x08++0x03 line.long 0x00 "COUNTER_VAL,no description available" hexmask.long.word 0x00 8.--21. 1. "REFRESH_CNT,Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER" hexmask.long.byte 0x00 0.--7. 1. "CLK_RATIO,Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes" group.long 0x0C++0x03 line.long 0x00 "COUNTER_CFG,no description available" bitfld.long 0x00 5.--7. "SHIFT4X,To be used to add precision to clock_ratio and determine 'entropy refill'" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2.--4. "CLOCK_SEL,Selects the internal clock on which to compute statistics" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--1. "MODE," "0,1,2,3" group.long 0x10++0x03 line.long 0x00 "ONLINE_TEST_CFG,no description available" bitfld.long 0x00 1.--2. "DATA_SEL,Selects source on which to apply online test" "0: LSB of COUNTER,1: MSB of COUNTER,2: RANDOM_NUMBER,3: ENCRYPTED_NUMBER 'activate' should be set to" bitfld.long 0x00 0. "ACTIVATE," "0,1" group.long 0x14++0x03 line.long 0x00 "ONLINE_TEST_VAL,no description available" rbitfld.long 0x00 8.--11. "MAX_CHI_SQUARED,This field is reset when 'activate'==0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. "MIN_CHI_SQUARED,This field is reset when 'activate'==0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "LIVE_CHI_SQUARED,This value is updated as described in field 'activate'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x03 line.long 0x00 "ENTROPY_INJECT,no description available" hexmask.long 0x00 0.--31. 1. "ENTROPY,Use this register to inject or restore entropy 32 bits at a time" group.long 0x1C++0x03 line.long 0x00 "MISC_CFG,no description available" bitfld.long 0x00 1. "AES_DT_CFG,Set this bit to re-seed AES" "0,1" bitfld.long 0x00 0. "AES_RESEED,If set ENCRYPTED_NUMBER generation becomes predictable provided all secrets and current internal state are known: independant from entropy source" "0,1" group.long 0xFF4++0x03 line.long 0x00 "POWERDOWN,Powerdown mode (standard but certainly useless here)" bitfld.long 0x00 31. "POWERDOWN,When set all accesses to standard registers are blocked" "0,1" bitfld.long 0x00 1. "FORCE_SOFT_RESET,When used with softreset it forces CORE_RESETN to low on acknowledge from CORE" "0,1" bitfld.long 0x00 0. "SOFT_RESET,Request softreset that will go low automaticaly after acknowledge from CORE" "0,1" rgroup.long 0xFFC++0x03 line.long 0x00 "MODULEID,IP identifier" hexmask.long.word 0x00 16.--31. 1. "ID,Identifier" bitfld.long 0x00 12.--15. "MAJ_REV,Major revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "MIN_REV,Minor revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture i" tree.end endif tree "RTC (Real-time Counter)" base ad:0x4002C000 group.word 0x00++0x01 line.word 0x00 "YEARMON,Year and Month Counters" hexmask.word.byte 0x00 8.--15. 1. "YROFST,Year Offset Count Value" bitfld.word 0x00 0.--3. "MON_CNT,Month Counter" "0: ILLEGAL_VALUE,1: JANUARY,2: FEBRUARY,3: MARCH,4: APRIL,5: MAY,6: JUNE,7: JULY,8: AUGUST,9: SEPTEMBER,10: OCTOBER,11: NOVEMBER,12: DECEMBER,13: ILLEGAL_VALUE,14: ILLEGAL_VALUE,15: ILLEGAL_VALUE" group.word 0x02++0x01 line.word 0x00 "DAYS,Days and Day-of-Week Counters" bitfld.word 0x00 8.--10. "DOW,Day of Week Counter Value" "0: SUNDAY,1: MONDAY,2: TUESDAY,3: WEDNESDAY,4: THURSDAY,5: FRIDAY,6: SATURDAY,?..." bitfld.word 0x00 0.--4. "DAY_CNT,Days Counter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x04++0x01 line.word 0x00 "HOURMIN,Hours and Minutes Counters" bitfld.word 0x00 8.--12. "HOUR_CNT,Hours Counter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--5. "MIN_CNT,Minutes Counter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x06++0x01 line.word 0x00 "SECONDS,Seconds Counters" bitfld.word 0x00 0.--5. "SEC_CNT,Seconds Counter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x08++0x01 line.word 0x00 "ALM_YEARMON,Year and Months Alarm" hexmask.word.byte 0x00 8.--15. 1. "ALM_YEAR,Year Value for Alarm" bitfld.word 0x00 0.--3. "ALM_MON,Months Value for Alarm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0A++0x01 line.word 0x00 "ALM_DAYS,Days Alarm" bitfld.word 0x00 0.--4. "ALM_DAY,Days Value for Alarm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x0C++0x01 line.word 0x00 "ALM_HOURMIN,Hours and Minutes Alarm" bitfld.word 0x00 8.--12. "ALM_HOUR,Hours Value for Alarm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--5. "ALM_MIN,Minutes Value for Alarm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x0E++0x01 line.word 0x00 "ALM_SECONDS,Seconds Alarm" bitfld.word 0x00 9. "INC_SEC,Increment Seconds Counter by 1" "0,1" bitfld.word 0x00 8. "DEC_SEC,Decrement Seconds Counter by 1" "0,1" newline bitfld.word 0x00 0.--5. "ALM_SEC,Seconds Alarm Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x10++0x01 line.word 0x00 "CTRL,Control" bitfld.word 0x00 13.--14. "CLKOUT,RTC Clock Output Selection" "0: No Output Clock,1: Fine 1 Hz Clock with both precise edges,2: 32.768 kHz Clock,3: Coarse 1 Hz Clock with both precise edges" bitfld.word 0x00 8. "SWR,Software Reset" "0: Software Reset cleared,1: Software Reset asserted" newline bitfld.word 0x00 6. "DST_EN,Daylight Saving Enable" "0: DISABLED,1: ENABLED" bitfld.word 0x00 4. "TIMER_STB_MASK,Sampling Timer Clocks Mask" "0: Sampling clocks are not gated when in standby..,1: Sampling clocks are gated in standby mode" newline bitfld.word 0x00 2.--3. "ALM_MATCH,Alarm Match" "0: Only Seconds Minutes and Hours matched,1: Only Seconds Minutes Hours and Days matched,2: Only Seconds Minutes Hours Days and Months..,3: Only Seconds Minutes Hours Days Months and.." bitfld.word 0x00 1. "COMP_EN,Compensation Enable" "0: Coarse Compensation is disabled,1: Coarse Compensation is enabled" newline bitfld.word 0x00 0. "FINEEN,Fine Compensation Enable" "0: Fine compensation is disabled,1: Fine compensation is enabled" group.word 0x12++0x01 line.word 0x00 "STATUS,Status" eventfld.word 0x00 11. "CMP_DONE,Compensation Done" "0: Compensation busy or not enabled,1: Compensation completed" eventfld.word 0x00 8. "BUS_ERR,Bus Error" "0: Read and Write accesses are normal,1: Read or Write accesses occurred when.." newline bitfld.word 0x00 6.--7. "WE,Write Enable" "0: Disable Write Protection - Registers are..,1: Disable Write Protection - Registers are..,2: Enable Write Protection - Registers are locked,3: Disable Write Protection - Registers are.." rbitfld.word 0x00 5. "CMP_INT,Compensation Interval" "0,1" newline rbitfld.word 0x00 3. "RST_SRC,Reset Source" "0: STANDBY_MODE_EXIT,1: Power-On Reset" rbitfld.word 0x00 2. "CPU_LOW_VOLT,CPU Low Voltage Warning Status" "0: CPU in Normal Operating Voltage,1: CPU Voltage is below Normal Operating Voltage" newline rbitfld.word 0x00 1. "WRITE_PROT_EN,Write Protect Enable Status" "0: Registers are unlocked and can be accessed,1: Registers are locked and in read-only mode" rbitfld.word 0x00 0. "INVAL_BIT,Invalidate CPU Read/Write Access" "0: Time /Date Counters can be read/written,1: Time /Date Counter values are changing or.." group.word 0x14++0x01 line.word 0x00 "ISR,Interrupt Status" eventfld.word 0x00 15. "IS_512HZ,512 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" eventfld.word 0x00 14. "IS_256HZ,256 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" newline eventfld.word 0x00 13. "IS_128HZ,128 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" eventfld.word 0x00 12. "IS_64HZ,64 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" newline eventfld.word 0x00 11. "IS_32HZ,32 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" eventfld.word 0x00 10. "IS_16HZ,16 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" newline eventfld.word 0x00 9. "IS_8HZ,8 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" eventfld.word 0x00 8. "IS_4HZ,4 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" newline eventfld.word 0x00 7. "IS_2HZ,2 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" eventfld.word 0x00 6. "IS_1HZ,1 Hz Interval Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" newline eventfld.word 0x00 5. "MIN_IS,Minutes Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" eventfld.word 0x00 4. "HOUR_IS,Hours Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" newline eventfld.word 0x00 3. "DAY_IS,Days Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" eventfld.word 0x00 2. "ALM_IS,Alarm Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted" newline rbitfld.word 0x00 0. "TAMPER_IS,Tamper Interrupt Status" "0: Interrupt is de-asserted,1: Interrupt is asserted (Default on reset)" group.word 0x16++0x01 line.word 0x00 "IER,Interrupt Enable" bitfld.word 0x00 15. "IE_512HZ,512 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.word 0x00 14. "IE_256HZ,256 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.word 0x00 13. "IE_128HZ,128 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.word 0x00 12. "IE_64HZ,64 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.word 0x00 11. "IE_32HZ,32 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.word 0x00 10. "IE_16HZ,16 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.word 0x00 9. "IE_8HZ,8 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.word 0x00 8. "IE_4HZ,4 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.word 0x00 7. "IE_2HZ,2 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.word 0x00 6. "IE_1HZ,1 Hz Interval Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.word 0x00 5. "MIN_IE,Minutes Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.word 0x00 4. "HOUR_IE,Hours Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.word 0x00 3. "DAY_IE,Days Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" bitfld.word 0x00 2. "ALM_IE,Alarm Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled" newline bitfld.word 0x00 0. "TAMPER_IE,Tamper Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled (Default on reset)" group.word 0x20++0x01 line.word 0x00 "GP_DATA_REG,General Purpose Data" bitfld.word 0x00 15. "CFG15,CFGn" "0,1" bitfld.word 0x00 14. "CFG14,CFGn" "0,1" newline bitfld.word 0x00 13. "CFG13,CFGn" "0,1" bitfld.word 0x00 12. "CFG12,CFGn" "0,1" newline bitfld.word 0x00 11. "CFG11,CFGn" "0,1" bitfld.word 0x00 10. "CFG10,CFGn" "0,1" newline bitfld.word 0x00 9. "CFG9,CFGn" "0,1" bitfld.word 0x00 8. "CFG8,CFGn" "0,1" newline bitfld.word 0x00 7. "CFG7,CFGn" "0,1" bitfld.word 0x00 6. "CFG6,CFGn" "0,1" newline bitfld.word 0x00 5. "CFG5,CFGn" "0,1" bitfld.word 0x00 4. "CFG4,CFGn" "0,1" newline bitfld.word 0x00 3. "CFG3,CFGn" "0,1" bitfld.word 0x00 2. "CFG2,CFGn" "0,1" newline bitfld.word 0x00 1. "CFG1,CFGn" "0,1" bitfld.word 0x00 0. "CFG0,CFGn" "0,1" group.word 0x22++0x01 line.word 0x00 "DST_HOUR,Daylight Saving Hour" bitfld.word 0x00 8.--12. "DST_START_HOUR,Daylight Saving Time (DST) Hours Start Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--4. "DST_END_HOUR,Daylight Saving Time (DST) Hours End Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x24++0x01 line.word 0x00 "DST_MONTH,Daylight Saving Month" bitfld.word 0x00 8.--11. "DST_START_MONTH,Daylight Saving Time (DST) Month Start Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. "DST_END_MONTH,Daylight Saving Time (DST) Month End Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x26++0x01 line.word 0x00 "DST_DAY,Daylight Saving Day" bitfld.word 0x00 8.--12. "DST_START_DAY,Daylight Saving Time (DST) Day Start Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 0.--4. "DST_END_DAY,Daylight Saving Time (DST) Day End Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.word 0x28++0x01 line.word 0x00 "COMPEN,Compensation" hexmask.word 0x00 0.--15. 1. "COMPEN_VAL,Compensation Value" group.word 0x2E++0x01 line.word 0x00 "TAMPER_QSCR,Tamper Queue Status and Control" bitfld.word 0x00 2. "Q_CLEAR,Q_CLEAR" "0,1" bitfld.word 0x00 1. "Q_FULL_INT_EN,Q_FULL_INT_EN" "0: Queue full interrupt is disabled,1: Queue full interrupt is enabled" newline eventfld.word 0x00 0. "Q_FULL,Q_FULL" "0: The tamper queue is not full,1: The tamper queue is full" group.word 0x32++0x01 line.word 0x00 "TAMPER_SCR,Tamper Status and Control" eventfld.word 0x00 8.--11. "TMPR_STS,Tamper Status" "0: No Tamper Detected,1: Tamper Event Detected,?..." bitfld.word 0x00 0.--3. "TMPR_EN,Tamper Control" "0: Tamper Status reporting disabled,1: Tamper Status reporting enabled,?..." group.word 0x34++0x01 line.word 0x00 "FILTER01_CFG,Tamper 01 Filter Configuration" bitfld.word 0x00 15. "POL0,Tamper Detect Input Bit 0 Polarity Control" "0: Tamper detect input bit 0 is active high,1: Tamper detect input bit 0 is active low" bitfld.word 0x00 12.--14. "CLK_SEL0,Tamper Filter 0 Clock Select" "0: 32 kHz clock,1: 512 Hz clock,2: 128 Hz clock,3: 64 Hz clock,4: 16 Hz clock,5: 8 Hz clock,6: 4 Hz clock,7: 2 Hz clock" newline bitfld.word 0x00 8.--11. "FIL_DUR0,Tamper Detect Bit 0 Filter Duration" "0: Filtering operation disabled,1: Number of tamper filter clock cycles to be..,2: Number of tamper filter clock cycles to be..,3: Number of tamper filter clock cycles to be..,4: Number of tamper filter clock cycles to be..,5: Number of tamper filter clock cycles to be..,6: Number of tamper filter clock cycles to be..,7: Number of tamper filter clock cycles to be..,8: Number of tamper filter clock cycles to be..,9: Number of tamper filter clock cycles to be..,?..." bitfld.word 0x00 7. "POL1,Tamper Detect Input Bit 1 Polarity Control" "0: Tamper detect input bit 1 is active high,1: Tamper detect input bit 1 is active low" newline bitfld.word 0x00 4.--6. "CLK_SEL1,Tamper Filter 1 Clock Select" "0: 32 kHz clock,1: 512 Hz clock,2: 128 Hz clock,3: 64 Hz clock,4: 16 Hz clock,5: 8 Hz clock,6: 4 Hz clock,7: 2 Hz clock" bitfld.word 0x00 0.--3. "FIL_DUR1,Tamper Detect Bit 1 Filter Duration" "0: Filtering operation disabled,1: Number of tamper filter clock cycles to be..,2: Number of tamper filter clock cycles to be..,3: Number of tamper filter clock cycles to be..,4: Number of tamper filter clock cycles to be..,5: Number of tamper filter clock cycles to be..,6: Number of tamper filter clock cycles to be..,7: Number of tamper filter clock cycles to be..,8: Number of tamper filter clock cycles to be..,9: Number of tamper filter clock cycles to be..,?..." group.word 0x36++0x01 line.word 0x00 "FILTER23_CFG,Tamper 23 Filter Configuration" bitfld.word 0x00 15. "POL2,Tamper Detect Input Bit 2 Polarity Control" "0: Tamper detect input bit 2 is active high,1: Tamper detect input bit 2 is active low" bitfld.word 0x00 12.--14. "CLK_SEL2,Tamper Filter 2 Clock Select" "0: 32 kHz clock,1: 512 Hz clock,2: 128 Hz clock,3: 64 Hz clock,4: 16 Hz clock,5: 8 Hz clock,6: 4 Hz clock,7: 2 Hz clock" newline bitfld.word 0x00 8.--11. "FIL_DUR2,Tamper Detect Bit 2 Filter Duration" "0: Filtering operation disabled,1: Number of tamper filter clock cycles to be..,2: Number of tamper filter clock cycles to be..,3: Number of tamper filter clock cycles to be..,4: Number of tamper filter clock cycles to be..,5: Number of tamper filter clock cycles to be..,6: Number of tamper filter clock cycles to be..,7: Number of tamper filter clock cycles to be..,8: Number of tamper filter clock cycles to be..,9: Number of tamper filter clock cycles to be..,?..." bitfld.word 0x00 7. "POL3,Tamper Detect Input Bit 3 Polarity Control" "0: Tamper detect input bit 3 is active high,1: Tamper detect input bit 3 is active low" newline bitfld.word 0x00 4.--6. "CLK_SEL3,Tamper Filter 3 Clock Select" "0: 32 kHz clock,1: 512 Hz clock,2: 128 Hz clock,3: 64 Hz clock,4: 16 Hz clock,5: 8 Hz clock,6: 4 Hz clock,7: 2 Hz clock" bitfld.word 0x00 0.--3. "FIL_DUR3,Tamper Detect Bit 3 Filter Duration" "0: Filtering operation disabled,1: Number of tamper filter clock cycles to be..,2: Number of tamper filter clock cycles to be..,3: Number of tamper filter clock cycles to be..,4: Number of tamper filter clock cycles to be..,5: Number of tamper filter clock cycles to be..,6: Number of tamper filter clock cycles to be..,7: Number of tamper filter clock cycles to be..,8: Number of tamper filter clock cycles to be..,9: Number of tamper filter clock cycles to be..,?..." rgroup.word 0x40++0x01 line.word 0x00 "TAMPER_QUEUE,Tamper Queue" hexmask.word 0x00 0.--15. 1. "TAMPER_DATA,Tamper type stamp and pin number information register" group.word 0x42++0x01 line.word 0x00 "CTRL2,Control 2" bitfld.word 0x00 0. "TAMP_CFG_OVER,Tamper Configuration Over" "0: Tamper filter processing disabled,1: Tamper filter processing enabled" tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "RTC_SUBSYSTEM (RTC subsystem)" base ad:0x4002C000 group.long 0x800++0x03 line.long 0x00 "SUBSECOND_CTRL,Sub-second control" bitfld.long 0x00 0. "SUB_SECOND_CNT_EN,Sub-second counter enable bit" "0: Disabled,1: Enabled" rgroup.long 0x804++0x03 line.long 0x00 "SUBSECOND_CNT,Sub-second counter" hexmask.long.word 0x00 0.--15. 1. "SUBSECOND_CNT,Current sub-second counter value" group.long 0xC00++0x03 line.long 0x00 "WAKE_TIMER_CTRL,Wake timer control" bitfld.long 0x00 5. "INTR_EN,Enable interrupt when WAKE_FLAG is set" "0: Disabled,1: Enabled" bitfld.long 0x00 4. "OSC_DIV_ENA,Enable the 5-bit clock divider to divide down the 32Khz input clock to generate the 1Khz clock source for the wake timer" "0: Disabled,1: Enabled" newline bitfld.long 0x00 2. "CLR_WAKE_TIMER,Clear wake timer" "0: No effect,1: Clears the wake counter and halt operation.." eventfld.long 0x00 1. "WAKE_FLAG,Wake timer status flag" "0: Wake timer has not timed out,1: Wake timer has timed out" group.long 0xC0C++0x03 line.long 0x00 "WAKE_TIMER_CNT,Wake timer counter" hexmask.long 0x00 0.--31. 1. "WAKE_CNT,Wake counter" tree.end endif tree "SAU" base ad:0xE000EDD0 group.long 0xD0++0x03 line.long 0x00 "CTRL,Security Attribution Unit Control Register" bitfld.long 0x00 1. "ALLNS,All Non-secure" "0: Memory is marked as Secure and is not..,1: Memory is marked as Non-secure" bitfld.long 0x00 0. "ENABLE,Enable" "0: The SAU is disabled,1: The SAU is enabled" group.long 0xD4++0x03 line.long 0x00 "TYPE,Security Attribution Unit Type Register" hexmask.long.byte 0x00 0.--7. 1. "SREGION,SAU regions" group.long 0xD8++0x03 line.long 0x00 "RNR,Security Attribution Unit Region Number Register" hexmask.long.byte 0x00 0.--7. 1. "REGION,Region number" group.long 0xDC++0x03 line.long 0x00 "RBAR,Security Attribution Unit Region Base Address Register" hexmask.long 0x00 5.--31. 1. "BADDR,Base address" group.long 0xE0++0x03 line.long 0x00 "RLAR,Security Attribution Unit Region Limit Address Register" hexmask.long 0x00 5.--31. 1. "LADDR,Limit address" bitfld.long 0x00 1. "NSC,Non-secure callable" "0: Region is not Non-secure callable,1: Region is Non-secure callable" bitfld.long 0x00 0. "ENABLE,Enable" "0: SAU region is enabled,1: SAU region is disabled" group.long 0xE4++0x03 line.long 0x00 "SFSR,Secure Fault Status Register" bitfld.long 0x00 7. "LSERR,Lazy state error flag" "0: Error has not occurred,1: Error has occurred" bitfld.long 0x00 6. "SFARVALID,Secure fault address valid" "0: SFAR content not valid,1: SFAR content valid" bitfld.long 0x00 5. "LSPERR,Lazy state preservation error flag" "0: Error has not occurred,1: Error has occurred" newline bitfld.long 0x00 4. "INVTRAN,Invalid transition flag" "0: Error has not occurred,1: Error has occurred" bitfld.long 0x00 3. "AUVIOL,Attribution unit violation flag" "0: Error has not occurred,1: Error has occurred" bitfld.long 0x00 2. "INVER,Invalid exception return flag" "0: Error has not occurred,1: Error has occurred" newline bitfld.long 0x00 1. "INVIS,Invalid integrity signature flag" "0: Error has not occurred,1: Error has occurred" bitfld.long 0x00 0. "INVEP,Invalid entry point" "0: Error has not occurred,1: Error has occurred" group.long 0xE8++0x03 line.long 0x00 "SFAR,Secure Fault Address Register" hexmask.long 0x00 0.--31. 1. "ADDRESS,When the SFARVALID bit of the SFSR is set to 1 this field holds the address of an access that caused an SAU violation" tree.end tree "SCB" base ad:0xE000ED00 group.long 0x0C++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key: Reads as 0xFA05" rbitfld.long 0x00 15. "ENDIANNESS,Data endianness bit" "0: Little-endian,1: BIG_ENDIAN" newline bitfld.long 0x00 14. "PRIS,Prioritize Secure exceptions" "0: Priority ranges of Secure and Non-secure..,1: Non-secure exceptions are de-prioritized" bitfld.long 0x00 13. "BFHFNMINS,BusFault HardFault and NMI Non-secure enable" "0: BusFault HardFault and NMI are Secure,1: BusFault and NMI are Non-secure and.." newline bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "SYSRESETREQS,System reset request Secure state only" "0: SYSRESETREQ functionality is available to..,1: SYSRESETREQ functionality is only available.." newline bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0: Do not request a system reset,1: Request a system reset" bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1" group.long 0x10++0x03 line.long 0x00 "SCR,The SCR controls features of entry to and exit from low-power state" bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup..,1: Enabled events and all interrupts including.." bitfld.long 0x00 3. "SLEEPDEEPS,Controls whether the SLEEPDEEP bit is only accessible from the Secure state" "0: The SLEEPDEEP bit is accessible from both..,1: The SLEEPDEEP bit behaves as RAZ/WI when.." newline bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low-power mode" "0: Sleep,1: Deep sleep" bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR" group.long 0x24++0x03 line.long 0x00 "SHCSR,System Handler Control and State Register" bitfld.long 0x00 21. "HARDFAULTPENDED,HardFault exception pended state" "0: HardFault exception modification is disabled,1: HardFault exception modification is enabled" bitfld.long 0x00 20. "SECUREFAULTPENDED,SecureFault exception pended state bit" "0: SecureFault exception modification is disabled,1: SecureFault exception modification is enabled" newline bitfld.long 0x00 19. "SECUREFAULTENA,SecureFault exception enable" "0: SecureFault exception is disabled,1: SecureFault exception is enabled" bitfld.long 0x00 18. "USGFAULTENA,UsageFault enable" "0: UsageFault is disabled,1: UsageFault is enabled" newline bitfld.long 0x00 17. "BUSFAULTENA,BusFault enable" "0: BusFault is disabled,1: BusFault is enabled" bitfld.long 0x00 16. "MEMFAULTENA,MemManage enable" "0: MemManage exception is disabled,1: MemManage exception is enabled" newline bitfld.long 0x00 15. "SVCALLPENDED,SVCall pending" "0: SVCall exception is not pending,1: SVCall exception is pending" bitfld.long 0x00 14. "BUSFAULTPENDED,BusFault exception pending" "0: BusFault exception is pending,1: BusFault exception is not pending" newline bitfld.long 0x00 13. "MEMFAULTPENDED,MemManage exception pending" "0: MemManage exception is not pending,1: MemManage exception is pending" bitfld.long 0x00 12. "USGFAULTPENDED,UsageFault exception pending" "0: UsageFault exception is not pending,1: UsageFault exception is pending" newline bitfld.long 0x00 11. "SYSTICKACT,SysTick exception active" "0: SysTick exception is not active,1: SysTick exception is active" bitfld.long 0x00 10. "PENDSVACT,PendSV exception active" "0: PendSV exception is not active,1: PendSV exception is active" newline bitfld.long 0x00 8. "MONITORACT,Debug monitor active" "0: Debug monitor exception is not active,1: Debug monitor exception is active" bitfld.long 0x00 7. "SVCALLACT,SVCall active" "0: SVCall exception is not active,1: SVCall exception is active" newline bitfld.long 0x00 5. "NMIACT,NMI exception active" "0: NMI exception is not active,1: NMI exception is active" bitfld.long 0x00 4. "SECUREFAULTACT,SecureFault exception active" "0: SecureFault exception is not active,1: SecureFault exception is active" newline bitfld.long 0x00 3. "USGFAULTACT,UsageFault exception active" "0: UsageFault exception is not active,1: UsageFault exception is active" bitfld.long 0x00 2. "HARDFAULTACT,HardFault exception active" "0: HardFault exception is not active,1: HardFault exception is active" newline bitfld.long 0x00 1. "BUSFAULTACT,BusFault exception active" "0: BusFault exception is not active,1: BusFault exception is active" bitfld.long 0x00 0. "MEMFAULTACT,MemManage exception active" "0: MemManage exception is not active,1: MemManage exception is active" group.long 0x8C++0x03 line.long 0x00 "NSACR,Non-secure Access Control Register" bitfld.long 0x00 11. "CP11,CP11 access" "0,1" bitfld.long 0x00 10. "CP10,CP10 access" "0: Non-secure accesses to the Floating-point..,1: Non-secure access to the Floatingpoint.." newline bitfld.long 0x00 7. "CP7,CP7 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" bitfld.long 0x00 6. "CP6,CP6 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" newline bitfld.long 0x00 5. "CP5,CP5 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" bitfld.long 0x00 4. "CP4,CP4 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" newline bitfld.long 0x00 3. "CP3,CP3 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" bitfld.long 0x00 2. "CP2,CP2 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" newline bitfld.long 0x00 1. "CP1,CP1 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" bitfld.long 0x00 0. "CP0,CP0 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted" tree.end tree "SCNSCB" base ad:0xE000E000 group.long 0x0C++0x03 line.long 0x00 "CPPWR,Coprocessor Power Control Register" bitfld.long 0x00 23. "SUS11,State UNKNOWN Secure only 11" "0,1" bitfld.long 0x00 22. "SU11,State UNKNOWN 11" "0,1" newline bitfld.long 0x00 21. "SUS10,State UNKNOWN Secure only 10" "0: The SU10 field is accessible from both..,1: The SU10 field is only accessible from the.." bitfld.long 0x00 20. "SU10,State UNKNOWN 10" "0: The floating-point state is not permitted to..,1: The floating-point state is permitted to.." newline bitfld.long 0x00 15. "SUS7,State UNKNOWN Secure only 7" "0: The SU7 field is accessible from both..,1: The SU7 field is only accessible from the.." bitfld.long 0x00 14. "SU7,State UNKNOWN 7" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." newline bitfld.long 0x00 13. "SUS6,State UNKNOWN Secure only 6" "0: The SU6 field is accessible from both..,1: The SU6 field is only accessible from the.." bitfld.long 0x00 12. "SU6,State UNKNOWN 6" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." newline bitfld.long 0x00 11. "SUS5,State UNKNOWN Secure only 5" "0: The SU5 field is accessible from both..,1: The SU5 field is only accessible from the.." bitfld.long 0x00 10. "SU5,State UNKNOWN 5" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." newline bitfld.long 0x00 9. "SUS4,State UNKNOWN Secure only 4" "0: The SU4 field is accessible from both..,1: The SU4 field is only accessible from the.." bitfld.long 0x00 8. "SU4,State UNKNOWN 4" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." newline bitfld.long 0x00 7. "SUS3,State UNKNOWN Secure only 3" "0: The SU3 field is accessible from both..,1: The SU3 field is only accessible from the.." bitfld.long 0x00 6. "SU3,State UNKNOWN 3" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." newline bitfld.long 0x00 5. "SUS2,State UNKNOWN Secure only 2" "0: The SU2 field is accessible from both..,1: The SU2 field is only accessible from the.." bitfld.long 0x00 4. "SU2,State UNKNOWN 2" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." newline bitfld.long 0x00 3. "SUS1,State UNKNOWN Secure only 1" "0: The SU7 field is accessible from both..,1: The SU7 field is only accessible from the.." bitfld.long 0x00 2. "SU1,State UNKNOWN 1" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." newline bitfld.long 0x00 1. "SUS0,State UNKNOWN Secure only 0" "0: The SU0 field is accessible from both..,1: The SU0 field is only accessible from the.." bitfld.long 0x00 0. "SU0,State UNKNOWN 0" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.." tree.end tree "SCT (SCTimer)" base ad:0x40085000 group.long 0x00++0x03 line.long 0x00 "CONFIG,SCTimer Configuration" bitfld.long 0x00 18. "AUTOLIMIT_H,Auto Limit Higher" "0: Disable,1: Enable" bitfld.long 0x00 17. "AUTOLIMIT_L,Auto Limit Lower" "0: Disable,1: Enable" newline hexmask.long.byte 0x00 9.--16. 1. "INSYNC,Input Synchronization" bitfld.long 0x00 8. "NORELOAD_H,No Reload Higher Match" "0: Reload,1: No Reload" newline bitfld.long 0x00 7. "NORELOAD_L,No Reload Lower Match" "0: Reload,1: No Reload" bitfld.long 0x00 3.--6. "CKSEL,SCT Clock Select" "0: Rising edges on input 0,1: Falling edges on input 0,2: Rising edges on input 1,3: Falling edges on input 1,4: Rising edges on input 2,5: Falling edges on input 2,6: Rising edges on input 3,7: Falling edges on input 3,8: Rising edges on input 4,9: Falling edges on input 4,10: Rising edges on input 5,11: Falling edges on input 5,12: Rising edges on input 6,13: Falling edges on input 6,14: Rising edges on input 7,15: Falling edges on input 7" newline bitfld.long 0x00 1.--2. "CLKMODE,SCT Clock Mode" "0: System Clock Mode,1: Sampled System Clock Mode,2: SCT Input Clock Mode,3: Asynchronous Mode" bitfld.long 0x00 0. "UNIFY,SCT Operation" "0: Dual counter,1: Unified counter" group.long 0x04++0x03 line.long 0x00 "CTRL,SCT Control" hexmask.long.byte 0x00 21.--28. 1. "PRE_H,Prescaler for High Counter" bitfld.long 0x00 20. "BIDIR_H,Bidirectional Select High" "0: Up,1: Up-down" newline bitfld.long 0x00 19. "CLRCTR_H,Clear Counter High" "0,1" bitfld.long 0x00 18. "HALT_H,Halt Counter High" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 17. "STOP_H,Stop Counter High" "0: DISABLE,1: ENABLE" bitfld.long 0x00 16. "DOWN_H,Down Counter High" "0: Up,1: Down" newline hexmask.long.byte 0x00 5.--12. 1. "PRE_L,Prescaler for Low Counter" bitfld.long 0x00 4. "BIDIR_L,Bidirectional Select Low" "0: Up,1: Up-down" newline bitfld.long 0x00 3. "CLRCTR_L,Clear Counter Low" "0,1" bitfld.long 0x00 2. "HALT_L,Halt Counter Low" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "STOP_L,Stop Counter Low" "0: DISABLE,1: ENABLE" bitfld.long 0x00 0. "DOWN_L,Down Counter Low" "0: Up,1: Down" group.long 0x08++0x03 line.long 0x00 "LIMIT,SCT Limit Event Select" hexmask.long.word 0x00 16.--31. 1. "LIMMSK_H,Limit Event Counter High" hexmask.long.word 0x00 0.--15. 1. "LIMMSK_L,Limit Event Counter Low" group.long 0x0C++0x03 line.long 0x00 "HALT,Halt Event Select" hexmask.long.word 0x00 16.--31. 1. "HALTMSK_H,Halt Event High" hexmask.long.word 0x00 0.--15. 1. "HALTMSK_L,Halt Event Low" group.long 0x10++0x03 line.long 0x00 "STOP,Stop Event Select" hexmask.long.word 0x00 16.--31. 1. "STOPMSK_H,Stop Event High" hexmask.long.word 0x00 0.--15. 1. "STOPMSK_L,Stop Event Low" group.long 0x14++0x03 line.long 0x00 "START,Start Event Select" abitfld.long 0x00 16.--31. "STARTMSK_H,If bit n is one event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits =" abitfld.long 0x00 0.--15. "STARTMSK_L,If bit n is one event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits" group.long 0x18++0x03 line.long 0x00 "DITHER,Dither Condition" abitfld.long 0x00 16.--31. "DITHER_H,If bit n is one event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits =" abitfld.long 0x00 0.--15. "DITHER_L,If bit n is one event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits" group.long 0x40++0x03 line.long 0x00 "COUNT,Counter" hexmask.long.word 0x00 16.--31. 1. "CTR_H,Counter High" hexmask.long.word 0x00 0.--15. 1. "CTR_L,Counter Low" group.long 0x44++0x03 line.long 0x00 "STATE,State" bitfld.long 0x00 16.--20. "STATE_H,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "STATE_L,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x48++0x03 line.long 0x00 "INPUT,Input" bitfld.long 0x00 31. "SIN15,Input 15 state" "0,1" bitfld.long 0x00 30. "SIN14,Input 14 state" "0,1" newline bitfld.long 0x00 29. "SIN13,Input 13 state" "0,1" bitfld.long 0x00 28. "SIN12,Input 12 state" "0,1" newline bitfld.long 0x00 27. "SIN11,Input 11 state" "0,1" bitfld.long 0x00 26. "SIN10,Input 10 state" "0,1" newline bitfld.long 0x00 25. "SIN9,Input 9 state" "0,1" bitfld.long 0x00 24. "SIN8,Input 8 state" "0,1" newline bitfld.long 0x00 23. "SIN7,Input 7 state" "0,1" bitfld.long 0x00 22. "SIN6,Input 6 state" "0,1" newline bitfld.long 0x00 21. "SIN5,Input 5 state" "0,1" bitfld.long 0x00 20. "SIN4,Input 4 state" "0,1" newline bitfld.long 0x00 19. "SIN3,Input 3 state" "0,1" bitfld.long 0x00 18. "SIN2,Input 2 state" "0,1" newline bitfld.long 0x00 17. "SIN1,Input 1 state" "0,1" bitfld.long 0x00 16. "SIN0,Input 0 state" "0,1" newline bitfld.long 0x00 15. "AIN15,Input 15 state" "0,1" bitfld.long 0x00 14. "AIN14,Input 14 state" "0,1" newline bitfld.long 0x00 13. "AIN13,Input 13 state" "0,1" bitfld.long 0x00 12. "AIN12,Input 12 state" "0,1" newline bitfld.long 0x00 11. "AIN11,Input 11 state" "0,1" bitfld.long 0x00 10. "AIN10,Input 10 state" "0,1" newline bitfld.long 0x00 9. "AIN9,Input 9 state" "0,1" bitfld.long 0x00 8. "AIN8,Input 8 state" "0,1" newline bitfld.long 0x00 7. "AIN7,Input 7 state" "0,1" bitfld.long 0x00 6. "AIN6,Input 6 state" "0,1" newline bitfld.long 0x00 5. "AIN5,Input 5 state" "0,1" bitfld.long 0x00 4. "AIN4,Input 4 state" "0,1" newline bitfld.long 0x00 3. "AIN3,Input 3 state" "0,1" bitfld.long 0x00 2. "AIN2,Input 2 state" "0,1" newline bitfld.long 0x00 1. "AIN1,Input 1 state" "0,1" bitfld.long 0x00 0. "AIN0,Input 0 state" "0,1" group.long 0x4C++0x03 line.long 0x00 "REGMODE,Match/Capture Mode" bitfld.long 0x00 31. "REGMOD_H15,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 30. "REGMOD_H14,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 29. "REGMOD_H13,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 28. "REGMOD_H12,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 27. "REGMOD_H11,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 26. "REGMOD_H10,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 25. "REGMOD_H9,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 24. "REGMOD_H8,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 23. "REGMOD_H7,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 22. "REGMOD_H6,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 21. "REGMOD_H5,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 20. "REGMOD_H4,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 19. "REGMOD_H3,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 18. "REGMOD_H2,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 17. "REGMOD_H1,Register Mode High n" "0: Match,1: Capture" bitfld.long 0x00 16. "REGMOD_H0,Register Mode High n" "0: Match,1: Capture" newline bitfld.long 0x00 15. "REGMOD_L15,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 14. "REGMOD_L14,Register Mode Low n" "0: Match,1: Capture" newline bitfld.long 0x00 13. "REGMOD_L13,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 12. "REGMOD_L12,Register Mode Low n" "0: Match,1: Capture" newline bitfld.long 0x00 11. "REGMOD_L11,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 10. "REGMOD_L10,Register Mode Low n" "0: Match,1: Capture" newline bitfld.long 0x00 9. "REGMOD_L9,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 8. "REGMOD_L8,Register Mode Low n" "0: Match,1: Capture" newline bitfld.long 0x00 7. "REGMOD_L7,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 6. "REGMOD_L6,Register Mode Low n" "0: Match,1: Capture" newline bitfld.long 0x00 5. "REGMOD_L5,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 4. "REGMOD_L4,Register Mode Low n" "0: Match,1: Capture" newline bitfld.long 0x00 3. "REGMOD_L3,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 2. "REGMOD_L2,Register Mode Low n" "0: Match,1: Capture" newline bitfld.long 0x00 1. "REGMOD_L1,Register Mode Low n" "0: Match,1: Capture" bitfld.long 0x00 0. "REGMOD_L0,Register Mode Low n" "0: Match,1: Capture" group.long 0x50++0x03 line.long 0x00 "OUTPUT,Output" bitfld.long 0x00 9. "OUT9,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." bitfld.long 0x00 8. "OUT8,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." newline bitfld.long 0x00 7. "OUT7,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." bitfld.long 0x00 6. "OUT6,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." newline bitfld.long 0x00 5. "OUT5,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." bitfld.long 0x00 4. "OUT4,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." newline bitfld.long 0x00 3. "OUT3,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." bitfld.long 0x00 2. "OUT2,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." newline bitfld.long 0x00 1. "OUT1,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." bitfld.long 0x00 0. "OUT0,Output n" "0: Writing a 0 forces the corresponding output low,1: Writing a 1 forces the corresponding output.." group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,Output Counter Direction Control" bitfld.long 0x00 18.--19. "SETCLR9,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." bitfld.long 0x00 16.--17. "SETCLR8,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." newline bitfld.long 0x00 14.--15. "SETCLR7,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." bitfld.long 0x00 12.--13. "SETCLR6,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." newline bitfld.long 0x00 10.--11. "SETCLR5,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." bitfld.long 0x00 8.--9. "SETCLR4,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." newline bitfld.long 0x00 6.--7. "SETCLR3,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." bitfld.long 0x00 4.--5. "SETCLR2,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." newline bitfld.long 0x00 2.--3. "SETCLR1,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." bitfld.long 0x00 0.--1. "SETCLR0,Set/Clear Operation on Output n" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..." group.long 0x58++0x03 line.long 0x00 "RES,Output Conflict Resolution" bitfld.long 0x00 18.--19. "O9RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" bitfld.long 0x00 16.--17. "O8RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" newline bitfld.long 0x00 14.--15. "O7RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" bitfld.long 0x00 12.--13. "O6RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" newline bitfld.long 0x00 10.--11. "O5RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" bitfld.long 0x00 8.--9. "O4RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" newline bitfld.long 0x00 6.--7. "O3RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" bitfld.long 0x00 4.--5. "O2RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" newline bitfld.long 0x00 2.--3. "O1RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" bitfld.long 0x00 0.--1. "O0RES,Effect of simultaneous set and clear on output n" "0: NO_CHANGE,1: Set output (or clear based on the..,2: Clear output (or set based on the..,3: TOGGLE_OUTPUT" group.long 0x5C++0x03 line.long 0x00 "DMAREQ0,DMA Request 0" rbitfld.long 0x00 31. "DRQ0,DMA Request 0 State" "0,1" bitfld.long 0x00 30. "DRL0,A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers" "0,1" newline bitfld.long 0x00 15. "DEV_15,DMA Request Event n" "0,1" bitfld.long 0x00 14. "DEV_14,DMA Request Event n" "0,1" newline bitfld.long 0x00 13. "DEV_13,DMA Request Event n" "0,1" bitfld.long 0x00 12. "DEV_12,DMA Request Event n" "0,1" newline bitfld.long 0x00 11. "DEV_11,DMA Request Event n" "0,1" bitfld.long 0x00 10. "DEV_10,DMA Request Event n" "0,1" newline bitfld.long 0x00 9. "DEV_9,DMA Request Event n" "0,1" bitfld.long 0x00 8. "DEV_8,DMA Request Event n" "0,1" newline bitfld.long 0x00 7. "DEV_7,DMA Request Event n" "0,1" bitfld.long 0x00 6. "DEV_6,DMA Request Event n" "0,1" newline bitfld.long 0x00 5. "DEV_5,DMA Request Event n" "0,1" bitfld.long 0x00 4. "DEV_4,DMA Request Event n" "0,1" newline bitfld.long 0x00 3. "DEV_3,DMA Request Event n" "0,1" bitfld.long 0x00 2. "DEV_2,DMA Request Event n" "0,1" newline bitfld.long 0x00 1. "DEV_1,DMA Request Event n" "0,1" bitfld.long 0x00 0. "DEV_0,DMA Request Event n" "0,1" group.long 0x60++0x03 line.long 0x00 "DMAREQ1,DMA Request 1" rbitfld.long 0x00 31. "DRQ1,DMA Request 1 State" "0,1" bitfld.long 0x00 30. "DRL1,A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers" "0,1" newline bitfld.long 0x00 15. "DEV_15,DMA Request Event n" "0,1" bitfld.long 0x00 14. "DEV_14,DMA Request Event n" "0,1" newline bitfld.long 0x00 13. "DEV_13,DMA Request Event n" "0,1" bitfld.long 0x00 12. "DEV_12,DMA Request Event n" "0,1" newline bitfld.long 0x00 11. "DEV_11,DMA Request Event n" "0,1" bitfld.long 0x00 10. "DEV_10,DMA Request Event n" "0,1" newline bitfld.long 0x00 9. "DEV_9,DMA Request Event n" "0,1" bitfld.long 0x00 8. "DEV_8,DMA Request Event n" "0,1" newline bitfld.long 0x00 7. "DEV_7,DMA Request Event n" "0,1" bitfld.long 0x00 6. "DEV_6,DMA Request Event n" "0,1" newline bitfld.long 0x00 5. "DEV_5,DMA Request Event n" "0,1" bitfld.long 0x00 4. "DEV_4,DMA Request Event n" "0,1" newline bitfld.long 0x00 3. "DEV_3,DMA Request Event n" "0,1" bitfld.long 0x00 2. "DEV_2,DMA Request Event n" "0,1" newline bitfld.long 0x00 1. "DEV_1,DMA Request Event n" "0,1" bitfld.long 0x00 0. "DEV_0,DMA Request Event n" "0,1" group.long 0xF0++0x03 line.long 0x00 "EVEN,Event Interrupt Enable" bitfld.long 0x00 15. "IEN15,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 14. "IEN14,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 13. "IEN13,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 12. "IEN12,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 11. "IEN11,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 10. "IEN10,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 9. "IEN9,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 8. "IEN8,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 7. "IEN7,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 6. "IEN6,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 5. "IEN5,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 4. "IEN4,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 3. "IEN3,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 2. "IEN2,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" newline bitfld.long 0x00 1. "IEN1,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" bitfld.long 0x00 0. "IEN0,Event Interrupt Enable n" "0: DISABLE,1: ENABLE" group.long 0xF4++0x03 line.long 0x00 "EVFLAG,Event Flag" bitfld.long 0x00 15. "FLAG15,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 14. "FLAG14,Event Flag n" "0: NO_FLAG,1: Event n Flag" newline bitfld.long 0x00 13. "FLAG13,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 12. "FLAG12,Event Flag n" "0: NO_FLAG,1: Event n Flag" newline bitfld.long 0x00 11. "FLAG11,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 10. "FLAG10,Event Flag n" "0: NO_FLAG,1: Event n Flag" newline bitfld.long 0x00 9. "FLAG9,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 8. "FLAG8,Event Flag n" "0: NO_FLAG,1: Event n Flag" newline bitfld.long 0x00 7. "FLAG7,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 6. "FLAG6,Event Flag n" "0: NO_FLAG,1: Event n Flag" newline bitfld.long 0x00 5. "FLAG5,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 4. "FLAG4,Event Flag n" "0: NO_FLAG,1: Event n Flag" newline bitfld.long 0x00 3. "FLAG3,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 2. "FLAG2,Event Flag n" "0: NO_FLAG,1: Event n Flag" newline bitfld.long 0x00 1. "FLAG1,Event Flag n" "0: NO_FLAG,1: Event n Flag" bitfld.long 0x00 0. "FLAG0,Event Flag n" "0: NO_FLAG,1: Event n Flag" group.long 0xF8++0x03 line.long 0x00 "CONEN,Conflict Interrupt Enable" bitfld.long 0x00 9. "NCEN9,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" bitfld.long 0x00 8. "NCEN8,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" newline bitfld.long 0x00 7. "NCEN7,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" bitfld.long 0x00 6. "NCEN6,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" newline bitfld.long 0x00 5. "NCEN5,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" bitfld.long 0x00 4. "NCEN4,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" newline bitfld.long 0x00 3. "NCEN3,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" bitfld.long 0x00 2. "NCEN2,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" newline bitfld.long 0x00 1. "NCEN1,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" bitfld.long 0x00 0. "NCEN0,No Change Conflict Event/Interrupt Enable" "0: NO_INTERRUPT,1: INTERRUPT" group.long 0xFC++0x03 line.long 0x00 "CONFLAG,Conflict Flag" bitfld.long 0x00 31. "BUSERRH,Bus Error High" "0,1" bitfld.long 0x00 30. "BUSERRL,Bus Error Low/Unified" "0,1" newline bitfld.long 0x00 9. "NCFLAG9,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" bitfld.long 0x00 8. "NCFLAG8,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" newline bitfld.long 0x00 7. "NCFLAG7,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" bitfld.long 0x00 6. "NCFLAG6,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" newline bitfld.long 0x00 5. "NCFLAG5,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" bitfld.long 0x00 4. "NCFLAG4,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" newline bitfld.long 0x00 3. "NCFLAG3,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" bitfld.long 0x00 2. "NCFLAG2,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" newline bitfld.long 0x00 1. "NCFLAG1,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" bitfld.long 0x00 0. "NCFLAG0,No Change Conflict Event Flag" "0: No Conflict Event,1: A No Change Conflict Event occured" group.long 0x100++0x03 line.long 0x00 "CAP0,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x100++0x03 line.long 0x00 "MATCH0,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x104++0x03 line.long 0x00 "CAP1,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x104++0x03 line.long 0x00 "MATCH1,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x108++0x03 line.long 0x00 "CAP2,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x108++0x03 line.long 0x00 "MATCH2,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x10C++0x03 line.long 0x00 "CAP3,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x10C++0x03 line.long 0x00 "MATCH3,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x110++0x03 line.long 0x00 "CAP4,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x110++0x03 line.long 0x00 "MATCH4,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x114++0x03 line.long 0x00 "CAP5,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x114++0x03 line.long 0x00 "MATCH5,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x118++0x03 line.long 0x00 "CAP6,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x118++0x03 line.long 0x00 "MATCH6,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x11C++0x03 line.long 0x00 "CAP7,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x11C++0x03 line.long 0x00 "MATCH7,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x120++0x03 line.long 0x00 "CAP8,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x120++0x03 line.long 0x00 "MATCH8,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x124++0x03 line.long 0x00 "CAP9,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x124++0x03 line.long 0x00 "MATCH9,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x128++0x03 line.long 0x00 "CAP10,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x128++0x03 line.long 0x00 "MATCH10,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x12C++0x03 line.long 0x00 "CAP11,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x12C++0x03 line.long 0x00 "MATCH11,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x130++0x03 line.long 0x00 "CAP12,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x130++0x03 line.long 0x00 "MATCH12,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x134++0x03 line.long 0x00 "CAP13,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x134++0x03 line.long 0x00 "MATCH13,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x138++0x03 line.long 0x00 "CAP14,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x138++0x03 line.long 0x00 "MATCH14,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" group.long 0x13C++0x03 line.long 0x00 "CAP15,Capture Value" hexmask.long.word 0x00 16.--31. 1. "CAPn_H,Capture n High" hexmask.long.word 0x00 0.--15. 1. "CAPn_L,Capture n Low" group.long 0x13C++0x03 line.long 0x00 "MATCH15,Match Value" hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,Match n High" hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,Match n Low" repeat 6. (increment 0 1) (increment 0 0x04) group.long ($2+0x140)++0x03 line.long 0x00 "FRACMAT[$1],Fractional Match $1" bitfld.long 0x00 16.--19. "FRACMAT_H,Fractional Match High" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "FRACMAT_L,Fractional Match Low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end group.long 0x200++0x03 line.long 0x00 "CAPCTRL0,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x200++0x03 line.long 0x00 "MATCHREL0,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x204++0x03 line.long 0x00 "CAPCTRL1,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x204++0x03 line.long 0x00 "MATCHREL1,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x208++0x03 line.long 0x00 "CAPCTRL2,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x208++0x03 line.long 0x00 "MATCHREL2,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x20C++0x03 line.long 0x00 "CAPCTRL3,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x20C++0x03 line.long 0x00 "MATCHREL3,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x210++0x03 line.long 0x00 "CAPCTRL4,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x210++0x03 line.long 0x00 "MATCHREL4,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x214++0x03 line.long 0x00 "CAPCTRL5,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x214++0x03 line.long 0x00 "MATCHREL5,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x218++0x03 line.long 0x00 "CAPCTRL6,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x218++0x03 line.long 0x00 "MATCHREL6,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x21C++0x03 line.long 0x00 "CAPCTRL7,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x21C++0x03 line.long 0x00 "MATCHREL7,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x220++0x03 line.long 0x00 "CAPCTRL8,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x220++0x03 line.long 0x00 "MATCHREL8,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x224++0x03 line.long 0x00 "CAPCTRL9,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x224++0x03 line.long 0x00 "MATCHREL9,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x228++0x03 line.long 0x00 "CAPCTRL10,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x228++0x03 line.long 0x00 "MATCHREL10,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x22C++0x03 line.long 0x00 "CAPCTRL11,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x22C++0x03 line.long 0x00 "MATCHREL11,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x230++0x03 line.long 0x00 "CAPCTRL12,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x230++0x03 line.long 0x00 "MATCHREL12,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x234++0x03 line.long 0x00 "CAPCTRL13,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x234++0x03 line.long 0x00 "MATCHREL13,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x238++0x03 line.long 0x00 "CAPCTRL14,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x238++0x03 line.long 0x00 "MATCHREL14,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" group.long 0x23C++0x03 line.long 0x00 "CAPCTRL15,Capture Control" hexmask.long.word 0x00 16.--31. 1. "CAPCONn_H,Capture Control n High" hexmask.long.word 0x00 0.--15. 1. "CAPCONn_L,Capture Control n Low" group.long 0x23C++0x03 line.long 0x00 "MATCHREL15,Match Reload Value" hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,Reload n High" hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,Reload n Low" repeat 6. (increment 0 1) (increment 0 0x04) group.long ($2+0x240)++0x03 line.long 0x00 "FRACMATREL[$1],Fractional Match Reload $1" bitfld.long 0x00 16.--19. "RELFRAC_H,Reload Fractional Match High" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "FRACMAT_L,Reload Fractional Match Low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end repeat 16. (increment 0 1)(increment 0 0x08) tree "EVENT[$1]" group.long ($2+0x300)++0x03 line.long 0x00 "EV_STATE,Event n State" hexmask.long 0x00 0.--31. 1. "STATEMSKn,Event State Mask n" group.long ($2+0x304)++0x03 line.long 0x00 "EV_CTRL,Event n Control" bitfld.long 0x00 21.--22. "DIRECTION,Direction" "0: Direction independent,1: Counting up,2: Counting down,?..." bitfld.long 0x00 20. "MATCHMEM,Match Mem" "0,1" bitfld.long 0x00 15.--19. "STATEV,State Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "STATELD,State Load" "0: Add,1: Load" newline bitfld.long 0x00 12.--13. "COMBMODE,Combination Mode" "0: OR,1: MATCH,2: IO,3: AND" bitfld.long 0x00 10.--11. "IOCOND,Input/Output Condition" "0: LOW,1: RISE,2: FALL,3: HIGH" bitfld.long 0x00 6.--9. "IOSEL,Input/Output Signal Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. "OUTSEL,Input/Output Select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL" newline bitfld.long 0x00 4. "HEVENT,High Event" "0: Low Counter,1: High Counter" bitfld.long 0x00 0.--3. "MATCHSEL,Match Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end repeat.end repeat 10. (increment 0 1)(increment 0 0x208) tree "OUT[$1]" group.long ($2+0x500)++0x03 line.long 0x00 "OUT_SET,Output n Set" hexmask.long.word 0x00 0.--15. 1. "SET,Set" group.long ($2+0x504)++0x03 line.long 0x00 "OUT_CLR,Output n Clear" hexmask.long.word 0x00 0.--15. 1. "CLR,Clear" tree.end repeat.end tree.end sif cpuis("LPC5526*")||cpuis("LPC5528*") tree "SDIF (SDMMC)" base ad:0x4009B000 group.long 0x00++0x03 line.long 0x00 "CTRL,Control register" bitfld.long 0x00 25. "USE_INTERNAL_DMAC,SD/MMC DMA use" "0,1" bitfld.long 0x00 18. "CARD_VOLTAGE_A2,Controls the state of the SD_VOLT2 pin" "0,1" newline bitfld.long 0x00 17. "CARD_VOLTAGE_A1,Controls the state of the SD_VOLT1 pin" "0,1" bitfld.long 0x00 16. "CARD_VOLTAGE_A0,Controls the state of the SD_VOLT0 pin" "0,1" newline bitfld.long 0x00 11. "CEATA_DEVICE_INTERRUPT_STATUS,CEATA device interrupt status" "0,1" bitfld.long 0x00 10. "SEND_AUTO_STOP_CCSD,Send auto stop ccsd" "0,1" newline bitfld.long 0x00 9. "SEND_CCSD,Send ccsd" "0,1" bitfld.long 0x00 8. "ABORT_READ_DATA,Abort read data" "0,1" newline bitfld.long 0x00 7. "SEND_IRQ_RESPONSE,Send irq response" "0,1" bitfld.long 0x00 6. "READ_WAIT,Read/wait" "0,1" newline bitfld.long 0x00 4. "INT_ENABLE,Global interrupt enable/disable bit" "0,1" bitfld.long 0x00 2. "DMA_RESET,DMA reset" "0,1" newline bitfld.long 0x00 1. "FIFO_RESET,Fifo reset" "0,1" bitfld.long 0x00 0. "CONTROLLER_RESET,Controller reset" "0,1" group.long 0x04++0x03 line.long 0x00 "PWREN,Power Enable register" bitfld.long 0x00 1. "POWER_ENABLE1,Power on/off switch for card 1 once power is turned on software should wait for regulator/switch ramp-up time before trying to initialize card 1" "0,1" bitfld.long 0x00 0. "POWER_ENABLE0,Power on/off switch for card 0 once power is turned on software should wait for regulator/switch ramp-up time before trying to initialize card 0" "0,1" group.long 0x08++0x03 line.long 0x00 "CLKDIV,Clock Divider register" hexmask.long.byte 0x00 0.--7. 1. "CLK_DIVIDER0,Clock divider-0 value" group.long 0x10++0x03 line.long 0x00 "CLKENA,Clock Enable register" bitfld.long 0x00 17. "CCLK1_LOW_POWER,Low-power control for SD card 1 clock" "0,1" bitfld.long 0x00 16. "CCLK0_LOW_POWER,Low-power control for SD card 0 clock" "0,1" newline bitfld.long 0x00 1. "CCLK1_ENABLE,Clock-enable control for SD card 1 clock" "0,1" bitfld.long 0x00 0. "CCLK0_ENABLE,Clock-enable control for SD card 0 clock" "0,1" group.long 0x14++0x03 line.long 0x00 "TMOUT,Time-out register" hexmask.long.tbyte 0x00 8.--31. 1. "DATA_TIMEOUT,Value for card Data Read time-out same value also used for Data Starvation by Host time-out" hexmask.long.byte 0x00 0.--7. 1. "RESPONSE_TIMEOUT,Response time-out value" group.long 0x18++0x03 line.long 0x00 "CTYPE,Card Type register" bitfld.long 0x00 17. "CARD1_WIDTH1,Indicates if card 1 is 8-bit" "0,1" bitfld.long 0x00 16. "CARD0_WIDTH1,Indicates if card 0 is 8-bit" "0,1" newline bitfld.long 0x00 1. "CARD1_WIDTH0,Indicates if card 1 is 1-bit or 4-bit" "0,1" bitfld.long 0x00 0. "CARD0_WIDTH0,Indicates if card 0 is 1-bit or 4-bit" "0,1" group.long 0x1C++0x03 line.long 0x00 "BLKSIZ,Block Size register" hexmask.long.word 0x00 0.--15. 1. "BLOCK_SIZE,Block size" group.long 0x20++0x03 line.long 0x00 "BYTCNT,Byte Count register" hexmask.long 0x00 0.--31. 1. "BYTE_COUNT,Number of bytes to be transferred should be integer multiple of Block Size for block transfers" group.long 0x24++0x03 line.long 0x00 "INTMASK,Interrupt Mask register" bitfld.long 0x00 16. "SDIO_INT_MASK,Mask SDIO interrupt" "0,1" bitfld.long 0x00 15. "EBE,End-bit error (read)/Write no CRC" "0,1" newline bitfld.long 0x00 14. "ACD,Auto command done" "0,1" bitfld.long 0x00 13. "SBE,Start-bit error" "0,1" newline bitfld.long 0x00 12. "HLE,Hardware locked write error" "0,1" bitfld.long 0x00 11. "FRUN,FIFO underrun/overrun error" "0,1" newline bitfld.long 0x00 10. "HTO,Data starvation-by-host time-out (HTO)" "0,1" bitfld.long 0x00 9. "DRTO,Data read time-out" "0,1" newline bitfld.long 0x00 8. "RTO,Response time-out" "0,1" bitfld.long 0x00 7. "DCRC,Data CRC error" "0,1" newline bitfld.long 0x00 6. "RCRC,Response CRC error" "0,1" bitfld.long 0x00 5. "RXDR,Receive FIFO data request" "0,1" newline bitfld.long 0x00 4. "TXDR,Transmit FIFO data request" "0,1" bitfld.long 0x00 3. "DTO,Data transfer over" "0,1" newline bitfld.long 0x00 2. "CDONE,Command done" "0,1" bitfld.long 0x00 1. "RE,Response error" "0,1" newline bitfld.long 0x00 0. "CDET,Card detect" "0,1" group.long 0x28++0x03 line.long 0x00 "CMDARG,Command Argument register" hexmask.long 0x00 0.--31. 1. "CMD_ARG,Value indicates command argument to be passed to card" group.long 0x2C++0x03 line.long 0x00 "CMD,Command register" bitfld.long 0x00 31. "START_CMD,Start command" "0,1" bitfld.long 0x00 29. "USE_HOLD_REG,Use Hold Register" "0,1" newline bitfld.long 0x00 28. "VOLT_SWITCH,Voltage switch bit" "0,1" bitfld.long 0x00 27. "BOOT_MODE,Boot Mode" "0,1" newline bitfld.long 0x00 26. "DISABLE_BOOT,Disable Boot" "0,1" bitfld.long 0x00 25. "EXPECT_BOOT_ACK,Expect Boot Acknowledge" "0,1" newline bitfld.long 0x00 24. "ENABLE_BOOT,Enable Boot - this bit should be set only for mandatory boot mode" "0,1" bitfld.long 0x00 23. "CCS_EXPECTED,CCS expected" "0,1" newline bitfld.long 0x00 22. "READ_CEATA_DEVICE,Read ceata device" "0,1" bitfld.long 0x00 21. "UPDATE_CLOCK_REGISTERS_ONLY,Update clock registers only" "0,1" newline bitfld.long 0x00 16.--20. "CARD_NUMBER,Specifies the card number of SDCARD for which the current Command is being executed" "0: Command will be execute on SDCARD 0,1: Command will be execute on SDCARD 1,?..." bitfld.long 0x00 15. "SEND_INITIALIZATION,Send initialization" "0,1" newline bitfld.long 0x00 14. "STOP_ABORT_CMD,Stop abort command" "0,1" bitfld.long 0x00 13. "WAIT_PRVDATA_COMPLETE,Wait prvdata complete" "0,1" newline bitfld.long 0x00 12. "SEND_AUTO_STOP,Send auto stop" "0,1" bitfld.long 0x00 11. "TRANSFER_MODE,Transfer mode" "0,1" newline bitfld.long 0x00 10. "READ_WRITE,read/" "0,1" bitfld.long 0x00 9. "DATA_EXPECTED,Data expected" "0,1" newline bitfld.long 0x00 8. "CHECK_RESPONSE_CRC,Check response CRC" "0,1" bitfld.long 0x00 7. "RESPONSE_LENGTH,Response length" "0,1" newline bitfld.long 0x00 6. "RESPONSE_EXPECT,Response expect" "0,1" bitfld.long 0x00 0.--5. "CMD_INDEX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" repeat 4. (increment 0 1) (increment 0 0x4) group.long ($2+0x30)++0x03 line.long 0x00 "RESP[$1],Response register $1" hexmask.long 0x00 0.--31. 1. "RESPONSE,Bits of response" repeat.end group.long 0x40++0x03 line.long 0x00 "MINTSTS,Masked Interrupt Status register" bitfld.long 0x00 16. "SDIO_INTERRUPT,Interrupt from SDIO card" "0,1" bitfld.long 0x00 15. "EBE,End-bit error (read)/write no CRC" "0,1" newline bitfld.long 0x00 14. "ACD,Auto command done" "0,1" bitfld.long 0x00 13. "SBE,Start-bit error" "0,1" newline bitfld.long 0x00 12. "HLE,Hardware locked write error" "0,1" bitfld.long 0x00 11. "FRUN,FIFO underrun/overrun error" "0,1" newline bitfld.long 0x00 10. "HTO,Data starvation-by-host time-out (HTO)" "0,1" bitfld.long 0x00 9. "DRTO,Data read time-out" "0,1" newline bitfld.long 0x00 8. "RTO,Response time-out" "0,1" bitfld.long 0x00 7. "DCRC,Data CRC error" "0,1" newline bitfld.long 0x00 6. "RCRC,Response CRC error" "0,1" bitfld.long 0x00 5. "RXDR,Receive FIFO data request" "0,1" newline bitfld.long 0x00 4. "TXDR,Transmit FIFO data request" "0,1" bitfld.long 0x00 3. "DTO,Data transfer over" "0,1" newline bitfld.long 0x00 2. "CDONE,Command done" "0,1" bitfld.long 0x00 1. "RE,Response error" "0,1" newline bitfld.long 0x00 0. "CDET,Card detect" "0,1" group.long 0x44++0x03 line.long 0x00 "RINTSTS,Raw Interrupt Status register" bitfld.long 0x00 16. "SDIO_INTERRUPT,Interrupt from SDIO card" "0,1" bitfld.long 0x00 15. "EBE,End-bit error (read)/write no CRC" "0,1" newline bitfld.long 0x00 14. "ACD,Auto command done" "0,1" bitfld.long 0x00 13. "SBE,Start-bit error" "0,1" newline bitfld.long 0x00 12. "HLE,Hardware locked write error" "0,1" bitfld.long 0x00 11. "FRUN,FIFO underrun/overrun error" "0,1" newline bitfld.long 0x00 10. "HTO,Data starvation-by-host time-out (HTO)" "0,1" bitfld.long 0x00 9. "DRTO_BDS,Data read time-out (DRTO)/Boot Data Start (BDS)" "0,1" newline bitfld.long 0x00 8. "RTO_BAR,Response time-out (RTO)/Boot Ack Received (BAR)" "0,1" bitfld.long 0x00 7. "DCRC,Data CRC error" "0,1" newline bitfld.long 0x00 6. "RCRC,Response CRC error" "0,1" bitfld.long 0x00 5. "RXDR,Receive FIFO data request" "0,1" newline bitfld.long 0x00 4. "TXDR,Transmit FIFO data request" "0,1" bitfld.long 0x00 3. "DTO,Data transfer over" "0,1" newline bitfld.long 0x00 2. "CDONE,Command done" "0,1" bitfld.long 0x00 1. "RE,Response error" "0,1" newline bitfld.long 0x00 0. "CDET,Card detect" "0,1" group.long 0x48++0x03 line.long 0x00 "STATUS,Status register" bitfld.long 0x00 31. "DMA_REQ,DMA request signal state" "0,1" bitfld.long 0x00 30. "DMA_ACK,DMA acknowledge signal state" "0,1" newline hexmask.long.word 0x00 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO" bitfld.long 0x00 11.--16. "RESPONSE_INDEX,Index of previous response including any auto-stop sent by core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy" "0,1" bitfld.long 0x00 9. "DATA_BUSY,Inverted version of raw selected card_data[0]" "0: card data not busy,1: card data busy" newline bitfld.long 0x00 8. "DATA_3_STATUS,Raw selected card_data[3] checks whether card is present" "0: card not present,1: card present" bitfld.long 0x00 4.--7. "CMDFSMSTATES,Command FSM states" "0: Idle,1: Send init sequence,2: Tx cmd start bit,3: Tx cmd tx bit,4: Tx cmd index + arg,5: Tx cmd crc7,6: Tx cmd end bit,7: Rx resp start bit,8: Rx resp IRQ response,9: Rx resp tx bit,10: Rx resp cmd idx,11: Rx resp data,12: Rx resp crc7,13: Rx resp end bit,14: Cmd path wait NCC,15: Wait CMD-to-response turnaround" newline bitfld.long 0x00 3. "FIFO_FULL,FIFO is full status" "0,1" bitfld.long 0x00 2. "FIFO_EMPTY,FIFO is empty status" "0,1" newline bitfld.long 0x00 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level not qualified with data transfer" "0,1" bitfld.long 0x00 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level not qualified with data transfer" "0,1" group.long 0x4C++0x03 line.long 0x00 "FIFOTH,FIFO Threshold Watermark register" bitfld.long 0x00 28.--30. "DMA_MTS,Burst size of multiple transaction should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--27. 1. "RX_WMARK,FIFO threshold watermark level when receiving data to card" newline hexmask.long.word 0x00 0.--11. 1. "TX_WMARK,FIFO threshold watermark level when transmitting data to card" group.long 0x50++0x03 line.long 0x00 "CDETECT,Card Detect register" bitfld.long 0x00 1. "CARD1_DETECT,Card 1 detect" "0,1" bitfld.long 0x00 0. "CARD0_DETECT,Card 0 detect" "0,1" group.long 0x54++0x03 line.long 0x00 "WRTPRT,Write Protect register" bitfld.long 0x00 0. "WRITE_PROTECT,Write protect" "0,1" group.long 0x5C++0x03 line.long 0x00 "TCBCNT,Transferred CIU Card Byte Count register" hexmask.long 0x00 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card" group.long 0x60++0x03 line.long 0x00 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register" hexmask.long 0x00 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO" group.long 0x64++0x03 line.long 0x00 "DEBNCE,Debounce Count register" hexmask.long.tbyte 0x00 0.--23. 1. "DEBOUNCE_COUNT,Number of host clocks (SD_CLK) used by debounce filter logic for card detect typical debounce time is 5-25 ms" group.long 0x78++0x03 line.long 0x00 "RST_N,Hardware Reset" bitfld.long 0x00 0. "CARD_RESET,Hardware reset" "0,1" group.long 0x80++0x03 line.long 0x00 "BMOD,Bus Mode register" bitfld.long 0x00 8.--10. "PBL,Programmable Burst Length" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "DE,SD/MMC DMA Enable" "0,1" newline bitfld.long 0x00 2.--6. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. "FB,Fixed Burst" "0,1" newline bitfld.long 0x00 0. "SWR,Software Reset" "0,1" group.long 0x84++0x03 line.long 0x00 "PLDMND,Poll Demand register" hexmask.long 0x00 0.--31. 1. "PD,Poll Demand" group.long 0x88++0x03 line.long 0x00 "DBADDR,Descriptor List Base Address register" hexmask.long 0x00 0.--31. 1. "SDL,Start of Descriptor List" group.long 0x8C++0x03 line.long 0x00 "IDSTS,Internal DMAC Status register" bitfld.long 0x00 13.--16. "FSM,DMAC state machine present state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--12. "EB,Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9. "AIS,Abnormal Interrupt Summary" "0,1" bitfld.long 0x00 8. "NIS,Normal Interrupt Summary" "0,1" newline bitfld.long 0x00 5. "CES,Card Error Summary" "0,1" bitfld.long 0x00 4. "DU,Descriptor Unavailable Interrupt" "0,1" newline bitfld.long 0x00 2. "FBE,Fatal Bus Error Interrupt" "0,1" bitfld.long 0x00 1. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x00 0. "TI,Transmit Interrupt" "0,1" group.long 0x90++0x03 line.long 0x00 "IDINTEN,Internal DMAC Interrupt Enable register" bitfld.long 0x00 9. "AIS,Abnormal Interrupt Summary Enable" "0,1" bitfld.long 0x00 8. "NIS,Normal Interrupt Summary Enable" "0,1" newline bitfld.long 0x00 5. "CES,Card Error summary Interrupt Enable" "0,1" bitfld.long 0x00 4. "DU,Descriptor Unavailable Interrupt" "0,1" newline bitfld.long 0x00 2. "FBE,Fatal Bus Error Enable" "0,1" bitfld.long 0x00 1. "RI,Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 0. "TI,Transmit Interrupt Enable" "0,1" group.long 0x94++0x03 line.long 0x00 "DSCADDR,Current Host Descriptor Address register" hexmask.long 0x00 0.--31. 1. "HDA,Host Descriptor Address Pointer" group.long 0x98++0x03 line.long 0x00 "BUFADDR,Current Buffer Descriptor Address register" hexmask.long 0x00 0.--31. 1. "HBA,Host Buffer Address Pointer" group.long 0x100++0x03 line.long 0x00 "CARDTHRCTL,Card Threshold Control" hexmask.long.byte 0x00 16.--23. 1. "CARDTHRESHOLD,Card Threshold size" bitfld.long 0x00 1. "BSYCLRINTEN,Busy Clear Interrupt Enable" "0,1" newline bitfld.long 0x00 0. "CARDRDTHREN,Card Read Threshold Enable" "0,1" group.long 0x104++0x03 line.long 0x00 "BACKENDPWR,Power control" bitfld.long 0x00 0. "BACKENDPWR,Back-end Power control for card application" "0,1" repeat 64. (increment 0 1) (increment 0 0x04) group.long ($2+0x200)++0x03 line.long 0x00 "FIFO[$1],SDIF FIFO $1" hexmask.long 0x00 0.--31. 1. "DATA,SDIF FIFO" repeat.end tree.end endif tree "SPI (Serial Peripheral Interfaces (SPI))" repeat 2. (list 0. 1.) (list ad:0x40086000 ad:0x40087000) tree "SPI$1" base $2 group.long 0x400++0x03 line.long 0x00 "CFG,SPI Configuration register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture" newline bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled" group.long 0x400++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback Mode Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 5. "CPOL,Clock Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase Select" "0: CHANGE,1: CAPTURE" newline bitfld.long 0x00 3. "LSBF,LSB First Mode Enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI Enable" "0: Disabled,1: Enabled" group.long 0x404++0x03 line.long 0x00 "DLY,Delay Register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Transfer Delay" "0: The minimum time that SSEL is deasserted is 1..,1: The minimum time that SSEL is deasserted is 2..,2: The minimum time that SSEL is deasserted is 3..,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is.." newline bitfld.long 0x00 8.--11. "FRAME_DELAY,Frame Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Post-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Pre-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x404++0x03 line.long 0x00 "DLY,SPI Delay register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16" newline bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x408++0x03 line.long 0x00 "STAT,Status Register" rbitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer Control" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled Status Flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x408++0x03 line.long 0x00 "STAT,SPI Status" rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x40C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Register" bitfld.long 0x00 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled,1: Enabled" group.long 0x40C++0x03 line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set" bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled" wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Interrupt Enable" "0: NO_EFFECT,1: Clear the Master Idle Interrupt Enable bit.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Deassert Interrupt.." newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Assert Interrupt.." wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear" bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" group.long 0x424++0x03 line.long 0x00 "DIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate Divider Value" group.long 0x424++0x03 line.long 0x00 "DIV,SPI clock Divider" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status" bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: MSTIDLE_INTERRUPT_DISABLED,1: MSTIDLE_INTERRUPT_ENABLED" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert Interrupt" "0: SSD_INTERRUPT_DISABLED,1: SSD_INTERRUPT_ENABLED" newline bitfld.long 0x00 4. "SSA,Slave Select Assert Interrupt" "0: SSA_INTERRUPT_DISABLED,1: SSA_INTERRUPT_ENABLED" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO configuration and enable register" bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART" newline bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration Register" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Issues a DMA request for the receive function.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: FIFO is configured as 8 entries of 16 bits,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO status register" rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1" newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1" newline rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status Register" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data.." newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.." newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15" newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Register" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register" bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive FIFO Level Interrupt Enable.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Transmit FIFO Level Interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive Error Interrupt Enable bit.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: NO_EFFECT,1: Clear the TX Error Interrupt Enable bit.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register" bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register" bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO write data" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline endif bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data Register" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of Frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of Transfer" "0: SSEL is not deasserted,1: SSEL is deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went.." newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO read data" bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop" bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: SOT_NOT_ACTIVE,1: SOT_ACTIVE" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: NOT_SELECTED,1: RXSSEL3_N_SELECTED" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: NOT_SELECTED,1: RXSSEL2_N_SELECTED" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: NOT_SELECTED,1: RXSSEL1_N_SELECTED" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: NOT_SELECTED,1: RXSSEL0_N_SELECTED" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO size register" rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" group.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end repeat.end sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") tree "SPI2" base ad:0x40088000 group.long 0x400++0x03 line.long 0x00 "CFG,SPI Configuration register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture" newline bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled" group.long 0x400++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback Mode Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 5. "CPOL,Clock Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase Select" "0: CHANGE,1: CAPTURE" newline bitfld.long 0x00 3. "LSBF,LSB First Mode Enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI Enable" "0: Disabled,1: Enabled" group.long 0x404++0x03 line.long 0x00 "DLY,Delay Register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Transfer Delay" "0: The minimum time that SSEL is deasserted is 1..,1: The minimum time that SSEL is deasserted is 2..,2: The minimum time that SSEL is deasserted is 3..,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is.." newline bitfld.long 0x00 8.--11. "FRAME_DELAY,Frame Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Post-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Pre-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x404++0x03 line.long 0x00 "DLY,SPI Delay register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16" newline bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x408++0x03 line.long 0x00 "STAT,Status Register" rbitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer Control" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled Status Flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x408++0x03 line.long 0x00 "STAT,SPI Status" rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x40C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Register" bitfld.long 0x00 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled,1: Enabled" group.long 0x40C++0x03 line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set" bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled" wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Interrupt Enable" "0: NO_EFFECT,1: Clear the Master Idle Interrupt Enable bit.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Deassert Interrupt.." newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Assert Interrupt.." wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear" bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" group.long 0x424++0x03 line.long 0x00 "DIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate Divider Value" group.long 0x424++0x03 line.long 0x00 "DIV,SPI clock Divider" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status" bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: MSTIDLE_INTERRUPT_DISABLED,1: MSTIDLE_INTERRUPT_ENABLED" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert Interrupt" "0: SSD_INTERRUPT_DISABLED,1: SSD_INTERRUPT_ENABLED" newline bitfld.long 0x00 4. "SSA,Slave Select Assert Interrupt" "0: SSA_INTERRUPT_DISABLED,1: SSA_INTERRUPT_ENABLED" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration Register" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Issues a DMA request for the receive function.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: FIFO is configured as 8 entries of 16 bits,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO configuration and enable register" bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART" newline bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO status register" rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1" newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1" newline rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status Register" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data.." newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.." newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Register" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15" newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register" bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive FIFO Level Interrupt Enable.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Transmit FIFO Level Interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive Error Interrupt Enable bit.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: NO_EFFECT,1: Clear the TX Error Interrupt Enable bit.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register" bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register" bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO write data" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline endif bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data Register" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of Frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of Transfer" "0: SSEL is not deasserted,1: SSEL is deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went.." newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO read data" bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop" bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: SOT_NOT_ACTIVE,1: SOT_ACTIVE" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: NOT_SELECTED,1: RXSSEL3_N_SELECTED" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: NOT_SELECTED,1: RXSSEL2_N_SELECTED" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: NOT_SELECTED,1: RXSSEL1_N_SELECTED" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: NOT_SELECTED,1: RXSSEL0_N_SELECTED" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" group.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO size register" rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end endif repeat 2. (list 3. 4.) (list ad:0x40089000 ad:0x4008A000) tree "SPI$1" base $2 group.long 0x400++0x03 line.long 0x00 "CFG,SPI Configuration register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture" newline bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled" group.long 0x400++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback Mode Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 5. "CPOL,Clock Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase Select" "0: CHANGE,1: CAPTURE" newline bitfld.long 0x00 3. "LSBF,LSB First Mode Enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI Enable" "0: Disabled,1: Enabled" group.long 0x404++0x03 line.long 0x00 "DLY,Delay Register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Transfer Delay" "0: The minimum time that SSEL is deasserted is 1..,1: The minimum time that SSEL is deasserted is 2..,2: The minimum time that SSEL is deasserted is 3..,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is.." newline bitfld.long 0x00 8.--11. "FRAME_DELAY,Frame Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Post-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Pre-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x404++0x03 line.long 0x00 "DLY,SPI Delay register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16" newline bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x408++0x03 line.long 0x00 "STAT,Status Register" rbitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer Control" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled Status Flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x408++0x03 line.long 0x00 "STAT,SPI Status" rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x40C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Register" bitfld.long 0x00 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled,1: Enabled" group.long 0x40C++0x03 line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set" bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled" wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Interrupt Enable" "0: NO_EFFECT,1: Clear the Master Idle Interrupt Enable bit.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Deassert Interrupt.." newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Assert Interrupt.." wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear" bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" group.long 0x424++0x03 line.long 0x00 "DIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate Divider Value" group.long 0x424++0x03 line.long 0x00 "DIV,SPI clock Divider" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status" bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: MSTIDLE_INTERRUPT_DISABLED,1: MSTIDLE_INTERRUPT_ENABLED" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert Interrupt" "0: SSD_INTERRUPT_DISABLED,1: SSD_INTERRUPT_ENABLED" newline bitfld.long 0x00 4. "SSA,Slave Select Assert Interrupt" "0: SSA_INTERRUPT_DISABLED,1: SSA_INTERRUPT_ENABLED" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO configuration and enable register" bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART" newline bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration Register" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Issues a DMA request for the receive function.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: FIFO is configured as 8 entries of 16 bits,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO status register" rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1" newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1" newline rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status Register" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data.." newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.." newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15" newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Register" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register" bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive FIFO Level Interrupt Enable.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Transmit FIFO Level Interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive Error Interrupt Enable bit.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: NO_EFFECT,1: Clear the TX Error Interrupt Enable bit.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register" bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register" bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO write data" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline endif bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data Register" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of Frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of Transfer" "0: SSEL is not deasserted,1: SSEL is deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went.." newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO read data" bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop" bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: SOT_NOT_ACTIVE,1: SOT_ACTIVE" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: NOT_SELECTED,1: RXSSEL3_N_SELECTED" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: NOT_SELECTED,1: RXSSEL2_N_SELECTED" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: NOT_SELECTED,1: RXSSEL1_N_SELECTED" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: NOT_SELECTED,1: RXSSEL0_N_SELECTED" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO size register" rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" group.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end repeat.end sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") tree "SPI5" base ad:0x40096000 group.long 0x400++0x03 line.long 0x00 "CFG,SPI Configuration register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture" newline bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled" group.long 0x400++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback Mode Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 5. "CPOL,Clock Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase Select" "0: CHANGE,1: CAPTURE" newline bitfld.long 0x00 3. "LSBF,LSB First Mode Enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI Enable" "0: Disabled,1: Enabled" group.long 0x404++0x03 line.long 0x00 "DLY,Delay Register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Transfer Delay" "0: The minimum time that SSEL is deasserted is 1..,1: The minimum time that SSEL is deasserted is 2..,2: The minimum time that SSEL is deasserted is 3..,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is.." newline bitfld.long 0x00 8.--11. "FRAME_DELAY,Frame Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Post-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Pre-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x404++0x03 line.long 0x00 "DLY,SPI Delay register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16" newline bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x408++0x03 line.long 0x00 "STAT,Status Register" rbitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer Control" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled Status Flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x408++0x03 line.long 0x00 "STAT,SPI Status" rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x40C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Register" bitfld.long 0x00 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled,1: Enabled" group.long 0x40C++0x03 line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set" bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled" wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Interrupt Enable" "0: NO_EFFECT,1: Clear the Master Idle Interrupt Enable bit.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Deassert Interrupt.." newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Assert Interrupt.." wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear" bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" group.long 0x424++0x03 line.long 0x00 "DIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate Divider Value" group.long 0x424++0x03 line.long 0x00 "DIV,SPI clock Divider" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status" bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: MSTIDLE_INTERRUPT_DISABLED,1: MSTIDLE_INTERRUPT_ENABLED" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert Interrupt" "0: SSD_INTERRUPT_DISABLED,1: SSD_INTERRUPT_ENABLED" newline bitfld.long 0x00 4. "SSA,Slave Select Assert Interrupt" "0: SSA_INTERRUPT_DISABLED,1: SSA_INTERRUPT_ENABLED" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration Register" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Issues a DMA request for the receive function.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: FIFO is configured as 8 entries of 16 bits,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO configuration and enable register" bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART" newline bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO status register" rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1" newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1" newline rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status Register" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data.." newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.." newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Register" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15" newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register" bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive FIFO Level Interrupt Enable.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Transmit FIFO Level Interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive Error Interrupt Enable bit.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: NO_EFFECT,1: Clear the TX Error Interrupt Enable bit.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register" bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register" bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO write data" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline endif bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data Register" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of Frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of Transfer" "0: SSEL is not deasserted,1: SSEL is deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went.." newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO read data" bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop" bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: SOT_NOT_ACTIVE,1: SOT_ACTIVE" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: NOT_SELECTED,1: RXSSEL3_N_SELECTED" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: NOT_SELECTED,1: RXSSEL2_N_SELECTED" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: NOT_SELECTED,1: RXSSEL1_N_SELECTED" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: NOT_SELECTED,1: RXSSEL0_N_SELECTED" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" group.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO size register" rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end endif repeat 3. (list 6. 7. 8.) (list ad:0x40097000 ad:0x40098000 ad:0x4009F000) tree "SPI$1" base $2 group.long 0x400++0x03 line.long 0x00 "CFG,SPI Configuration register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture" newline bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled" group.long 0x400++0x03 line.long 0x00 "CFG,Configuration Register" bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 7. "LOOP,Loopback Mode Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 5. "CPOL,Clock Polarity Select" "0: Low,1: High" newline bitfld.long 0x00 4. "CPHA,Clock Phase Select" "0: CHANGE,1: CAPTURE" newline bitfld.long 0x00 3. "LSBF,LSB First Mode Enable" "0: Standard,1: Reverse" newline bitfld.long 0x00 2. "MASTER,Master Mode Select" "0: Slave mode,1: Master mode" newline bitfld.long 0x00 0. "ENABLE,SPI Enable" "0: Disabled,1: Enabled" group.long 0x404++0x03 line.long 0x00 "DLY,Delay Register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Transfer Delay" "0: The minimum time that SSEL is deasserted is 1..,1: The minimum time that SSEL is deasserted is 2..,2: The minimum time that SSEL is deasserted is 3..,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is.." newline bitfld.long 0x00 8.--11. "FRAME_DELAY,Frame Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Post-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Pre-Delay" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x404++0x03 line.long 0x00 "DLY,SPI Delay register" bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16" newline bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" newline bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted" group.long 0x408++0x03 line.long 0x00 "STAT,Status Register" rbitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer Control" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled Status Flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x408++0x03 line.long 0x00 "STAT,SPI Status" rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1" newline bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1" newline rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" group.long 0x40C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Register" bitfld.long 0x00 8. "MSTIDLEEN,Master Idle Interrupt Enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: Disabled,1: Enabled" group.long 0x40C++0x03 line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set" bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.." newline bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled" wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Interrupt Enable" "0: NO_EFFECT,1: Clear the Master Idle Interrupt Enable bit.." newline bitfld.long 0x00 5. "SSDEN,Slave Select Deassert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Deassert Interrupt.." newline bitfld.long 0x00 4. "SSAEN,Slave Select Assert Interrupt Enable" "0: NO_EFFECT,1: Clear the Slave Select Assert Interrupt.." wgroup.long 0x410++0x03 line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear" bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" newline bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1" group.long 0x424++0x03 line.long 0x00 "DIV,Clock Divider Register" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate Divider Value" group.long 0x424++0x03 line.long 0x00 "DIV,SPI clock Divider" hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,SPI Interrupt Status" bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1" newline bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1" rgroup.long 0x428++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 8. "MSTIDLE,Master Idle Status Flag Interrupt" "0: MSTIDLE_INTERRUPT_DISABLED,1: MSTIDLE_INTERRUPT_ENABLED" newline bitfld.long 0x00 5. "SSD,Slave Select Deassert Interrupt" "0: SSD_INTERRUPT_DISABLED,1: SSD_INTERRUPT_ENABLED" newline bitfld.long 0x00 4. "SSA,Slave Select Assert Interrupt" "0: SSA_INTERRUPT_DISABLED,1: SSA_INTERRUPT_ENABLED" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO configuration and enable register" bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1" newline bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1" newline bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART" newline bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration Register" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Issues a DMA request for the receive function.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Issues DMA request for the transmit function.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: FIFO is configured as 8 entries of 16 bits,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO status register" rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1" newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1" newline rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status Register" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: When 0 the receive FIFO is empty,1: When 1 the receive FIFO is not empty so data.." newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: The peripheral function has not asserted an..,1: Indicates that the peripheral function has.." newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15" newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Register" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register" bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.." newline bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA]=1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive FIFO Level Interrupt Enable.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the Transmit FIFO Level Interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the Receive Error Interrupt Enable bit.." newline bitfld.long 0x00 0. "TXERR,TX Error Interrupt Enable" "0: NO_EFFECT,1: Clear the TX Error Interrupt Enable bit.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register" bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" newline bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register" bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1" newline bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1" newline bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO write data" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline endif bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data Register" bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length" newline bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data" newline bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data" newline bitfld.long 0x00 21. "EOF,End of Frame" "0: Data not EOF,1: Data EOF" newline bitfld.long 0x00 20. "EOT,End of Transfer" "0: SSEL is not deasserted,1: SSEL is deasserted" newline bitfld.long 0x00 19. "TXSSEL3_N,Transmit Slave Select 3" "0: SSEL3 is asserted,1: SSEL3 is not asserted" newline bitfld.long 0x00 18. "TXSSEL2_N,Transmit Slave Select 2" "0: SSEL2 is asserted,1: SSEL2 is not asserted" newline bitfld.long 0x00 17. "TXSSEL1_N,Transmit Slave Select 1" "0: SSEL1 is asserted,1: SSEL1 is not asserted" newline bitfld.long 0x00 16. "TXSSEL0_N,Transmit Slave Select 0" "0: SSEL0 is asserted,1: SSEL0 is not asserted" newline hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit Data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: This is not the 1st data after the SSELs went..,1: This is the 1st data after the SSELs went.." newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: Slave Select 3 is active,1: Slave Select 3 is not active" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: Slave Select 2 is active,1: Slave Select 2 is not active" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: Slave Select 1 is active,1: Slave Select 1 is not active" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: Slave Select 0 is active,1: Slave Select 0 is not active" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO read data" bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop" bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with no FIFO Pop Register" bitfld.long 0x00 20. "SOT,Start of Transfer Flag" "0: SOT_NOT_ACTIVE,1: SOT_ACTIVE" newline bitfld.long 0x00 19. "RXSSEL3_N,Slave Select 3 for Receive" "0: NOT_SELECTED,1: RXSSEL3_N_SELECTED" newline bitfld.long 0x00 18. "RXSSEL2_N,Slave Select 2 for Receive" "0: NOT_SELECTED,1: RXSSEL2_N_SELECTED" newline bitfld.long 0x00 17. "RXSSEL1_N,Slave Select 1 for Receive" "0: NOT_SELECTED,1: RXSSEL1_N_SELECTED" newline bitfld.long 0x00 16. "RXSSEL0_N,Slave Select 0 for Receive" "0: NOT_SELECTED,1: RXSSEL0_N_SELECTED" newline hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size Register" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO size register" rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" group.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral identification register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification Register" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end repeat.end tree.end tree "SYSCON" base ad:0x40000000 group.long 0x00++0x03 line.long 0x00 "MEMORYREMAP,Memory Remap control register" bitfld.long 0x00 0.--1. "MAP,Select the location of the vector table" "0: Vector Table in ROM,1: Vector Table in RAM,2: Vector Table in Flash,3: Vector Table in Flash" group.long 0x00++0x03 line.long 0x00 "MEMORYREMAP,Memory Remap Control" bitfld.long 0x00 0.--1. "MAP,Select the location of the vector table" "0: Vector Table in ROM,1: Vector Table in RAM,2: Vector Table in Flash,3: Vector Table in Flash" group.long 0x10++0x03 line.long 0x00 "AHBMATPRIO,AHB Matrix priority control register Priority values are" sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 24.--25. "PRI_SDMA1,DMA1 controller priority" "0,1,2,3" newline bitfld.long 0x00 22.--23. "PRI_USB_HS,USB-HS.(USB1)" "0,1,2,3" newline bitfld.long 0x00 20.--21. "PRI_HASH_AES,HASH_AES" "0,1,2,3" newline bitfld.long 0x00 18.--19. "PRI_PQ,PQ (HW Accelerator)" "0,1,2,3" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 18.--19. "PRI_CANFD,CANFD" "0,1,2,3" newline bitfld.long 0x00 16.--17. "PRI_HASH_AES,HASH_AES" "0,1,2,3" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 16.--17. "PRI_SDIO,SDIO" "0,1,2,3" newline bitfld.long 0x00 10.--11. "PRI_SDMA0,DMA0 controller priority" "0,1,2,3" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 10.--11. "PRI_USB_FSH,USB0-FS host.(USB0)" "0,1,2,3" newline bitfld.long 0x00 8.--9. "PRI_USB_FSD,USB0-FS Device.(USB0)" "0,1,2,3" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 8.--9. "PRI_USB_FS,USB-FS.(USB0)" "0,1,2,3" newline bitfld.long 0x00 6.--7. "PRI_CPU1_SBUS,CPU1 S-AHB bus" "0,1,2,3" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 6.--7. "PRI_SDMA1,DMA1 controller priority" "0,1,2,3" newline bitfld.long 0x00 4.--5. "PRI_SDMA0,DMA0 controller priority" "0,1,2,3" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 4.--5. "PRI_CPU1_CBUS,CPU1 C-AHB bus" "0,1,2,3" newline endif bitfld.long 0x00 2.--3. "PRI_CPU0_SBUS,CPU0 S-AHB bus" "0,1,2,3" newline bitfld.long 0x00 0.--1. "PRI_CPU0_CBUS,CPU0 C-AHB bus" "0,1,2,3" group.long 0x10++0x03 line.long 0x00 "AHBMATPRIO,AHB Matrix priority control" bitfld.long 0x00 30.--31. "PKC,PKC" "0,1,2,3" newline bitfld.long 0x00 26.--27. "PRI_MCAN,MCAN" "0,1,2,3" newline bitfld.long 0x00 24.--25. "PRI_SDMA1,DMA1 controller priority" "0,1,2,3" newline bitfld.long 0x00 22.--23. "PRI_USB_FS,USB-FS host" "0,1,2,3" newline bitfld.long 0x00 20.--21. "PRI_CSSV2,CSSV2" "0,1,2,3" newline bitfld.long 0x00 18.--19. "PRI_PQ,PQ (HW Accelerator)" "0,1,2,3" newline bitfld.long 0x00 14.--15. "PRI_EZH_B_I,EZH B instruction bus" "0,1,2,3" newline bitfld.long 0x00 12.--13. "PRI_EZH_B_D,EZH B data bus" "0,1,2,3" newline bitfld.long 0x00 10.--11. "PRI_SDMA0,DMA0 controller priority" "0,1,2,3" newline bitfld.long 0x00 8.--9. "PRI_USB_FSD,USB0-FS Device.(USB0)" "0,1,2,3" newline bitfld.long 0x00 2.--3. "PRI_CPU0_SBUS,CPU0 S-AHB bus" "0,1,2,3" newline bitfld.long 0x00 0.--1. "PRI_CPU0_CBUS,CPU0 C-AHB bus" "0,1,2,3" group.long 0x14++0x03 line.long 0x00 "AHBMATPRIO1,AHB Matrix priority control" bitfld.long 0x00 4.--5. "DSP_I,DSP I bus" "0,1,2,3" newline bitfld.long 0x00 2.--3. "DSP_D,DSP D bus" "0,1,2,3" group.long 0x38++0x03 line.long 0x00 "CPU0STCKCAL,System tick calibration for secure part of CPU0" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 25. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: Reference clock provided,1: No reference clock provided" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 25. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: reference clock provided,1: no reference clock provided" newline bitfld.long 0x00 24. "SKEW,Initial value for the Systick timer" "0,1" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 24. "SKEW,Indicates whether the TENMS value is exact" "0: TENMS value is exact,1: TENMS value is inexact or not given" newline endif hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value for 10ms (100Hz) timing subject to system clock skew errors" group.long 0x3C++0x03 line.long 0x00 "CPU0NSTCKCAL,System tick calibration for non-secure part of CPU0" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 25. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: Reference clock provided,1: No reference clock provided" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 25. "NOREF,Initial value for the Systick timer" "0,1" newline bitfld.long 0x00 24. "SKEW,Indicates whether the TENMS value is exact" "0: TENMS value is exact,1: TENMS value is inexact or not given" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 24. "SKEW,Indicates whether the TENMS value is exact" "0: TENMS value is exact,1: TENMS value is inexact or not given" newline endif hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value for 10 ms (100 Hz) timing subject to system clock skew errors" group.long 0x40++0x03 line.long 0x00 "CPU1STCKCAL,System tick calibration for CPU1" bitfld.long 0x00 25. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: reference clock provided,1: no reference clock provided" newline bitfld.long 0x00 24. "SKEW,Indicates whether the TENMS value is exact" "0: TENMS value is exact,1: TENMS value is inexact or not given" newline hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value for 10ms (100Hz) timing subject to system clock skew errors" group.long 0x48++0x03 line.long 0x00 "NMISRC,NMI Source Select" bitfld.long 0x00 31. "NMIENCPU0,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0" "0,1" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 30. "NMIENCPU1,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1" "0,1" newline bitfld.long 0x00 8.--13. "IRQCPU1,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1 if enabled by NMIENCPU1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline endif bitfld.long 0x00 0.--5. "IRQCPU0,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0 if enabled by NMIENCPU0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x100++0x03 line.long 0x00 "PRESETCTRL0,Peripheral reset control 0" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 29. "DAC0_RST,DAC0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 28. "ADC1_RST,ADC1 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 27. "ADC_RST,ADC reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 27. "ADC0_RST,ADC0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 26. "MAILBOX_RST,Inter CPU communication Mailbox reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 26. "MAILBOX_RST,Inter CPU communication Mailbox reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 23. "RTC_RST,Real Time Clock (RTC) reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 23. "RTC_RST,Real Time Clock (RTC) reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 22. "WWDT_RST,Watchdog Timer reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 22. "WWDT_RST,Watchdog Timer reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 21. "CRCGEN_RST,CRCGEN reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 21. "CRCGEN_RST,CRCGEN reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 20. "DMA0_RST,DMA0 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 20. "DMA0_RST,DMA0 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 19. "GINT_RST,Group interrupt (GINT) reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 19. "GINT_RST,Group interrupt (GINT) reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 18. "PINT_RST,Pin interrupt (PINT) reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18. "PINT_RST,Pin interrupt (PINT) reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 17. "GPIO3_RST,GPIO3 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 17. "GPIO3_RST,GPIO3 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 16. "GPIO2_RST,GPIO2 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 16. "GPIO2_RST,GPIO2 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 15. "GPIO1_RST,GPIO1 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 15. "GPIO1_RST,GPIO1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 14. "GPIO0_RST,GPIO0 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 14. "GPIO0_RST,GPIO0 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 13. "IOCON_RST,I/O controller reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 13. "IOCON_RST,I/O controller reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 11. "MUX_RST,Input Mux reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 10. "FLEXSPI_RST,FLEXSPI reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 8. "FMC_RST,FMC controller reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 8. "FMC_RST,FMC controller reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 7. "FLASH_RST,Flash controller reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 7. "FLASH_RST,Flash controller reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6. "SRAM_CTRL4_RST,SRAM Controller 4 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 6. "SRAM_CTRL4_RST,SRAM Controller 4 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 5. "SRAM_CTRL3_RST,SRAM Controller 3 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 5. "SRAM_CTRL3_RST,SRAM Controller 3 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 4. "SRAM_CTRL2_RST,SRAM Controller 2 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 4. "SRAM_CTRL2_RST,SRAM Controller 2 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 3. "SRAM_CTRL1_RST,SRAM Controller 1 reset control" "0: Block is not reset,1: Block is reset" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 3. "SRAM_CTRL1_RST,SRAM Controller 1 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 1. "ROM_RST,ROM reset control" "0: Bloc is not reset,1: Bloc is reset" endif group.long 0x100++0x03 line.long 0x00 "PRESETCTRLX0,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x104++0x03 line.long 0x00 "PRESETCTRL1,Peripheral reset control 1" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 31. "EZHB_RST,EZH b reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 30. "EZHA_RST,EZH a reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 27. "TIMER1_RST,Timer 1 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 27. "TIMER1_RST,Timer 1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 26. "TIMER0_RST,Timer 0 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 26. "TIMER0_RST,Timer 0 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 25. "USB0_DEV_RST,USB0-FS DEV reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 25. "USB0_DEV_RST,USB0-FS DEV reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 25. "USB0_DEV_RST,USB0 DEV reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 22. "TIMER2_RST,Timer 2 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 22. "TIMER2_RST,Timer 2 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 19. "DMIC_RST,DMIC reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 18. "FC7_RST,FC7 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18. "FC7_RST,FC7 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 17. "FC6_RST,FC6 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 17. "FC6_RST,FC6 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 16. "FC5_RST,FC5 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 16. "FC5_RST,FC5 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 15. "FC4_RST,FC4 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 15. "FC4_RST,FC4 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 14. "FC3_RST,FC3 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 14. "FC3_RST,FC3 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 13. "FC2_RST,FC2 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 13. "FC2_RST,FC2 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 12. "FC1_RST,FC1 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 12. "FC1_RST,FC1 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 11. "FC0_RST,FC0 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 11. "FC0_RST,FC0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 10. "UTICK_RST,UTICK reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 10. "UTICK_RST,UTICK reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 7. "CAN_RST,CAN reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 7. "CAN_RST,CAN reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6. "SCTIPU_RST,SCTIPU reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 2. "SCT_RST,SCT reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 2. "SCT_RST,SCT reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 1. "OSTIMER_RST,OS Event Timer reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 1. "OSTIMER_RST,OS Event Timer reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 0. "MRT_RST,MRT reset control" "0: Bloc is not reset,1: Bloc is reset" endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0. "MRT_RST,MRT reset control" "0: Block is not reset,1: Block is reset" endif group.long 0x104++0x03 line.long 0x00 "PRESETCTRLX1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x108++0x03 line.long 0x00 "PRESETCTRL2,Peripheral reset control 2" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 30. "GPIO_SEC_INT_RST,GPIO secure int reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 30. "GPIO_SEC_INT_RST,GPIO secure int reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 29. "GPIO_SEC_RST,GPIO secure reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 29. "GPIO_SEC_RST,GPIO secure reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 28. "HS_LSPI_RST,HS LSPI reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 28. "HS_SPI_RST,HS SPI reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 27. "ANACTRL_RST,Analog control reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 27. "ANALOG_CTRL_RST,analog control reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 24. "CASPER_RST,Casper reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 24. "PKC_RST,PKC reset control" "0: Block is not reset.g,1: Block is reset" newline bitfld.long 0x00 23. "PUF_RST,PUF reset control reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 23. "PUF_RST,PUF reset control reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 22. "TIMER4_RST,Timer 4 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 22. "TIMER4_RST,Timer 4 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 21. "TIMER3_RST,Timer 3 reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 21. "TIMER3_RST,Timer 3 reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 20. "PLULUT_RST,PLU LUT reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 19. "PQ_RST,Power Quad reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 19. "PQ_RST,Power Quad reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18. "HASH_AES_RST,HASH_AES reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 18. "CSS_RST,CSS reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 17. "USB0_HOSTS_RST,USB0 Host Slave reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 17. "USB0_HOSTS_RST,USB0-FS Host Slave reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 17. "USB0_HOSTS_RST,USB0-FS Host Slave reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 16. "USB0_HOSTM_RST,USB0-FS Host Master reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 16. "USB0_HOSTM_RST,USB0-FS Host Master reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 16. "USB0_HOSTM_RST,USB0 Host Master reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 15. "SYSCTL_RST,SYSCTL Block reset" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 15. "SYSCTL_RST,SYSCTL Block reset" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 13. "RNG_RST,RNG reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 13. "RNG_RST,RNG reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 11. "CDOG_RST,Code Watchdog reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 8. "FREQME_RST,Frequency meter reset control" "0: Block is not reset,1: Block is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 8. "FREQME_RST,Frequency meter reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 7. "USB1_PHY_RST,USB1 PHY reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 7. "USB1_PHY_RST,USB1-HS PHY reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6. "USB1_RAM_RST,USB1 RAM reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 6. "SRAM_CTRL3_RST,SRAM Controller 3 reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 6. "USB1_RAM_RST,USB1-HS RAM reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 5. "USB1_DEV_RST,USB1 dev reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 5. "USB1_DEV_RST,USB1-HS dev reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 4. "USB1_HOST_RST,USB1-HS Host reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 4. "USB1_HOST_RST,USB1 Host reset control" "0: Bloc is not reset,1: Bloc is reset" newline bitfld.long 0x00 3. "SDIO_RST,SDIO reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 2. "COMP_RST,Comparator reset control" "0: Bloc is not reset,1: Bloc is reset" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 2. "COMP_RST,Analog comparator reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 1. "DMA1_RST,DMA1 reset control" "0: Block is not reset,1: Block is reset" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 1. "DMA1_RST,DMA1 reset control" "0: Bloc is not reset,1: Bloc is reset" endif group.long 0x108++0x03 line.long 0x00 "PRESETCTRLX2,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x10C++0x03 line.long 0x00 "PRESETCTRL3,Peripheral reset control 3" bitfld.long 0x00 18. "VREF_RST,VREF reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 17. "HSCMP2_RST,HSCMP2 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 16. "HSCMP1_RST,HSCMP1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 15. "HSCMP0_RST,HSCMP0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 14. "OPAMP2_RST,OPAMP2 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 13. "OPAMP1_RST,OPAMP1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 12. "OPAMP0_RST,OPAMP0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 11. "DAC2_RST,DAC2 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 10. "DAC1_RST,DAC1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 9. "FTM0_RST,FTM0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 8. "AOI1_RST,AOI1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 7. "AOI0_RST,AOI0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 6. "PWM1_RST,PWM1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 5. "PWM0_RST,PWM0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 4. "ENC1_RST,ENC1 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 3. "ENC0_RST,ENC0 reset control" "0: Block is not reset,1: Block is reset" newline bitfld.long 0x00 0. "I3C0_RST,I3C reset control" "0: Block is not reset,1: Block is reset" group.long 0x120++0x03 line.long 0x00 "PRESETCTRLSET[0],Peripheral reset control set register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" wgroup.long 0x120++0x03 line.long 0x00 "PRESETCTRLSET0,Peripheral reset control set n" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x124++0x03 line.long 0x00 "PRESETCTRLSET[1],Peripheral reset control set register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" wgroup.long 0x124++0x03 line.long 0x00 "PRESETCTRLSET1,Peripheral reset control set n" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x128++0x03 line.long 0x00 "PRESETCTRLSET[2],Peripheral reset control set register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" wgroup.long 0x128++0x03 line.long 0x00 "PRESETCTRLSET2,Peripheral reset control set n" hexmask.long.tbyte 0x00 12.--31. 1. "DATA_U,Data array value" newline hexmask.long.word 0x00 0.--10. 1. "DATA_L,Data array value" wgroup.long 0x12C++0x03 line.long 0x00 "PRESETCTRLSET3,Peripheral reset control set n" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x140++0x03 line.long 0x00 "PRESETCTRLCLR[0],Peripheral reset control clear register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat 2. (strings "0" "1" )(list 0x00 0x04 ) wgroup.long ($2+0x140)++0x03 line.long 0x00 "PRESETCTRLCLR$1,Peripheral reset control clear n" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) group.long ($2+0x144)++0x03 line.long 0x00 "PRESETCTRLCLR[$1],Peripheral reset control clear register $1" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end wgroup.long 0x148++0x03 line.long 0x00 "PRESETCTRLCLR2,Peripheral reset control clear n" hexmask.long.tbyte 0x00 12.--31. 1. "DATA_U,Data array value" newline hexmask.long.word 0x00 0.--10. 1. "DATA_L,Data array value" wgroup.long 0x14C++0x03 line.long 0x00 "PRESETCTRLCLR3,Peripheral reset control clear n" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" wgroup.long 0x160++0x03 line.long 0x00 "SWR_RESET,Software Reset" hexmask.long 0x00 0.--31. 1. "SWR_RESET,Write 0x5A00_0001 to generate a software_reset" wgroup.long 0x160++0x03 line.long 0x00 "SWR_RESET,generate a software_reset" hexmask.long 0x00 0.--31. 1. "SWR_RESET,Write 0x5A00_0001 to generate a software_reset" group.long 0x200++0x03 line.long 0x00 "AHBCLKCTRL0,AHB Clock control 0" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 29. "DAC0,Enables the clock for DAC0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 28. "ADC1,Enables the clock for ADC1" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 27. "ADC,Enables the clock for the ADC" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 27. "ADC0,Enables the clock for ADC0" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 26. "MAILBOX,Enables the clock for the Inter CPU communication Mailbox" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 23. "RTC,Enables the clock for the Real Time Clock (RTC)" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 22. "WWDT,Enables the clock for the Watchdog Timer" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 21. "CRCGEN,Enables the clock for the CRCGEN" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 20. "DMA0,Enables the clock for the DMA0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 19. "GINT,Enables the clock for the Group interrupt (GINT)" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 18. "PINT,Enables the clock for the Pin interrupt (PINT)" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 17. "GPIO3,Enables the clock for the GPIO3" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 16. "GPIO2,Enables the clock for the GPIO2" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 15. "GPIO1,Enables the clock for the GPIO1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 14. "GPIO0,Enables the clock for the GPIO0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 13. "IOCON,Enables the clock for the I/O controller" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 11. "MUX,Enables the clock for the Input Mux" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 10. "FLEXSPI,Enables the clock for the Flexspi" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 8. "FMC,Enables the clock for the FMC controller" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 7. "FLASH,Enables the clock for the Flash controller" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 6. "SRAM_CTRL4,Enables the clock for the SRAM Controller 4" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 5. "SRAM_CTRL3,Enables the clock for the SRAM Controller 3" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 4. "SRAM_CTRL2,Enables the clock for the SRAM Controller 2" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 3. "SRAM_CTRL1,Enables the clock for the SRAM Controller 1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 1. "ROM,Enables the clock for the ROM" "0: Disable Clock,1: Enable Clock" group.long 0x200++0x03 line.long 0x00 "AHBCLKCTRLX0,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x204++0x03 line.long 0x00 "AHBCLKCTRL1,AHB Clock control 1" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 31. "EZHB,Enables the clock for the EZH b" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 30. "EZHA,Enables the clock for the EZH a" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 27. "TIMER1,Enables the clock for the Timer 1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 26. "TIMER0,Enables the clock for the Timer 0" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 25. "USB0_DEV,Enables the clock for the USB0 DEV" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 25. "USB0_DEV,Enables the clock for the USB0-FS device" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 22. "TIMER2,Enables the clock for the Timer 2" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 19. "DMIC,Enables the clock for DMIC" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 18. "FC7,Enables the clock for the FC7" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 17. "FC6,Enables the clock for the FC6" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 16. "FC5,Enables the clock for the FC5" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 15. "FC4,Enables the clock for the FC4" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 14. "FC3,Enables the clock for the FC3" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 13. "FC2,Enables the clock for the FC2" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 12. "FC1,Enables the clock for the FC1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 11. "FC0,Enables the clock for the FC0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 10. "UTICK,Enables the clock for the UTICK" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 7. "CAN,Enables the clock for the CAN" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 2. "SCT,Enables the clock for the SCT" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 1. "OSTIMER,Enables the clock for the OS Event Timer" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 0. "MRT,Enables the clock for the MRT" "0: Disable Clock,1: Enable Clock" repeat 2. (strings "1" "2" )(list 0x00 0x04 ) group.long ($2+0x204)++0x03 line.long 0x00 "AHBCLKCTRLX$1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x208++0x03 line.long 0x00 "AHBCLKCTRL2,AHB Clock control 2" bitfld.long 0x00 30. "GPIO_SEC_INT,Enables the clock for the GPIO secure int" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 29. "GPIO_SEC,Enables the clock for the GPIO secure" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 28. "HS_LSPI,Enables the clock for the HS LSPI" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 28. "HS_SPI,Enables the clock for the HS SPI" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 27. "ANALOG_CTRL,Enables the clock for the Analog Controller block" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 27. "ANALOG_CTRL,Enables the clock for the analog control" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 24. "CASPER,Enables the clock for the Casper" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 24. "PKC,Enables the clock for the PKC" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 23. "PUF,Enables the clock for the PUF reset control" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 22. "TIMER4,Enables the clock for the Timer 4" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 21. "TIMER3,Enables the clock for the Timer 3" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 20. "PLULUT,Enables the clock for the PLU LUT" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 19. "PQ,Enables the clock for the Power Quad" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 18. "HASH_AES,Enables the clock for the HASH_AES" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 18. "CSS,Enables the clock for CSS" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 17. "USB0_HOSTS,Enables the clock for the USB0 Host Slave" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 17. "USB0_HOSTS,Enables the clock for the USB0-FS Host Slave" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 16. "USB0_HOSTM,Enables the clock for the USB0-FS Host Master" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 16. "USB0_HOSTM,Enables the clock for the USB0 Host Master" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 15. "SYSCTL,SYSCTL block clock" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 14. "PMUX1,Enables the clock for Peripheral Input Mux 1" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 13. "RNG,Enables the clock for the RNG" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 11. "CDOG,Enables the clock for the code watchdog" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 8. "FREQME,Enables the clock for the Frequency meter" "0: Disable Clock,1: Enable Clock" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 7. "USB1_PHY,Enables the clock for the USB1 PHY" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 7. "USB1_PHY,Enables the clock for the USB1-HS PHY" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6. "USB1_RAM,Enables the clock for the USB1 RAM" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 6. "USB1_RAM,Enables the clock for the USB1-HS RAM" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") bitfld.long 0x00 6. "SRAM_CTRL3,Enables the clock for the SRAM Controller 3" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 5. "USB1_DEV,Enables the clock for the USB1 dev" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 5. "USB1_DEV,Enables the clock for the USB1-HS device" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 4. "USB1_HOST,Enables the clock for the USB1-HS Host" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 4. "USB1_HOST,Enables the clock for the USB1 Host" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 3. "SDIO,Enables the clock for the SDIO" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 2. "COMP,Enables the clock for the Analog comparator" "0: Disable Clock,1: Enable Clock" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 2. "COMP,Enables the clock for the Comparator" "0: Disable Clock,1: Enable Clock" newline endif bitfld.long 0x00 1. "DMA1,Enables the clock for the DMA1" "0: Disable Clock,1: Enable Clock" group.long 0x20C++0x03 line.long 0x00 "AHBCLKCTRL3,AHB Clock Control 3" bitfld.long 0x00 18. "VREF,Enables the clock for VREF" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 17. "HSCMP2,Enables the clock for HSCMP2" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 16. "HSCMP1,Enables the clock for HSCMP1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 15. "HSCMP0,Enables the clock for HSCMP0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 14. "OPAMP2,Enables the clock for OPAMP2" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 13. "OPAMP1,Enables the clock for OPAMP1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 12. "OPAMP0,Enables the clock for OPAMP0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 11. "DAC2,Enables the clock for DAC2" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 10. "DAC1,Enables the clock for DAC1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 9. "FTM0,Enables the clock for FTM0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 8. "AOI1,Enables the clock for AOI1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 7. "AOI0,Enables the clock for AOI0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 6. "PWM1,Enables the clock for PWM1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 5. "PWM0,Enables the clock for PWM0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 4. "ENC1,Enables the clock for ENC1" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 3. "ENC0,Enables the clock for ENC0" "0: Disable Clock,1: Enable Clock" newline bitfld.long 0x00 0. "I3C0,Enables the clock for I3C0" "0: Disable Clock,1: Enable Clock" group.long 0x220++0x03 line.long 0x00 "AHBCLKCTRLSET[0],Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat 2. (increment 0 1) (increment 0 0x04) group.long ($2+0x220)++0x03 line.long 0x00 "AHBCLKCTRLSET[$1],AHB Clock Control Set $1" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x224++0x03 line.long 0x00 "AHBCLKCTRLSET[1],Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x228++0x03 line.long 0x00 "AHBCLKCTRLSET[2],AHB Clock Control Set" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x228++0x03 line.long 0x00 "AHBCLKCTRLSET[2],Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x22C++0x03 line.long 0x00 "AHBCLKCTRLSET[3],AHB Clock Control Set" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x240++0x03 line.long 0x00 "AHBCLKCTRLCLR[0],Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat 2. (increment 0 1) (increment 0 0x04) group.long ($2+0x240)++0x03 line.long 0x00 "AHBCLKCTRLCLR[$1],AHB Clock Control Clear $1" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) group.long ($2+0x244)++0x03 line.long 0x00 "AHBCLKCTRLCLR[$1],Peripheral reset control register $1" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end repeat 2. (increment 0 1) (increment 0 0x04) group.long ($2+0x248)++0x03 line.long 0x00 "AHBCLKCTRLCLR[$1],AHB Clock Control Clear $1" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x260++0x03 line.long 0x00 "SYSTICKCLKSEL0,System Tick Timer for CPU0 source select" bitfld.long 0x00 0.--2. "SEL,System Tick Timer for CPU0 source select" "0: System Tick 0 divided clock,1: FRO 1MHz clock,2: Oscillator 32 kHz clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x260++0x03 line.long 0x00 "SYSTICKCLKSELX0,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x268++0x03 line.long 0x00 "TRACECLKSEL,Trace clock source select" bitfld.long 0x00 0.--2. "SEL,Trace clock source select" "0: Trace divided clock,1: FRO 1MHz clock,2: Oscillator 32 kHz clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x26C++0x03 line.long 0x00 "CTIMERCLKSEL0,CTimer 0 clock source select" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,CTimer 0 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0.--2. "SEL,CTimer 0 clock source select" "0: Main clock,1: PLL0 clock,2: PLL1 clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif repeat 2. (strings "0" "1" )(list 0x00 0x04 ) group.long ($2+0x26C)++0x03 line.long 0x00 "CTIMERCLKSELX$1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x270++0x03 line.long 0x00 "CTIMERCLKSEL1,CTimer 1 clock source select" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,CTimer 1 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0.--2. "SEL,CTimer 1 clock source select" "0: Main clock,1: PLL0 clock,2: PLL1 clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif group.long 0x274++0x03 line.long 0x00 "CTIMERCLKSEL2,CTimer 2 clock source select" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,CTimer 2 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0.--2. "SEL,CTimer 2 clock source select" "0: Main clock,1: PLL0 clock,2: PLL1 clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif repeat 2. (strings "2" "3" )(list 0x00 0x04 ) group.long ($2+0x274)++0x03 line.long 0x00 "CTIMERCLKSELX$1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x278++0x03 line.long 0x00 "CTIMERCLKSEL3,CTimer 3 clock source select" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0.--2. "SEL,CTimer 3 clock source select" "0: Main clock,1: PLL0 clock,2: PLL1 clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,CTimer 3 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif group.long 0x27C++0x03 line.long 0x00 "CTIMERCLKSEL4,CTimer 4 clock source select" sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0.--2. "SEL,CTimer 4 clock source select" "0: Main clock,1: PLL0 clock,2: PLL1 clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,CTimer 4 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock" endif group.long 0x27C++0x03 line.long 0x00 "CTIMERCLKSELX4,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x280++0x03 line.long 0x00 "MAINCLKSELA,Main clock A source select" bitfld.long 0x00 0.--2. "SEL,Main clock A source select" "0: FRO 12 MHz clock,1: CLKIN clock,2: FRO 1MHz clock,3: FRO 96 MHz clock,?..." group.long 0x280++0x03 line.long 0x00 "MAINCLKSELA,Main clock source select A" bitfld.long 0x00 0.--2. "SEL,Main clock source select A" "0: FRO 12 MHz clock,1: CLKIN clock,2: FRO 1MHz clock,3: FRO 96 MHz clock,?..." group.long 0x284++0x03 line.long 0x00 "MAINCLKSELB,Main clock source select" bitfld.long 0x00 0.--2. "SEL,Main clock source select" "0: Main Clock A,1: PLL0 clock,2: PLL1 clock,3: Oscillator 32 kHz clock,?..." group.long 0x284++0x03 line.long 0x00 "MAINCLKSELB,Main clock source select B" bitfld.long 0x00 0.--2. "SEL,Main clock source select B" "0: Use the source selected in MAINCLKSELA,1: PLL0 clock,2: PLL1 clock,3: Oscillator 32 kHz clock,?..." group.long 0x288++0x03 line.long 0x00 "CLKOUTSEL,CLKOUT clock source select" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0.--3. "SEL,CLKOUT clock source select" "0: Main clock,1: PLL0 clock,2: CLKIN clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: PLL1 clock,6: Oscillator 32kHz clock,7: No clock,?,?,?,?,12: No clock,13: No clock,14: No clock,15: No clock" endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,CLKOUT clock source select" "0: Main clock,1: PLL0 clock,2: CLKIN clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: PLL1 clock,6: Oscillator 32kHz clock,7: No clock" endif group.long 0x290++0x03 line.long 0x00 "PLL0CLKSEL,PLL0 clock source select" bitfld.long 0x00 0.--2. "SEL,PLL0 clock source select" "0: FRO 12 MHz clock,1: CLKIN clock,2: FRO 1MHz clock,3: Oscillator 32kHz clock,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x294++0x03 line.long 0x00 "PLL1CLKSEL,PLL1 clock source select" bitfld.long 0x00 0.--2. "SEL,PLL1 clock source select" "0: FRO 12 MHz clock,1: CLKIN clock,2: FRO 1MHz clock,3: Oscillator 32kHz clock,4: No clock,5: No clock,6: No clock,7: No clock" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") group.long 0x2A0++0x03 line.long 0x00 "CANCLKSEL,CAN clock source select" bitfld.long 0x00 0.--2. "SEL,CAN clock source select" "0: CAN divided clock,1: FRO 1MHz clock,2: Oscillator 32 kHz clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock" endif group.long 0x2A4++0x03 line.long 0x00 "ADCCLKSEL,ADC clock source select" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 0.--2. "SEL,ADC clock source select" "0: Main clock,1: PLL0 clock,2: FRO 96 MHz clock,?,4: Xtal clock coming directly,5: No clock,6: No clock,7: No clock" endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,ADC clock source select" "0: Main clock,1: PLL0 clock,2: FRO 96 MHz clock,?,4: No clock,5: No clock,6: No clock,7: No clock" endif group.long 0x2A4++0x03 line.long 0x00 "ADC0CLKSEL,ADC0 clock source select" bitfld.long 0x00 0.--2. "SEL,ADC clock source select" "0: Main clock,1: PLL0 clock,2: FRO 96 MHz clock,?,4: XO to ADC Clock,5: No clock,6: No clock,7: No clock" group.long 0x2A8++0x03 line.long 0x00 "USB0CLKSEL,FS USB clock source select" bitfld.long 0x00 0.--2. "SEL,FS USB clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: No clock,5: PLL1 clock,6: No clock,7: No clock" group.long 0x2AC++0x03 line.long 0x00 "CLK32KCLKSEL,clock low speed source select for HS USB" bitfld.long 0x00 3. "SEL,clock low speed source select for HS USB" "0: Oscillator 32 kHz clock,1: FRO1MHz_divided clock" group.long 0x2B0++0x03 line.long 0x00 "FCCLKSEL0,Flexcomm Interface 0 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 0 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2B0++0x03 line.long 0x00 "FCCLKSELX0,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x2B0++0x03 line.long 0x00 "FCCLKSEL0,Flexcomm 0 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 0 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2B4++0x03 line.long 0x00 "FCCLKSEL1,Flexcomm Interface 1 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 1 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2B4++0x03 line.long 0x00 "FCCLKSEL1,Flexcomm 1 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 1 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2B4++0x03 line.long 0x00 "FCCLKSELX1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x2B8++0x03 line.long 0x00 "FCCLKSEL2,Flexcomm Interface 2 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 2 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2B8++0x03 line.long 0x00 "FCCLKSELX2,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x2B8++0x03 line.long 0x00 "FCCLKSEL2,Flexcomm 2 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 2 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2BC++0x03 line.long 0x00 "FCCLKSEL3,Flexcomm Interface 3 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 3 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2BC++0x03 line.long 0x00 "FCCLKSELX3,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x2BC++0x03 line.long 0x00 "FCCLKSEL3,Flexcomm 3 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 3 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2C0++0x03 line.long 0x00 "FCCLKSEL4,Flexcomm Interface 4 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 4 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2C0++0x03 line.long 0x00 "FCCLKSELX4,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x2C0++0x03 line.long 0x00 "FCCLKSEL4,Flexcomm 4 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 4 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2C4++0x03 line.long 0x00 "FCCLKSEL5,Flexcomm Interface 5 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 5 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2C4++0x03 line.long 0x00 "FCCLKSELX5,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x2C4++0x03 line.long 0x00 "FCCLKSEL5,Flexcomm 5 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 5 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2C8++0x03 line.long 0x00 "FCCLKSEL6,Flexcomm 6 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 6 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2C8++0x03 line.long 0x00 "FCCLKSEL6,Flexcomm Interface 6 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 6 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" repeat 2. (strings "6" "7" )(list 0x00 0x04 ) group.long ($2+0x2C8)++0x03 line.long 0x00 "FCCLKSELX$1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x2CC++0x03 line.long 0x00 "FCCLKSEL7,Flexcomm 7 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm 7 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2CC++0x03 line.long 0x00 "FCCLKSEL7,Flexcomm Interface 7 clock source select for Fractional Rate Divider" bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 7 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2D0++0x03 line.long 0x00 "HSSPICLKSEL,HS SPI clock source select" bitfld.long 0x00 0.--2. "SEL,HS SPI clock source select" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: No clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2D0++0x03 line.long 0x00 "HSLSPICLKSEL,HS LSPI clock source select" bitfld.long 0x00 0.--2. "SEL,HS LSPI clock source select" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: No clock,6: Oscillator 32 kHz clock,7: No clock" group.long 0x2E0++0x03 line.long 0x00 "MCLKCLKSEL,MCLK clock source select" bitfld.long 0x00 0.--2. "SEL,MCLK clock source select" "0: FRO 96 MHz clock,1: PLL0 clock,?,?,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x2F0++0x03 line.long 0x00 "SCTCLKSEL,SCTimer/PWM clock source select" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--2. "SEL,SCTimer/PWM clock source select" "0: Main clock,1: PLL0 clock,2: CLKIN clock,3: FRO 96 MHz clock,4: No clock,5: MCLK clock,6: No clock,7: No clock" endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 0.--2. "SEL,SCTimer/PWM clock source select" "0: Main clock,1: PLL0 clock,2: CLKIN clock,3: FRO 96 MHz clock,4: PLL1 clock,5: MCLK clock,6: No clock,7: No clock" endif group.long 0x2F8++0x03 line.long 0x00 "SDIOCLKSEL,SDIO clock source select" bitfld.long 0x00 0.--2. "SEL,SDIO clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: No clock,5: PLL1 clock,6: No clock,7: No clock" group.long 0x300++0x03 line.long 0x00 "SYSTICKCLKDIV0,System Tick Timer divider for CPU0" sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x304++0x03 line.long 0x00 "SYSTICKCLKDIV1,System Tick Timer divider for CPU1" rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x308++0x03 line.long 0x00 "TRACECLKDIV,TRACE clock divider" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") group.long 0x30C++0x03 line.long 0x00 "CANCLKDIV,CAN clock divider" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" endif group.long 0x320++0x03 line.long 0x00 "FLEXFRG0CTRL,Fractional rate divider for flexcomm 0" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x320++0x03 line.long 0x00 "FRGCTRL[0],Fractional rate divider for flexcomm n" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x320++0x03 line.long 0x00 "FLEXFRGXCTRL0,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x324++0x03 line.long 0x00 "FRGCTRL[1],Fractional rate divider for flexcomm n" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x324++0x03 line.long 0x00 "FLEXFRG1CTRL,Fractional rate divider for flexcomm 1" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" repeat 2. (strings "1" "2" )(list 0x00 0x04 ) group.long ($2+0x324)++0x03 line.long 0x00 "FLEXFRGXCTRL$1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x328++0x03 line.long 0x00 "FLEXFRG2CTRL,Fractional rate divider for flexcomm 2" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x328++0x03 line.long 0x00 "FRGCTRL[2],Fractional rate divider for flexcomm n" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x32C++0x03 line.long 0x00 "FLEXFRGXCTRL3,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x32C++0x03 line.long 0x00 "FLEXFRG3CTRL,Fractional rate divider for flexcomm 3" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" repeat 2. (increment 0 1) (increment 0 0x04) group.long ($2+0x32C)++0x03 line.long 0x00 "FRGCTRL[$1],Fractional rate divider for flexcomm n $1" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" repeat.end group.long 0x330++0x03 line.long 0x00 "FLEXFRGXCTRL4,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x330++0x03 line.long 0x00 "FLEXFRG4CTRL,Fractional rate divider for flexcomm 4" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x334++0x03 line.long 0x00 "FLEXFRG5CTRL,Fractional rate divider for flexcomm 5" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x334++0x03 line.long 0x00 "FLEXFRGXCTRL5,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" group.long 0x334++0x03 line.long 0x00 "FRGCTRL[5],Fractional rate divider for flexcomm n" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x338++0x03 line.long 0x00 "FLEXFRG6CTRL,Fractional rate divider for flexcomm 6" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x338++0x03 line.long 0x00 "FRGCTRL[6],Fractional rate divider for flexcomm n" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" repeat 2. (strings "6" "7" )(list 0x00 0x04 ) group.long ($2+0x338)++0x03 line.long 0x00 "FLEXFRGXCTRL$1,Peripheral reset control register" hexmask.long 0x00 0.--31. 1. "DATA,Data array value" repeat.end group.long 0x33C++0x03 line.long 0x00 "FRGCTRL[7],Fractional rate divider for flexcomm n" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x33C++0x03 line.long 0x00 "FLEXFRG7CTRL,Fractional rate divider for flexcomm 7" hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider" group.long 0x380++0x03 line.long 0x00 "AHBCLKDIV,System clock divider" sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x384++0x03 line.long 0x00 "CLKOUTDIV,CLKOUT clock divider" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x388++0x03 line.long 0x00 "FROHFDIV,FRO_HF (96MHz) clock divider" sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x38C++0x03 line.long 0x00 "WDTCLKDIV,WDT clock divider" sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--5. "DIV,Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x394++0x03 line.long 0x00 "ADCCLKDIV,ADC clock divider" rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x394++0x03 line.long 0x00 "ADC0CLKDIV,ADC0 clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") group.long 0x398++0x03 line.long 0x00 "USB0CLKDIV,USB0-FS Clock divider" sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" endif group.long 0x398++0x03 line.long 0x00 "USB0CLKDIV,USB0 Clock divider" rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x3A0++0x03 line.long 0x00 "FRO1MCLKDIV,FRO1MHz Clock divider (FRO1M_divided)" rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x3AC++0x03 line.long 0x00 "MCLKDIV,I2S MCLK clock divider" sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x3B4++0x03 line.long 0x00 "SCTCLKDIV,SCT/PWM clock divider" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline endif bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x3BC++0x03 line.long 0x00 "SDIOCLKDIV,SDIO clock divider" rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x3C4++0x03 line.long 0x00 "PLLCLKDIV,PLL clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x3C4++0x03 line.long 0x00 "PLL0CLKDIV,PLL0 clock divider" rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" repeat 5. (increment 0 1) (increment 0 0x04) group.long ($2+0x3D0)++0x03 line.long 0x00 "CTIMERCLKDIV[$1],CTimer i clock divider $1" bitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Stable divider clock,1: Unstable clock frequency" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock has stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" repeat.end group.long 0x3FC++0x03 line.long 0x00 "CLOCKGENUPDATELOCKOUT,Control clock configuration registers access (like xxxDIV xxxSEL)" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") hexmask.long 0x00 0.--31. 1. "CLOCKGENUPDATELOCKOUT,Control clock configuration registers access (for example xxxDIV xxxSEL)" endif sif cpuis("LPC5526*")||cpuis("LPC5528*") hexmask.long 0x00 0.--31. 1. "CLOCKGENUPDATELOCKOUT,Control clock configuration registers access (like xxxDIV xxxSEL)" endif group.long 0x3FC++0x03 line.long 0x00 "CLKUNLOCK,Clock configuration unlock" hexmask.long 0x00 0.--31. 1. "UNLOCK,Control clock configuration registers access (for example xxxDIV xxxSEL)" group.long 0x400++0x03 line.long 0x00 "FMCCR,FMC configuration register" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 12.--15. "FLASHTIM,Flash memory access time" "0: 1 system clock flash access time (for system..,1: 2 system clocks flash access time (for system..,2: 3 system clocks flash access time (for system..,3: 4 system clocks flash access time (for system..,4: 5 system clocks flash access time (for system..,5: 6 system clocks flash access time (for system..,6: 7 system clocks flash access time (for system..,7: 8 system clocks flash access time (for system..,8: 9 system clocks flash access time (for system..,9: 10 system clocks flash access time (for..,10: 11 system clocks flash access time (for..,11: 12 system clocks flash access time (for..,?..." newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 12.--15. "FLASHTIM,Flash memory access time" "0: 1 system clock flash access time (for system..,1: 2 system clocks flash access time (for system..,2: 3 system clocks flash access time (for system..,3: 4 system clocks flash access time (for system..,4: 5 system clocks flash access time (for system..,5: 6 system clocks flash access time (for system..,6: 7 system clocks flash access time (for system..,7: 8 system clocks flash access time (for system..,8: 9 system clocks flash access time (for system..,9: 10 system clocks flash access time (for..,10: 11 system clocks flash access time (for..,11: 12 system clocks flash access time (for..,?..." newline endif bitfld.long 0x00 6. "PREFOVR,Prefetch override" "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.." newline bitfld.long 0x00 5. "PREFEN,Prefetch enable" "0: No instruction prefetch is performed,1: Instruction prefetch is enabled" newline bitfld.long 0x00 4. "ACCEL,Acceleration enable" "0: Flash acceleration is disabled,1: Flash acceleration is enabled" newline bitfld.long 0x00 2.--3. "DATACFG,Data read configuration" "0: Data accesses from flash are not buffered,1: One buffer is used for all data accesses,2: All buffers can be used for data accesses,?..." newline bitfld.long 0x00 0.--1. "FETCHCFG,Instruction fetch configuration" "0: Instruction fetches from flash are not buffered,1: One buffer is used for all instruction fetches,2: All buffers may be used for instruction fetches,?..." group.long 0x400++0x03 line.long 0x00 "FMCCR,FMC configuration" bitfld.long 0x00 26.--27. "CLKDIV,CLKDIV default value is 00" "0: 1 division,1: 2 division,2: 3 division,3: 4 division" newline bitfld.long 0x00 20.--21. "ECCABORTEN,ECC error abort enable" "0,1,2,3" newline bitfld.long 0x00 12.--15. "FLASHTIM,Flash memory access time" "0: 1 system clock flash access time (for system..,1: 2 system clocks flash access time (for system..,2: 3 system clocks flash access time (for system..,3: 4 system clocks flash access time (for system..,4: 5 system clocks flash access time (for system..,5: 6 system clocks flash access time (for system..,6: 7 system clocks flash access time (for system..,7: 8 system clocks flash access time (for system..,8: 9 system clocks flash access time (for system..,9: 10 system clocks flash access time (for..,10: 11 system clocks flash access time (for..,11: 12 system clocks flash access time (for..,?..." newline bitfld.long 0x00 6. "PREFOVR,Prefetch override" "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.." newline bitfld.long 0x00 5. "PREFEN,Prefetch enable" "0: No instruction prefetch is performed,1: Instruction prefetch is enabled" newline bitfld.long 0x00 4. "ACCEL,Acceleration enable" "0: Flash acceleration is disabled,1: Flash acceleration is enabled" newline bitfld.long 0x00 2.--3. "DATACFG,Data read configuration" "0: Data accesses from flash are not buffered,1: One buffer is used for all data accesses,2: All buffers can be used for data accesses,?..." newline bitfld.long 0x00 0.--1. "FETCHCFG,Instruction fetch configuration" "0: Instruction fetches from flash are not buffered,1: One buffer is used for all instruction fetches,2: All buffers may be used for instruction fetches,?..." group.long 0x404++0x03 line.long 0x00 "ROMCR,ROM wait state" bitfld.long 0x00 0. "ROM_WAIT,ROM waiting Arm core and other masters" "0,1" group.long 0x40C++0x03 line.long 0x00 "USB0NEEDCLKCTRL,USB0 need clock control" bitfld.long 0x00 3. "POL_FS_HOST_NEEDCLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.." newline bitfld.long 0x00 2. "AP_FS_HOST_NEEDCLK,USB0 Host USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high" newline bitfld.long 0x00 1. "POL_FS_DEV_NEEDCLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.." newline bitfld.long 0x00 0. "AP_FS_DEV_NEEDCLK,USB0 Device USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") group.long 0x40C++0x03 line.long 0x00 "USB0NEEDCLKCTRL,USB0-FS need clock control" bitfld.long 0x00 3. "POL_FS_HOST_NEEDCLK,USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.." newline bitfld.long 0x00 2. "AP_FS_HOST_NEEDCLK,USB0-FS Host USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high" newline bitfld.long 0x00 1. "POL_FS_DEV_NEEDCLK,USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.." newline bitfld.long 0x00 0. "AP_FS_DEV_NEEDCLK,USB0-FS Device USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high" endif group.long 0x410++0x03 line.long 0x00 "USB0NEEDCLKSTAT,USB0 need clock status" rbitfld.long 0x00 1. "HOST_NEEDCLK,USB0 Host USB0_NEEDCLK signal status" "0: USB0 Host clock is low,1: USB0 Host clock is high" newline rbitfld.long 0x00 0. "DEV_NEEDCLK,USB0 Device USB0_NEEDCLK signal status" "0: USB0 Device clock is low,1: USB0 Device clock is high" sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5534*")||cpuis("LPC5536*") group.long 0x410++0x03 line.long 0x00 "USB0NEEDCLKSTAT,USB0-FS need clock status" rbitfld.long 0x00 1. "HOST_NEEDCLK,USB0-FS Host USB0_NEEDCLK signal status" "0: USB0-FS Host clock is low,1: USB0-FS Host clock is high" newline rbitfld.long 0x00 0. "DEV_NEEDCLK,USB0-FS Device USB0_NEEDCLK signal status" "0: USB0-FS Device clock is low,1: USB0-FS Device clock is high" endif group.long 0x414++0x03 line.long 0x00 "EZHINT,EZH interrupt hijack" hexmask.long 0x00 0.--31. 1. "EZHINT,EZH interrupt hijack" wgroup.long 0x41C++0x03 line.long 0x00 "FMCFLUSH,FMCflush control" bitfld.long 0x00 0. "FLUSH,Flush control" "0: No action is performed,1: Flush the FMC buffer contents" wgroup.long 0x41C++0x03 line.long 0x00 "FMCFLUSH,FMC flush control" bitfld.long 0x00 0. "FLUSH,Flush control" "0: No action,1: Flush the FMC buffer contents" group.long 0x420++0x03 line.long 0x00 "MCLKIO,MCLK control" bitfld.long 0x00 0. "MCLKIO,MCLK control" "0: input mode,1: output mode" group.long 0x424++0x03 line.long 0x00 "USB1NEEDCLKCTRL,USB1 need clock control" bitfld.long 0x00 4. "HS_DEV_WAKEUP_N,Software override of device controller PHY wake up logic" "0: Forces USB1_PHY to wake-up,1: Normal USB1_PHY behavior" newline bitfld.long 0x00 3. "POL_HS_HOST_NEEDCLK,USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of HOST_NEEDCLK triggers wake-up,1: Rising edge of HOST_NEEDCLK triggers wake-up" newline bitfld.long 0x00 2. "AP_HS_HOST_NEEDCLK,USB1 Host need clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high" newline bitfld.long 0x00 1. "POL_HS_DEV_NEEDCLK,USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of DEV_NEEDCLK triggers wake-up,1: Rising edge of DEV_NEEDCLK triggers wake-up" newline bitfld.long 0x00 0. "AP_HS_DEV_NEEDCLK,USB1 Device need_clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high" group.long 0x424++0x03 line.long 0x00 "USB1NEEDCLKCTRL,USB1-HS need clock control" bitfld.long 0x00 4. "HS_DEV_WAKEUP_N,Software override of device controller PHY wake up logic" "0: Forces USB1_PHY to wake-up,1: Normal USB1_PHY behavior" newline bitfld.long 0x00 3. "POL_HS_HOST_NEEDCLK,USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of HOST_NEEDCLK triggers wake-up,1: Rising edge of HOST_NEEDCLK triggers wake-up" newline bitfld.long 0x00 2. "AP_HS_HOST_NEEDCLK,USB1-HS Host need clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high" newline bitfld.long 0x00 1. "POL_HS_DEV_NEEDCLK,USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of DEV_NEEDCLK triggers wake-up,1: Rising edge of DEV_NEEDCLK triggers wake-up" newline bitfld.long 0x00 0. "AP_HS_DEV_NEEDCLK,USB1-HS Device need_clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high" group.long 0x428++0x03 line.long 0x00 "USB1NEEDCLKSTAT,USB1 need clock status" rbitfld.long 0x00 1. "HOST_NEEDCLK,USB1 Host need_clock signal status" "0: HOST_NEEDCLK is low,1: HOST_NEEDCLK is high" newline rbitfld.long 0x00 0. "DEV_NEEDCLK,USB1 Device need_clock signal status" "0: DEV_NEEDCLK is low,1: DEV_NEEDCLK is high" group.long 0x428++0x03 line.long 0x00 "USB1NEEDCLKSTAT,USB1-HS need clock status" rbitfld.long 0x00 1. "HOST_NEEDCLK,USB1-HS Host need_clock signal status" "0: HOST_NEEDCLK is low,1: HOST_NEEDCLK is high" newline rbitfld.long 0x00 0. "DEV_NEEDCLK,USB1-HS Device need_clock signal status" "0: DEV_NEEDCLK is low,1: DEV_NEEDCLK is high" group.long 0x440++0x03 line.long 0x00 "FLASHREMAP_SIZE,This 32-bit register contains the size of the image to remap in bytes" hexmask.long 0x00 0.--31. 1. "FLASHREMAP_SIZE,no description available" group.long 0x444++0x03 line.long 0x00 "FLASHREMAP_SIZE_DP,This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security" hexmask.long 0x00 0.--31. 1. "FLASHREMAP_SIZE,no description available" group.long 0x448++0x03 line.long 0x00 "FLASHREMAP_OFFSET,This 32-bit register contains the offset by which the image is to be remapped" hexmask.long 0x00 0.--31. 1. "FLASHREMAP_OFFSET,no description available" group.long 0x44C++0x03 line.long 0x00 "FLASHREMAP_OFFSET_DP,This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*") hexmask.long 0x00 0.--31. 1. "FLASHREMAP_OFFSET_DP,no description available" endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") hexmask.long 0x00 0.--31. 1. "FLASHREMAP_OFFSET,no description available" endif group.long 0x45C++0x03 line.long 0x00 "FLASHREMAP_LOCK,Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers" hexmask.long 0x00 0.--31. 1. "LOCK,Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers" group.long 0x460++0x03 line.long 0x00 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control" bitfld.long 0x00 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay as controlled by the CCLK_SAMPLE_DELAY field" "0: Disables sample delay,1: Enables sample delay" newline bitfld.long 0x00 24.--28. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay as controlled by the CCLK_DRV_DELAY field" "0: Disable drive delay,1: Enable drive delay" newline bitfld.long 0x00 16.--20. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7. "PHASE_ACTIVE,Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE" "0: Bypassed,1: Activates phase shift logic" newline bitfld.long 0x00 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in" "0: 0 degree shift,1: 90 degree shift,2: 180 degree shift,3: 270 degree shift" newline bitfld.long 0x00 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in" "0: 0 degree shift,1: 90 degree shift,2: 180 degree shift,3: 270 degree shift" group.long 0x464++0x03 line.long 0x00 "ADC1CLKSEL,ADC1 clock source select" bitfld.long 0x00 0.--2. "SEL,ADC clock source select" "0: Main clock,1: PLL0 clock,2: FRO 96 MHz clock,?,4: XO to ADC clock,5: No clock,6: No clock,7: No clock" group.long 0x468++0x03 line.long 0x00 "ADC1CLKDIV,ADC1 clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x470++0x03 line.long 0x00 "RAM_INTERLEAVE,Control RAM interleave integration" bitfld.long 0x00 0. "INTERLEAVE,Control RAM access for RAM_02 and RAM_03" "0: RAM access to RAM_02 and RAM_03 is consecutive,1: RAM access to RAM_02 and RAM_03 is interleaved" group.long 0x470++0x03 line.long 0x00 "CASPER_CTRL,Control CASPER integration" bitfld.long 0x00 0. "INTERLEAVE,Control RAM access for RAMX0 and RAMX1" "0: RAM access to RAMX0 and RAMX1 is consecutive,1: RAM access to RAMX0 and RAMX1 is interleaved" group.long 0x490++0x03 line.long 0x00 "DAC0CLKSEL,DAC0 functional clock selection" bitfld.long 0x00 0.--2. "SEL,DAC clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: ENUM_0x3,4: ENUM_0x4,5: PLL1 clock,6: ENUM_0x6,7: No clock" group.long 0x494++0x03 line.long 0x00 "DAC0CLKDIV,DAC0 functional clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x498++0x03 line.long 0x00 "DAC1CLKSEL,DAC1 functional clock selection" bitfld.long 0x00 0.--2. "SEL,DAC clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: ENUM_0x3,4: ENUM_0x4,5: PLL1 clock,6: ENUM_0x6,7: No clock" group.long 0x49C++0x03 line.long 0x00 "DAC1CLKDIV,DAC1 functional clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x4A0++0x03 line.long 0x00 "DAC2CLKSEL,DAC2 functional clock selection" bitfld.long 0x00 0.--2. "SEL,DAC clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: ENUM_0x3,4: ENUM_0x4,5: PLL1 clock,6: ENUM_0x6,7: No clock" group.long 0x4A4++0x03 line.long 0x00 "DAC2CLKDIV,DAC2 functional clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x4A8++0x03 line.long 0x00 "FLEXSPICLKSEL,FLEXSPI clock selection" bitfld.long 0x00 0.--3. "SEL,Flexspi clock select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO_HF,4: No clock,5: PLL1 clock,6: No clock,7: No clock,8: No clock,9: No clock,10: No clock,11: No clock,12: No clock,13: No clock,14: No clock,15: No clock" group.long 0x4AC++0x03 line.long 0x00 "FLEXSPICLKDIV,FLEXSPI clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x4B0++0x03 line.long 0x00 "CDPA_ENABLE,Enable protection" bitfld.long 0x00 0.--1. "CDPA_ENABLE,Enable control" "0,1,2,3" group.long 0x4B4++0x03 line.long 0x00 "CDPA_ENABLE_DP,Enable protection duplicate" bitfld.long 0x00 0.--1. "CDPA_ENABLE_DP,Enable control" "0,1,2,3" group.long 0x4B8++0x03 line.long 0x00 "CDPA_CONFIG,CDPA base address" hexmask.long.word 0x00 0.--8. 1. "CDPA_START_PAGE,Specifies the size of CDPA in number of pages" group.long 0x4D0++0x03 line.long 0x00 "FLASH_HIDING_LOCKOUT_ADDR,Flash hiding lockout address" hexmask.long 0x00 0.--31. 1. "flash_hiding_lockout_addr,while flash hiding is disabled register write is locked" group.long 0x4D4++0x03 line.long 0x00 "FLASH_HIDING_BASE_ADDR,Flash hiding base address" hexmask.long.tbyte 0x00 0.--17. 1. "flash_hiding_base_addr,Base address for flash hiding" group.long 0x4D8++0x03 line.long 0x00 "FLASH_HIDING_BASE_DP_ADDR,Flash hiding base DP address" hexmask.long.tbyte 0x00 0.--17. 1. "flash_hiding_base_addr,Base address for flash hiding" group.long 0x4DC++0x03 line.long 0x00 "FLASH_HIDING_SIZE_ADDR,Hiding size address" hexmask.long.tbyte 0x00 0.--17. 1. "flash_hiding_size_addr,Size address for flash hiding" group.long 0x4E0++0x03 line.long 0x00 "FLASH_HIDING_SIZE_DP_ADDR,Hiding size DP address" hexmask.long.tbyte 0x00 0.--17. 1. "flash_hiding_size_dp_addr,Size address for flash hiding" group.long 0x52C++0x03 line.long 0x00 "PLLCLKDIVSEL,PLL clock divider clock selection" bitfld.long 0x00 0.--2. "SEL,Flexspi clock select" "0: PLL0 clock,1: PLL1 clock,2: No clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x530++0x03 line.long 0x00 "I3CFCLKSEL,I3C functional clock selection" bitfld.long 0x00 0.--2. "SEL,I3C clock select" "0: Main clock,1: FRO_HF_DIV,2: No clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x534++0x03 line.long 0x00 "I3CFCLKSTCSEL,I3C FCLK_STC clock selection" bitfld.long 0x00 0.--2. "SEL,I3C FCLK_STC clock select" "0: I3CFCLK,1: FRO_1M,2: No clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x538++0x03 line.long 0x00 "I3CFCLKSTCDIV,I3C FCLK_STC clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x53C++0x03 line.long 0x00 "I3CFCLKSDIV,I3C FCLKS clock divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x540++0x03 line.long 0x00 "I3CFCLKDIV,I3C FCLK divider" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7" group.long 0x544++0x03 line.long 0x00 "I3CFCLKSSEL,I3C FCLK_S selection" bitfld.long 0x00 0.--2. "SEL,I3C FCLK_S clock select" "0: FRO_1M,1: No clock,2: No clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock" group.long 0x548++0x03 line.long 0x00 "DMICFCLKSEL,DMIC clock selection" bitfld.long 0x00 0.--2. "SEL,DMIC clock select" "0: Main clock,1: PLL0 clock,2: Clock in,3: FRO_HF,4: PLL1 clock,5: MCLK in,6: No clock,7: No clock" group.long 0x54C++0x03 line.long 0x00 "DMICFCLKDIV,DMIC clock division" rbitfld.long 0x00 31. "UNSTAB,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stopped" newline bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" group.long 0x560++0x03 line.long 0x00 "PLL1CTRL,PLL1 550m control" bitfld.long 0x00 24. "SKEWEN,Skew mode" "0: skewmode is disable,1: skewmode is enable" newline bitfld.long 0x00 23. "FRMCLKSTABLE,free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable" "0,1" newline bitfld.long 0x00 22. "FRMEN," "0,1" newline bitfld.long 0x00 21. "CLKEN,enable the output clock" "0: Disable the output clock,1: Enable the output clock" newline bitfld.long 0x00 20. "BYPASSPOSTDIV,bypass of the post-divider" "0: use the post-divider,1: bypass of the post-divider" newline bitfld.long 0x00 19. "BYPASSPREDIV,bypass of the pre-divider" "0: use the pre-divider,1: bypass of the pre-divider" newline bitfld.long 0x00 18. "BWDIRECT,control of the bandwidth of the PLL" "0: the bandwidth is changed synchronously with..,1: modify the bandwidth of the PLL directly" newline bitfld.long 0x00 17. "LIMUPOFF,limup_off = 1 in spread spectrum and fractional PLL applications" "0,1" newline bitfld.long 0x00 16. "BYPASSPOSTDIV2,bypass of the divide-by-2 divider in the post-divider" "0: use the divide-by-2 divider in the post-divider,1: bypass of the divide-by-2 divider in the.." newline bitfld.long 0x00 15. "BYPASSPLL,Bypass PLL input clock is sent directly to the PLL output (default)" "0: use PLL,1: PLL input clock is sent directly to the PLL.." newline bitfld.long 0x00 10.--14. "SELP,Bandwidth select P value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--9. "SELI,Bandwidth select I value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--3. "SELR,Bandwidth select R value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x564++0x03 line.long 0x00 "PLL1STAT,PLL1 550m status" rbitfld.long 0x00 4. "FRMDET,free running detector output (active high)" "0,1" newline rbitfld.long 0x00 3. "POSTDIVACK,post-divider ratio change acknowledge" "0,1" newline rbitfld.long 0x00 2. "FEEDDIVACK,feedback divider ratio change acknowledge" "0,1" newline rbitfld.long 0x00 1. "PREDIVACK,pre-divider ratio change acknowledge" "0,1" newline rbitfld.long 0x00 0. "LOCK,lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz" "0,1" group.long 0x568++0x03 line.long 0x00 "PLL1NDEC,PLL1 550m N divider" bitfld.long 0x00 8. "NREQ,pre-divider ratio change request" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "NDIV,pre-divider divider ratio (N-divider)" group.long 0x56C++0x03 line.long 0x00 "PLL1MDEC,PLL1 550m M divider" bitfld.long 0x00 16. "MREQ,feedback ratio change request" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "MDIV,feedback divider divider ratio (M-divider)" group.long 0x570++0x03 line.long 0x00 "PLL1PDEC,PLL1 550m P divider" bitfld.long 0x00 5. "PREQ,feedback ratio change request" "0,1" newline bitfld.long 0x00 0.--4. "PDIV,post-divider divider ratio (P-divider)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x580++0x03 line.long 0x00 "PLL0CTRL,PLL0 550m control" bitfld.long 0x00 24. "SKEWEN,skew mode" "0: skew mode is disable,1: skew mode is enable" newline bitfld.long 0x00 23. "FRMCLKSTABLE,free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable" "0,1" newline bitfld.long 0x00 22. "FRMEN,free running mode" "0: free running mode is disable,1: free running mode is enable" newline bitfld.long 0x00 21. "CLKEN,enable the output clock" "0: disable the output clock,1: enable the output clock" newline bitfld.long 0x00 20. "BYPASSPOSTDIV,bypass of the post-divider" "0: use the post-divider,1: bypass of the post-divider" newline bitfld.long 0x00 19. "BYPASSPREDIV,bypass of the pre-divider" "0: use the pre-divider,1: bypass of the pre-divider" newline bitfld.long 0x00 18. "BWDIRECT,Control of the bandwidth of the PLL" "0: the bandwidth is changed synchronously with..,1: modify the bandwidth of the PLL directly" newline bitfld.long 0x00 17. "LIMUPOFF,limup_off = 1 in spread spectrum and fractional PLL applications" "0,1" newline bitfld.long 0x00 16. "BYPASSPOSTDIV2,bypass of the divide-by-2 divider in the post-divider" "0: use the divide-by-2 divider in the post-divider,1: bypass of the divide-by-2 divider in the.." newline bitfld.long 0x00 15. "BYPASSPLL,Bypass PLL input clock is sent directly to the PLL output (default)" "0: use PLL,1: Bypass PLL input clock is sent directly to.." newline bitfld.long 0x00 10.--14. "SELP,Bandwidth select P value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 4.--9. "SELI,Bandwidth select I value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--3. "SELR,Bandwidth select R value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x584++0x03 line.long 0x00 "PLL0STAT,PLL0 550m status" rbitfld.long 0x00 4. "FRMDET,free running detector output (active high)" "0,1" newline rbitfld.long 0x00 3. "POSTDIVACK,post-divider ratio change acknowledge" "0,1" newline rbitfld.long 0x00 2. "FEEDDIVACK,feedback divider ratio change acknowledge" "0,1" newline rbitfld.long 0x00 1. "PREDIVACK,pre-divider ratio change acknowledge" "0,1" newline rbitfld.long 0x00 0. "LOCK,lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz" "0,1" group.long 0x588++0x03 line.long 0x00 "PLL0NDEC,PLL0 550m N divider" bitfld.long 0x00 8. "NREQ,pre-divider ratio change request" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "NDIV,pre-divider divider ratio (N-divider)" group.long 0x58C++0x03 line.long 0x00 "PLL0PDEC,PLL0 550m P divider" bitfld.long 0x00 5. "PREQ,feedback ratio change request" "0,1" newline bitfld.long 0x00 0.--4. "PDIV,post-divider divider ratio (P-divider)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x590++0x03 line.long 0x00 "PLL0SSCG0,PLL0 Spread Spectrum Wrapper control register 0" hexmask.long 0x00 0.--31. 1. "MD_LBS,input word of the wrapper bit 31 to 0" group.long 0x590++0x03 line.long 0x00 "PLL0SSCG0,PLL0 Spread Spectrum control 0" hexmask.long 0x00 0.--31. 1. "MD_LBS,input word of the wrapper bit 31 to 0" group.long 0x594++0x03 line.long 0x00 "PLL0SSCG1,PLL0 Spread Spectrum control 1" bitfld.long 0x00 28. "SEL_EXT,to select mdiv_ext and mreq_ext sel_ext =" "0: mdiv ~ md[32:0] mreq = 1 sel_ext =,1: mdiv = mdiv_ext mreq = mreq_ext" newline bitfld.long 0x00 27. "DITHER,dithering between two modulation frequencies in a random way or in a pseudo random way (white noise) in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen" "0,1" newline bitfld.long 0x00 26. "MREQ,to select an external mreq value" "0,1" newline hexmask.long.word 0x00 10.--25. 1. "MDIV_EXT,to select an external mdiv value" newline bitfld.long 0x00 8.--9. "MC,modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL giving a flat frequency spectrum" "0,1,2,3" newline bitfld.long 0x00 5.--7. "MR,programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] =" "0: kss = 0 (no spread spectrum),1: kss ~ 1 mr[2:0] =,2: kss ~ 1,?..." newline bitfld.long 0x00 2.--4. "MF,programmable modulation frequency fm = Fref/Nss mf[2:0] =" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1. "MD_REQ,md change request" "0,1" newline bitfld.long 0x00 0. "MD_MBS,input word of the wrapper bit 32" "0,1" group.long 0x594++0x03 line.long 0x00 "PLL0SSCG1,PLL0 Spread Spectrum Wrapper control register 1" bitfld.long 0x00 28. "SEL_EXT,to select mdiv_ext and mreq_ext sel_ext =" "0: mdiv ~ md[32:0] mreq = 1 sel_ext =,1: mdiv = mdiv_ext mreq = mreq_ext" newline bitfld.long 0x00 27. "DITHER,dithering between two modulation frequencies in a random way or in a pseudo random way (white noise) in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen" "0,1" newline bitfld.long 0x00 26. "MREQ,to select an external mreq value" "0,1" newline hexmask.long.word 0x00 10.--25. 1. "MDIV_EXT,to select an external mdiv value" newline bitfld.long 0x00 8.--9. "MC,modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL giving a flat frequency spectrum" "0,1,2,3" newline bitfld.long 0x00 5.--7. "MR,programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] =" "0: kss = 0 (no spread spectrum),1: kss ~ 1 mr[2:0] =,2: kss ~ 1,?..." newline bitfld.long 0x00 2.--4. "MF,programmable modulation frequency fm = Fref/Nss mf[2:0] =" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1. "MD_REQ,md change request" "0,1" newline bitfld.long 0x00 0. "MD_MBS,input word of the wrapper bit 32" "0,1" group.long 0x5D0++0x03 line.long 0x00 "DAC_ISO_CTRL,DAC Isolation Control" bitfld.long 0x00 2. "DAC2_ISO,DAC2 Isolation" "0: DAC2 isolation disabled,1: DAC2 isolation enabled" newline bitfld.long 0x00 1. "DAC1_ISO,DAC1 Isolation" "0: DAC1 isolation disabled,1: DAC1 isolation enabled" newline bitfld.long 0x00 0. "DAC0_ISO,DAC0 Isolation" "0: DAC0 isolation disabled,1: DAC0 isolation enabled" group.long 0x680++0x03 line.long 0x00 "STARTER0,Start logic wake-up enable" bitfld.long 0x00 31. "WAKEUP_MAILBOX0,WAKEUP_MAILBOX0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 30. "EZH_ARCH_B0,EZH_ARCH_B0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 29. "RTC_LITE0,RTC_LITE0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 28. "USB0,USB0-FS interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 27. "USB0_NEEDCLK,USB0_NEEDCLK interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 25. "DMIC,DMIC interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 24. "ACMP_OVR,ACMP_OVR interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 23. "ADC1,ADC1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 22. "ADC0,ADC0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 21. "FLEXINT7,FLEXINT7 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 20. "FLEXINT6,FLEXINT6 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 19. "FLEXINT5,FLEXINT5 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 18. "FLEXINT4,FLEXINT4 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 17. "FLEXINT3,FLEXINT3 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 16. "FLEXINT2,FLEXINT2 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 15. "FLEXINT1,FLEXINT1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 14. "FLEXINT0,FLEXINT0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 13. "CTIMER3,CTIMER3 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 12. "SCT0,SCT0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 11. "CTIMER1,CTIMER1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 10. "CTIMER0,CTIMER0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 9. "MRT0,MRT0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 8. "UTICK0,UTICK0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 7. "PIO_INT3,PIO_INT3 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 6. "PIO_INT2,PIO_INT2 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 5. "PIO_INT1,PIO_INT1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 4. "PIO_INT0,PIO_INT0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 3. "GINT1,GINT1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 2. "GINT0,GINT0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 1. "SDMA0,SDMA0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 0. "SYS,SYS interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" group.long 0x684++0x03 line.long 0x00 "STARTER1,Start logic wake-up enable" bitfld.long 0x00 30. "I3C0,I3C0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 28. "CODE_WDG0,CODE WDG0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 27. "SPI_HS,SPI_HS interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 26. "SDMA1,SDMA1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 25. "PQ,PQ interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 24. "QDDKEY,QDDKEY interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 23. "PKC,PKC interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 22. "SHA,SHA interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 21. "SEC_VIO,SEC_VIO interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 20. "FREQ_ME_PLUS,FREQME interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 19. "SEC_GPIO_INT01,SEC_GPIO_INT01 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 18. "SEC_GPIO_INT00,SEC_GPIO_INT00 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 17. "SEC_HYPERVISOR_CALL,SEC_HYPERVISOR_CALL interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 13. "SPI_FILTER,SPI_FILTER interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 12. "CAN0_IRQ1,CAN0_IRQ0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 11. "CAN0_IRQ0,CAN0_IRQ0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 7. "FLEXSPI,FLEXSPI interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 6. "OS_EVENT,OS_EVENT interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 5. "CTIMER4,CTIMER4 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 4. "CTIMER2,CTIMER2 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 3. "GPIO_INT07,GPIO_INT07 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 2. "GPIO_INT06,GPIO_INT06 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 1. "GPIO_INT05,GPIO_INT05 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 0. "GPIO_INT04,GPIO_INT04 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" group.long 0x688++0x03 line.long 0x00 "STARTER2,Start logic wake-up enable" bitfld.long 0x00 31. "FLEXPWM1_RELOAD0_IRQ,FlexPWM1 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 30. "FLEXPWM1_COMPARE0_IRQ,FlexPWM1 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 29. "FLEXPWM1_RELOAD_ERR_IRQ,FlexPWM1 reload error interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 28. "FLEXPWM1_FAULT_IRQ,FlexPWM1 fault interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 27. "FLEXPWM1_CAPTURE_IRQ,FlexPWM1 capture interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 26. "FLEXPWM0_RELOAD3_IRQ,FlexPWM0 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 25. "FLEXPWM0_COMPARE3_IRQ,FlexPWM0 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 24. "FLEXPWM0_RELOAD2_IRQ,FlexPWM0 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 23. "FLEXPWM0_COMPARE2_IRQ,FlexPWM0 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 22. "FLEXPWM0_RELOAD1_IRQ,FlexPWM0 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 21. "FLEXPWM0_COMPARE1_IRQ,FlexPWM0 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 20. "FLEXPWM0_RELOAD0_IRQ,FlexPWM0 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 19. "FLEXPWM0_COMPARE0_IRQ,FlexPWM0 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 18. "FLEXPWM0_RELOAD_ERR_IRQ,FlexPWM0 reload error interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 17. "FLEXPWM0_FAULT_IRQ,FlexPWM0 fault interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 16. "FLEXPWM0_CAPTURE_IRQ,FlexPWM0 capture interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 15. "HS_CMP2_IRQ,HS_CMP2 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 14. "HS_CMP1_IRQ,HS_CMP1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 13. "HS_CMP0_IRQ,HS_CMP0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 12. "DAC2_IRQ,DAC2 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 11. "DAC1_IRQ,DAC1 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 10. "DAC0_IRQ,DAC0 interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 2. "TAMPER_IRQ,Tamper interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 1. "CSS_IRQ1,CSS_IRQ1 (Digital Glitch Detect)" "0: Wake-up disabled,1: Wake-up enabled" group.long 0x68C++0x03 line.long 0x00 "STARTER3,Start logic wake-up enable" bitfld.long 0x00 21. "PVTVF1_RED_IRQ,PVTVF1 red interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 20. "PVTVF1_AMBER_IRQ,PVTVF1 amber interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 19. "PVTVF0_RED_IRQ,PVTVF0 red interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 18. "PVTVF0_AMBER_IRQ,PVTVF0 amber interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 17. "PKC_ERR_IRQ,PKC error interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 16. "CSSV2_ERR,CSSv2 error interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 14. "ITRC_IRQ,ITRC interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 13. "ENC1_IDX_IRQ,ENC1 IDX interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 12. "ENC1_WDG_IRQ,ENC1 WDOG interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 11. "ENC1_HOME_IRQ,ENC1 home interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 10. "ENC1_COMPARE_IRQ,ENC1 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 9. "ENCO_IDX_IRQ,ENC0 IDX interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 8. "ENCO_WDG_IRQ,ENC0 WDOG interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 7. "ENCO_HOME_IRQ,ENC0 home interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 6. "ENCO_COMPARE_IRQ,ENC0 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 5. "FLEXPWM1_RELOAD3_IRQ,FlexPWM1 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 4. "FLEXPWM1_COMPARE3_IRQ,FlexPWM1 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 3. "FLEXPWM1_RELOAD2_IRQ,FlexPWM1 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 2. "FLEXPWM1_COMPARE2_IRQ,FlexPWM1 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 1. "FLEXPWM1_RELOAD1_IRQ,FlexPWM1 reload interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" newline bitfld.long 0x00 0. "FLEXPWM1_COMPARE1_IRQ,FlexPWM1 compare interrupt wake-up" "0: Wake-up disabled,1: Wake-up enabled" wgroup.long 0x6A0++0x03 line.long 0x00 "STARTERSET0,Set bits in STARTER" bitfld.long 0x00 31. "WAKEUP_MAILBOX0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 30. "EZH_ARCH_B0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 29. "RTC_LITE0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 28. "USB0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 27. "USB0_NEEDCLK_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 24. "ADC0_THCMP_OVR_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 22. "ADC0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 21. "FLEXINT7_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 20. "FLEXINT6_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 19. "FLEXINT5_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 18. "FLEXINT4_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 17. "FLEXINT3_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 16. "FLEXINT2_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 15. "FLEXINT1_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 14. "FLEXINT0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 13. "CTIMER3_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 12. "SCT0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 11. "CTIMER1_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 10. "CTIMER0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 9. "MRT0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 8. "UTICK0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 7. "GPIO_INT03_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 6. "GPIO_INT02_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 5. "GPIO_INT01_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 4. "GPIO_INT00_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 3. "GPIO_GLOBALINT1_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 2. "GPIO_GLOBALINT0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 1. "SDMA0_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 0. "SYS_SET,Writing ones to this register sets the corresponding bit in the STARTER0 register" "0,1" wgroup.long 0x6A4++0x03 line.long 0x00 "STARTERSET1,Set bits in STARTER" bitfld.long 0x00 31. "WAKEUPPADS_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 27. "SPI_HS_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 26. "SDMA1_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 25. "PQ_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 24. "QDDKEY_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 19. "SEC_GPIO_INT01_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 18. "SEC_GPIO_INT00_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 17. "SEC_HYPERVISOR_CALL_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 6. "OS_EVENT_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 5. "CTIMER4_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 4. "CTIMER2_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 3. "GPIO_INT07_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 2. "GPIO_INT06_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 1. "GPIO_INT05_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 0. "GPIO_INT04_SET,Writing ones to this register sets the corresponding bit in the STARTER1 register" "0,1" group.long 0x6A8++0x03 line.long 0x00 "STARTERSET2,Set bits in STARTER" bitfld.long 0x00 31. "FLEXPWM1_RELOAD0_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 30. "FLEXPWM1_COMPARE0_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 29. "FLEXPWM1_RELOAD_ERROR_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 28. "FLEXPWM1_FAULT_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 27. "FLEXPWM1_CAPTURE_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 26. "FLEXPWM0_RELOAD3_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 25. "FLEXPWM0_COMPARE3_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 24. "FLEXPWM0_RELOAD2_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 23. "FLEXPWM0_COMPARE2_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 22. "FLEXPWM0_RELOAD1_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 21. "FLEXPWM0_COMPARE1_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 20. "FLEXPWM0_RELOAD0_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 19. "FLEXPWM0_COMPARE0_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 18. "FLEXPWM0_RELOAD_ERROR_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 17. "FLEXPWM0_FAULT_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 16. "FLEXPWM0_CAPTURE_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 15. "HS_CMP2_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 14. "HS_CMP1_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 13. "HS_CMP0_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 12. "DAC2_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 11. "DAC1_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 10. "DAC0_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 2. "TAMPER_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" newline bitfld.long 0x00 1. "CSS_SET,Writing ones to this register sets the corresponding bit in the STARTER2 register" "0,1" group.long 0x6AC++0x03 line.long 0x00 "STARTERSET3,Set bits in STARTER" bitfld.long 0x00 21. "PVTVF1_RED_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 20. "PVTVF1_AMBER_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 19. "PVTVF0_RED_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 18. "PVTVF0_AMBER_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 17. "PKC_ERR_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 16. "CSSV2_ERR_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 14. "ITRC_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 13. "ENC1_IDX_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 12. "ENC1_WDG_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 11. "ENC1_HOME_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 10. "ENC1_COMPARE_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 9. "ENC0_IDX_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 8. "ENC0_WDG_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 7. "ENC0_HOME_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 6. "ENC0_COMPARE_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 5. "FLEXPWM1_RELOAD3_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 4. "FLEXPWM1_COMPARE3_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 3. "FLEXPWM1_RELOAD2_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 2. "FLEXPWM1_COMPARE2_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 1. "FLEXPWM1_RELOAD1_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" newline bitfld.long 0x00 0. "FLEXPWM1_COMPARE1_SET,Writing ones to this register sets the corresponding bit in the STARTER3 register" "0,1" wgroup.long 0x6C0++0x03 line.long 0x00 "STARTERCLR0,Clear bits in STARTER" bitfld.long 0x00 31. "WAKEUP_MAILBOX0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 30. "EZH_ARCH_B0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 29. "RTC_LITE0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 28. "USB0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 27. "USB0_NEEDCLK_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 24. "ADC0_THCMP_OVR_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 22. "ADC0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 21. "FLEXINT7_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 20. "FLEXINT6_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 19. "FLEXINT5_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 18. "FLEXINT4_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 17. "FLEXINT3_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 16. "FLEXINT2_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 15. "FLEXINT1_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 14. "FLEXINT0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 13. "CTIMER3_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 12. "SCT0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 11. "CTIMER1_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 10. "CTIMER0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 9. "MRT0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 8. "UTICK0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 7. "GPIO_INT03_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 6. "GPIO_INT02_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 5. "GPIO_INT01_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 4. "GPIO_INT00_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 3. "GPIO_GLOBALINT1_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 2. "GPIO_GLOBALINT0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 1. "SDMA0_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" newline bitfld.long 0x00 0. "SYS_CLR,Writing ones to this register clears the corresponding bit in the STARTER0 register" "0,1" wgroup.long 0x6C4++0x03 line.long 0x00 "STARTERCLR1,Clear bits in STARTER" bitfld.long 0x00 31. "WAKEUPPADS_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 27. "SPI_HS_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 26. "SDMA1_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 25. "PQ_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 24. "QDDKEY_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 19. "SEC_GPIO_INT01_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 18. "SEC_GPIO_INT00_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 17. "SEC_HYPERVISOR_CALL_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 6. "OS_EVENT_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 5. "CTIMER4_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 4. "CTIMER2_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 3. "GPIO_INT07_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 2. "GPIO_INT06_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 1. "GPIO_INT05_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" newline bitfld.long 0x00 0. "GPIO_INT04_CLR,Writing ones to this register clears the corresponding bit in the STARTER1 register" "0,1" group.long 0x704++0x03 line.long 0x00 "FUNCRETENTIONCTRL,Functional retention control" hexmask.long.word 0x00 14.--23. 1. "RET_LENTH,lenth of Scan chains to save" newline hexmask.long.word 0x00 1.--13. 1. "RET_START,Start address divided by 4 inside SRAMX bank" newline bitfld.long 0x00 0. "FUNCRETENA,functional retention in power down only" "0: disable functional retention,1: enable functional retention" group.long 0x704++0x03 line.long 0x00 "FUNCRETENTIONCTRL,Functional retention control register" hexmask.long.word 0x00 14.--23. 1. "RET_LENTH,lenth of Scan chains to save" newline hexmask.long.word 0x00 1.--13. 1. "RET_START,Start address divided by 4 inside SRAMX bank" newline bitfld.long 0x00 0. "FUNCRETENA,functional retention in power down only" "0: disable functional retention,1: enable functional retention" group.long 0x780++0x03 line.long 0x00 "HARDWARESLEEP,Hardware Sleep control" bitfld.long 0x00 31. "HW_ENABLE_FRO192M,Set this bit if FRO192M is diabled" "0,1" newline bitfld.long 0x00 6. "DAC,Wake for DAC0/1/2" "0,1" newline bitfld.long 0x00 5. "SDMA1,Wake for DMA1" "0,1" newline bitfld.long 0x00 3. "SDMA0,Wake for DMA0" "0,1" newline bitfld.long 0x00 2. "DMIC,Wake for DMIC" "0,1" newline bitfld.long 0x00 1. "PERIPHERALS,Wake for Flexcomms" "0,1" newline bitfld.long 0x00 0. "FORCED,Force peripheral clocking to stay on during Deep Sleep and Power-down modes" "0,1" group.long 0x800++0x03 line.long 0x00 "CPUCTRL,CPU Control for multiple processors" bitfld.long 0x00 5. "CPU1RSTEN,CPU1 reset" "0: The CPU1 is not being reset,1: The CPU1 is being reset" newline bitfld.long 0x00 3. "CPU1CLKEN,CPU1 clock enable" "0: The CPU1 clock is not enabled,1: The CPU1 clock is enabled" group.long 0x804++0x03 line.long 0x00 "CPBOOT,Coprocessor Boot Address" hexmask.long 0x00 0.--31. 1. "CPBOOT,Coprocessor Boot Address for CPU1" group.long 0x80C++0x03 line.long 0x00 "CPSTAT,CPU Status" sif cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 3. "CPU1LOCKUP,The CPU1 lockup state" "0: the CPU is not in lockup,1: the CPU is in lockup" newline endif rbitfld.long 0x00 2. "CPU0LOCKUP,The CPU0 lockup state" "0: the CPU is not in lockup,1: the CPU is in lockup" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 1. "CPU1SLEEPING,The CPU1 sleeping state" "0: the CPU is not sleeping,1: the CPU is sleeping" newline endif rbitfld.long 0x00 0. "CPU0SLEEPING,The CPU0 sleeping state" "0: the CPU is not sleeping,1: the CPU is sleeping" rgroup.long 0x80C++0x03 line.long 0x00 "CPUSTAT,CPU Status" bitfld.long 0x00 2. "CPU0LOCKUP,The CPU0 lockup state" "0: the CPU is not in lockup,1: the CPU is in lockup" newline bitfld.long 0x00 0. "CPU0SLEEPING,The CPU0 sleeping state" "0: the CPU is not sleeping,1: the CPU is sleeping" group.long 0x824++0x03 line.long 0x00 "LPCAC_CTRL,LPCAC control" bitfld.long 0x00 3. "PARITY_MISS_EN,Enable parity miss" "0: DISABLE,1: Enable parity miss on parity error" newline bitfld.long 0x00 2. "FRC_NO_ALLOC,Force no allocation" "0: Force allocation,1: Force no allocation" newline bitfld.long 0x00 1. "CLR_LPCAC,Clear cache function" "0: Unclear cache,1: Clear cache" newline bitfld.long 0x00 0. "DIS_LPCAC,Disable/enable cache function" "0: ENABLE,1: DISABLE" group.long 0x82C++0x03 line.long 0x00 "FC32KCLKSEL,Flexcomm 32K clock select" bitfld.long 0x00 0. "FC32KCLKSEL,Flexcomm 32K clock select" "0: DISABLE,1: XTAL 32K" repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x830)++0x03 line.long 0x00 "FRGCLKSEL[$1],FRG Clock Source Select $1" bitfld.long 0x00 0.--2. "FRG_SRC_SEL,FRG clock source select" "0: main clock,1: PLL clock,2: fro_div_hf,3: bit3,4: bit4,5: bit5,6: bit6,7: bit7" repeat.end repeat 8. (increment 0 1) (increment 0 0x04) group.long ($2+0x850)++0x03 line.long 0x00 "FLEXCOMMCLKDIV[$1],Flexcomm clock divider $1" rbitfld.long 0x00 31. "REQFLAG,Reset" "0: Divider clock is stable,1: Clock frequency is not stable" newline bitfld.long 0x00 30. "HALT,Reset" "0: Divider clock is running,1: Divider clock has stopped" newline bitfld.long 0x00 29. "RESET,Reset" "0: Divider is not reset,1: Divider is reset" newline hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value" repeat.end group.long 0x920++0x03 line.long 0x00 "BOOT_SEED_REG0,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG0,no description available" group.long 0x924++0x03 line.long 0x00 "BOOT_SEED_REG1,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG1,no description available" group.long 0x928++0x03 line.long 0x00 "BOOT_SEED_REG2,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG2,no description available" group.long 0x92C++0x03 line.long 0x00 "BOOT_SEED_REG3,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG3,no description available" group.long 0x930++0x03 line.long 0x00 "BOOT_SEED_REG4,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG4,no description available" group.long 0x934++0x03 line.long 0x00 "BOOT_SEED_REG5,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG5,no description available" group.long 0x938++0x03 line.long 0x00 "BOOT_SEED_REG6,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG6,no description available" group.long 0x93C++0x03 line.long 0x00 "BOOT_SEED_REG7,boot seed (256-bit random value)" hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG7,no description available" group.long 0x940++0x03 line.long 0x00 "HMAC_REG0,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG0,no description available" group.long 0x944++0x03 line.long 0x00 "HMAC_REG1,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG1,no description available" group.long 0x948++0x03 line.long 0x00 "HMAC_REG2,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG2,no description available" group.long 0x94C++0x03 line.long 0x00 "HMAC_REG3,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG3,no description available" group.long 0x950++0x03 line.long 0x00 "HMAC_REG4,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG4,no description available" group.long 0x954++0x03 line.long 0x00 "HMAC_REG5,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG5,no description available" group.long 0x958++0x03 line.long 0x00 "HMAC_REG6,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG6,no description available" group.long 0x95C++0x03 line.long 0x00 "HMAC_REG7,HMAC" hexmask.long 0x00 0.--31. 1. "HMAC_REG7,no description available" group.long 0x960++0x03 line.long 0x00 "BOOT_LOCK,Control write access to boot seed security registers" bitfld.long 0x00 1. "LOCK_HMAC,Control write access to HMAC_REG registers" "?,1: write access to all 8 registers HMAC_REG is.." newline bitfld.long 0x00 0. "LOCK_BOOT_SEED,Control write access to BOOT_SEED_REG registers" "?,1: write access to all 8 registers BOOT_SEED_REG.." group.long 0x988++0x03 line.long 0x00 "CSS_TEMPORAL_STATE,CSS temporal state" bitfld.long 0x00 0.--3. "TEMPORAL_STATE,Temporal state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98C++0x03 line.long 0x00 "CSS_KDF_MASK,Key derivation function mask" hexmask.long 0x00 0.--31. 1. "KDF_MASK,Key derivation function mask" group.long 0x990++0x03 line.long 0x00 "CSS_FEATURE0,CSS command feature" bitfld.long 0x00 22.--23. "KDELETE,Enables KDELETE command" "0,1,2,3" newline bitfld.long 0x00 20.--21. "KEYOUT,Enables KEYOUT command" "0,1,2,3" newline bitfld.long 0x00 18.--19. "KEYIN,Enables KEYIN command" "0,1,2,3" newline bitfld.long 0x00 16.--17. "KEYGEN,Enables KEYGEN command" "0,1,2,3" newline bitfld.long 0x00 12.--13. "ECKXCH,Enables ECKXCH command" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ECVFY,Enables ECVFY command" "0,1,2,3" newline bitfld.long 0x00 8.--9. "ECSIGN,Enables ECSIGN command" "0,1,2,3" newline bitfld.long 0x00 2.--3. "AUTH_CIPHER,Enables AUTH_CIPHER command" "0,1,2,3" newline bitfld.long 0x00 0.--1. "CIPHER,Enables CIPHER command" "0,1,2,3" group.long 0x994++0x03 line.long 0x00 "CSS_FEATURE1,CSS command feature" bitfld.long 0x00 28.--29. "GDET_CFG_LOAD,Enables GDET_CFG_LOAD command" "0,1,2,3" newline bitfld.long 0x00 26.--27. "DTRNG_EVAL,Enables DTRNG_EVAL command" "0,1,2,3" newline bitfld.long 0x00 24.--25. "DTRNG_CFG_LOAD,Enables DTRNG_CFG_LOAD command" "0,1,2,3" newline bitfld.long 0x00 18.--19. "DRBG_TEST,Enables DRBG_TEST command" "0,1,2,3" newline bitfld.long 0x00 16.--17. "DRBG_REQ,Enables DRBG_REQ command" "0,1,2,3" newline bitfld.long 0x00 12.--13. "CMAC,Enables CMAC command" "0,1,2,3" newline bitfld.long 0x00 10.--11. "HMAC,Enables HMAC command" "0,1,2,3" newline bitfld.long 0x00 8.--9. "HASH,Enables HASH command" "0,1,2,3" newline bitfld.long 0x00 4.--5. "TLS_INIT,Enables TLS_INIT command" "0,1,2,3" newline bitfld.long 0x00 2.--3. "HKDF,Enables HKDF command" "0,1,2,3" newline bitfld.long 0x00 0.--1. "CKDF,Enables CKDF command" "0,1,2,3" group.long 0x998++0x03 line.long 0x00 "CSS_FEATURE0_DP,CSS command feature - duplicate version" bitfld.long 0x00 22.--23. "KDELETE,Enables KDELETE command" "0,1,2,3" newline bitfld.long 0x00 20.--21. "KEYOUT,Enables KEYOUT command" "0,1,2,3" newline bitfld.long 0x00 18.--19. "KEYIN,Enables KEYIN command" "0,1,2,3" newline bitfld.long 0x00 16.--17. "KEYGEN,Enables KEYGEN command" "0,1,2,3" newline bitfld.long 0x00 12.--13. "ECKXCH,Enables ECSIGN command" "0,1,2,3" newline bitfld.long 0x00 10.--11. "ECVFY,Enables ECSIGN command" "0,1,2,3" newline bitfld.long 0x00 8.--9. "ECSIGN,Enables ECSIGN command" "0,1,2,3" newline bitfld.long 0x00 2.--3. "AUTH_CIPHER,Enables AUTH_CIPHER command" "0,1,2,3" newline bitfld.long 0x00 0.--1. "CIPHER,Enables CIPHER command" "0,1,2,3" group.long 0x99C++0x03 line.long 0x00 "CSS_FEATURE1_DP,CSS command feature - duplicate version" bitfld.long 0x00 28.--29. "GDET_CFG_LOAD,Enables GDET_CFG_LOAD command" "0,1,2,3" newline bitfld.long 0x00 26.--27. "DTRNG_EVAL,Enables DTRNG_EVAL command" "0,1,2,3" newline bitfld.long 0x00 24.--25. "DTRNG_CFG_LOAD,Enables DTRNG_CFG_LOAD command" "0,1,2,3" newline bitfld.long 0x00 18.--19. "DRBG_TEST,Enables DRBG_TEST command" "0,1,2,3" newline bitfld.long 0x00 16.--17. "DRBG_REQ,Enables DRBG_REQ command" "0,1,2,3" newline bitfld.long 0x00 12.--13. "CMAC,Enables CMAC command" "0,1,2,3" newline bitfld.long 0x00 10.--11. "HMAC,Enables HMAC command" "0,1,2,3" newline bitfld.long 0x00 8.--9. "HASH,Enables HASH command" "0,1,2,3" newline bitfld.long 0x00 4.--5. "TLS_INIT,Enables TLS_INIT command" "0,1,2,3" newline bitfld.long 0x00 2.--3. "HKDF,Enables HKDF command" "0,1,2,3" newline bitfld.long 0x00 0.--1. "CKDF,Enables CKDF command" "0,1,2,3" group.long 0x9A4++0x03 line.long 0x00 "CSS_BOOT_RETRY_CNT,CSS boot retry counter" hexmask.long 0x00 0.--31. 1. "BOOT_RETRY_CNT,Boot retry counter bit" group.long 0x9B0++0x03 line.long 0x00 "CSS_CLK_CTRL,CSS clock control" bitfld.long 0x00 1. "DTRNG_REFCLK_EN,DTRNG reference clock enable bit" "0,1" newline bitfld.long 0x00 0. "GDET_REFCLK_EN,GDET reference clock enable bit" "0,1" wgroup.long 0x9B4++0x03 line.long 0x00 "CSS_CLK_CTRL_SET,CSS clock control set" bitfld.long 0x00 1. "DTRNG_REFCLK_EN_SET,DTRNG reference clock enable set bit" "0,1" newline bitfld.long 0x00 0. "GDET_REFCLK_EN_SET,GDET reference clock enable set bit" "0,1" wgroup.long 0x9B8++0x03 line.long 0x00 "CSS_CLK_CTRL_CLR,CSS clock control clear" bitfld.long 0x00 1. "DTRNG_REFCLK_EN_CLR,DTRNG reference clock enable clear bit" "0,1" newline bitfld.long 0x00 0. "GDET_REFCLK_EN_CLR,GDET reference clock enable clear bit" "0,1" group.long 0x9BC++0x03 line.long 0x00 "CSS_CLK_SEL,CSS clock select" bitfld.long 0x00 0.--1. "GDET_REFCLK_SEL,GDET reference clock select bit" "0,1,2,3" rgroup.long 0x9D0++0x03 line.long 0x00 "CSS_AS_CFG0,CSS AS configuration" bitfld.long 0x00 29. "CFG_QK_DISABLE_WRAP,When CONFIG[DIS_PUF_WRAP_KEY] bit is set 1 this bit indicates state 1" "0,1" newline bitfld.long 0x00 28. "CFG_QK_DISABLE_ENROLL,When CONFIG[DIS_PUF_ENROLL] bit is set 1 this bit indicates state 1" "0,1" newline bitfld.long 0x00 24.--27. "CFG_FLASH_BANK1_ENABLE,The state of FLASHBANK_ENABLE1 register (0x4000_0454) reflects to this register as below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "CFG_FLASH_BANK0_ENABLE,The state of FLASHBANK_ENABLE0 register (0x4000_0450) reflects to this register as below" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "CFG_FLASH_IS_REMAPPED_DP,When FLASHREMAP_OFFSET_DP register (0x4000_044C) is not equal to 0x0000_0000 this bit indicates state 1" "0,1" newline bitfld.long 0x00 18. "CFG_FLASH_IS_REMAPPED,When FLASHREMAP_OFFSET register (0x4000_0448) is not equal to 0x0000_0000 this bit indicates state 1" "0,1" newline bitfld.long 0x00 17. "CFG_TAMPER_DET_ENABLED,When tamper detector is enabled in RTC this bit indicates state 1" "0,1" newline bitfld.long 0x00 16. "CFG_ANA_GDET_ENABLED,When ANALOG GDET is enabled this bit indicates state 1" "0,1" newline bitfld.long 0x00 15. "CFG_CSS_GDET_ENABLED,When CSS GDET is enabled this bit indicates state 1" "0,1" newline bitfld.long 0x00 13. "CFG_CWDT_ENABLED,When Code WatchDog Timer is activated this bit indicates state 1" "0,1" newline bitfld.long 0x00 12. "CFG_WDT_ENABLED,When WatchDog Timer is activated this bit indicates state 1" "0,1" newline bitfld.long 0x00 10. "CFG_BOD_VDDMAIN_IRQ_ENABLED,When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN IRQ is enabled this bit indicates state 1" "0,1" newline bitfld.long 0x00 9. "CFG_BOD_CORE_RESET_ENABLED,When BOD CORE analog detector is turned on and BOD CORE reset is enabled this bit indicates state 1" "0,1" newline bitfld.long 0x00 8. "CFG_BOD_VDDMAIN_RESET_ENABLED,When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN reset is enabled this bit indicates state 1" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "CFG_LC_STATE,LC state configuration bit" rgroup.long 0x9D4++0x03 line.long 0x00 "CSS_AS_CFG1,CSS AS configuration1" bitfld.long 0x00 12. "CFG_SEC_LOCK_SAU,When LOCK_SAU bits in CPU0_LOCK_REG on AHB secure controller are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 11. "CFG_SEC_LOCK_S_VTAIRCR,When LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on AHB secure controller are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 10. "CFG_SEC_LOCK_S_MPU,When LOCK_S_MPU bits in CPU0_LOCK_REG on AHB secure controller are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 9. "CFG_SEC_LOCK_NS_VTOR,When LOCK_NS_VTOR bits in CPU0_LOCK_REG on AHB secure controller are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 8. "CFG_SEC_LOCK_NS_MPU,When LOCK_NS_MPU bits in CPU0_LOCK_REG on AHB secure controller are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 6. "CFG_SEC_IDAU_ALLNS,When IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on AHB secure controller both bits are equal to 01 this bit indicates state 1" "0,1" newline bitfld.long 0x00 5. "CFG_SEC_ENA_SEC_CHK,When ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on AHB secure controller both bits are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 4. "CFG_SEC_ENA_S_PRIV_CHK,When ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on AHB secure controller both bits are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 3. "CFG_SEC_ENA_NS_PRIV_CHK,When ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on AHB secure controller both bits are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 2. "CFG_SEC_DIS_VIOL_ABORT,When DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on AHB secure controller both bits are not equal to 10 this bit indicates state 1" "0,1" newline bitfld.long 0x00 1. "CFG_SEC_DIS_STRICT_MODE,When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on AHB secure controller both bits are equal to 01 this bit indicates state 1" "0,1" rgroup.long 0x9D8++0x03 line.long 0x00 "CSS_AS_CFG2,CSS AS configuration2" hexmask.long 0x00 0.--31. 1. "CFG_CSS_CMD_EN,CSS configuration command enable bit" rgroup.long 0x9E0++0x03 line.long 0x00 "CSS_AS_ST0,CSS AS state register" bitfld.long 0x00 15. "ST_XO32K_FAILED,When XO32K oscillation fail flag is state 1 in PMC register block this bit indicates state 1" "0,1" newline bitfld.long 0x00 14. "ST_ALLOW_TEST_ACCESS,When JTAG TAP access is allowed this bit indicates state 1" "0,1" newline bitfld.long 0x00 13. "ST_CSS_DEBUG_EN,When CSS uCode code fetch out of AHB for debug is enabled this bit indicates state 1" "0,1" newline bitfld.long 0x00 10. "ST_DAP_ENABLE_CPU0,When DAP to AP0 for CPU0 (CM33) debug access is allowed this bit indicates state 1" "0,1" newline bitfld.long 0x00 7. "ST_CPU0_SPNIDEN,When CPU0 (CM33) spniden input is state 1 this bit indicates state 1" "0,1" newline bitfld.long 0x00 6. "ST_CPU0_SPIDEN,When CPU0 (CM33) spiden input is state 1 this bit indicates state 1" "0,1" newline bitfld.long 0x00 5. "ST_CPU0_NIDEN,When CPU0 (CM33) niden input is state 1 this bit indicates state 1" "0,1" newline bitfld.long 0x00 4. "ST_CPU0_DBGEN,When CPU0 (CM33) deben input is state 1 this bit indicates state 1" "0,1" newline bitfld.long 0x00 0.--3. "ST_TEMPORAL_STATE,TEMPORAL_STATE[3:0] on CSS_TEMPORAL_STATE register reflects this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x9E4++0x03 line.long 0x00 "CSS_AS_ST1,CSS AS state1" bitfld.long 0x00 12.--15. "ST_BOOT_RETRY_CNT,BOOT_RETRY_CNT[3:0] on CSS_BOOT_RETRY_CNT register reflects this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. "ST_BOOT_MODE,BOOTMODE[1:0] status on STATUS register in PMC block will reflect to this register" "0,1,2,3" newline bitfld.long 0x00 6.--9. "ST_DCDC_VOUT,VOUT[3:0] setting on DCDC0 register in PMC block will reflect to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. "ST_MAIN_CLK_IS_EXT,When MAIN_CLK is running from external clock source either XO32M XO32K or GPIO CLKIN this bit indicates state 1" "0,1" newline bitfld.long 0x00 4. "ST_QK_ZEROIZED,This register bit indicates the state of qk_zeroized output from QK PUF block" "0,1" newline bitfld.long 0x00 0.--3. "ST_QK_PUF_SCORE,These register bits indicate the state of qk_puf_score[3:0] outputs from QK PUF block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x9E8++0x03 line.long 0x00 "CSS_AS_ST2,CSS AS state2" hexmask.long 0x00 0.--31. 1. "CSS_AS_ST2,BOOT_STATE[31:0] on CSS_BOOT_STATE register reflects this register" rgroup.long 0x9F0++0x03 line.long 0x00 "CSS_AS_FLAG0,CSS AS flag0" bitfld.long 0x00 19. "FLAG_CPU0_NS_D_ACC_OCCURED,This flag register is set 1 when CPU0 (CM33) makes non-secure data transactions" "0,1" newline bitfld.long 0x00 18. "FLAG_CPU0_NS_C_ACC_OCCURED,This flag bit is set 1 when CPU0 (CM33) makes non-secure code transactions" "0,1" newline bitfld.long 0x00 17. "FLAG_SEC_VIOL_IRQ_OCURRED,This flag bit is set 1 when security violation is indicated from FLASH sub-system or AHB bus matrix" "0,1" newline bitfld.long 0x00 16. "FLAG_FLASH_ECC_INVALID,This flag bit is set 1 when FLASH controller indicates ECC error" "0,1" newline bitfld.long 0x00 15. "FLAG_TAMPER_EVENT_DETECTED,This flag bit is set 1 when tamper event is flagged from RTC" "0,1" newline bitfld.long 0x00 14. "FLAG_ANA_GLITCH_DETECTED,This flag bit is set 1 when ANALOG GDET error is flagged in SYSCON block" "0,1" newline bitfld.long 0x00 13. "FLAG_CSS_GLITCH_DETECTED,This flag bit is set 1 when GDET error is flagged from CSS" "0,1" newline bitfld.long 0x00 12. "FLAG_QK_ERROR,This flag bit is set 1 when QK_ERROR is flagged from QK PUF block" "0,1" newline bitfld.long 0x00 11. "FLAG_CWDT_IRQ_OCCURED,This flag bit is set 1 when Code WatchDog Timer IRQ is enabled and IRQ event is triggered" "0,1" newline bitfld.long 0x00 10. "FLAG_WDT_IRQ_OCCURED,This flag register is set 1 when WatchDog Timer IRQ is enabled and IRQ event is triggered" "0,1" newline bitfld.long 0x00 9. "FLAG_CWDT_RESET_OCCURED,This flag bit is set 1 when Code WatchDog Timer reset is enabled and reset event is triggered" "0,1" newline bitfld.long 0x00 8. "FLAG_WDT_RESET_OCCURED,This flag bit is set 1 when WatchDog Timer reset is enabled and reset event is triggered" "0,1" newline bitfld.long 0x00 7. "FLAG_BOD_CORE_IRQ_OCCURED,This flag bit is set 1 when BOD CORE IRQ is enabled and BOD CORE analog detector is tripped" "0,1" newline bitfld.long 0x00 6. "FLAG_BOD_VDDMAIN_IRQ_OCCURED,This flag bit is set 1 when BOD VDDMAIN IRQ is enabled and BOD VDDMAIN analog detector is tripped" "0,1" newline bitfld.long 0x00 5. "FLAG_BOD_CORE_RESET_OCCURED,This flag bit is set 1 when BOD CORE reset is enabled and BOD CORE analog detector is tripped" "0,1" newline bitfld.long 0x00 4. "FLAG_BOD_VDDMAIN_RESET_OCCURED,This flag bit is set 1 when BOD VDDMAIN reset is enabled and BOD VDDMAIN analog detector is tripped" "0,1" newline bitfld.long 0x00 0. "FLAG_AP_ENABLE_CPU0,This flag bit is set 1 when DAP enables AP0 for CPU0 (CM33) debug access" "0,1" group.long 0xA18++0x03 line.long 0x00 "CLOCK_CTRL,Various system clock controls : Flash clock (48 MHz) control clocks to Frequency Measures" bitfld.long 0x00 9. "PLU_DEGLITCH_CLK_ENA,Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 8. "XO_CAL_CLK_ENA,Enable clock for cristal oscilator calibration" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 7. "ANA_FRO12M_CLK_ENA,Enable FRO 12MHz clock for analog control of the FRO 192MHz" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 6. "FRO1MHZ_CLK_ENA,Enable FRO 1MHz clock for clock muxing in clock gen" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 5. "CLKIN_ENA,Enable clock_in clock for clock module" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 4. "FRO_HF_FREQM_ENA,Enable FRO 96MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 3. "FRO12MHZ_FREQM_ENA,Enable FRO 12MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 2. "FRO1MHZ_UTICK_ENA,Enable FRO 1MHz clock for Frequency Measure module and for UTICK" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 1. "XTAL32MHZ_FREQM_ENA,Enable XTAL32MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled" group.long 0xA18++0x03 line.long 0x00 "CLOCK_CTRL,Clock Control" bitfld.long 0x00 8. "XO_CAL_CLK_ENA,Enable clock for crystal oscillator calibration" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 7. "ANA_FRO12M_CLK_ENA,Enable FRO 12MHz clock for analog control of the FRO 192MHz" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 6. "FRO1MHZ_CLK_ENA,Enable FRO 1MHz clock for clock muxing in clock gen" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 5. "CLKIN_ENA,Enable clock_in clock for clock module" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 4. "FRO_HF_FREQM_ENA,Enable FRO 96MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 3. "FRO12MHZ_FREQM_ENA,Enable FRO 12MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 2. "FRO1MHZ_UTICK_ENA,Enable FRO 1MHz clock for Frequency Measure module and for UTICK" "0: The clock is not enabled,1: The clock is enabled" newline bitfld.long 0x00 1. "XTAL32MHZ_FREQM_ENA,Enable XTAL32MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled" group.long 0xB10++0x03 line.long 0x00 "COMP_INT_CTRL,Comparator Interrupt control" bitfld.long 0x00 5. "INT_SOURCE,Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection" "0: Select Analog Comparator filtered output as..,1: Select Analog Comparator raw output.." newline bitfld.long 0x00 2.--4. "INT_CTRL,Comparator interrupt type selector" "0: The analog comparator interrupt edge..,1: The analog comparator interrupt level..,2: analog comparator interrupt is rising edge..,3: Analog Comparator interrupt is high level..,4: analog comparator interrupt is falling edge..,5: Analog Comparator interrupt is low level..,6: analog comparator interrupt is rising and..,7: The analog comparator interrupt level.." newline bitfld.long 0x00 1. "INT_CLEAR,Analog Comparator interrupt clear" "0: No effect,1: Clear the interrupt" newline bitfld.long 0x00 0. "INT_ENABLE,Analog Comparator interrupt enable control" "0: interrupt disable,1: interrupt enable" group.long 0xB14++0x03 line.long 0x00 "COMP_INT_STATUS,Comparator Interrupt status" rbitfld.long 0x00 2. "VAL,comparator analog output" "0: P+ is smaller than P,1: P+ is greater than P" newline rbitfld.long 0x00 1. "INT_STATUS,Interrupt status AFTER Interrupt Enable" "0: no interrupt pending,1: interrupt pending" newline sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") rbitfld.long 0x00 0. "STATUS,Interrupt status BEFORE Interrupt Enable" "0: no interrupt pending,1: interrupt pending" endif sif cpuis("LPC5534*")||cpuis("LPC5536*") rbitfld.long 0x00 0. "STATUS,Interrupt status BEFORE Interrupt Enable" "0: No interrupt pending,1: Interrupt pending" endif group.long 0xE04++0x03 line.long 0x00 "AUTOCLKGATEOVERRIDE,Control automatic clock gating" hexmask.long.word 0x00 16.--31. 1. "ENABLEUPDATE,The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect" newline bitfld.long 0x00 15. "SYSCON,Control automatic clock gating of synchronous system controller registers bank" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 14. "USB0,Control automatic clock gating of USB controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif bitfld.long 0x00 13. "SDMA1,Control automatic clock gating of DMA1 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 12. "SDMA0,Control automatic clock gating of DMA0 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 11. "CRCGEN,Control automatic clock gating of CRCGEN controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 8. "SYNC1_APB,Control automatic clock gating of synchronous bridge controller 1" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 7. "SYNC0_APB,Control automatic clock gating of synchronous bridge controller 0" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 6. "RAM4,Control automatic clock gating of RAM4 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 6. "RAM4_CTRL,Control automatic clock gating of RAM4 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 5. "RAM3_CTRL,Control automatic clock gating of RAM3 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 5. "RAM3,Control automatic clock gating of RAM3 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 4. "RAM2_CTRL,Control automatic clock gating of RAM2 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 4. "RAM2,Control automatic clock gating of RAM2 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 3. "RAM1,Control automatic clock gating of RAM1 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 3. "RAM1_CTRL,Control automatic clock gating of RAM1 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 2. "RAM0_CTRL,Control automatic clock gating of RAM0 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif sif cpuis("LPC5534*")||cpuis("LPC5536*") bitfld.long 0x00 2. "RAM0,Control automatic clock gating of RAM0 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline bitfld.long 0x00 1. "RAMX,Control automatic clock gating of RAMX controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 1. "RAMX_CTRL,Control automatic clock gating of RAMX controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." newline endif bitfld.long 0x00 0. "ROM,Control automatic clock gating of ROM controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.." group.long 0xE08++0x03 line.long 0x00 "GPIOPSYNC,Enable bypass of the first stage of synchonization inside GPIO_INT module" bitfld.long 0x00 0. "PSYNC,Enable bypass of the first stage of synchonization inside GPIO_INT module" "0: use the first stage of synchonization inside..,1: bypass of the first stage of synchonization.." group.long 0xE08++0x03 line.long 0x00 "GPIOPSYNC,GPIO Synchronization" bitfld.long 0x00 0. "PSYNC,Enable bypass of the first stage of synchronization inside GPIO_INT module" "0: Use the first stage of synchronization inside..,1: Bypass of the first stage of synchronization.." group.long 0xE24++0x03 line.long 0x00 "AUTOCLKGATEOVERRIDE1,Control automatic clock gating" bitfld.long 0x00 11. "PWM1,PWM1" "0,1" newline bitfld.long 0x00 10. "PWM0,PWM0" "0,1" newline bitfld.long 0x00 9. "VREF,VREF" "0,1" newline bitfld.long 0x00 8. "HSCMP2,HSCMP2" "0,1" newline bitfld.long 0x00 7. "HSCMP1,HSCMP0" "0,1" newline bitfld.long 0x00 6. "HSCMP0,HSCMP0" "0,1" newline bitfld.long 0x00 5. "OPAMP2,OPAMP2" "0,1" newline bitfld.long 0x00 4. "OPAMP1,OPAMP1" "0,1" newline bitfld.long 0x00 3. "OPAMP0,OPAMP0" "0,1" newline bitfld.long 0x00 2. "DAC2,DAC2" "0,1" newline bitfld.long 0x00 1. "DAC1,DAC1" "0,1" newline bitfld.long 0x00 0. "DAC0,DAC0" "0,1" group.long 0xE30++0x03 line.long 0x00 "ENABLE_MEM_PARITY_ECC_CHECK,Memory parity ECC enable" bitfld.long 0x00 26. "RAME_PARITY_ERROR_INTEN,Interrupt enable for RAME parity error" "0: Disable,1: Enable RAM error interrupt when RAME parity.." newline bitfld.long 0x00 25. "RAMD_PARITY_ERROR_INTEN,Interrupt enable for RAMD parity error" "0: Disable,1: Enable RAM error interrupt when RAMD parity.." newline bitfld.long 0x00 24. "RAMC_PARITY_ERROR_INTEN,Interrupt enable for RAMC parity error" "0: Disable,1: Enable RAM error interrupt when RAMC parity.." newline bitfld.long 0x00 23. "RAMB_ECC_SBIT_ERROR_INTEN,Interrupt enable for RAMB ECC sbit_err" "0: Disable,1: Enable RAM error interrupt when RAMB ECC.." newline bitfld.long 0x00 22. "RAMB_ECC_MBIT_ERROR_INTEN,Interrupt enable for RAMB ECC mbit_err" "0: Disable,1: Enable RAM error interrupt when RAMB ECC.." newline bitfld.long 0x00 21. "RAMA_PARITY_ERROR_INTEN,Interrupt enable for RAMA parity error" "0: Disable,1: Enable RAM error interrupt when RAMA parity.." newline bitfld.long 0x00 20. "RAMX_PARITY_ERROR_INTEN,Interrupt enable for RAMX parity error" "0: Disable,1: Enable RAM error interrupt when RAMX parity.." newline bitfld.long 0x00 12. "ENABLE_RAM43,Enable RAM43 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 11. "ENABLE_RAM42,Enable RAM42 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 10. "ENABLE_RAM41,Enable RAM41 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 9. "ENABLE_RAM40,Enable RAM40 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 8. "ENABLE_RAM3,Enable RAM3 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "ENABLE_RAM2,Enable RAM2 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 6. "ENABLE_RAM1_SBIT,Enable RAM1 ECC sbit error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 5. "ENABLE_RAM1_MBIT,Enable RAM1 ECC mbit error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 4. "ENABLE_RAM03,Enable RAM03 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 3. "ENABLE_RAMx02,Enable RAMx02 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 2. "ENABLE_RAM01,Enable RAM01 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 1. "ENABLE_RAM00,Enable RAM00 parity error check" "0: Disabled,1: Enabled" newline bitfld.long 0x00 0. "ENABLE_RAMx,Enable RAMx parity error check" "0: Disabled,1: Enabled" rgroup.long 0xE34++0x03 line.long 0x00 "MEM_PARITY_ECC_ERROR_FLAG,Memory parity ECC error flag" bitfld.long 0x00 6. "RAM4_PARITY_ERROR,RAM4 parity error detected" "0: No error detected,1: Error detected" newline bitfld.long 0x00 5. "RAM3_PARITY_ERROR,RAM3 parity error detected" "0: No error detected,1: Error detected" newline bitfld.long 0x00 4. "RAM2_PARITY_ERROR,RAM2 parity error detected" "0: No error detected,1: Error detected" newline bitfld.long 0x00 3. "RAM1_ECC_SBIT_ERROR,RAM1 ECC sbit error detected" "0: No error detected,1: Error detected" newline bitfld.long 0x00 2. "RAM1_ECC_MBIT_ERROR,RAM1 ECC mbit error detected" "0: No error detected,1: Error detected" newline bitfld.long 0x00 1. "RAM0_PARITY_ERROR,RAM0 parity error detected" "0: No error detected,1: Error detected" newline bitfld.long 0x00 0. "RAMX_PARITY_ERROR,RAMx parity error detected" "0: No error detected,1: Error detected" group.long 0xE38++0x03 line.long 0x00 "PWM0SUBCTL,PWM0 submodule control" bitfld.long 0x00 15. "DMAVALM3,PWM0 submodule 3 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 14. "DMAVALM2,PWM0 submodule 2 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 13. "DMAVALM1,PWM0 submodule 1 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 12. "DMAVALM0,PWM0 submodule 0 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 3. "CLK3_EN,PWM0 SUB Clock3 enable" "0,1" newline bitfld.long 0x00 2. "CLK2_EN,PWM0 SUB Clock2 enable" "0,1" newline bitfld.long 0x00 1. "CLK1_EN,PWM0 SUB Clock1 enable" "0,1" newline bitfld.long 0x00 0. "CLK0_EN,PWM0 SUB Clock0 enable" "0,1" group.long 0xE3C++0x03 line.long 0x00 "PWM1SUBCTL,PWM1 submodule control" bitfld.long 0x00 15. "DMAVALM3,PWM1 submodule 3 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 14. "DMAVALM2,PWM1 submodule 2 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 13. "DMAVALM1,PWM1 submodule 1 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 12. "DMAVALM0,PWM1 submodule 0 DMA Compare Value Done Mask" "0,1" newline bitfld.long 0x00 3. "CLK3_EN,PWM1 SUB Clock3 enable" "0,1" newline bitfld.long 0x00 2. "CLK2_EN,PWM1 SUB Clock2 enable" "0,1" newline bitfld.long 0x00 1. "CLK1_EN,PWM1 SUB Clock1 enable" "0,1" newline bitfld.long 0x00 0. "CLK0_EN,PWM1 SUB Clock0 enable" "0,1" group.long 0xE40++0x03 line.long 0x00 "CTIMERGLOBALSTARTEN,CTIMER global start enable" bitfld.long 0x00 4. "CTIMER4_CLK_EN,CTIMER4 function clock enable" "0,1" newline bitfld.long 0x00 3. "CTIMER3_CLK_EN,CTIMER3 function clock enable" "0,1" newline bitfld.long 0x00 2. "CTIMER2_CLK_EN,CTIMER2 function clock enable" "0,1" newline bitfld.long 0x00 1. "CTIMER1_CLK_EN,CTIMER1 function clock enable" "0,1" newline bitfld.long 0x00 0. "CTIMER0_CLK_EN,CTIMER0 function clock enable" "0,1" group.long 0xF88++0x03 line.long 0x00 "HASHRESTHWKEY,Controls whether the HASH AES hardware secret key is restricted to use by secure code" hexmask.long 0x00 0.--31. 1. "UNLOCKCODE,Code value that controls whether HASH AES hardware secret key is unlocked" group.long 0xFA0++0x03 line.long 0x00 "DEBUG_LOCK_EN,Control write access to security" bitfld.long 0x00 0.--3. "LOCK_ALL,Control write access to security registers" "0: Any other value than b1010,?,?,?,?,?,?,?,?,?,10: 1010,?..." group.long 0xFA0++0x03 line.long 0x00 "DEBUG_LOCK_EN,Control write access to security registers" sif cpuis("LPC5502*")||cpuis("LPC5504*")||cpuis("LPC5506*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*") bitfld.long 0x00 0.--3. "LOCK_ALL,Control write access to security registers" "0: Any other value than b1010,?,?,?,?,?,?,?,?,?,10: 1010,?..." endif sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 0.--3. "LOCK_ALL,Control write access to CODESECURITYPROTTEST CODESECURITYPROTCPU0 CODESECURITYPROTCPU1 CPU0_DEBUG_FEATURES CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers" "0: Any other value than b1010,?,?,?,?,?,?,?,?,?,10: 1010,?..." endif group.long 0xFA4++0x03 line.long 0x00 "DEBUG_FEATURES,Cortex debug features control" bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Privileged Non Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." newline bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Privileged Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." newline bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." newline bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." group.long 0xFA4++0x03 line.long 0x00 "DEBUG_FEATURES,Cortex debug features control" bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 Invasive debug control" "?,1: Any other value than b10,2: 10,?..." group.long 0xFA4++0x03 line.long 0x00 "DEBUG_FEATURES,Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control" bitfld.long 0x00 10.--11. "CPU1_NIDEN,CPU1 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 8.--9. "CPU1_DBGEN,CPU1 Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 Invasive debug control" "?,1: Any other value than b10,2: 10,?..." group.long 0xFA8++0x03 line.long 0x00 "DEBUG_FEATURES_DP,Cortex debug features control (duplicate)" bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Privileged Non Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." newline bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Privileged Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." newline bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." newline bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 Invasive Debug Control" "?,1: Disable debug,2: Enable debug,?..." group.long 0xFA8++0x03 line.long 0x00 "DEBUG_FEATURES_DP,Cortex debug features control" bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 (CPU0) Invasive debug control" "?,1: Any other value than b10,2: 10,?..." group.long 0xFA8++0x03 line.long 0x00 "DEBUG_FEATURES_DP,Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register" bitfld.long 0x00 10.--11. "CPU1_NIDEN,CPU1 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 8.--9. "CPU1_DBGEN,CPU1 Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..." newline bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 (CPU0) Invasive debug control" "?,1: Any other value than b10,2: 10,?..." group.long 0xFB4++0x03 line.long 0x00 "SWD_ACCESS_CPU0,CPU0 Software Debug Access" hexmask.long 0x00 0.--31. 1. "SEC_CODE,CPU0 SWD-AP: 0x12345678" group.long 0xFB4++0x03 line.long 0x00 "SWD_ACCESS_CPU0,This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0" hexmask.long 0x00 0.--31. 1. "SEC_CODE,CPU0 SWD-AP: 0x12345678" wgroup.long 0xFBC++0x03 line.long 0x00 "KEY_BLOCK,block quiddikey/PUF all index" hexmask.long 0x00 0.--31. 1. "KEY_BLOCK,Write a value to block quiddikey/PUF all index" group.long 0xFC0++0x03 line.long 0x00 "DEBUG_AUTH_BEACON,Debug authentication BEACON" hexmask.long 0x00 0.--31. 1. "BEACON,Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code" group.long 0xFC0++0x03 line.long 0x00 "DEBUG_AUTH_BEACON,Debug authentication BEACON register" hexmask.long 0x00 0.--31. 1. "BEACON,Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code" group.long 0xFC4++0x03 line.long 0x00 "SWD_ACCESS_DSP,DSP Software Debug Access" hexmask.long 0x00 0.--31. 1. "SEC_CODE,DSP SWD-AP: 0x12345678" rgroup.long 0xFF4++0x03 line.long 0x00 "DEVICE_TYPE,Device type" rgroup.long 0xFF8++0x03 line.long 0x00 "DEVICE_ID0,Device ID" bitfld.long 0x00 20.--23. "ROM_REV_MINOR,ROM revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFC++0x03 line.long 0x00 "DIEID,Chip revision ID and Number" hexmask.long.tbyte 0x00 4.--23. 1. "MCO_NUM_IN_DIE_ID,Chip Number 0x426B" newline bitfld.long 0x00 0.--3. "REV_ID,Chip Metal Revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "SYSCTL (System controller)" base ad:0x40023000 group.long 0x00++0x03 line.long 0x00 "UPDATELCKOUT,Write Lock Out" bitfld.long 0x00 0. "UPDATELCKOUT,Lock Out" "0: Normal Mode,1: Protected Mode" repeat 8. (increment 0 1) (increment 0 0x4) group.long ($2+0x40)++0x03 line.long 0x00 "FCCTRLSEL[$1],Shared Signal Select for Flexcomm n $1" bitfld.long 0x00 24.--25. "DATAOUTSEL,DATA Output Select" "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA..,1: Selects from shared signal set 0..,2: Selects from shared signal set 1..,?..." bitfld.long 0x00 16.--17. "DATAINSEL,DATA Input Select" "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA..,1: Selects from shared signal set 0..,2: Selects from shared signal set 1..,?..." newline bitfld.long 0x00 8.--9. "WSINSEL,WS Input Select" "0: Selects the dedicated FCn_TXD_SCL_MISO_WS..,1: Selects from shared signal set 0..,2: Selects from shared signal set 1..,?..." bitfld.long 0x00 0.--1. "SCKINSEL,SCK Input Select" "0: Selects the dedicated FCn_SCK signal,1: Selects from shared signal set 0..,2: Selects from shared signal set 1..,?..." repeat.end repeat 2. (increment 0 1) (increment 0 0x4) group.long ($2+0x80)++0x03 line.long 0x00 "SHAREDCTRLSET[$1],Shared Signal Set n $1" bitfld.long 0x00 23. "FC7DATAOUTEN,DATAOUT Enable for Flexcomm 7" "0: Does not contribute,1: Contributes" bitfld.long 0x00 22. "FC6DATAOUTEN,DATAOUT Enable for Flexcomm 6" "0: Does not contribute,1: Contributes" newline bitfld.long 0x00 21. "FC5DATAOUTEN,DATAOUT Enable for Flexcomm 5" "0: Does not contribute,1: Contributes" bitfld.long 0x00 20. "FC4DATAOUTEN,DATAOUT Enable for Flexcomm 4" "0: Does not contribute,1: Contributes" newline bitfld.long 0x00 18. "FC2DATAOUTEN,DATAOUT Enable for Flexcomm 2" "0: Does not contribute,1: Contributes" bitfld.long 0x00 17. "FC1DATAOUTEN,DATAOUT Enable for Flexcomm 1" "0: Does not contribute,1: Contributes" newline bitfld.long 0x00 16. "FC0DATAOUTEN,DATAOUT Enable for Flexcomm 0" "0: Does not contribute,1: Contributes" bitfld.long 0x00 8.--10. "SHAREDDATASEL,DATA Input Source Select" "0: Flexcomm 0,1: Flexcomm 1,2: Flexcomm 2,?,4: Flexcomm 4,5: Flexcomm 5,6: Flexcomm 6,7: Flexcomm 7" newline bitfld.long 0x00 4.--6. "SHAREDWSSEL,WS Source Select" "0: Flexcomm 0,1: Flexcomm 1,2: Flexcomm 2,?,4: Flexcomm 4,5: Flexcomm 5,6: Flexcomm 6,7: Flexcomm 7" bitfld.long 0x00 0.--2. "SHAREDSCKSEL,SCK Source Select" "0: Flexcomm 0,1: Flexcomm 1,2: Flexcomm 2,?,4: Flexcomm 4,5: Flexcomm 5,6: Flexcomm 6,7: Flexcomm 7" repeat.end group.long 0x180++0x03 line.long 0x00 "CODE_GRAY_LSB,Gray Code LSB Input" hexmask.long 0x00 0.--31. 1. "CODE_GRAY_LSB,Gray code (least-significant)" group.long 0x184++0x03 line.long 0x00 "CODE_GRAY_MSB,Gray Code MSB Input" hexmask.long.word 0x00 0.--9. 1. "CODE_GRAY_MSB,Gray code (most-significant)" rgroup.long 0x188++0x03 line.long 0x00 "CODE_BIN_LSB,Binary Code LSB Input" hexmask.long 0x00 0.--31. 1. "CODE_BIN_LSB,Binary converted code (least-significant)" rgroup.long 0x18C++0x03 line.long 0x00 "CODE_BIN_MSB,Binary Code MSB Input" hexmask.long.word 0x00 0.--9. 1. "CODE_BIN_MSB,Binary converted code (most-significant)" tree.end tree "USART (Flexcomm USART)" tree "USART0" base ad:0x40086000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "USART1" base ad:0x40087000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "USART2" base ad:0x40088000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "USART3" base ad:0x40089000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "USART4" base ad:0x4008A000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "USART5" base ad:0x40096000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "USART6" base ad:0x40097000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree "USART7" base ad:0x40098000 group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration" bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 22. "RXPOL,Receive Data Polarity" "0: STANDARD,1: INVERTED" newline bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High" newline bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485" newline bitfld.long 0x00 19. "AUTOADDR,Automatic Address Matching Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 18. "OETA,Output Enable Turnaround Time Enable for RS-485 Operation" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 15. "LOOP,Loopback Mode" "0: Normal operation,1: Loopback mode" newline bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master Select" "0: Slave,1: Master" newline bitfld.long 0x00 12. "CLKPOL,Clock Polarity" "0: Falling edge,1: Rising edge" newline bitfld.long 0x00 11. "SYNCEN,Synchronous Enable" "0: ASYNCHRONOUS_MODE,1: SYNCHRONOUS_MODE" newline bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled" newline bitfld.long 0x00 8. "LINMODE,LIN Break Mode Enable" "0: Disabled,1: Enabled" newline bitfld.long 0x00 7. "MODE32K,Mode 32 kHz" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 6. "STOPLEN,Stop Length" "0: 1 stop bit,1: 2 stop bits" newline bitfld.long 0x00 4.--5. "PARITYSEL,Parity Select" "0: NO_PARITY,?,2: EVEN_PARITY,3: ODD_PARITY" newline bitfld.long 0x00 2.--3. "DATALEN,Data Length" "0: 7 bit data length,1: 8 bit data length,2: 9 bit data length,?..." newline bitfld.long 0x00 0. "ENABLE,USART Enable" "0: DISABLED,1: Enabled" group.long 0x04++0x03 line.long 0x00 "CTL,USART Control" bitfld.long 0x00 16. "AUTOBAUD,Autobaud Enable" "0: DISABLED,1: ENABLED" newline bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: AUTO_CLEAR" newline bitfld.long 0x00 8. "CC,Continuous Clock Generation" "0: CLOCK_ON_CHARACTER,1: Continuous clock" newline bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled" newline bitfld.long 0x00 2. "ADDRDET,Enable Address Detect Mode" "0: Disabled,1: ENABLED" newline bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break" group.long 0x08++0x03 line.long 0x00 "STAT,USART Status" eventfld.long 0x00 16. "ABERR,Auto Baud Error" "0,1" newline eventfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline eventfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline eventfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline eventfld.long 0x00 12. "START,Start" "0,1" newline eventfld.long 0x00 11. "DELTARXBRK,Delta Received Break" "0,1" newline rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1" newline rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status Flag" "0: Not Idle,1: Idle" newline eventfld.long 0x00 5. "DELTACTS,Delta CTS" "0,1" newline rbitfld.long 0x00 4. "CTS,CTS value" "0,1" newline rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0: The transmitter is currently sending data,1: The transmitter is not currently sending data" newline rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0: The receiver is currently receiving data,1: The receiver is not currently receiving data" group.long 0x0C++0x03 line.long 0x00 "INTENSET,Interrupt Enable Read and Set for USART (not FIFO) Status" bitfld.long 0x00 16. "ABERREN,Auto Baud Error Enable" "?,1: Enables an interrupt when an auto baud error.." newline bitfld.long 0x00 15. "RXNOISEEN,Receive Noise Enable" "?,1: Enables an interrupt when noise is detected" newline bitfld.long 0x00 14. "PARITYERREN,Parity Error Enble" "?,1: Enables an interrupt when a parity error has.." newline bitfld.long 0x00 13. "FRAMERREN,Frame Error Enable" "?,1: Enables an interrupt when a framing error has.." newline bitfld.long 0x00 12. "STARTEN,Start Enable" "?,1: Enables an interrupt when a received start.." newline bitfld.long 0x00 11. "DELTARXBRKEN,Delta Receive Break Enable" "?,1: ENABLE" newline bitfld.long 0x00 6. "TXDISEN,Transmit Disabled Flag" "?,1: Enables an interrupt when the transmitter is.." newline bitfld.long 0x00 5. "DELTACTSEN,Delta CTS Input Flag" "?,1: Enables an interrupt when there is a change.." newline bitfld.long 0x00 3. "TXIDLEEN,Transmit Idle Flag" "?,1: Enables an interrupt when the transmitter.." wgroup.long 0x10++0x03 line.long 0x00 "INTENCLR,Interrupt Enable Clear" bitfld.long 0x00 16. "ABERRCLR,Auto Baud Error Clear" "0,1" newline bitfld.long 0x00 15. "RXNOISECLR,Receive Noise Clear" "0,1" newline bitfld.long 0x00 14. "PARITYERRCLR,Parity Error Clear" "0,1" newline bitfld.long 0x00 13. "FRAMERRCLR,Frame Error Clear" "0,1" newline bitfld.long 0x00 12. "STARTCLR,Start Clear" "0,1" newline bitfld.long 0x00 11. "DELTARXBRKCLR,Delta Receive Break Clear" "0,1" newline bitfld.long 0x00 6. "TXDISCLR,Transmit Disable Clear" "0,1" newline bitfld.long 0x00 5. "DELTACTSCLR,Delta CTS Clear" "0,1" newline bitfld.long 0x00 3. "TXIDLECLR,Transmit Idle Clear" "0,1" group.long 0x20++0x03 line.long 0x00 "BRG,Baud Rate Generator" hexmask.long.word 0x00 0.--15. 1. "BRGVAL,Baud Rate Generator Value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status" bitfld.long 0x00 16. "ABERRINT,Auto Baud Error Interrupt Flag" "0,1" newline bitfld.long 0x00 15. "RXNOISEINT,Received Noise Interrupt Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERRINT,Parity Error Interrupt Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERRINT,Framing Error Interrupt Flag" "0,1" newline bitfld.long 0x00 12. "START,Start Detected on Receiver Flag" "0,1" newline bitfld.long 0x00 11. "DELTARXBRK,Delta Receiver Break Change Flag" "0,1" newline bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt Flag" "0,1" newline bitfld.long 0x00 5. "DELTACTS,Delta CTS Change Flag" "0,1" newline bitfld.long 0x00 3. "TXIDLE,Transmitter Idle Flag" "0,1" group.long 0x28++0x03 line.long 0x00 "OSR,Oversample Selection Register for Asynchronous Communication" bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "0: Not supported,1: Not supported,2: Not supported,3: Not supported,4: 5 function clocks are used to transmit and..,5: 6 function clocks are used to transmit and..,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and.." group.long 0x2C++0x03 line.long 0x00 "ADDR,Address Register for Automatic Address Matching" hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,Address" group.long 0xE00++0x03 line.long 0x00 "FIFOCFG,FIFO Configuration" bitfld.long 0x00 18. "POPDBG,Pop FIFO for Debug Reads" "0: Debug reads of the FIFO do not pop the FIFO,1: A debug read will cause the FIFO to pop" newline bitfld.long 0x00 17. "EMPTYRX,Empty Command for the Receive FIFO" "0: NO_EFFECT,1: The RX FIFO is emptied" newline bitfld.long 0x00 16. "EMPTYTX,Empty Command for the Transmit FIFO" "0: NO_EFFECT,1: The TX FIFO is emptied" newline bitfld.long 0x00 15. "WAKERX,Wake-up for Receive FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 14. "WAKETX,Wake-up for Transmit FIFO Level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.." newline bitfld.long 0x00 13. "DMARX,DMA Configuration for Receive" "0: DMA is not used for the receive function,1: Triggers DMA for the receive function if the.." newline bitfld.long 0x00 12. "DMATX,DMA Configuration for Transmit" "0: DMA is not used for the transmit function,1: Triggers DMA for the transmit function if the.." newline rbitfld.long 0x00 4.--5. "SIZE,FIFO Size Configuration" "0: FIFO is configured as 16 entries of 8 bits,1: SIZEINVALID1,2: SIZEINVALID2,3: SIZEINVALID3" newline bitfld.long 0x00 1. "ENABLERX,Enable the Receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled" newline bitfld.long 0x00 0. "ENABLETX,Enable the Transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled" group.long 0xE04++0x03 line.long 0x00 "FIFOSTAT,FIFO Status" eventfld.long 0x00 24. "RXTIMEOUT,Receive FIFO Timeout" "0: RX FIFO on,1: RX FIFO has timed out based on the timeout.." newline rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO Current Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 7. "RXFULL,Receive FIFO is Full" "0: The receive FIFO is not full,1: The receive FIFO is full" newline rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO is Not Empty" "0: The receive FIFO is empty,1: The receive FIFO is not empty so data can be" newline rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO is Not Full" "0: The transmit FIFO is full and another write..,1: The transmit FIFO is not full so more data.." newline rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO Empty" "0: The transmit FIFO is not empty,1: The transmit FIFO is empty although the.." newline rbitfld.long 0x00 3. "PERINT,Peripheral Interrupt" "0: No Peripheral Interrupt,1: Peripheral Interrupt" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error" "0: A receive FIFO overflow has not occurred,1: A receive FIFO overflow has occurred caused.." newline bitfld.long 0x00 0. "TXERR,TX FIFO Error" "0: A transmit FIFO error has not occurred,1: A transmit FIFO error has occurred" group.long 0xE08++0x03 line.long 0x00 "FIFOTRIG,FIFO Trigger Settings for Interrupt and DMA Request" bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO Level Trigger Point" "0: Trigger when the RX FIFO has received 1 entry..,1: Trigger when the RX FIFO has received 2 entries,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the RX FIFO has received 16.." newline bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO Level Trigger Point" "0: Trigger when the TX FIFO becomes empty,1: Trigger when the TX FIFO level decreases to 1..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: Trigger when the TX FIFO level decreases to.." newline bitfld.long 0x00 1. "RXLVLENA,Receive FIFO Level Trigger Enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.." newline bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO Level Trigger Enable" "0: Transmit FIFO level does not generate a FIFO..,1: A trigger will be generated if the transmit.." group.long 0xE10++0x03 line.long 0x00 "FIFOINTENSET,FIFO Interrupt Enable" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: No RX interrupt will be generated,1: Asserts RX interrupt if RX FIFO Timeout event.." newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[RXLVLENA] = 1 an interrupt will.." newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: No interrupt will be generated based on the..,1: If FIFOTRIG[TXLVLENA] = 1 then an interrupt.." newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.." newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.." group.long 0xE14++0x03 line.long 0x00 "FIFOINTENCLR,FIFO Interrupt Enable Clear" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 1. "RXERR,Receive Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" newline bitfld.long 0x00 0. "TXERR,Transmit Error Interrupt Enable" "0: NO_EFFECT,1: Clear the interrupt" rgroup.long 0xE18++0x03 line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status" bitfld.long 0x00 24. "RXTIMEOUT,Receive Timeout Status" "0: ISNOTPENDING,1: IS_PENDING" newline bitfld.long 0x00 4. "PERINT,Peripheral Interrupt Status" "0: PERINT_ISNOTPENDING,1: PERINT_ISPENDING" newline bitfld.long 0x00 3. "RXLVL,Receive FIFO Level Interrupt Status" "0: RXLVL_ISNOTPENDING,1: RXLVL_ISPENDING" newline bitfld.long 0x00 2. "TXLVL,Transmit FIFO Level Interrupt Status" "0: TXLVL_ISNOTPENDING,1: TXLVL_ISPENDING" newline bitfld.long 0x00 1. "RXERR,RX FIFO Error Interrupt Status" "0: RXERR_ISNOTPENDING,1: RXERR_ISPENDING" newline bitfld.long 0x00 0. "TXERR,TX FIFO Error Interrupt Status" "0: TXERR_ISNOTPENDING,1: TXERR_ISPENDING" wgroup.long 0xE20++0x03 line.long 0x00 "FIFOWR,FIFO Write Data" hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO" rgroup.long 0xE30++0x03 line.long 0x00 "FIFORD,FIFO Read Data" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE40++0x03 line.long 0x00 "FIFORDNOPOP,FIFO Data Read with No FIFO Pop" bitfld.long 0x00 15. "RXNOISE,Received Noise Flag" "0,1" newline bitfld.long 0x00 14. "PARITYERR,Parity Error Status Flag" "0,1" newline bitfld.long 0x00 13. "FRAMERR,Framing Error Status Flag" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received Data from the FIFO" rgroup.long 0xE48++0x03 line.long 0x00 "FIFOSIZE,FIFO Size" bitfld.long 0x00 0.--4. "FIFOSIZE,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4C++0x03 line.long 0x00 "FIFORXTIMEOUTCFG,FIFO Receive Timeout Configuration" bitfld.long 0x00 26. "RXTIMEOUT_COE,Receive Timeout Continue On Empty" "0: RX FIFO timeout counter is reset when the RX..,1: RX FIFO timeout counter is not reset when the.." newline bitfld.long 0x00 25. "RXTIMEOUT_COW,Receive Timeout Continue On Write" "0: RX FIFO timeout counter is reset every time..,1: RX FIFO timeout counter is not reset every.." newline bitfld.long 0x00 24. "RXTIMEOUT_EN,Receive Timeout Enable" "0: Disable RX FIFO timeout,1: Enable RX FIFO timeout" newline hexmask.long.word 0x00 8.--23. 1. "RXTIMEOUT_VALUE,Receive Timeout Value" newline hexmask.long.byte 0x00 0.--7. 1. "RXTIMEOUT_PRESCALER,Receive Timeout Counter Clock Prescaler" rgroup.long 0xE50++0x03 line.long 0x00 "FIFORXTIMEOUTCNT,FIFO Receive Timeout Counter" hexmask.long.word 0x00 0.--15. 1. "RXTIMEOUT_CNT,Current RX FIFO timeout counter value" rgroup.long 0xFFC++0x03 line.long 0x00 "ID,Peripheral Identification" hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function" newline bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture" tree.end tree.end sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "USB (Universal Serial Bus)" base ad:0x40084000 group.long 0x00++0x03 line.long 0x00 "DEVCMDSTAT,USB Device Command/Status register" rbitfld.long 0x00 28. "VBUSDEBOUNCED,This bit indicates if Vbus is detected or not" "0,1" bitfld.long 0x00 26. "DRES_C,Device status - reset change" "0,1" newline bitfld.long 0x00 25. "DSUS_C,Device status - suspend change" "0,1" bitfld.long 0x00 24. "DCON_C,Device status - connect change" "0,1" newline rbitfld.long 0x00 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host" "0,1" bitfld.long 0x00 19. "LPM_SUS,Device status - LPM Suspend" "0,1" newline bitfld.long 0x00 17. "DSUS,Device status - suspend" "0,1" bitfld.long 0x00 16. "DCON,Device status - connect" "0,1" newline bitfld.long 0x00 15. "INTONNAK_CI,Interrupt on NAK for control IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." bitfld.long 0x00 14. "INTONNAK_CO,Interrupt on NAK for control OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." newline bitfld.long 0x00 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." bitfld.long 0x00 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." newline bitfld.long 0x00 11. "LPM_SUP,LPM Supported" "0: LPM not supported,1: LPM supported" bitfld.long 0x00 9. "FORCE_NEEDCLK,Forces the NEEDCLK output to always be on" "0: USB_NEEDCLK has normal function,1: USB_NEEDCLK always 1" newline bitfld.long 0x00 8. "SETUP,SETUP token received" "0,1" bitfld.long 0x00 7. "DEV_EN,USB device enable" "0,1" newline hexmask.long.byte 0x00 0.--6. 1. "DEV_ADDR,USB device address" group.long 0x04++0x03 line.long 0x00 "INFO,USB Info register" hexmask.long.byte 0x00 24.--31. 1. "MAJREV,Major Revision" hexmask.long.byte 0x00 16.--23. 1. "MINREV,Minor Revision" newline bitfld.long 0x00 11.--14. "ERR_CODE,The error code which last occurred" "0: NO_ERROR,1: PID_ENCODING_ERROR,2: PID_UNKNOWN,3: PACKET_UNEXPECTED,4: TOKEN_CRC_ERROR,5: DATA_CRC_ERROR,6: Time out,7: BABBLE,8: TRUNCATED_EOP,9: SENT_RECEIVED_NAK,10: SENT_STALL,11: OVERRUN,12: SENT_EMPTY_PACKET,13: BITSTUFF_ERROR,14: SYNC_ERROR,15: WRONG_DATA_TOGGLE" hexmask.long.word 0x00 0.--10. 1. "FRAME_NR,Frame number" group.long 0x08++0x03 line.long 0x00 "EPLISTSTART,USB EP Command/Status List start address" hexmask.long.tbyte 0x00 8.--31. 1. "EP_LIST,Start address of the USB EP Command/Status List" group.long 0x0C++0x03 line.long 0x00 "DATABUFSTART,USB Data buffer start address" hexmask.long.word 0x00 22.--31. 1. "DA_BUF,Start address of the buffer pointer page where all endpoint data buffers are located" group.long 0x10++0x03 line.long 0x00 "LPM,USB Link Power Management register" bitfld.long 0x00 8. "DATA_PENDING,As long as this bit is set to one and LPM supported bit is set to one HW will return a NYET handshake on every LPM token it receives" "0,1" bitfld.long 0x00 4.--7. "HIRD_SW,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. "HIRD_HW,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x03 line.long 0x00 "EPSKIP,USB Endpoint skip" hexmask.long.word 0x00 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software" group.long 0x18++0x03 line.long 0x00 "EPINUSE,USB Endpoint Buffer in use" abitfld.long 0x00 2.--9. "BUF,Buffer in use: This register has one bit per physical endpoint" "0x00=0: HW is accessing buffer 0,0x01=1: HW is accessing buffer 1" group.long 0x1C++0x03 line.long 0x00 "EPBUFCFG,USB Endpoint Buffer Configuration register" abitfld.long 0x00 2.--9. "BUF_SB,Buffer usage: This register has one bit per physical endpoint" "0x00=0: Single-buffer,0x01=1: Double-buffer" group.long 0x20++0x03 line.long 0x00 "INTSTAT,USB interrupt status register" bitfld.long 0x00 31. "DEV_INT,Device status interrupt" "0,1" bitfld.long 0x00 30. "FRAME_INT,Frame interrupt" "0,1" newline bitfld.long 0x00 9. "EP4IN,Interrupt status register bit for the EP4 IN direction" "0,1" bitfld.long 0x00 8. "EP4OUT,Interrupt status register bit for the EP4 OUT direction" "0,1" newline bitfld.long 0x00 7. "EP3IN,Interrupt status register bit for the EP3 IN direction" "0,1" bitfld.long 0x00 6. "EP3OUT,Interrupt status register bit for the EP3 OUT direction" "0,1" newline bitfld.long 0x00 5. "EP2IN,Interrupt status register bit for the EP2 IN direction" "0,1" bitfld.long 0x00 4. "EP2OUT,Interrupt status register bit for the EP2 OUT direction" "0,1" newline bitfld.long 0x00 3. "EP1IN,Interrupt status register bit for the EP1 IN direction" "0,1" bitfld.long 0x00 2. "EP1OUT,Interrupt status register bit for the EP1 OUT direction" "0,1" newline bitfld.long 0x00 1. "EP0IN,Interrupt status register bit for the Control EP0 IN direction" "0,1" bitfld.long 0x00 0. "EP0OUT,Interrupt status register bit for the Control EP0 OUT direction" "0,1" group.long 0x24++0x03 line.long 0x00 "INTEN,USB interrupt enable register" bitfld.long 0x00 31. "DEV_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" "0,1" bitfld.long 0x00 30. "FRAME_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "EP_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" group.long 0x28++0x03 line.long 0x00 "INTSETSTAT,USB set interrupt status register" bitfld.long 0x00 31. "DEV_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1" bitfld.long 0x00 30. "FRAME_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "EP_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" group.long 0x34++0x03 line.long 0x00 "EPTOGGLE,USB Endpoint toggle register" hexmask.long.word 0x00 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint" tree.end endif sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "USBFSD (USB 2.0 Full Speed Device Controller)" base ad:0x40084000 group.long 0x00++0x03 line.long 0x00 "DEVCMDSTAT,USB Device Command/Status register" rbitfld.long 0x00 28. "VBUSDEBOUNCED,This bit indicates if Vbus is detected or not" "0,1" bitfld.long 0x00 26. "DRES_C,Device status - reset change" "0,1" newline bitfld.long 0x00 25. "DSUS_C,Device status - suspend change" "0,1" bitfld.long 0x00 24. "DCON_C,Device status - connect change" "0,1" newline rbitfld.long 0x00 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host" "0,1" bitfld.long 0x00 19. "LPM_SUS,Device status - LPM Suspend" "0,1" newline bitfld.long 0x00 17. "DSUS,Device status - suspend" "0,1" bitfld.long 0x00 16. "DCON,Device status - connect" "0,1" newline bitfld.long 0x00 15. "INTONNAK_CI,Interrupt on NAK for control IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." bitfld.long 0x00 14. "INTONNAK_CO,Interrupt on NAK for control OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." newline bitfld.long 0x00 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." bitfld.long 0x00 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.." newline bitfld.long 0x00 11. "LPM_SUP,LPM Supported" "0: LPM not supported,1: LPM supported" bitfld.long 0x00 9. "FORCE_NEEDCLK,Forces the NEEDCLK output to always be on" "0: USB_NEEDCLK has normal function,1: USB_NEEDCLK always 1" newline bitfld.long 0x00 8. "SETUP,SETUP token received" "0,1" bitfld.long 0x00 7. "DEV_EN,USB device enable" "0,1" newline hexmask.long.byte 0x00 0.--6. 1. "DEV_ADDR,USB device address" group.long 0x04++0x03 line.long 0x00 "INFO,USB Info register" hexmask.long.byte 0x00 24.--31. 1. "MAJREV,Major Revision" hexmask.long.byte 0x00 16.--23. 1. "MINREV,Minor Revision" newline bitfld.long 0x00 11.--14. "ERR_CODE,The error code which last occurred" "0: NO_ERROR,1: PID_ENCODING_ERROR,2: PID_UNKNOWN,3: PACKET_UNEXPECTED,4: TOKEN_CRC_ERROR,5: DATA_CRC_ERROR,6: Time out,7: BABBLE,8: TRUNCATED_EOP,9: SENT_RECEIVED_NAK,10: SENT_STALL,11: OVERRUN,12: SENT_EMPTY_PACKET,13: BITSTUFF_ERROR,14: SYNC_ERROR,15: WRONG_DATA_TOGGLE" hexmask.long.word 0x00 0.--10. 1. "FRAME_NR,Frame number" group.long 0x08++0x03 line.long 0x00 "EPLISTSTART,USB EP Command/Status List start address" hexmask.long.tbyte 0x00 8.--31. 1. "EP_LIST,Start address of the USB EP Command/Status List" group.long 0x0C++0x03 line.long 0x00 "DATABUFSTART,USB Data buffer start address" hexmask.long.word 0x00 22.--31. 1. "DA_BUF,Start address of the buffer pointer page where all endpoint data buffers are located" group.long 0x10++0x03 line.long 0x00 "LPM,USB Link Power Management register" bitfld.long 0x00 8. "DATA_PENDING,As long as this bit is set to one and LPM supported bit is set to one HW will return a NYET handshake on every LPM token it receives" "0,1" bitfld.long 0x00 4.--7. "HIRD_SW,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. "HIRD_HW,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x03 line.long 0x00 "EPSKIP,USB Endpoint skip" hexmask.long.word 0x00 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software" group.long 0x18++0x03 line.long 0x00 "EPINUSE,USB Endpoint Buffer in use" abitfld.long 0x00 2.--9. "BUF,Buffer in use: This register has one bit per physical endpoint" "0x00=0: HW is accessing buffer 0,0x01=1: HW is accessing buffer 1" group.long 0x1C++0x03 line.long 0x00 "EPBUFCFG,USB Endpoint Buffer Configuration register" abitfld.long 0x00 2.--9. "BUF_SB,Buffer usage: This register has one bit per physical endpoint" "0x00=0: Single-buffer,0x01=1: Double-buffer" group.long 0x20++0x03 line.long 0x00 "INTSTAT,USB interrupt status register" bitfld.long 0x00 31. "DEV_INT,Device status interrupt" "0,1" bitfld.long 0x00 30. "FRAME_INT,Frame interrupt" "0,1" newline bitfld.long 0x00 9. "EP4IN,Interrupt status register bit for the EP4 IN direction" "0,1" bitfld.long 0x00 8. "EP4OUT,Interrupt status register bit for the EP4 OUT direction" "0,1" newline bitfld.long 0x00 7. "EP3IN,Interrupt status register bit for the EP3 IN direction" "0,1" bitfld.long 0x00 6. "EP3OUT,Interrupt status register bit for the EP3 OUT direction" "0,1" newline bitfld.long 0x00 5. "EP2IN,Interrupt status register bit for the EP2 IN direction" "0,1" bitfld.long 0x00 4. "EP2OUT,Interrupt status register bit for the EP2 OUT direction" "0,1" newline bitfld.long 0x00 3. "EP1IN,Interrupt status register bit for the EP1 IN direction" "0,1" bitfld.long 0x00 2. "EP1OUT,Interrupt status register bit for the EP1 OUT direction" "0,1" newline bitfld.long 0x00 1. "EP0IN,Interrupt status register bit for the Control EP0 IN direction" "0,1" bitfld.long 0x00 0. "EP0OUT,Interrupt status register bit for the Control EP0 OUT direction" "0,1" group.long 0x24++0x03 line.long 0x00 "INTEN,USB interrupt enable register" bitfld.long 0x00 31. "DEV_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" "0,1" bitfld.long 0x00 30. "FRAME_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "EP_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" group.long 0x28++0x03 line.long 0x00 "INTSETSTAT,USB set interrupt status register" bitfld.long 0x00 31. "DEV_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1" bitfld.long 0x00 30. "FRAME_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "EP_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" group.long 0x34++0x03 line.long 0x00 "EPTOGGLE,USB Endpoint toggle register" hexmask.long.word 0x00 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint" tree.end endif sif cpuis("LPC5534*")||cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*")||cpuis("LPC5536*") tree "USBFSH (USB 2.0 Full-speed Host controller)" sif cpuis("LPC5534*")||cpuis("LPC5536*") base ad:0x400A2000 rgroup.long 0x00++0x03 line.long 0x00 "HCREVISION,Host controller revision" hexmask.long.byte 0x00 0.--7. 1. "REV,Revision" group.long 0x04++0x03 line.long 0x00 "HCCONTROL,Host controller control" bitfld.long 0x00 10. "RWE,RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling" "0,1" bitfld.long 0x00 9. "RWC,RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling" "0,1" newline bitfld.long 0x00 8. "IR,InterruptRouting" "0,1" bitfld.long 0x00 6.--7. "HCFS,HostControllerFunctionalState" "0: USBRESET,1: USBRESUME,2: USBOPERATIONAL,3: USBSUSPEND" newline bitfld.long 0x00 5. "BLE,BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame" "0,1" bitfld.long 0x00 4. "CLE,ControlListEnable" "0,1" newline bitfld.long 0x00 3. "IE,IsochronousEnable" "0,1" bitfld.long 0x00 2. "PLE,PeriodicListEnable" "0,1" newline bitfld.long 0x00 0.--1. "CBSR,ControlBulkServiceRatio" "0,1,2,3" group.long 0x08++0x03 line.long 0x00 "HCCOMMANDSTATUS,Host controller command status" bitfld.long 0x00 6.--7. "SOC,SchedulingOverrunCount These bits are incremented on each scheduling overrun error" "0,1,2,3" bitfld.long 0x00 3. "OCR,OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC" "0,1" newline bitfld.long 0x00 2. "BLF,BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list" "0,1" bitfld.long 0x00 1. "CLF,ControlListFilled This bit is used to indicate whether there are any TDs on the Control list" "0,1" newline bitfld.long 0x00 0. "HCR,HostControllerReset" "0,1" group.long 0x0C++0x03 line.long 0x00 "HCINTERRUPTSTATUS,Host controller interrupt status" hexmask.long.tbyte 0x00 10.--31. 1. "OC,OwnershipChange" bitfld.long 0x00 6. "RHSC,RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed" "0,1" newline bitfld.long 0x00 5. "FNO,FrameNumberOverflow" "0,1" bitfld.long 0x00 4. "UE,UnrecoverableError" "0,1" newline bitfld.long 0x00 3. "RD,ResumeDetected" "0,1" bitfld.long 0x00 2. "SF,StartofFrame" "0,1" newline bitfld.long 0x00 1. "WDH,WritebackDoneHead" "0,1" bitfld.long 0x00 0. "SO,SchedulingOverrun" "0,1" group.long 0x10++0x03 line.long 0x00 "HCINTERRUPTENABLE,Host Controller interrupt enable" bitfld.long 0x00 31. "MIE,Master Interrupt Enable" "0,1" bitfld.long 0x00 30. "OC,Ownership Change interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 6. "RHSC,Root Hub Status Change interrupt" "0: No effect,1: Enables interrupt" bitfld.long 0x00 5. "FNO,Frame Number Overflow interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 4. "UE,Unrecoverable Error interrupt" "0: No effect,1: Enables interrupt" bitfld.long 0x00 3. "RD,Resume Detect interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 2. "SF,Start of Frame interrupt" "0: No effect,1: Enables interrupt" bitfld.long 0x00 1. "WDH,HcDoneHead Writeback interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 0. "SO,Scheduling Overrun interrupt" "0: No effect,1: Enables interrupt" group.long 0x14++0x03 line.long 0x00 "HCINTERRUPTDISABLE,The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt" bitfld.long 0x00 31. "MIE,A 0 written to this field is ignored by HC" "0: No effect,1: Disables interrupt" bitfld.long 0x00 30. "OC,Ownership Change interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 6. "RHSC,Root Hub Status Change interrupt" "0: No effect,1: Disables interrupt" bitfld.long 0x00 5. "FNO,Frame Number Overflow interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 4. "UE,Unrecoverable Error interrupt" "0: No effect,1: Disables interrupt" bitfld.long 0x00 3. "RD,Resume Detect interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 2. "SF,Start of Frame interrupt" "0: No effect,1: Disables interrupt" bitfld.long 0x00 1. "WDH,HcDoneHead Writeback interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 0. "SO,Scheduling Overrun interrupt" "0: No effect,1: Disables interrupt" group.long 0x18++0x03 line.long 0x00 "HCHCCA,Host controller communication area" hexmask.long.tbyte 0x00 8.--31. 1. "HCCA,Host Controller Communication Area" group.long 0x1C++0x03 line.long 0x00 "HCPERIODCURRENTED,Host controller period current endpoint descriptor" hexmask.long 0x00 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed" group.long 0x20++0x03 line.long 0x00 "HCCONTROLHEADED,Host controller control head endpoint descriptor" hexmask.long 0x00 4.--31. 1. "CHED,HC traverses the Control list starting with the HcControlHeadED pointer" group.long 0x24++0x03 line.long 0x00 "HCCONTROLCURRENTED,Host controller control current endpoint descriptor" hexmask.long 0x00 4.--31. 1. "CCED,ControlCurrentED" group.long 0x28++0x03 line.long 0x00 "HCBULKHEADED,Host controller bulk head endpoint descriptor" hexmask.long 0x00 4.--31. 1. "BHED,BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer" group.long 0x2C++0x03 line.long 0x00 "HCBULKCURRENTED,Host controller bulk current endpoint descriptor" hexmask.long 0x00 4.--31. 1. "BCED,BulkCurrentED" group.long 0x30++0x03 line.long 0x00 "HCDONEHEAD,Host controller done head" hexmask.long 0x00 4.--31. 1. "DH,DoneHead When a TD is completed HC writes the content of HcDoneHead to the NextTD field of the TD" group.long 0x34++0x03 line.long 0x00 "HCFMINTERVAL,Host controller frame interval" bitfld.long 0x00 31. "FIT,FrameIntervalToggle" "0,1" hexmask.long.word 0x00 16.--30. 1. "FSMPS,FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame" newline hexmask.long.word 0x00 0.--13. 1. "FI,FrameInterval This specifies the interval between two consecutive SOFs in bit times" group.long 0x38++0x03 line.long 0x00 "HCFMREMAINING,Host controller frame remaining" rbitfld.long 0x00 31. "FRT,FrameRemainingToggle" "0,1" hexmask.long.word 0x00 0.--13. 1. "FR,FrameRemaining" group.long 0x3C++0x03 line.long 0x00 "HCFMNUMBER,Host controller frame number" hexmask.long.word 0x00 0.--15. 1. "FN,FrameNumber" group.long 0x40++0x03 line.long 0x00 "HCPERIODICSTART,Host controller periodic start" hexmask.long.word 0x00 0.--13. 1. "PS,PeriodicStart" group.long 0x44++0x03 line.long 0x00 "HCLSTHRESHOLD,Host controller low speed threshold" hexmask.long.word 0x00 0.--11. 1. "LST,LSThreshold" group.long 0x48++0x03 line.long 0x00 "HCRHDESCRIPTORA,Host controller root hub descriptor A" hexmask.long.byte 0x00 24.--31. 1. "POTPGT,PowerOnToPowerGoodTime" bitfld.long 0x00 12. "NOCP,NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported" "0: Over-current status is reported collectively..,1: No overcurrent protection supported" newline bitfld.long 0x00 11. "OCPM,OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported" "0: Over-current status is reported collectively..,1: Over-current status is reported on a per-port.." bitfld.long 0x00 10. "DT,DeviceType" "0,1" newline bitfld.long 0x00 9. "NPS,NoPowerSwitching" "0: Ports are power switched,1: Ports are always powered on when the host.." bitfld.long 0x00 8. "PSM,PowerSwitchingMode" "0: All ports are powered at the same time,1: Each port is powered individually" newline hexmask.long.byte 0x00 0.--7. 1. "NDP,NumberDownstreamPorts" group.long 0x4C++0x03 line.long 0x00 "HCRHDESCRIPTORB,Host controller root hub descriptor B" hexmask.long.word 0x00 16.--31. 1. "PPCM,PortPowerControlMask" hexmask.long.word 0x00 0.--15. 1. "DR,DeviceRemovable" group.long 0x50++0x03 line.long 0x00 "HCRHSTATUS,This register is divided into two parts" bitfld.long 0x00 31. "CRWE,(write) ClearRemoteWakeupEnable" "0,1" bitfld.long 0x00 17. "OCIC,OverCurrentIndicatorChange" "0,1" newline bitfld.long 0x00 16. "LPSC,(read) LocalPowerStatusChange(Write) SetGlobalPower" "0,1" bitfld.long 0x00 15. "DRWE,(read) DeviceRemoteWakeupEnable (Write) SetRemoteWakeupEnable" "0: ConnectStatusChange is not a remote wakeup..,1: ConnectStatusChange is a remote wakeup event" newline bitfld.long 0x00 1. "OCI,OverCurrentIndicator" "0,1" bitfld.long 0x00 0. "LPS,(read) LocalPowerStatus (write) ClearGlobalPower" "0,1" group.long 0x54++0x03 line.long 0x00 "HCRHPORTSTATUS,Host controller root hub port status" bitfld.long 0x00 20. "PRSC,PortResetStatusChange" "0: Port reset is not complete,1: Port reset is complete" bitfld.long 0x00 19. "OCIC,PortOverCurrentIndicatorChange" "0: PortOverCurrentIndicator has not changed,1: PortOverCurrentIndicator has changed" newline bitfld.long 0x00 18. "PSSC,PortSuspendStatusChange" "0: Resume sequence is not complete,1: Resume sequence is complete" bitfld.long 0x00 17. "PESC,PortEnableStatusChange" "0: PortEnableStatus has not changed,1: PortEnableStatus has changed" newline bitfld.long 0x00 16. "CSC,ConnectStatusChange" "0: CurrentConnectStatus has not changed,1: CurrentConnectStatus has changed" bitfld.long 0x00 9. "LSDA,(read) LowSpeedDeviceAttached" "0: Full speed device is attached,1: Low speed device is attached" newline bitfld.long 0x00 8. "PPS,(read) PortPowerStatus" "0: Port power is off,1: Port power is on" bitfld.long 0x00 4. "PRS,(read) PortResetStatus When this bit is set by a write to SetPortReset port reset signaling is asserted" "0: Port reset signal is not active,1: Port reset signal is active" newline bitfld.long 0x00 3. "POCI,(read) PortOverCurrentIndicator" "0: Overcurrent condition is not detected,1: Overcurrent condition is detected" bitfld.long 0x00 2. "PSS,(Read) PortSuspendStatus" "0: Port is not suspended,1: Port is suspended" newline bitfld.long 0x00 1. "PES,(Read)PortEnableStatus" "0: Port is disabled,1: Port is enabled" bitfld.long 0x00 0. "CCS,CurrentConnectStatus" "0: Device is not connected,1: Device is connected" group.long 0x5C++0x03 line.long 0x00 "PORTMODE,Port Mode" bitfld.long 0x00 16. "DEV_ENABLE,Device Enable" "0: Device,1: Host" bitfld.long 0x00 8. "ID_EN,Port ID pin pull-up enable" "0,1" newline bitfld.long 0x00 0. "ID,Port ID pin value" "0,1" endif sif cpuis("LPC5512*")||cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") base ad:0x400A2000 rgroup.long 0x00++0x03 line.long 0x00 "HCREVISION,Host controller revision" hexmask.long.byte 0x00 0.--7. 1. "REV,Revision" group.long 0x04++0x03 line.long 0x00 "HCCONTROL,Host controller control" bitfld.long 0x00 10. "RWE,RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling" "0,1" bitfld.long 0x00 9. "RWC,RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling" "0,1" newline bitfld.long 0x00 8. "IR,InterruptRouting" "0,1" bitfld.long 0x00 6.--7. "HCFS,HostControllerFunctionalState" "0: USBRESET,1: USBRESUME,2: USBOPERATIONAL,3: USBSUSPEND" newline bitfld.long 0x00 5. "BLE,BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame" "0,1" bitfld.long 0x00 4. "CLE,ControlListEnable" "0,1" newline bitfld.long 0x00 3. "IE,IsochronousEnable" "0,1" bitfld.long 0x00 2. "PLE,PeriodicListEnable" "0,1" newline bitfld.long 0x00 0.--1. "CBSR,ControlBulkServiceRatio" "0,1,2,3" group.long 0x08++0x03 line.long 0x00 "HCCOMMANDSTATUS,Host controller command status" bitfld.long 0x00 6.--7. "SOC,SchedulingOverrunCount These bits are incremented on each scheduling overrun error" "0,1,2,3" bitfld.long 0x00 3. "OCR,OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC" "0,1" newline bitfld.long 0x00 2. "BLF,BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list" "0,1" bitfld.long 0x00 1. "CLF,ControlListFilled This bit is used to indicate whether there are any TDs on the Control list" "0,1" newline bitfld.long 0x00 0. "HCR,HostControllerReset" "0,1" group.long 0x0C++0x03 line.long 0x00 "HCINTERRUPTSTATUS,Host controller interrupt status" hexmask.long.tbyte 0x00 10.--31. 1. "OC,OwnershipChange" bitfld.long 0x00 6. "RHSC,RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed" "0,1" newline bitfld.long 0x00 5. "FNO,FrameNumberOverflow" "0,1" bitfld.long 0x00 4. "UE,UnrecoverableError" "0,1" newline bitfld.long 0x00 3. "RD,ResumeDetected" "0,1" bitfld.long 0x00 2. "SF,StartofFrame" "0,1" newline bitfld.long 0x00 1. "WDH,WritebackDoneHead" "0,1" bitfld.long 0x00 0. "SO,SchedulingOverrun" "0,1" group.long 0x10++0x03 line.long 0x00 "HCINTERRUPTENABLE,Host Controller interrupt enable" bitfld.long 0x00 31. "MIE,Master Interrupt Enable" "0,1" bitfld.long 0x00 30. "OC,Ownership Change interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 6. "RHSC,Root Hub Status Change interrupt" "0: No effect,1: Enables interrupt" bitfld.long 0x00 5. "FNO,Frame Number Overflow interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 4. "UE,Unrecoverable Error interrupt" "0: No effect,1: Enables interrupt" bitfld.long 0x00 3. "RD,Resume Detect interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 2. "SF,Start of Frame interrupt" "0: No effect,1: Enables interrupt" bitfld.long 0x00 1. "WDH,HcDoneHead Writeback interrupt" "0: No effect,1: Enables interrupt" newline bitfld.long 0x00 0. "SO,Scheduling Overrun interrupt" "0: No effect,1: Enables interrupt" group.long 0x14++0x03 line.long 0x00 "HCINTERRUPTDISABLE,The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt" bitfld.long 0x00 31. "MIE,A 0 written to this field is ignored by HC" "0: No effect,1: Disables interrupt" bitfld.long 0x00 30. "OC,Ownership Change interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 6. "RHSC,Root Hub Status Change interrupt" "0: No effect,1: Disables interrupt" bitfld.long 0x00 5. "FNO,Frame Number Overflow interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 4. "UE,Unrecoverable Error interrupt" "0: No effect,1: Disables interrupt" bitfld.long 0x00 3. "RD,Resume Detect interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 2. "SF,Start of Frame interrupt" "0: No effect,1: Disables interrupt" bitfld.long 0x00 1. "WDH,HcDoneHead Writeback interrupt" "0: No effect,1: Disables interrupt" newline bitfld.long 0x00 0. "SO,Scheduling Overrun interrupt" "0: No effect,1: Disables interrupt" group.long 0x18++0x03 line.long 0x00 "HCHCCA,Host controller communication area" hexmask.long.tbyte 0x00 8.--31. 1. "HCCA,Host Controller Communication Area" group.long 0x1C++0x03 line.long 0x00 "HCPERIODCURRENTED,Host controller period current endpoint descriptor" hexmask.long 0x00 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed" group.long 0x20++0x03 line.long 0x00 "HCCONTROLHEADED,Host controller control head endpoint descriptor" hexmask.long 0x00 4.--31. 1. "CHED,HC traverses the Control list starting with the HcControlHeadED pointer" group.long 0x24++0x03 line.long 0x00 "HCCONTROLCURRENTED,Host controller control current endpoint descriptor" hexmask.long 0x00 4.--31. 1. "CCED,ControlCurrentED" group.long 0x28++0x03 line.long 0x00 "HCBULKHEADED,Host controller bulk head endpoint descriptor" hexmask.long 0x00 4.--31. 1. "BHED,BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer" group.long 0x2C++0x03 line.long 0x00 "HCBULKCURRENTED,Host controller bulk current endpoint descriptor" hexmask.long 0x00 4.--31. 1. "BCED,BulkCurrentED" group.long 0x30++0x03 line.long 0x00 "HCDONEHEAD,Host controller done head" hexmask.long 0x00 4.--31. 1. "DH,DoneHead When a TD is completed HC writes the content of HcDoneHead to the NextTD field of the TD" group.long 0x34++0x03 line.long 0x00 "HCFMINTERVAL,Host controller frame interval" bitfld.long 0x00 31. "FIT,FrameIntervalToggle" "0,1" hexmask.long.word 0x00 16.--30. 1. "FSMPS,FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame" newline hexmask.long.word 0x00 0.--13. 1. "FI,FrameInterval This specifies the interval between two consecutive SOFs in bit times" group.long 0x38++0x03 line.long 0x00 "HCFMREMAINING,Host controller frame remaining" rbitfld.long 0x00 31. "FRT,FrameRemainingToggle" "0,1" hexmask.long.word 0x00 0.--13. 1. "FR,FrameRemaining" group.long 0x3C++0x03 line.long 0x00 "HCFMNUMBER,Host controller frame number" hexmask.long.word 0x00 0.--15. 1. "FN,FrameNumber" group.long 0x40++0x03 line.long 0x00 "HCPERIODICSTART,Host controller periodic start" hexmask.long.word 0x00 0.--13. 1. "PS,PeriodicStart" group.long 0x44++0x03 line.long 0x00 "HCLSTHRESHOLD,Host controller low speed threshold" hexmask.long.word 0x00 0.--11. 1. "LST,LSThreshold" group.long 0x48++0x03 line.long 0x00 "HCRHDESCRIPTORA,Host controller root hub descriptor A" hexmask.long.byte 0x00 24.--31. 1. "POTPGT,PowerOnToPowerGoodTime" bitfld.long 0x00 12. "NOCP,NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported" "0: Over-current status is reported collectively..,1: No overcurrent protection supported" newline bitfld.long 0x00 11. "OCPM,OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported" "0: Over-current status is reported collectively..,1: Over-current status is reported on a per-port.." bitfld.long 0x00 10. "DT,DeviceType" "0,1" newline bitfld.long 0x00 9. "NPS,NoPowerSwitching" "0: Ports are power switched,1: Ports are always powered on when the host.." bitfld.long 0x00 8. "PSM,PowerSwitchingMode" "0: All ports are powered at the same time,1: Each port is powered individually" newline hexmask.long.byte 0x00 0.--7. 1. "NDP,NumberDownstreamPorts" group.long 0x4C++0x03 line.long 0x00 "HCRHDESCRIPTORB,Host controller root hub descriptor B" hexmask.long.word 0x00 16.--31. 1. "PPCM,PortPowerControlMask" hexmask.long.word 0x00 0.--15. 1. "DR,DeviceRemovable" group.long 0x50++0x03 line.long 0x00 "HCRHSTATUS,This register is divided into two parts" bitfld.long 0x00 31. "CRWE,(write) ClearRemoteWakeupEnable" "0,1" bitfld.long 0x00 17. "OCIC,OverCurrentIndicatorChange" "0,1" newline bitfld.long 0x00 16. "LPSC,(read) LocalPowerStatusChange(Write) SetGlobalPower" "0,1" bitfld.long 0x00 15. "DRWE,(read) DeviceRemoteWakeupEnable (Write) SetRemoteWakeupEnable" "0: ConnectStatusChange is not a remote wakeup..,1: ConnectStatusChange is a remote wakeup event" newline bitfld.long 0x00 1. "OCI,OverCurrentIndicator" "0,1" bitfld.long 0x00 0. "LPS,(read) LocalPowerStatus (write) ClearGlobalPower" "0,1" group.long 0x54++0x03 line.long 0x00 "HCRHPORTSTATUS,Host controller root hub port status" bitfld.long 0x00 20. "PRSC,PortResetStatusChange" "0: Port reset is not complete,1: Port reset is complete" bitfld.long 0x00 19. "OCIC,PortOverCurrentIndicatorChange" "0: PortOverCurrentIndicator has not changed,1: PortOverCurrentIndicator has changed" newline bitfld.long 0x00 18. "PSSC,PortSuspendStatusChange" "0: Resume sequence is not complete,1: Resume sequence is complete" bitfld.long 0x00 17. "PESC,PortEnableStatusChange" "0: PortEnableStatus has not changed,1: PortEnableStatus has changed" newline bitfld.long 0x00 16. "CSC,ConnectStatusChange" "0: CurrentConnectStatus has not changed,1: CurrentConnectStatus has changed" bitfld.long 0x00 9. "LSDA,(read) LowSpeedDeviceAttached" "0: Full speed device is attached,1: Low speed device is attached" newline bitfld.long 0x00 8. "PPS,(read) PortPowerStatus" "0: Port power is off,1: Port power is on" bitfld.long 0x00 4. "PRS,(read) PortResetStatus When this bit is set by a write to SetPortReset port reset signaling is asserted" "0: Port reset signal is not active,1: Port reset signal is active" newline bitfld.long 0x00 3. "POCI,(read) PortOverCurrentIndicator" "0: Overcurrent condition is not detected,1: Overcurrent condition is detected" bitfld.long 0x00 2. "PSS,(Read) PortSuspendStatus" "0: Port is not suspended,1: Port is suspended" newline bitfld.long 0x00 1. "PES,(Read)PortEnableStatus" "0: Port is disabled,1: Port is enabled" bitfld.long 0x00 0. "CCS,CurrentConnectStatus" "0: Device is not connected,1: Device is connected" group.long 0x5C++0x03 line.long 0x00 "PORTMODE,Port Mode" bitfld.long 0x00 16. "DEV_ENABLE,Device Enable" "0: Device,1: Host" bitfld.long 0x00 8. "ID_EN,Port ID pin pull-up enable" "0,1" newline bitfld.long 0x00 0. "ID,Port ID pin value" "0,1" endif tree.end endif sif cpuis("LPC5514*")||cpuis("LPC5516*")||cpuis("LPC5526*")||cpuis("LPC5528*") tree "USBHSD (USB1 High-speed Device Controller)" base ad:0x40094000 group.long 0x00++0x03 line.long 0x00 "DEVCMDSTAT,USB Device Command/Status register" bitfld.long 0x00 29.--31. "PHY_TEST_MODE,This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification" "0: Test mode disabled,1: Test_J,2: Test_K,3: Test_SE0_NAK,4: Test_Packet,5: Test_Force_Enable,?..." rbitfld.long 0x00 28. "VBUS_DEBOUNCED,This bit indicates if VBUS is detected or not" "0,1" bitfld.long 0x00 26. "DRES_C,Device status - reset change" "0,1" bitfld.long 0x00 25. "DSUS_C,Device status - suspend change" "0,1" newline bitfld.long 0x00 24. "DCON_C,Device status - connect change" "0,1" rbitfld.long 0x00 22.--23. "Speed,This field indicates the speed at which the device operates" "0: reserved,1: full-speed,2: high-speed,3: super-speed (reserved for" rbitfld.long 0x00 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host" "0,1" bitfld.long 0x00 19. "LPM_SUS,Device status - LPM Suspend" "0,1" newline bitfld.long 0x00 17. "DSUS,Device status - suspend" "0,1" bitfld.long 0x00 16. "DCON,Device status - connect" "0,1" bitfld.long 0x00 15. "INTONNAK_CI,Interrupt on NAK for control IN EP" "0,1" bitfld.long 0x00 14. "INTONNAK_CO,Interrupt on NAK for control OUT EP" "0,1" newline bitfld.long 0x00 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP" "0,1" bitfld.long 0x00 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP" "0,1" bitfld.long 0x00 11. "LPM_SUP,LPM Supported" "0,1" bitfld.long 0x00 9. "FORCE_NEEDCLK,Forces the NEEDCLK output to always be on" "0,1" newline bitfld.long 0x00 8. "SETUP,SETUP token received" "0,1" bitfld.long 0x00 7. "DEV_EN,USB device enable" "0,1" hexmask.long.byte 0x00 0.--6. 1. "DEV_ADDR,USB device address" rgroup.long 0x04++0x03 line.long 0x00 "INFO,USB Info register" hexmask.long.byte 0x00 24.--31. 1. "MAJREV,Major revision" hexmask.long.byte 0x00 16.--23. 1. "MINREV,Minor revision" bitfld.long 0x00 11.--14. "ERR_CODE,The error code which last occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--10. 1. "FRAME_NR,Frame number" group.long 0x08++0x03 line.long 0x00 "EPLISTSTART,USB EP Command/Status List start address" hexmask.long.word 0x00 20.--31. 1. "EP_LIST_FIXED,Fixed portion of USB EP Command/Status List address" hexmask.long.word 0x00 8.--19. 1. "EP_LIST_PRG,Programmable portion of the USB EP Command/Status List address" group.long 0x0C++0x03 line.long 0x00 "DATABUFSTART,USB Data buffer start address" hexmask.long 0x00 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located" group.long 0x10++0x03 line.long 0x00 "LPM,USB Link Power Management register" bitfld.long 0x00 8. "DATA_PENDING,As long as this bit is set to one and LPM supported bit is set to one HW will return a NYET handshake on every LPM token it receives" "0,1" bitfld.long 0x00 4.--7. "HIRD_SW,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 0.--3. "HIRD_HW,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x03 line.long 0x00 "EPSKIP,USB Endpoint skip" hexmask.long.word 0x00 0.--11. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software" group.long 0x18++0x03 line.long 0x00 "EPINUSE,USB Endpoint Buffer in use" hexmask.long.word 0x00 2.--11. 1. "BUF,Buffer in use: This register has one bit per physical endpoint" group.long 0x1C++0x03 line.long 0x00 "EPBUFCFG,USB Endpoint Buffer Configuration register" hexmask.long.word 0x00 2.--11. 1. "BUF_SB,Buffer usage: This register has one bit per physical endpoint" group.long 0x20++0x03 line.long 0x00 "INTSTAT,USB interrupt status register" bitfld.long 0x00 31. "DEV_INT,Device status interrupt" "0,1" bitfld.long 0x00 30. "FRAME_INT,Frame interrupt" "0,1" bitfld.long 0x00 11. "EP5IN,Interrupt status register bit for the EP5 IN direction" "0,1" bitfld.long 0x00 10. "EP5OUT,Interrupt status register bit for the EP5 OUT direction" "0,1" newline bitfld.long 0x00 9. "EP4IN,Interrupt status register bit for the EP4 IN direction" "0,1" bitfld.long 0x00 8. "EP4OUT,Interrupt status register bit for the EP4 OUT direction" "0,1" bitfld.long 0x00 7. "EP3IN,Interrupt status register bit for the EP3 IN direction" "0,1" bitfld.long 0x00 6. "EP3OUT,Interrupt status register bit for the EP3 OUT direction" "0,1" newline bitfld.long 0x00 5. "EP2IN,Interrupt status register bit for the EP2 IN direction" "0,1" bitfld.long 0x00 4. "EP2OUT,Interrupt status register bit for the EP2 OUT direction" "0,1" bitfld.long 0x00 3. "EP1IN,Interrupt status register bit for the EP1 IN direction" "0,1" bitfld.long 0x00 2. "EP1OUT,Interrupt status register bit for the EP1 OUT direction" "0,1" newline bitfld.long 0x00 1. "EP0IN,Interrupt status register bit for the Control EP0 IN direction" "0,1" bitfld.long 0x00 0. "EP0OUT,Interrupt status register bit for the Control EP0 OUT direction" "0,1" group.long 0x24++0x03 line.long 0x00 "INTEN,USB interrupt enable register" bitfld.long 0x00 31. "DEV_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line" "0,1" bitfld.long 0x00 30. "FRAME_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line" "0,1" hexmask.long.word 0x00 0.--11. 1. "EP_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line" group.long 0x28++0x03 line.long 0x00 "INTSETSTAT,USB set interrupt status register" bitfld.long 0x00 31. "DEV_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1" bitfld.long 0x00 30. "FRAME_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1" hexmask.long.word 0x00 0.--11. 1. "EP_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" rgroup.long 0x34++0x03 line.long 0x00 "EPTOGGLE,USB Endpoint toggle register" hexmask.long 0x00 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint" tree.end tree "USBHSH (USB1 High-speed Host Controller)" base ad:0x400A3000 rgroup.long 0x00++0x03 line.long 0x00 "CAPLENGTH_CHIPID,This register contains the offset value towards the start of the operational register space and the version number of the IP block" hexmask.long.word 0x00 16.--31. 1. "CHIPID,Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used" hexmask.long.byte 0x00 0.--7. 1. "CAPLENGTH,Capability Length: This is used as an offset" rgroup.long 0x04++0x03 line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters" bitfld.long 0x00 16. "P_INDICATOR,This bit indicates whether the ports support port indicator control" "0,1" bitfld.long 0x00 4. "PPC,This field indicates whether the host controller implementation includes port power control" "0,1" newline bitfld.long 0x00 0.--3. "N_PORTS,This register specifies the number of physical downstream ports implemented on this host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x08++0x03 line.long 0x00 "HCCPARAMS,Host Controller Capability Parameters" bitfld.long 0x00 17. "LPMC,Link Power Management Capability" "0,1" group.long 0x0C++0x03 line.long 0x00 "FLADJ_FRINDEX,Frame Length Adjustment" hexmask.long.word 0x00 16.--29. 1. "FRINDEX,Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet" bitfld.long 0x00 0.--5. "FLADJ,Frame Length Timing Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "ATLPTD,Memory base address where ATL PTD0 is stored" hexmask.long.tbyte 0x00 9.--31. 1. "ATL_BASE,Base address to be used by the hardware to find the start of the ATL list" bitfld.long 0x00 4.--8. "ATL_CUR,This indicates the current PTD that is used by the hardware when it is processing the ATL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x03 line.long 0x00 "ISOPTD,Memory base address where ISO PTD0 is stored" hexmask.long.tbyte 0x00 10.--31. 1. "ISO_BASE,Base address to be used by the hardware to find the start of the ISO list" bitfld.long 0x00 5.--9. "ISO_FIRST,This indicates the first PTD that is used by the hardware when it is processing the ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x03 line.long 0x00 "INTPTD,Memory base address where INT PTD0 is stored" hexmask.long.tbyte 0x00 10.--31. 1. "INT_BASE,Base address to be used by the hardware to find the start of the INT list" bitfld.long 0x00 5.--9. "INT_FIRST,This indicates the first PTD that is used by the hardware when it is processing the INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C++0x03 line.long 0x00 "DATAPAYLOAD,Memory base address that indicates the start of the data payload buffers" hexmask.long.word 0x00 16.--31. 1. "DAT_BASE,Base address to be used by the hardware to find the start of the data payload section" group.long 0x20++0x03 line.long 0x00 "USBCMD,USB Command register" bitfld.long 0x00 10. "INT_EN,INT List enabled" "0,1" bitfld.long 0x00 9. "ISO_EN,ISO List enabled" "0,1" newline bitfld.long 0x00 8. "ATL_EN,ATL List enabled" "0,1" bitfld.long 0x00 7. "LHCR,Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports" "0,1" newline bitfld.long 0x00 2.--3. "FLS,Frame List Size: This field specifies the size of the frame list" "0,1,2,3" bitfld.long 0x00 1. "HCRESET,Host Controller Reset: This control bit is used by the software to reset the host controller" "0,1" newline bitfld.long 0x00 0. "RS,Run/Stop" "0,1" group.long 0x20++0x03 line.long 0x00 "USBCMD,USB Command register" bitfld.long 0x00 28. "LPM_RWU,bRemoteWake field" "0,1" bitfld.long 0x00 24.--27. "HIRD,Host-Initiated Resume Duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. "INT_EN,INT List enabled" "0,1" bitfld.long 0x00 9. "ISO_EN,ISO List enabled" "0,1" newline bitfld.long 0x00 8. "ATL_EN,ATL List enabled" "0,1" bitfld.long 0x00 7. "LHCR,Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports" "0,1" newline bitfld.long 0x00 2.--3. "FLS,Frame List Size: This field specifies the size of the frame list" "0,1,2,3" bitfld.long 0x00 1. "HCRESET,Host Controller Reset: This control bit is used by the software to reset the host controller" "0,1" newline bitfld.long 0x00 0. "RS,Run/Stop" "0,1" group.long 0x24++0x03 line.long 0x00 "USBSTS,USB Interrupt Status register" bitfld.long 0x00 19. "SOF_IRQ,SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus this bit is set" "0,1" bitfld.long 0x00 18. "INT_IRQ,INT IRQ: Indicates that an INT PTD (with I-bit set) was completed" "0,1" newline bitfld.long 0x00 17. "ISO_IRQ,ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed" "0,1" bitfld.long 0x00 16. "ATL_IRQ,ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed" "0,1" newline bitfld.long 0x00 3. "FLR,Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0" "0,1" bitfld.long 0x00 2. "PCD,Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port" "0,1" group.long 0x28++0x03 line.long 0x00 "USBINTR,USB Interrupt Enable register" bitfld.long 0x00 19. "SOF_E,SOF Interrupt Enable bit" "0: disable,1: enable" bitfld.long 0x00 18. "INT_IRQ_E,INT IRQ Enable bit" "0: disable,1: enable" newline bitfld.long 0x00 17. "ISO_IRQ_E,ISO IRQ Enable bit" "0: disable,1: enable" bitfld.long 0x00 16. "ATL_IRQ_E,ATL IRQ Enable bit" "0: disable,1: enable" newline bitfld.long 0x00 3. "FLRE,Frame List Rollover Interrupt Enable" "0: disable,1: enable" bitfld.long 0x00 2. "PCDE,Port Change Detect Interrupt Enable" "0: disable,1: enable" group.long 0x2C++0x03 line.long 0x00 "PORTSC1,Port Status and Control register" hexmask.long.byte 0x00 25.--31. 1. "DEV_ADD,Device Address for LPM tokens" bitfld.long 0x00 23.--24. "SUS_STAT,These two bits are used by software to determine whether the most recent L1 suspend request was successful" "0: Success-state transition was successful (ACK),1: Not Yet - Device was unable to enter the L1,2: Not supported - Device does not support the L1,3: Timeout/Error - Device failed to respond or an" newline bitfld.long 0x00 22. "WOO,Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events" "0,1" bitfld.long 0x00 20.--21. "PSPD,Port Speed" "0: Low-speed,1: Full-speed,2: High-speed,3: Reserved" newline bitfld.long 0x00 16.--19. "PTC,Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "PIC,Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0" "0,1,2,3" newline bitfld.long 0x00 12. "PP,Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register" "0,1" rbitfld.long 0x00 10.--11. "LS,Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines" "0,1,2,3" newline bitfld.long 0x00 9. "SUS_L1,Suspend using L1" "0: Suspend using L2,1: Suspend using L1 When this bit is set to a 1" bitfld.long 0x00 8. "PR,Port Reset: Logic 1 means the port is in the reset state" "0,1" newline bitfld.long 0x00 7. "SUSP,Suspend: Logic 1 means port is in the suspend state" "0,1" bitfld.long 0x00 6. "FPR,Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port" "0,1" newline bitfld.long 0x00 5. "OCC,Over-current change: Logic 1 means that the value of OCA has changed" "0,1" bitfld.long 0x00 4. "OCA,Over-current active: Logic 1 means that this port has an over-current condition" "0,1" newline bitfld.long 0x00 3. "PEDC,Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed" "0,1" bitfld.long 0x00 2. "PED,Port Enabled/Disabled" "0,1" newline bitfld.long 0x00 1. "CSC,Connect Status Change: Logic 1 means that the value of CCS has changed" "0,1" bitfld.long 0x00 0. "CCS,Current Connect Status: Logic 1 indicates a device is present on the port" "0,1" group.long 0x2C++0x03 line.long 0x00 "PORTSC1,Port Status and Control register" bitfld.long 0x00 22. "WOO,Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events" "0,1" bitfld.long 0x00 20.--21. "PSPD,Port Speed" "0: Low-speed,1: Full-speed,2: High-speed,3: Reserved" newline bitfld.long 0x00 16.--19. "PTC,Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "PIC,Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0" "0,1,2,3" newline bitfld.long 0x00 12. "PP,Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register" "0,1" rbitfld.long 0x00 10.--11. "LS,Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines" "0,1,2,3" newline bitfld.long 0x00 8. "PR,Port Reset: Logic 1 means the port is in the reset state" "0,1" bitfld.long 0x00 7. "SUSP,Suspend: Logic 1 means port is in the suspend state" "0,1" newline bitfld.long 0x00 6. "FPR,Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port" "0,1" bitfld.long 0x00 5. "OCC,Over-current change: Logic 1 means that the value of OCA has changed" "0,1" newline bitfld.long 0x00 4. "OCA,Over-current active: Logic 1 means that this port has an over-current condition" "0,1" bitfld.long 0x00 3. "PEDC,Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed" "0,1" newline bitfld.long 0x00 2. "PED,Port Enabled/Disabled" "0,1" bitfld.long 0x00 1. "CSC,Connect Status Change: Logic 1 means that the value of CCS has changed" "0,1" newline bitfld.long 0x00 0. "CCS,Current Connect Status: Logic 1 indicates a device is present on the port" "0,1" group.long 0x30++0x03 line.long 0x00 "ATLPTDD,Done map for each ATL PTD" hexmask.long 0x00 0.--31. 1. "ATL_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed" group.long 0x34++0x03 line.long 0x00 "ATLPTDS,Skip map for each ATL PTD" hexmask.long 0x00 0.--31. 1. "ATL_SKIP,When a bit in the PTD Skip Map is set to logic 1 the corresponding PTD will be skipped independent of the V bit setting" group.long 0x38++0x03 line.long 0x00 "ISOPTDD,Done map for each ISO PTD" hexmask.long 0x00 0.--31. 1. "ISO_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed" group.long 0x3C++0x03 line.long 0x00 "ISOPTDS,Skip map for each ISO PTD" hexmask.long 0x00 0.--31. 1. "ISO_SKIP,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed" group.long 0x40++0x03 line.long 0x00 "INTPTDD,Done map for each INT PTD" hexmask.long 0x00 0.--31. 1. "INT_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed" group.long 0x44++0x03 line.long 0x00 "INTPTDS,Skip map for each INT PTD" hexmask.long 0x00 0.--31. 1. "INT_SKIP,When a bit in the PTD Skip Map is set to logic 1 the corresponding PTD will be skipped independent of the V bit setting" group.long 0x48++0x03 line.long 0x00 "LASTPTD,Marks the last PTD in the list for ISO INT and ATL" bitfld.long 0x00 16.--20. "INT_LAST,This indicates the last PTD in the INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "ISO_LAST,This indicates the last PTD in the ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "ATL_LAST,If hardware has reached this PTD and the J bit is not set it will go to PTD0 as the next PTD to be processed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x50++0x03 line.long 0x00 "PORTMODE,Controls the port if it is attached to the host block or the device block" bitfld.long 0x00 19. "SW_PDCOM,This bit is only used when SW_CTRL_PDCOM is set to 1b" "0,1" bitfld.long 0x00 18. "SW_CTRL_PDCOM,This bit indicates if the PHY power-down input is controlled by software or by hardware" "0,1" newline bitfld.long 0x00 16. "DEV_ENABLE,If this bit is set to one one of the ports will behave as a USB device" "0,1" tree.end tree "USBPHY (Universal System Bus Physical Layer)" base ad:0x40038000 group.long 0x00++0x03 line.long 0x00 "PWD,USB PHY Power-Down Register" bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.." newline bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.." newline bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.." newline bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.." newline bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.." newline bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.." newline bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers" group.long 0x04++0x03 line.long 0x00 "PWD_SET,USB PHY Power-Down Register" bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.." newline bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.." newline bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.." newline bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.." newline bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.." newline bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.." newline bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers" group.long 0x08++0x03 line.long 0x00 "PWD_CLR,USB PHY Power-Down Register" bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.." newline bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.." newline bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.." newline bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.." newline bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.." newline bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.." newline bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers" group.long 0x0C++0x03 line.long 0x00 "PWD_TOG,USB PHY Power-Down Register" bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.." newline bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.." newline bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.." newline bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.." newline bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.." newline bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.." newline bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers" group.long 0x10++0x03 line.long 0x00 "TX,USB PHY Transmitter Control Register" bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1" newline bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1" newline bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.." group.long 0x14++0x03 line.long 0x00 "TX_SET,USB PHY Transmitter Control Register" bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1" newline bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1" newline bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.." group.long 0x18++0x03 line.long 0x00 "TX_CLR,USB PHY Transmitter Control Register" bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1" newline bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1" newline bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.." group.long 0x1C++0x03 line.long 0x00 "TX_TOG,USB PHY Transmitter Control Register" bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1" newline bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1" newline bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.." group.long 0x20++0x03 line.long 0x00 "RX,USB PHY Receiver Control Register" bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.." newline bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..." newline bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..." group.long 0x24++0x03 line.long 0x00 "RX_SET,USB PHY Receiver Control Register" bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.." newline bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..." newline bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..." group.long 0x28++0x03 line.long 0x00 "RX_CLR,USB PHY Receiver Control Register" bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.." newline bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..." newline bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..." group.long 0x2C++0x03 line.long 0x00 "RX_TOG,USB PHY Receiver Control Register" bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.." newline bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..." newline bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..." group.long 0x30++0x03 line.long 0x00 "CTRL,USB PHY General Control Register" bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1" newline bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1" newline bitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1" newline bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1" newline bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1" newline bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1" newline bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1" newline bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1" newline bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1" newline bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1" newline bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1" newline bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1" newline bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1" newline bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1" newline bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.." newline bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1" newline bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1" newline bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1" group.long 0x34++0x03 line.long 0x00 "CTRL_SET,USB PHY General Control Register" bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1" newline bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1" newline rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1" newline bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1" newline bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1" newline bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1" newline bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1" newline bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1" newline bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1" newline bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1" newline bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1" newline bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1" newline bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1" newline bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1" newline bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.." newline bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1" newline bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1" newline bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1" group.long 0x38++0x03 line.long 0x00 "CTRL_CLR,USB PHY General Control Register" bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1" newline bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1" newline bitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1" newline bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1" newline bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1" newline bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1" newline bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1" newline bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1" newline bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1" newline bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1" newline bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1" newline bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1" newline bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1" newline bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1" newline bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.." newline bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1" newline bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1" newline bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1" group.long 0x3C++0x03 line.long 0x00 "CTRL_TOG,USB PHY General Control Register" bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1" newline bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1" newline bitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1" newline bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1" newline bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1" newline bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1" newline bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1" newline bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1" newline bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1" newline bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1" newline bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1" newline bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1" newline bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1" newline bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1" newline bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1" newline bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1" newline bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1" newline bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.." newline bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1" newline bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1" newline bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1" group.long 0x40++0x03 line.long 0x00 "STATUS,USB PHY Status Register" rbitfld.long 0x00 10. "RESUME_STATUS,Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt" "0,1" newline rbitfld.long 0x00 6. "DEVPLUGIN_STATUS,Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4]" "0: No attachment to a USB host is detected,1: Cable attachment to a USB host is detected" newline rbitfld.long 0x00 3. "HOSTDISCONDETECT_STATUS,Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode" "0: USB cable disconnect has not been detected at..,1: USB cable disconnect has been detected at the.." newline rbitfld.long 0x00 0. "OK_STATUS_3V,Indicates the USB 3v power rails are in range" "0,1" group.long 0xA0++0x03 line.long 0x00 "PLL_SIC,USB PHY PLL Control/Status Register" rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked" newline bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1" newline bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240" newline bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1" newline bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1" newline bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.." newline bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1" newline bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1" newline bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1" group.long 0xA4++0x03 line.long 0x00 "PLL_SIC_SET,USB PHY PLL Control/Status Register" rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked" newline bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1" newline bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240" newline bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1" newline bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1" newline bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.." newline bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1" newline bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1" newline bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1" group.long 0xA8++0x03 line.long 0x00 "PLL_SIC_CLR,USB PHY PLL Control/Status Register" rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked" newline bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1" newline bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240" newline bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1" newline bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1" newline bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.." newline bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1" newline bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1" newline bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1" group.long 0xAC++0x03 line.long 0x00 "PLL_SIC_TOG,USB PHY PLL Control/Status Register" rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked" newline bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1" newline bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240" newline bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1" newline bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1" newline bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.." newline bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1" newline bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1" newline bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1" group.long 0xC0++0x03 line.long 0x00 "USB1_VBUS_DETECT,USB PHY VBUS Detect Control Register" bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled" newline bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1" newline endif bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.." newline bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external VBUS VALID value" newline bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external ID value" newline bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1" newline bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1" newline bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..." newline bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.." newline bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1" newline bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.." newline bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7" group.long 0xC4++0x03 line.long 0x00 "USB1_VBUS_DETECT_SET,USB PHY VBUS Detect Control Register" bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled" newline bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1" newline endif bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.." newline bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external VBUS VALID value" newline bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external ID value" newline bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1" newline bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1" newline bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..." newline bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.." newline bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1" newline bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.." newline bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7" group.long 0xC8++0x03 line.long 0x00 "USB1_VBUS_DETECT_CLR,USB PHY VBUS Detect Control Register" bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled" newline bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1" newline endif bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.." newline bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pin muxed value" "0: Select the muxed value chosen using..,1: Select the external VBUS VALID value" newline bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external ID value" newline bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1" newline bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1" newline bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..." newline bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.." newline bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1" newline bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.." newline bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7" group.long 0xCC++0x03 line.long 0x00 "USB1_VBUS_DETECT_TOG,USB PHY VBUS Detect Control Register" bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled" newline bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)" newline sif cpuis("LPC5526*")||cpuis("LPC5528*") bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1" newline endif bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.." newline bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pin muxed value" "0: Select the Muxed value chosen using..,1: Select the external VBUS VALID value" newline bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pin muxed value" "0: Select the muxed value chosen using..,1: Select the external ID value" newline bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1" newline bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1" newline bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..." newline bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.." newline bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1" newline bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1" newline bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.." newline bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7" rgroup.long 0xD0++0x03 line.long 0x00 "USB1_VBUS_DET_STAT,USB PHY VBUS Detector Status Register" bitfld.long 0x00 4. "VBUS_VALID_3V,VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on the USB1_VBUS pin than either the Session Valid or VBUS_VALID comparators" "0: VBUS voltage is below VBUS_VALID_3V threshold,1: VBUS voltage is above VBUS_VALID_3V threshold" newline bitfld.long 0x00 3. "VBUS_VALID,VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin" "0: VBUS is below the comparator threshold,1: VBUS is above the comparator threshold" newline bitfld.long 0x00 2. "AVALID,A-Device Session Valid status A-Device Session Valid status determined by the Session Valid comparator" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.." newline bitfld.long 0x00 1. "BVALID,B-Device Session Valid status B-Device Session Valid status determined by the Session Valid comparator" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.." newline bitfld.long 0x00 0. "SESSEND,Session End indicator Session End status value inverted from Session Valid comparator" "0: The VBUS voltage is above the Session Valid..,1: The VBUS voltage is below the Session Valid.." group.long 0x100++0x03 line.long 0x00 "ANACTRL,USB PHY Analog Control Register" bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.." newline bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3" newline bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1" group.long 0x104++0x03 line.long 0x00 "ANACTRL_SET,USB PHY Analog Control Register" bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.." newline bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3" newline bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1" group.long 0x108++0x03 line.long 0x00 "ANACTRL_CLR,USB PHY Analog Control Register" bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.." newline bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3" newline bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1" group.long 0x10C++0x03 line.long 0x00 "ANACTRL_TOG,USB PHY Analog Control Register" bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.." newline bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3" newline bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1" tree.end endif tree "UTICK" base ad:0x4000E000 group.long 0x00++0x03 line.long 0x00 "CTRL,Control" bitfld.long 0x00 31. "REPEAT,Repeat delay" "0: One-time delay,1: Delay repeats continuously" hexmask.long 0x00 0.--30. 1. "DELAYVAL,Tick interval" group.long 0x04++0x03 line.long 0x00 "STAT,Status" bitfld.long 0x00 1. "ACTIVE,Timer active flag" "0: The Micro-Tick Timer is not active (stopped),1: The Micro-Tick Timer is currently active" bitfld.long 0x00 0. "INTR,Interrupt flag" "0: No interrupt is pending,1: An interrupt is pending" group.long 0x08++0x03 line.long 0x00 "CFG,Capture Configuration" bitfld.long 0x00 11. "CAPPOL3,Capture Polarity 3" "0: CAPPOL3POSEDGECAPTURE,1: CAPPOL3NEGEDGECAPTURE" bitfld.long 0x00 10. "CAPPOL2,Capture Polarity 2" "0: CAPPOL2POSEDGECAPTURE,1: CAPPOL2NEGEDGECAPTURE" newline bitfld.long 0x00 9. "CAPPOL1,Capture Polarity 1" "0: CAPPOL1POSEDGECAPTURE,1: CAPPOL1NEGEDGECAPTURE" bitfld.long 0x00 8. "CAPPOL0,Capture Polarity 0" "0: CAPPOL0POSEDGECAPTURE,1: CAPPOL0NEGEDGECAPTURE" newline bitfld.long 0x00 3. "CAPEN3,Enable Capture 3" "0: CAPEN3ISDISABLED,1: CAPEN3ISENABLED" bitfld.long 0x00 2. "CAPEN2,Enable Capture 2" "0: CAPEN2ISDISABLED,1: CAPEN2ISENABLED" newline bitfld.long 0x00 1. "CAPEN1,Enable Capture 1" "0: CAPEN1ISDISABLED,1: CAPEN1ISENABLED" bitfld.long 0x00 0. "CAPEN0,Enable Capture 0" "0: CAPEN0ISDISABLED,1: CAPEN0ISENABLED" wgroup.long 0x0C++0x03 line.long 0x00 "CAPCLR,Capture Clear" bitfld.long 0x00 3. "CAPCLR3,Clear capture 3" "0: CAPCLR3NOTHING,1: Write 1 to clear the CAP3 register value" bitfld.long 0x00 2. "CAPCLR2,Clear capture 2" "0: CAPCLR2NOTHING,1: Write 1 to clear the CAP2 register value" newline bitfld.long 0x00 1. "CAPCLR1,Clear capture 1" "0: CAPCLR1NOTHING,1: Write 1 to clear the CAP1 register value" bitfld.long 0x00 0. "CAPCLR0,Clear capture 0" "0: CAPCLR0NOTHING,1: Write 1 to clear the CAP0 register value" repeat 4. (increment 0 1) (increment 0 0x4) rgroup.long ($2+0x10)++0x03 line.long 0x00 "CAP[$1],Capture $1" bitfld.long 0x00 31. "VALID,Captured value is valid" "0: A valid value has been not been captured,1: A valid value has been captured based on a.." hexmask.long 0x00 0.--30. 1. "CAP_VALUE,Captured value for the related capture event" repeat.end tree.end sif cpuis("LPC5534*")||cpuis("LPC5536*") tree "VREF" base ad:0x400B5000 rgroup.long 0x00++0x03 line.long 0x00 "VERID,VREF Version ID" hexmask.long.byte 0x00 24.--31. 1. "MAJOR,MAJOR" hexmask.long.byte 0x00 16.--23. 1. "MINOR,MINOR" newline hexmask.long.word 0x00 0.--15. 1. "FEATURE,FEATURE" rgroup.long 0x04++0x03 line.long 0x00 "PARAM,VREF Parameter" group.long 0x08++0x03 line.long 0x00 "CSR,VREF Control and Status Register" rbitfld.long 0x00 31. "VREFST,Internal HC Voltage Reference stable" "0: The module is disabled or not stable,1: The module is stable" bitfld.long 0x00 16. "Buf21EN,Internal buf21 Enable" "0: buf21 is disabled,1: buf21 is enabled" newline bitfld.long 0x00 11. "HI_PWR_LV,Buffer21 mode control" "0,1" bitfld.long 0x00 10. "REFL_GRD_SEL,Bit for the ground select" "0: REFL_GRD_SEL_0,1: REFL_GRD_SEL_1" newline bitfld.long 0x00 8.--9. "VRSEL,Control bits for voltage reference selection" "0: Internal bandgap,1: Low power buffered 1v,2: Buffer 2.1v output,?..." bitfld.long 0x00 7. "REFCHSELP_EN,Positive channel to ADC select enable" "0: REFCHSELP_EN_0,1: REFCHSELP_EN_1" newline bitfld.long 0x00 6. "REFCHSELN_EN,Negative channel to ADC select enable" "0: REFCHSELN_EN_0,1: REFCHSELN_EN_1" bitfld.long 0x00 5. "REGEN,Regulator enable" "0: Internal 1.75 V regulator is disabled,1: Internal 1.75 V regulator is enabled" newline bitfld.long 0x00 4. "ICOMPEN,Second order curvature compensation enable" "0: ICOMPEN_0,1: ICOMPEN_1" bitfld.long 0x00 3. "CHOPEN,Chop oscillator enable" "0: Chop oscillator is disabled,1: Chop oscillator is enabled" newline bitfld.long 0x00 2. "LPBG_BUF_EN,Low power buffer enable for lpbg with latch function enable" "0: LPBG_BUF_EN_0,1: LPBG_BUF_EN_1" bitfld.long 0x00 1. "LPBGEN,Low Power Bandgap enable" "0: LP Bandgap is disabled,1: LP Bandgap is enabled" newline bitfld.long 0x00 0. "HCBGEN,HC Bandgap enabled" "0: HC Bandgap is disabled,1: HC Bandgap is enabled" group.long 0x10++0x03 line.long 0x00 "UTRIM,VREF User Trim" bitfld.long 0x00 8.--13. "VREFTRIM,VREF Trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. "TRIM2V1,VREF 2.1V Trim Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "TEST_UNLOCK,Unlock test registers" hexmask.long.word 0x00 1.--15. 1. "test_unlock_value,Test unlock value" rbitfld.long 0x00 0. "test_unlock,Test_unlock status bit" "0: Lock read/write into test register,1: Unlock read/write into test register" group.long 0x24++0x03 line.long 0x00 "TRIM0,VREF Test Trim 0" bitfld.long 0x00 31. "FLIP,Amplifier Polarity" "0,1" bitfld.long 0x00 24.--27. "P7_TRIM,P7_TRIM" "0: VREF 2.1V is enabled,1: VREF 2.1V is disabled,?..." newline bitfld.long 0x00 16.--19. "CHOPOSCTRIM,CHOPOSCTRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13.--15. "BPMSB,BPMSB" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--11. "BPLSB,BPLSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--7. "COMPMSB,COMPMSB" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "COMPLSB,COMPLSB" "0,1,2,3,4,5,6,7" group.long 0x28++0x03 line.long 0x00 "TRIM1,VREF Test Trim 1" bitfld.long 0x00 16.--18. "IREF_TRIM,IREF_TRIM" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "LP_TCTRIM,LP_TCTRIM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--4. "LP_VTRIM,LP Bandgap Voltage Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end endif tree "WWDT" base ad:0x4000C000 group.long 0x00++0x03 line.long 0x00 "MOD,Mode" bitfld.long 0x00 5. "LOCK,Lock" "0: NO_LOCK,1: LOCK" bitfld.long 0x00 4. "WDPROTECT,Watchdog Update Mode" "0: FLEXIBLE,1: THRESHOLD" eventfld.long 0x00 3. "WDINT,Warning Interrupt Flag" "0: No flag,1: Flag" bitfld.long 0x00 2. "WDTOF,Watchdog Timeout Flag" "0: Clear,1: Reset" bitfld.long 0x00 1. "WDRESET,Watchdog Reset Enable" "0: Interrupt,1: Reset" bitfld.long 0x00 0. "WDEN,Watchdog Enable" "0: Stop,1: Run" group.long 0x04++0x03 line.long 0x00 "TC,Timer Constant" hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Watchdog Timeout Value" wgroup.long 0x08++0x03 line.long 0x00 "FEED,Feed Sequence" hexmask.long.byte 0x00 0.--7. 1. "FEED,Feed Value" rgroup.long 0x0C++0x03 line.long 0x00 "TV,Timer Value" hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Counter Timer Value" group.long 0x14++0x03 line.long 0x00 "WARNINT,Warning Interrupt Compare Value" hexmask.long.word 0x00 0.--9. 1. "WARNINT,Watchdog Warning Interrupt Compare Value" group.long 0x18++0x03 line.long 0x00 "WINDOW,Window Compare Value" hexmask.long.tbyte 0x00 0.--23. 1. "WINDOW,Watchdog Window Value" tree.end autoindent.off newline