; --------------------------------------------------------------------------------
; @Title: LPC55Sxx On-Chip Peripherals
; @Props: Released
; @Author: JAM, RSA, KRZ
; @Changelog: 2019-05-27 JAM
;             2022-02-18 RSA
;             2023-01-31 KRZ
; @Manufacturer: NXP - NXP Semiconductors
; @Doc: SVD generated (SVD2PER 1.8.6), based on:
;       LPC55S04.svd (Ver. 1.0), LPC55S06.svd (Ver. 1.0), LPC55S14.svd (Ver. 1.0),
;       LPC55S16.svd (Ver. 1.0), LPC55S26.svd (Ver. 1.0), LPC55S28.svd (Ver. 1.0),
;       LPC55S66_cm33_core0.svd (Ver. 1.0), LPC55S69_cm33_core0.svd (Ver. 1.0)
; @Core: Cortex-M33 / Cortex-M33F
; @Chip: LPC55S04JBD64, LPC55S04JHI48, LPC55S06JBD64, LPC55S06JHI48,
;        LPC55S14JBD100, LPC55S14JBD64, LPC55S16JBD100, LPC55S16JBD64,
;        LPC55S16JEV98, LPC55S26JBD100, LPC55S26JBD64, LPC55S26JEV98,
;        LPC55S28JBD100, LPC55S28JBD64, LPC55S28JEV98, LPC55S66JBD100-CPU0,
;        LPC55S66JBD100-CPU1, LPC55S66JBD64-CPU0, LPC55S66JBD64-CPU1,
;        LPC55S66JEV98-CPU0, LPC55S66JEV98-CPU1, LPC55S69JBD100-CPU0,
;        LPC55S69JBD100-CPU1, LPC55S69JBD64-CPU0, LPC55S69JBD64-CPU1,
;        LPC55S69JEV98-CPU0, LPC55S69JEV98-CPU1
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perlpc55sxx.per 15702 2023-01-31 17:03:57Z kwisniewski $

sif (CORENAME()=="CORTEXM33F")
tree.close "Core Registers (Cortex-M33F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL      ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. "              DISITMATBFLUSH    ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. "            FPEXCODIS      ,Disables FPU exception outputs" "No,Yes"
textline "                     "
bitfld.long 0x00 9. " DISOOFP         ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD           ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. "            DISMCYCINT     ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10           ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. "      SU10              ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. "  SUS7           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 14. " SU7             ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. "    SUS6              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. "    SU6            ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline "                     "
bitfld.long 0x00 11. " SUS5            ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. "      SU5               ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. "  SUS4           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 8. " SU4             ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. "    SUS3              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. "    SU3            ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline "                     "
bitfld.long 0x00 5. " SUS2            ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. "      SU2               ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. "  SUS1           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 2. " SU1             ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. "    SUS0              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. "    SU0            ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG       ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. "      CLKSOURCE         ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. "       TICKINT        ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x04 0. " ENABLE          ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD          ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT         ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF           ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW              ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "        TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER     ,Indicates implementer"
bitfld.long 0x00 20.--23. "               VARIANT           ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "     ARCHITECTURE   ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO          ,Indicates part number"
bitfld.long 0x00 0.--3. "             REVISION          ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET      , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. "      PENDSVSET         , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. "    PENDSTSET      ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline "                     "
bitfld.long 0x00 24. " STTNS           ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. "       ISRPREEMPT        ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. "       ISRPENDING     ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline "                     "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING     ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. "             RETTOBASE         ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. "        VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF          ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT     ,Vector Key"
rbitfld.long 0x08 15. "             ENDIANNESS        ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. "  PRIS           ,Prioritize Secure exceptions" "Disabled,Enabled"
textline "                     "
bitfld.long 0x08 13. " BFHFNMINS       ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. "         PRIGROUP          ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. "    SYSRESETREQS   ,System reset request Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ     ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. "    VECTCLRACTIVE     ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND       ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. "       SLEEPDEEPS        ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. "    SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                     "
bitfld.long 0x0C 1. " SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP              ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "         IC                ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "       DC             ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 10. " STKOFHFNMIGN    ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. "      BFHFNMIGN         ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. "    DIV_0_TRP      ,Controls the trap on divide by 0" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP     ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. "         USERSETMPEND      ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7           ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. "               PRI_6             ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. "             PRI_5          ,Priority of system handler 5, BusFault"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4           ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11          ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15          ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. "               PRI_14            ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. "             PRI_12         ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. "      SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. "    SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 18. " USGFAULTENA     ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. "         BUSFAULTENA       ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. "       MEMFAULTENA    ,MemManage exception enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED    ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. "      BUSFAULTPENDED    ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. "    MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED  ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. "      SYSTICKACT        ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. "     PENDSVACT      ,PendSV exception status" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT      ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. "       SVCALLACT         ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. "     NMIACT         ,NMI exception status" "Not active,Active"
textline "                     "
bitfld.long 0x20 4. " SECUREFAULTACT  ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT       ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. "     HARDFAULTACT   ,HardFault exception status for the selected Security state" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT     ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. "       MEMFAULTACT       ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID       ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "        MLSPERR           ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "   MSTKERR        ,Stacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR       ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "     DACCVIOL          ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "   IACCVIOL       ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID       ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "        LSPERR            ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "   STKERR         ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR        ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "     IMPRECISERR       ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "   PRECISERR      ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR         ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. "     DIVBYZERO       ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. "         UNALIGNED         ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. "       STKOF          ,Stack overflow error" "No error,Error"
textline "                     "
eventfld.word 0x00 3. " NOCP            ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. "         INVPC             ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. "       INVSTATE       , Invalid Combination of EPSR and Instruction" "No error,Error"
textline "                     "
eventfld.word 0x00 0. " UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT        ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "     FORCED            ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. "   VECTTBL        ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10            ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. "       CP7               ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 12.--13. " CP6             ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. "       CP5               ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. "     CP4            ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 6.--7. " CP3             ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. "       CP2               ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. "     CP1            ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 0.--1. " CP0             ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11            ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. "         CP10              ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. "       CP7            ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " CP6             ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. "         CP5               ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. "       CP4            ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " CP3             ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. "         CP2               ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. "       CP1            ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 0. " CP0             ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID           ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB      ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. "  LOU      ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. "        LOC           ,Level of Coherency" "Level 1,Level 2,?..."
textline "                   "
bitfld.long 0x00 18.--20. " CL7      ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. "   CL6      ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. "       CL5           ,Cache type field level 5" "No cache,?..."
textline "                   "
bitfld.long 0x00 9.--11. " CL4      ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. "          CL3      ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. "       CL2           ,Cache type field level 2" "No cache,?..."
textline "                   "
bitfld.long 0x00 0.--2. " CL1      ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT   ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. "          CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. "              ERG           ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline "                   "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT   ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "     WB       ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. "  RA            ,Indicates support available for read allocation" "Not supported,Supported"
textline "                   "
bitfld.long 0x00 28. " WA       ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. "     NUMSETS  ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline "                   "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. "           IND      ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "                    STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. "                      SECURITY       ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG  ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. "                TCM            ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "                PMSASUP        ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT   ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. "                CMAINTSW       ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. "        CMAINTVA  ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "                DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "                BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. "                IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x00 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. "         MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline "                   "
bitfld.long 0x00 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. "                MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. "                THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "                SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline "                   "
bitfld.long 0x00 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. "                SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. "            BARRIER   ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. "                WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. "           UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT       ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION    ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "         SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "   HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "   ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. "  ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. "  ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. "  ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. "  ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. "  ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. "  ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. "  ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. "  ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS   ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. "  ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR   ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. "  SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. "    LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline "                        "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. "  AUVIOL    ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER  ,Invalid exception return flag" "Not occurred,Occurred"
textline "                        "
bitfld.long 0x00 1. " INVIS   ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. "  INVEP     ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31  ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS30  ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS29  ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS28  ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS27  ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS26  ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS25  ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS24  ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS23  ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS22  ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS21  ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS20  ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS19  ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS18  ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS17  ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS16  ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS15  ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS14  ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS13  ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS12  ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS11  ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS10  ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS9   ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS8   ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS7   ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS6   ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS5   ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS4   ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS3   ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS2   ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS1   ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS0   ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63  ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS62  ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS61  ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS60  ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS59  ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS58  ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS57  ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS56  ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS55  ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS54  ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS53  ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS52  ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS51  ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS50  ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS49  ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS48  ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS47  ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS46  ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS45  ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS44  ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS43  ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS42  ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS41  ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS40  ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS39  ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS38  ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS37  ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS36  ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS35  ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS34  ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS33  ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS32  ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95  ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS94  ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS93  ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS92  ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS91  ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS90  ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS89  ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS88  ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS87  ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS86  ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS85  ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS84  ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS83  ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS82  ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS81  ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS80  ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS79  ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS78  ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS77  ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS76  ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS75  ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS74  ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS73  ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS72  ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS71  ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS70  ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS69  ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS68  ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS67  ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS66  ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS65  ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS64  ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS99  ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS98  ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS97  ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS96  ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN     ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. "       LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET     ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. "                      CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. "    TS     ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. "                      SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. "           MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. "                      BFRDY     ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "       MMRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. "                      THREAD    ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. "        S      ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER         ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "                  LSPACT    ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN        ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ     ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. "                 SQRROOT   ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. "      DIV    ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC      ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. "                 SNGLPREC  ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "      A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP   ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE  ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC     ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL   ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "         DWTTRAP      ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT       ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR     ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA     ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. "       SDME       ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. "            MON_REQ      ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND   ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. "              VC_SFERR     ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR  ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "              VC_STATERR   ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. "       VC_CHKERR  ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. "              VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA     ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. "       SDME       ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. "            MON_REQ      ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND   ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. "              VC_SFERR     ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR  ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "              VC_STATERR   ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. "       VC_CHKERR  ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. "              VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. "       SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. "  INTSPIDEN    ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. "       SPIDENSEL  ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS        ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. "     SBRSEL     ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. "            SBRSELEN     ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI        ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. "    SNE        ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. "                     SI           ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. "    SE         ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI       ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. "    NSNE       ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. "                     NSI          ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. "    NSE        ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV    ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "      NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. "         NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 1. " KEY    ,Key Field" "Low,High"
bitfld.long 0x00 0. "           ENABLE   ,Flash Patch Unit Enable" "Disabled,Enabled"
textline "                     "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 "  REMAP    ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB           ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. "           MAJOR          ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT       ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP    ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. "                     NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. "              NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline "                         "
rbitfld.long 0x00 24. " NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. "         CYCDISS    ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. "                        CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "              LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "                   SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 18. " EXCEVTENA  ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "              CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "                   EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "              SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "                 CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                         "
bitfld.long 0x00 5.--8. " POSTINIT   ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "                    POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "                         CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT     ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT     ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT   ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT     ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT    ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                         "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. "                            PRESENT        ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB           ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. "           MAJOR          ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
elif (CORENAME()=="CORTEXM33")
tree.close "Core Registers (Cortex-M33)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 29. " EXTEXCLALL      ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
bitfld.long 0x00 12. "              DISITMATBFLUSH    ,Disables ITM and DWT ATB flush" "No,Yes"
bitfld.long 0x00 10. "            FPEXCODIS      ,Disables FPU exception outputs" "No,Yes"
textline "                     "
bitfld.long 0x00 9. " DISOOFP         ,Disables floating-point" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD           ,Disables dual-issue functionality" "No,Yes"
bitfld.long 0x00 0. "            DISMCYCINT     ,Disables interruption of multi-cycle" "No,Yes"
group.long 0x0C++0x0F
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 21. " SUS10           ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 20. "      SU10              ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 15. "  SUS7           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 14. " SU7             ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 13. "    SUS6              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 12. "    SU6            ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline "                     "
bitfld.long 0x00 11. " SUS5            ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 10. "      SU5               ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 9. "  SUS4           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 8. " SU4             ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 7. "    SUS3              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 6. "    SU3            ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
textline "                     "
bitfld.long 0x00 5. " SUS2            ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 4. "      SU2               ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 3. "  SUS1           ,State unknown Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x00 2. " SU1             ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
bitfld.long 0x00 1. "    SUS0              ,State unknown Secure only" "Both states,Secure only"
bitfld.long 0x00 0. "    SU0            ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x04 16. " COUNTFLAG       ,Counter Flag" "Not counted,Counted"
bitfld.long 0x04 2. "      CLKSOURCE         ,SysTick clock source" "External,Core"
bitfld.long 0x04 1. "       TICKINT        ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x04 0. " ENABLE          ,Counter Enable" "Disabled,Enabled"
line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD          ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x0C "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT         ,Current counter value"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
bitfld.long 0x00 31. " NOREF           ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW              ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "        TENMS          ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER     ,Indicates implementer"
bitfld.long 0x00 20.--23. "               VARIANT           ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "     ARCHITECTURE   ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO          ,Indicates part number"
bitfld.long 0x00 0.--3. "             REVISION          ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control and State Register"
setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET      , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x00 27. "      PENDSVSET         , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x00 25. "    PENDSTSET      ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
textline "                     "
bitfld.long 0x00 24. " STTNS           ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
rbitfld.long 0x00 23. "       ISRPREEMPT        ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
rbitfld.long 0x00 22. "       ISRPENDING     ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
textline "                     "
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING     ,The exception number of the highest priority pending and enabled interrupt"
rbitfld.long 0x00 11. "             RETTOBASE         ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
hexmask.long.word 0x00 0.--8. 1. "        VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF          ,Bits[31:7] of the vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT     ,Vector Key"
rbitfld.long 0x08 15. "             ENDIANNESS        ,Indicates the memory system endianness" "Little endian,Big endian"
bitfld.long 0x08 14. "  PRIS           ,Prioritize Secure exceptions" "Disabled,Enabled"
textline "                     "
bitfld.long 0x08 13. " BFHFNMINS       ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
bitfld.long 0x08 8.--10. "         PRIGROUP          ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
bitfld.long 0x08 3. "    SYSRESETREQS   ,System reset request Secure only" "Both states,Secure only"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ     ,System reset request" "Not requested,Requested"
bitfld.long 0x08 1. "    VECTCLRACTIVE     ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND       ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 3. "       SLEEPDEEPS        ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
bitfld.long 0x0C 2. "    SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                     "
bitfld.long 0x0C 1. " SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration and Control Register"
bitfld.long 0x10 18. " BP              ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "         IC                ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "       DC             ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 10. " STKOFHFNMIGN    ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 8. "      BFHFNMIGN         ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
bitfld.long 0x10 4. "    DIV_0_TRP      ,Controls the trap on divide by 0" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP     ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
bitfld.long 0x10 1. "         USERSETMPEND      ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
line.long 0x14 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7           ,Priority of system handler 7, SecureFault"
hexmask.long.byte 0x14 16.--23. 1. "               PRI_6             ,Priority of system handler 6, UsageFault"
hexmask.long.byte 0x14 8.--15. 1. "             PRI_5          ,Priority of system handler 5, BusFault"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4           ,Priority of system handler 4, MemManage"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11          ,Priority of system handler 11, SVCall"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15          ,Priority of system handler 15, SysTick"
hexmask.long.byte 0x1C 16.--23. 1. "               PRI_14            ,Priority of system handler 14, PendSV"
hexmask.long.byte 0x1C 0.--7. 1. "             PRI_12         ,Priority of system handler 12, DebugMonitor"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
bitfld.long 0x20 20. "      SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
bitfld.long 0x20 19. "    SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 18. " USGFAULTENA     ,UsageFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 17. "         BUSFAULTENA       ,BusFault exception enable" "Disabled,Enabled"
bitfld.long 0x20 16. "       MEMFAULTENA    ,MemManage exception enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED    ,SVCall exception status" "Not pending,Pending"
bitfld.long 0x20 14. "      BUSFAULTPENDED    ,BusFault exception status" "Not pending,Pending"
bitfld.long 0x20 13. "    MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED  ,UsageFault exception status" "Not pending,Pending"
bitfld.long 0x20 11. "      SYSTICKACT        ,SysTick exception status" "Not active,Active"
bitfld.long 0x20 10. "     PENDSVACT      ,PendSV exception status" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT      ,Monitor exception status" "Not active,Active"
bitfld.long 0x20 7. "       SVCALLACT         ,SVCall exception status" "Not active,Active"
bitfld.long 0x20 5. "     NMIACT         ,NMI exception status" "Not active,Active"
textline "                     "
bitfld.long 0x20 4. " SECUREFAULTACT  ,SecureFault exception status" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT       ,UsageFault exception status" "Not active,Active"
bitfld.long 0x20 2. "     HARDFAULTACT   ,HardFault exception status for the selected Security state" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT     ,BusFault exception status" "Not active,Active"
bitfld.long 0x20 0. "       MEMFAULTACT       ,MemManage exception status" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID       ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "        MLSPERR           ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "   MSTKERR        ,Stacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR       ,Unstacking Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "     DACCVIOL          ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "   IACCVIOL       ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID       ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "        LSPERR            ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "   STKERR         ,Derived bus fault (exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR        ,Derived bus fault (exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "     IMPRECISERR       ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "   PRECISERR      ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR         ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "UFSR,Usage Fault Status Register"
eventfld.word 0x00 9. "     DIVBYZERO       ,Divide by zero error" "No error,Error"
eventfld.word 0x00 8. "         UNALIGNED         ,Unaligned access error" "No error,Error"
eventfld.word 0x00 4. "       STKOF          ,Stack overflow error" "No error,Error"
textline "                     "
eventfld.word 0x00 3. " NOCP            ,A coprocessor access error" "No error,Error"
eventfld.word 0x00 2. "         INVPC             ,An integrity check error" "No error,Error"
eventfld.word 0x00 1. "       INVSTATE       , Invalid Combination of EPSR and Instruction" "No error,Error"
textline "                     "
eventfld.word 0x00 0. " UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x03
line.long 0x00 "HFSR,HardFault Status Register"
bitfld.long 0x00 31. " DEBUGEVT        ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "     FORCED            ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
bitfld.long 0x00 1. "   VECTTBL        ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 20.--21. " CP10            ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
bitfld.long 0x00 14.--15. "       CP7               ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 12.--13. " CP6             ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
bitfld.long 0x00 10.--11. "       CP5               ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
bitfld.long 0x00 8.--9. "     CP4            ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 6.--7. " CP3             ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
bitfld.long 0x00 4.--5. "       CP2               ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
bitfld.long 0x00 2.--3. "     CP1            ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
textline "                     "
bitfld.long 0x00 0.--1. " CP0             ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
group.long 0xD8C++0x03
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 11. " CP11            ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
bitfld.long 0x00 10. "         CP10              ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
bitfld.long 0x00 7. "       CP7            ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " CP6             ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
bitfld.long 0x00 5. "         CP5               ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
bitfld.long 0x00 4. "       CP4            ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " CP3             ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
bitfld.long 0x00 2. "         CP2               ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
bitfld.long 0x00 1. "       CP1            ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 0. " CP0             ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
else
hgroup.long 0xD8C++0x03
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
endif
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Triggered Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID           ,Indicates the interrupt to be pended"
tree "Memory System"
width 10.
rgroup.long 0xD78++0x03
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. " ICB      ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
bitfld.long 0x00 27.--29. "  LOU      ,LOUU" "Level 1,Level 2,?..."
bitfld.long 0x00 24.--26. "        LOC           ,Level of Coherency" "Level 1,Level 2,?..."
textline "                   "
bitfld.long 0x00 18.--20. " CL7      ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
bitfld.long 0x00 15.--17. "   CL6      ,Cache type field level 6" "No cache,?..."
bitfld.long 0x00 12.--14. "       CL5           ,Cache type field level 5" "No cache,?..."
textline "                   "
bitfld.long 0x00 9.--11. " CL4      ,Cache type field level 4" "No cache,?..."
bitfld.long 0x00 6.--8. "          CL3      ,Cache type field level 3" "No cache,?..."
bitfld.long 0x00 3.--5. "       CL2           ,Cache type field level 2" "No cache,?..."
textline "                   "
bitfld.long 0x00 0.--2. " CL1      ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT   ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
bitfld.long 0x00 24.--27. "          CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
bitfld.long 0x00 20.--23. "              ERG           ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
textline "                   "
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "                IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
rgroup.long 0xD7C++0x03
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 29.--31. " FORMAT   ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
endif
rgroup.long 0xD80++0x03
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Indicates support available for Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "     WB       ,Indicates support available for Write-Back" "Not supported,Supported"
bitfld.long 0x00 29. "  RA            ,Indicates support available for read allocation" "Not supported,Supported"
textline "                   "
bitfld.long 0x00 28. " WA       ,Indicates support available for write allocation" "Not supported,Supported"
hexmask.long.word 0x00 13.--27. 1. "     NUMSETS  ,Indicates the number of sets as (number of sets) - 1"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
textline "                   "
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
group.long 0xD84++0x03
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
bitfld.long 0x00 0. "           IND      ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
wgroup.long 0xF50++0x03
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
wgroup.long 0xF58++0x23
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
hexmask.long 0x08 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x08 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
hexmask.long 0x14 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x14 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
hexmask.long 0x1C 4.--31. 1. " SETWAY   ,Defines number of the way to operate on and number of the set to operate on"
bitfld.long 0x1C 1.--3. "          LEVEL    ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
tree.end
tree "Feature Registers"
width 10.
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,T32 instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "                    STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
bitfld.long 0x04 4.--7. "                      SECURITY       ,Security support" "Not implemented,Implemented,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " MPROFDBG  ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
rgroup.long 0xD4C++0x03
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. "                TCM            ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "                PMSASUP        ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
rgroup.long 0xD54++0x03
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD5C++0x03
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 8.--11. " BPMAINT   ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. "                CMAINTSW       ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
bitfld.long 0x00 0.--3. "        CMAINTVA  ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
rgroup.long 0xD60++0x03
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "                DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "                BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
rgroup.long 0xD64++0x03
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x00 20.--23. "                IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x00 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x00 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
rgroup.long 0xD68++0x03
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x00 20.--23. "         MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x00 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
textline "                   "
bitfld.long 0x00 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
bitfld.long 0x00 8.--11. "                MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x00 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
rgroup.long 0xD6C++0x03
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x00 20.--23. "                THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x00 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "                SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x00 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
textline "                   "
bitfld.long 0x00 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
rgroup.long 0xD70++0x03
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
bitfld.long 0x00 20.--23. "                SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
bitfld.long 0x00 16.--19. "            BARRIER   ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x00 4.--7. "                WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
bitfld.long 0x00 0.--3. "           UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
tree.end
tree "CoreSight Identification Registers"
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 11.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                    "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT       ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "DPIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DPIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DPIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DPIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "DCIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "DCIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "DCIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. " DREGION    ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "         SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "   HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "   ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
bitfld.long 0x00 3.--4. "       SH       ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
bitfld.long 0x00 1.--2. "     AP  ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
textline "                   "
bitfld.long 0x00 0. "      XN         ,Defines whether code can be executed from this region" "Execute,Not Execute"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
hexmask.long 0x00 5.--31. 0x20 " LIMIT      ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
bitfld.long 0x00 1.--3. "       ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "                   EN  ,Enable" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
textline "                   "
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
endif
tree.end
newline
group.long 0xDC0++0x07
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 24.--27. "  ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 16.--19. "  ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 8.--11. "  ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x00 0.--3. "  ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 24.--27. "  ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 16.--19. "  ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 8.--11. "  ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
newline
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
bitfld.long 0x04 0.--3. "  ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Security Attribution Unit (SAU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
group.long 0xDD0++0x03
line.long 0x00 "SAU_CTRL,SAU Control Register"
bitfld.long 0x00 1. " ALLNS   ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
bitfld.long 0x00 0. "  ENABLE ,Enables the SAU" "Disabled,Enabled"
rgroup.long 0xDD4++0x03
line.long 0x00 "SAU_TYPE,SAU Type Register"
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xDD8++0x03
line.long 0x00 "SAU_RNR,SAU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
tree.close "SAU regions"
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
group.long 0xDDC++0x03 "Region 0"
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
group.long 0xDDC++0x03 "Region 1"
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
group.long 0xDDC++0x03 "Region 2"
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
group.long 0xDDC++0x03 "Region 3"
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
group.long 0xDDC++0x03 "Region 4"
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
group.long 0xDDC++0x03 "Region 5"
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
group.long 0xDDC++0x03 "Region 6"
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
endif
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
group.long 0xDDC++0x03 "Region 7"
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR    ,Base address of the region"
group.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " LADDR   ,Holds bits [31:5] of the limit address for the selected SAU region"
bitfld.long 0x00 1. "  NSC    ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
bitfld.long 0x00 0. "  ENABLE ,SAU region enable" "Disabled,Enabled"
else
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
else
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x0
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x1
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x2
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x3
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x4
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x5
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x6
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
hgroup.long 0xDE0++0x03
saveout 0xDD8 %l 0x7
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
endif
tree.end
group.long 0xDE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. " LSERR   ,Lazy state error flag" "Not occurred,Occurred"
bitfld.long 0x00 6. "  SFARVALID ,Secure fault address valid" "Not valid,Valid"
bitfld.long 0x00 5. "    LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
textline "                        "
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
bitfld.long 0x00 3. "  AUVIOL    ,Attribution unit violation flag" "Not occurred,Occurred"
bitfld.long 0x00 2. " INVER  ,Invalid exception return flag" "Not occurred,Occurred"
textline "                        "
bitfld.long 0x00 1. " INVIS   ,Invalid integrity signature flag" "Not occurred,Occurred"
bitfld.long 0x00 0. "  INVEP     ,Invalid entry point" "Not occurred,Occurred"
group.long 0xDE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
group.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
width 24.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x104++0x03
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x104++0x03
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x108++0x03
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x108++0x03
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x10C++0x03
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x10C++0x03
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x110++0x03
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x110++0x03
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x114++0x03
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x114++0x03
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x118++0x03
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x118++0x03
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x11C++0x03
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x11C++0x03
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x120++0x03
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x120++0x03
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x124++0x03
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x124++0x03
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x128++0x03
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x128++0x03
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x12C++0x03
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x12C++0x03
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x130++0x03
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x130++0x03
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x134++0x03
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x134++0x03
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x138++0x03
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x138++0x03
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x13C++0x03
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x13C++0x03
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
width 24.
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x204++0x03
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x204++0x03
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x208++0x03
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x208++0x03
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x20C++0x03
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x20C++0x03
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x210++0x03
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x210++0x03
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x214++0x03
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x214++0x03
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x218++0x03
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x218++0x03
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x21C++0x03
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x21C++0x03
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x220++0x03
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x220++0x03
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x224++0x03
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x224++0x03
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x228++0x03
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x228++0x03
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x22C++0x03
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x22C++0x03
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x230++0x03
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x230++0x03
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x234++0x03
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x234++0x03
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x238++0x03
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x238++0x03
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
group.long 0x23C++0x03
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x23C++0x03
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
width 11.
tree "Interrupt Active Bit Registers"
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE0,Active Bit Register 0"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
rgroup.long 0x304++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x304++0x03
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
rgroup.long 0x308++0x03
line.long 0x00 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x00 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x308++0x03
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
rgroup.long 0x30C++0x03
line.long 0x00 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x30C++0x03
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
rgroup.long 0x310++0x03
line.long 0x00 "ACTIVE4,Active Bit Register 4"
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x310++0x03
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
rgroup.long 0x314++0x03
line.long 0x00 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x314++0x03
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
rgroup.long 0x318++0x03
line.long 0x00 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x318++0x03
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
rgroup.long 0x31C++0x03
line.long 0x00 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x31C++0x03
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
rgroup.long 0x320++0x03
line.long 0x00 "ACTIVE8,Active Bit Register 8"
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x320++0x03
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
rgroup.long 0x324++0x03
line.long 0x00 "ACTIVE9,Active Bit Register 9"
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x324++0x03
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
rgroup.long 0x328++0x03
line.long 0x00 "ACTIVE10,Active Bit Register 10"
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x328++0x03
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
rgroup.long 0x32C++0x03
line.long 0x00 "ACTIVE11,Active Bit Register 11"
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x32C++0x03
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
rgroup.long 0x330++0x03
line.long 0x00 "ACTIVE12,Active Bit Register 12"
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x330++0x03
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
rgroup.long 0x334++0x03
line.long 0x00 "ACTIVE13,Active Bit Register 13"
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x334++0x03
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
rgroup.long 0x338++0x03
line.long 0x00 "ACTIVE14,Active Bit Register 14"
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x338++0x03
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
rgroup.long 0x33C++0x03
line.long 0x00 "ACTIVE15,Active Bit Register 15"
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
textline "                    "
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x33C++0x03
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
endif
tree.end
width 13.
tree "Interrupt Target Non-Secure Registers"
group.long 0x380++0x03
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
bitfld.long 0x00 31. " ITNS31  ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS30  ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS29  ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS28  ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS27  ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS26  ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS25  ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS24  ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS23  ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS22  ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS21  ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS20  ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS19  ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS18  ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS17  ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS16  ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS15  ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS14  ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS13  ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS12  ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS11  ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS10  ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS9   ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS8   ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS7   ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS6   ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS5   ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS4   ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS3   ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS2   ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS1   ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS0   ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x384++0x03
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
bitfld.long 0x00 31. " ITNS63  ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS62  ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS61  ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS60  ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS59  ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS58  ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS57  ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS56  ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS55  ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS54  ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS53  ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS52  ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS51  ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS50  ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS49  ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS48  ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS47  ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS46  ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS45  ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS44  ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS43  ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS42  ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS41  ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS40  ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS39  ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS38  ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS37  ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS36  ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS35  ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS34  ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS33  ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS32  ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
else
hgroup.long 0x384++0x03
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x388++0x03
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
bitfld.long 0x00 31. " ITNS95  ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS94  ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS93  ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS92  ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS91  ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS90  ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS89  ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS88  ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS87  ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS86  ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS85  ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS84  ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS83  ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS82  ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS81  ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS80  ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS79  ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS78  ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS77  ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS76  ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS75  ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS74  ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS73  ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS72  ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS71  ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS70  ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS69  ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS68  ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS67  ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS66  ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS65  ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS64  ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
else
hgroup.long 0x388++0x03
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x38C++0x03
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS99  ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS98  ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS97  ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS96  ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
else
hgroup.long 0x38C++0x03
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x390++0x03
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
else
hgroup.long 0x390++0x03
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x394++0x03
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
else
hgroup.long 0x394++0x03
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x398++0x03
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
else
hgroup.long 0x398++0x03
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x39C++0x03
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
else
hgroup.long 0x39C++0x03
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x3A0++0x03
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
else
hgroup.long 0x3A0++0x03
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x3A4++0x03
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
else
hgroup.long 0x3A4++0x03
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x3A8++0x03
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
else
hgroup.long 0x3A8++0x03
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x3AC++0x03
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
else
hgroup.long 0x3AC++0x03
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x3B0++0x03
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
else
hgroup.long 0x3B0++0x03
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x3B4++0x03
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
else
hgroup.long 0x3B4++0x03
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x3B8++0x03
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
else
hgroup.long 0x3B8++0x03
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
group.long 0x3BC++0x03
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
bitfld.long 0x00 30. "  ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
bitfld.long 0x00 29. "  ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
bitfld.long 0x00 27. "  ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
bitfld.long 0x00 26. "  ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
bitfld.long 0x00 24. "  ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
bitfld.long 0x00 23. "  ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
bitfld.long 0x00 21. "  ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
bitfld.long 0x00 20. "  ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
bitfld.long 0x00 18. "  ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
bitfld.long 0x00 17. "  ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
bitfld.long 0x00 15. "  ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
bitfld.long 0x00 14. "  ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
bitfld.long 0x00 12. "  ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
bitfld.long 0x00 11. "  ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
bitfld.long 0x00 9. "  ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
bitfld.long 0x00 8. "  ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
bitfld.long 0x00 6. "  ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
bitfld.long 0x00 5. "  ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
bitfld.long 0x00 3. "  ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
bitfld.long 0x00 2. "  ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
textline "                      "
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
bitfld.long 0x00 0. "  ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
else
hgroup.long 0x3BC++0x03
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
endif
tree.end
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
group.long 0x420++0x1F
line.long 0x0 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x4 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x8 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0xC "IPR11,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x10 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x14 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x18 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x1C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
else
hgroup.long 0x420++0x1F
hide.long 0x0 "IPR8,Interrupt Priority Register"
hide.long 0x4 "IPR9,Interrupt Priority Register"
hide.long 0x8 "IPR10,Interrupt Priority Register"
hide.long 0xC "IPR11,Interrupt Priority Register"
hide.long 0x10 "IPR12,Interrupt Priority Register"
hide.long 0x14 "IPR13,Interrupt Priority Register"
hide.long 0x18 "IPR14,Interrupt Priority Register"
hide.long 0x1C "IPR15,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
group.long 0x440++0x1F
line.long 0x0 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x4 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x8 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0xC "IPR19,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x10 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x14 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x18 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x1C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
else
hgroup.long 0x440++0x1F
hide.long 0x0 "IPR16,Interrupt Priority Register"
hide.long 0x4 "IPR17,Interrupt Priority Register"
hide.long 0x8 "IPR18,Interrupt Priority Register"
hide.long 0xC "IPR19,Interrupt Priority Register"
hide.long 0x10 "IPR20,Interrupt Priority Register"
hide.long 0x14 "IPR21,Interrupt Priority Register"
hide.long 0x18 "IPR22,Interrupt Priority Register"
hide.long 0x1C "IPR23,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
group.long 0x460++0x1F
line.long 0x0 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x4 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x8 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0xC "IPR27,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x10 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x14 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x18 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x1C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
else
hgroup.long 0x460++0x1F
hide.long 0x0 "IPR24,Interrupt Priority Register"
hide.long 0x4 "IPR25,Interrupt Priority Register"
hide.long 0x8 "IPR26,Interrupt Priority Register"
hide.long 0xC "IPR27,Interrupt Priority Register"
hide.long 0x10 "IPR28,Interrupt Priority Register"
hide.long 0x14 "IPR29,Interrupt Priority Register"
hide.long 0x18 "IPR30,Interrupt Priority Register"
hide.long 0x1C "IPR31,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
group.long 0x480++0x1F
line.long 0x0 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x4 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x8 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0xC "IPR35,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x10 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x14 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x18 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x1C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
else
hgroup.long 0x480++0x1F
hide.long 0x0 "IPR32,Interrupt Priority Register"
hide.long 0x4 "IPR33,Interrupt Priority Register"
hide.long 0x8 "IPR34,Interrupt Priority Register"
hide.long 0xC "IPR35,Interrupt Priority Register"
hide.long 0x10 "IPR36,Interrupt Priority Register"
hide.long 0x14 "IPR37,Interrupt Priority Register"
hide.long 0x18 "IPR38,Interrupt Priority Register"
hide.long 0x1C "IPR39,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
group.long 0x4A0++0x1F
line.long 0x0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0x4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0x8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0x10 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0x14 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0x18 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0x1C "IPR47,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
else
hgroup.long 0x4A0++0x1F
hide.long 0x0 "IPR40,Interrupt Priority Register"
hide.long 0x4 "IPR41,Interrupt Priority Register"
hide.long 0x8 "IPR42,Interrupt Priority Register"
hide.long 0xC "IPR43,Interrupt Priority Register"
hide.long 0x10 "IPR44,Interrupt Priority Register"
hide.long 0x14 "IPR45,Interrupt Priority Register"
hide.long 0x18 "IPR46,Interrupt Priority Register"
hide.long 0x1C "IPR47,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
group.long 0x4C0++0x1F
line.long 0x0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0x4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0x8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0x10 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0x14 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0x18 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0x1C "IPR55,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
else
hgroup.long 0x4C0++0x1F
hide.long 0x0 "IPR48,Interrupt Priority Register"
hide.long 0x4 "IPR49,Interrupt Priority Register"
hide.long 0x8 "IPR50,Interrupt Priority Register"
hide.long 0xC "IPR51,Interrupt Priority Register"
hide.long 0x10 "IPR52,Interrupt Priority Register"
hide.long 0x14 "IPR53,Interrupt Priority Register"
hide.long 0x18 "IPR54,Interrupt Priority Register"
hide.long 0x1C "IPR55,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
group.long 0x4E0++0x1F
line.long 0x0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0x4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0x8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
line.long 0x10 "IPR60,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_242 ,Interrupt 242 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_241 ,Interrupt 241 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_240 ,Interrupt 240 Priority"
line.long 0x14 "IPR61,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_246 ,Interrupt 246 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_245 ,Interrupt 245 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_244 ,Interrupt 244 Priority"
line.long 0x18 "IPR62,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_250 ,Interrupt 250 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_249 ,Interrupt 249 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_248 ,Interrupt 248 Priority"
line.long 0x1C "IPR63,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_254 ,Interrupt 254 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_253 ,Interrupt 253 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_252 ,Interrupt 252 Priority"
else
hgroup.long 0x4E0++0x1F
hide.long 0x0 "IPR56,Interrupt Priority Register"
hide.long 0x4 "IPR57,Interrupt Priority Register"
hide.long 0x8 "IPR58,Interrupt Priority Register"
hide.long 0xC "IPR59,Interrupt Priority Register"
hide.long 0x10 "IPR60,Interrupt Priority Register"
hide.long 0x14 "IPR61,Interrupt Priority Register"
hide.long 0x18 "IPR62,Interrupt Priority Register"
hide.long 0x1C "IPR63,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
group.long 0x500++0x1F
line.long 0x0 "IPR64,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_258 ,Interrupt 258 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_257 ,Interrupt 257 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_256 ,Interrupt 256 Priority"
line.long 0x4 "IPR65,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_262 ,Interrupt 262 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_261 ,Interrupt 261 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_260 ,Interrupt 260 Priority"
line.long 0x8 "IPR66,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_266 ,Interrupt 266 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_265 ,Interrupt 265 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_264 ,Interrupt 264 Priority"
line.long 0xC "IPR67,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_270 ,Interrupt 270 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_269 ,Interrupt 269 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_268 ,Interrupt 268 Priority"
line.long 0x10 "IPR68,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_274 ,Interrupt 274 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_273 ,Interrupt 273 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_272 ,Interrupt 272 Priority"
line.long 0x14 "IPR69,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_278 ,Interrupt 278 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_277 ,Interrupt 277 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_276 ,Interrupt 276 Priority"
line.long 0x18 "IPR70,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_282 ,Interrupt 282 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_281 ,Interrupt 281 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_280 ,Interrupt 280 Priority"
line.long 0x1C "IPR71,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_286 ,Interrupt 286 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_285 ,Interrupt 285 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_284 ,Interrupt 284 Priority"
else
hgroup.long 0x500++0x1F
hide.long 0x0 "IPR64,Interrupt Priority Register"
hide.long 0x4 "IPR65,Interrupt Priority Register"
hide.long 0x8 "IPR66,Interrupt Priority Register"
hide.long 0xC "IPR67,Interrupt Priority Register"
hide.long 0x10 "IPR68,Interrupt Priority Register"
hide.long 0x14 "IPR69,Interrupt Priority Register"
hide.long 0x18 "IPR70,Interrupt Priority Register"
hide.long 0x1C "IPR71,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
group.long 0x520++0x1F
line.long 0x0 "IPR72,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_290 ,Interrupt 290 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_289 ,Interrupt 289 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_288 ,Interrupt 288 Priority"
line.long 0x4 "IPR73,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_294 ,Interrupt 294 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_293 ,Interrupt 293 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_292 ,Interrupt 292 Priority"
line.long 0x8 "IPR74,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_298 ,Interrupt 298 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_297 ,Interrupt 297 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_296 ,Interrupt 296 Priority"
line.long 0xC "IPR75,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_302 ,Interrupt 302 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_301 ,Interrupt 301 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_300 ,Interrupt 300 Priority"
line.long 0x10 "IPR76,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_306 ,Interrupt 306 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_305 ,Interrupt 305 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_304 ,Interrupt 304 Priority"
line.long 0x14 "IPR77,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_310 ,Interrupt 310 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_309 ,Interrupt 309 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_308 ,Interrupt 308 Priority"
line.long 0x18 "IPR78,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_314 ,Interrupt 314 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_313 ,Interrupt 313 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_312 ,Interrupt 312 Priority"
line.long 0x1C "IPR79,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_318 ,Interrupt 318 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_317 ,Interrupt 317 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_316 ,Interrupt 316 Priority"
else
hgroup.long 0x520++0x1F
hide.long 0x0 "IPR72,Interrupt Priority Register"
hide.long 0x4 "IPR73,Interrupt Priority Register"
hide.long 0x8 "IPR74,Interrupt Priority Register"
hide.long 0xC "IPR75,Interrupt Priority Register"
hide.long 0x10 "IPR76,Interrupt Priority Register"
hide.long 0x14 "IPR77,Interrupt Priority Register"
hide.long 0x18 "IPR78,Interrupt Priority Register"
hide.long 0x1C "IPR79,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
group.long 0x540++0x1F
line.long 0x0 "IPR80,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_322 ,Interrupt 322 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_321 ,Interrupt 321 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_320 ,Interrupt 320 Priority"
line.long 0x4 "IPR81,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_326 ,Interrupt 326 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_325 ,Interrupt 325 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_324 ,Interrupt 324 Priority"
line.long 0x8 "IPR82,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_330 ,Interrupt 330 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_329 ,Interrupt 329 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_328 ,Interrupt 328 Priority"
line.long 0xC "IPR83,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_334 ,Interrupt 334 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_333 ,Interrupt 333 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_332 ,Interrupt 332 Priority"
line.long 0x10 "IPR84,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_338 ,Interrupt 338 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_337 ,Interrupt 337 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_336 ,Interrupt 336 Priority"
line.long 0x14 "IPR85,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_342 ,Interrupt 342 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_341 ,Interrupt 341 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_340 ,Interrupt 340 Priority"
line.long 0x18 "IPR86,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_346 ,Interrupt 346 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_345 ,Interrupt 345 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_344 ,Interrupt 344 Priority"
line.long 0x1C "IPR87,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_350 ,Interrupt 350 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_349 ,Interrupt 349 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_348 ,Interrupt 348 Priority"
else
hgroup.long 0x540++0x1F
hide.long 0x0 "IPR80,Interrupt Priority Register"
hide.long 0x4 "IPR81,Interrupt Priority Register"
hide.long 0x8 "IPR82,Interrupt Priority Register"
hide.long 0xC "IPR83,Interrupt Priority Register"
hide.long 0x10 "IPR84,Interrupt Priority Register"
hide.long 0x14 "IPR85,Interrupt Priority Register"
hide.long 0x18 "IPR86,Interrupt Priority Register"
hide.long 0x1C "IPR87,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
group.long 0x560++0x1F
line.long 0x0 "IPR88,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_354 ,Interrupt 354 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_353 ,Interrupt 353 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_352 ,Interrupt 352 Priority"
line.long 0x4 "IPR89,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_358 ,Interrupt 358 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_357 ,Interrupt 357 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_356 ,Interrupt 356 Priority"
line.long 0x8 "IPR90,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_362 ,Interrupt 362 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_361 ,Interrupt 361 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_360 ,Interrupt 360 Priority"
line.long 0xC "IPR91,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_366 ,Interrupt 366 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_365 ,Interrupt 365 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_364 ,Interrupt 364 Priority"
line.long 0x10 "IPR92,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_370 ,Interrupt 370 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_369 ,Interrupt 369 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_368 ,Interrupt 368 Priority"
line.long 0x14 "IPR93,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_374 ,Interrupt 374 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_373 ,Interrupt 373 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_372 ,Interrupt 372 Priority"
line.long 0x18 "IPR94,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_378 ,Interrupt 378 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_377 ,Interrupt 377 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_376 ,Interrupt 376 Priority"
line.long 0x1C "IPR95,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_382 ,Interrupt 382 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_381 ,Interrupt 381 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_380 ,Interrupt 380 Priority"
else
hgroup.long 0x560++0x1F
hide.long 0x0 "IPR88,Interrupt Priority Register"
hide.long 0x4 "IPR89,Interrupt Priority Register"
hide.long 0x8 "IPR90,Interrupt Priority Register"
hide.long 0xC "IPR91,Interrupt Priority Register"
hide.long 0x10 "IPR92,Interrupt Priority Register"
hide.long 0x14 "IPR93,Interrupt Priority Register"
hide.long 0x18 "IPR94,Interrupt Priority Register"
hide.long 0x1C "IPR95,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
group.long 0x580++0x1F
line.long 0x0 "IPR96,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_386 ,Interrupt 386 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_385 ,Interrupt 385 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_384 ,Interrupt 384 Priority"
line.long 0x4 "IPR97,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_390 ,Interrupt 390 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_389 ,Interrupt 389 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_388 ,Interrupt 388 Priority"
line.long 0x8 "IPR98,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_394 ,Interrupt 394 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_393 ,Interrupt 393 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_392 ,Interrupt 392 Priority"
line.long 0xC "IPR99,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_398 ,Interrupt 398 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_397 ,Interrupt 397 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_396 ,Interrupt 396 Priority"
line.long 0x10 "IPR100,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_402 ,Interrupt 402 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_401 ,Interrupt 401 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_400 ,Interrupt 400 Priority"
line.long 0x14 "IPR101,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_406 ,Interrupt 406 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_405 ,Interrupt 405 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_404 ,Interrupt 404 Priority"
line.long 0x18 "IPR102,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_410 ,Interrupt 410 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_409 ,Interrupt 409 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_408 ,Interrupt 408 Priority"
line.long 0x1C "IPR103,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_414 ,Interrupt 414 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_413 ,Interrupt 413 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_412 ,Interrupt 412 Priority"
else
hgroup.long 0x580++0x1F
hide.long 0x0 "IPR96,Interrupt Priority Register"
hide.long 0x4 "IPR97,Interrupt Priority Register"
hide.long 0x8 "IPR98,Interrupt Priority Register"
hide.long 0xC "IPR99,Interrupt Priority Register"
hide.long 0x10 "IPR100,Interrupt Priority Register"
hide.long 0x14 "IPR101,Interrupt Priority Register"
hide.long 0x18 "IPR102,Interrupt Priority Register"
hide.long 0x1C "IPR103,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
group.long 0x5A0++0x1F
line.long 0x0 "IPR104,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_418 ,Interrupt 418 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_417 ,Interrupt 417 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_416 ,Interrupt 416 Priority"
line.long 0x4 "IPR105,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_422 ,Interrupt 422 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_421 ,Interrupt 421 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_420 ,Interrupt 420 Priority"
line.long 0x8 "IPR106,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_426 ,Interrupt 426 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_425 ,Interrupt 425 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_424 ,Interrupt 424 Priority"
line.long 0xC "IPR107,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_430 ,Interrupt 430 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_429 ,Interrupt 429 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_428 ,Interrupt 428 Priority"
line.long 0x10 "IPR108,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_434 ,Interrupt 434 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_433 ,Interrupt 433 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_432 ,Interrupt 432 Priority"
line.long 0x14 "IPR109,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_438 ,Interrupt 438 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_437 ,Interrupt 437 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_436 ,Interrupt 436 Priority"
line.long 0x18 "IPR110,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_442 ,Interrupt 442 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_441 ,Interrupt 441 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_440 ,Interrupt 440 Priority"
line.long 0x1C "IPR111,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_446 ,Interrupt 446 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_445 ,Interrupt 445 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_444 ,Interrupt 444 Priority"
else
hgroup.long 0x5A0++0x1F
hide.long 0x0 "IPR104,Interrupt Priority Register"
hide.long 0x4 "IPR105,Interrupt Priority Register"
hide.long 0x8 "IPR106,Interrupt Priority Register"
hide.long 0xC "IPR107,Interrupt Priority Register"
hide.long 0x10 "IPR108,Interrupt Priority Register"
hide.long 0x14 "IPR109,Interrupt Priority Register"
hide.long 0x18 "IPR110,Interrupt Priority Register"
hide.long 0x1C "IPR111,Interrupt Priority Register"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
group.long 0x5C0++0x1F
line.long 0x0 "IPR112,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_450 ,Interrupt 450 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_449 ,Interrupt 449 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_448 ,Interrupt 448 Priority"
line.long 0x4 "IPR113,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_454 ,Interrupt 454 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_453 ,Interrupt 453 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_452 ,Interrupt 452 Priority"
line.long 0x8 "IPR114,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_458 ,Interrupt 458 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_457 ,Interrupt 457 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_456 ,Interrupt 456 Priority"
line.long 0xC "IPR115,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_462 ,Interrupt 462 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_461 ,Interrupt 461 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_460 ,Interrupt 460 Priority"
line.long 0x10 "IPR116,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_466 ,Interrupt 466 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_465 ,Interrupt 465 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_464 ,Interrupt 464 Priority"
line.long 0x14 "IPR117,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_470 ,Interrupt 470 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_469 ,Interrupt 469 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_468 ,Interrupt 468 Priority"
line.long 0x18 "IPR118,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_474 ,Interrupt 474 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_473 ,Interrupt 473 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_472 ,Interrupt 472 Priority"
line.long 0x1C "IPR119,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_478 ,Interrupt 478 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_477 ,Interrupt 477 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_476 ,Interrupt 476 Priority"
else
hgroup.long 0x5C0++0x1F
hide.long 0x0 "IPR112,Interrupt Priority Register"
hide.long 0x4 "IPR113,Interrupt Priority Register"
hide.long 0x8 "IPR114,Interrupt Priority Register"
hide.long 0xC "IPR115,Interrupt Priority Register"
hide.long 0x10 "IPR116,Interrupt Priority Register"
hide.long 0x14 "IPR117,Interrupt Priority Register"
hide.long 0x18 "IPR118,Interrupt Priority Register"
hide.long 0x1C "IPR119,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif (CORENAME()=="CORTEXM33F")
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN     ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 29. "       LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
newline
bitfld.long 0x00 28. " CLRONRET     ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
bitfld.long 0x00 27. "                      CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
bitfld.long 0x00 26. "    TS     ,Treat as Secure" "Disabled,Enabled"
newline
bitfld.long 0x00 10. " UFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
bitfld.long 0x00 9. "                      SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
bitfld.long 0x00 8. "           MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
newline
bitfld.long 0x00 7. " SFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
bitfld.long 0x00 6. "                      BFRDY     ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "       MMRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
newline
bitfld.long 0x00 4. " HFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
bitfld.long 0x00 3. "                      THREAD    ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 2. "        S      ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
newline
bitfld.long 0x00 1. " USER         ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "                  LSPACT    ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN        ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ     ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
newline
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x0B
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 20.--23. "                 SQRROOT   ,Indicates the hardware support for FP square root operations" ",Supported,?..."
bitfld.long 0x00 16.--19. "      DIV    ,Indicates the hardware support for FP divide operations" ",Supported,?..."
newline
bitfld.long 0x00 8.--11. " DBLPREC      ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
bitfld.long 0x00 4.--7. "                 SNGLPREC  ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "      A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP   ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
newline
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE  ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
bitfld.long 0x08 4.--7. " VFP_MISC     ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 13.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL   ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "         DWTTRAP      ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT       ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR     ,Specifies the access type for the transfer" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA     ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. "       SDME       ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. "            MON_REQ      ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND   ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. "              VC_SFERR     ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR  ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "              VC_STATERR   ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. "       VC_CHKERR  ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. "              VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA     ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 20. "       SDME       ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
bitfld.long 0x00 19. "            MON_REQ      ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND   ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 11. "              VC_SFERR     ,SecureFault vector catch enable" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR  ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "              VC_STATERR   ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
bitfld.long 0x00 6. "       VC_CHKERR  ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
newline
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
bitfld.long 0x00 0. "              VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
newline
group.long 0xE04++0x07
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 2. "       SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
bitfld.long 0x00 1. "  INTSPIDEN    ,Internal secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 0. "       SPIDENSEL  ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
bitfld.long 0x04 16. " CDS        ,This field indicates the current security state of the processor" "Non-secure,Secure"
bitfld.long 0x04 1. "     SBRSEL     ,Secure banked register select" "Non-secure,Secure"
bitfld.long 0x04 0. "            SBRSELEN     ,Secure banked register select enable" "Disabled,Enabled"
rgroup.long 0xFB8++0x03
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI        ,Secure non-invasive debug implemented" ",Implemented"
bitfld.long 0x00 6. "    SNE        ,Secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 5. "                     SI           ,Secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 4. "    SE         ,Secure invasive debug enabled" "0,1"
newline
bitfld.long 0x00 3. " NSNI       ,Non-secure non-invasive debug features implemented" ",Implemented"
bitfld.long 0x00 2. "    NSNE       ,Non-secure non-invasive debug enabled" "0,1"
bitfld.long 0x00 1. "                     NSI          ,Non-secure invasive debug features implemented" ",Implemented"
bitfld.long 0x00 0. "    NSE        ,Non-secure invasive debug enabled" "0,1"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 12.
group.long 0x00++0x03
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV    ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "      NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
rbitfld.long 0x00 8.--11. "         NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 1. " KEY    ,Key Field" "Low,High"
bitfld.long 0x00 0. "           ENABLE   ,Flash Patch Unit Enable" "Disabled,Enabled"
textline "                     "
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
hexmask.long 0x00 5.--28. 0x20 "  REMAP    ,Remap address"
else
rgroup.long 0x04++0x03
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 31. " FE     ,Specifies if Flash Patch enabled" "Disabled,Enabled"
hexmask.long 0x00 2.--28. 0x04 "       FPADDR   ,Specifies bits[28:2] of the Flash Patch address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
textfld "                      "
hexmask.long 0x00 1.--31. 0x02 " BPADDR   ,Breakpoint address"
bitfld.long 0x00 0. "  BE      ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
endif
tree "CoreSight Identification Registers"
width 12.
rgroup.long 0xFCC++0x03
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUB           ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. "           MAJOR          ,Major type"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
bitfld.long 0x00 20. " PRESENT       ,Register present" "Not present,Present"
endif
rgroup.long 0xFE0++0x0F
line.long 0x00 "FP_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "FP_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "FP_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "FP_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "FP_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "FP_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "FP_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 16.
group.long 0x00++0x03
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP    ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
rbitfld.long 0x00 27. "                     NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 25. "              NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
textline "                         "
rbitfld.long 0x00 24. " NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 23. "         CYCDISS    ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
bitfld.long 0x00 22. "                        CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "              LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "                   SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 18. " EXCEVTENA  ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "              CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "                   EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                         "
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "              SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "                 CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                         "
bitfld.long 0x00 5.--8. " POSTINIT   ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "                    POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "                         CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
group.long 0x04++0x03
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
group.long 0x08++0x17
line.long 0x00 "DWT_CPICNT,CPI Count register"
hexmask.long.byte 0x00 0.--7. 1. " CPICNT     ,Base instruction overhead counter"
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT     ,The exception overhead counter"
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT   ,Sleep Counter"
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT     ,Load-store overhead counter"
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT    ,Folded-instruction counter"
endif
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                         "
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x20++0x03
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
endif
group.long (0x20+0x08)++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x30++0x03
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
endif
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x40++0x03
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
endif
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " CYCVALUE   ,Cycle value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 1.--31. 1. " PCVALUE    ,PC value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 1. " DVALUE     ,Data1 value"
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
hexmask.long 0x00 0.--31. 0x01 " DADDR      ,Data address"
else
group.long 0x50++0x03
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
endif
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
bitfld.long 0x00 27.--31. " ID         ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 24. "                    MATCHED    ,Comparator match" "Not matched,Matched"
bitfld.long 0x00 10.--11. "                DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
textline "                         "
bitfld.long 0x00 4.--5. " ACTION     ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
bitfld.long 0x00 0.--3. "  MATCH      ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
tree "CoreSight Identification Registers"
width 13.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT     ,Component architect"
bitfld.long 0x00 20. "         PRESENT        ,Register present" "Not present,Present"
bitfld.long 0x00 16.--19. "  REVISION      ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                      "
bitfld.long 0x00 12.--15. " ARCHVER       ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "           ARCHPART       ,Architecture part"
else
rgroup.long 0xFBC++0x03
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
bitfld.long 0x00 20. "                            PRESENT        ,Register present" "Not present,Present"
endif
rgroup.long 0xFCC++0x03
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
hexmask.long.byte 0x00 4.--7. 1. " SUB           ,Sub-type"
hexmask.long.byte 0x00 0.--3. 1. "           MAJOR          ,Major type"
rgroup.long 0xFE0++0x0F
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "           Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "           JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "        JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "           CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "           JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0       ,CoreSight component identification preamble"
line.long 0x04 "DWT_CIDR1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "           PRMBL_1        ,CoreSight component class"
line.long 0x08 "DWT_CIDR2,Component ID2"
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2       ,CoreSight component identification preamble"
line.long 0x0c "DWT_CIDR3,Component ID3"
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3       ,CoreSight component identification preamble"
tree.end
width 0x0b
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
autoindent.on center tree
tree "ADC (Analog-to-Digital Converter)"
base ad:0x400A0000
rgroup.long 0x00++0x03
line.long 0x00 "VERID,Version ID Register"
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
newline
bitfld.long 0x00 12.--14. "NUM_FIFO,Number of FIFOs" "0: NUM_FIFO_0,1: This design supports one result FIFO,2: This design supports two result FIFOs,3: This design supports three result FIFOs,4: This design supports four result FIFOs,?..."
bitfld.long 0x00 11. "NUM_SEC,Number of Single Ended Outputs Supported" "0: This design supports one single ended..,1: This design supports two simultanious single.."
newline
bitfld.long 0x00 10. "CALOFSI,Calibration Function Implemented" "0: Calibration Not Implemented,1: Calibration Implemented"
bitfld.long 0x00 9. "IADCKI,Internal ADC Clock implemented" "0: Internal clock source not implemented,1: Internal clock source (and CFG[ADCKEN]).."
newline
bitfld.long 0x00 8. "VR1RNGI,Voltage Reference 1 Range Control Bit Implemented" "0: Range control not required,1: Range control required"
bitfld.long 0x00 4.--6. "CSW,Channel Scale Width" "0: Channel scaling not supported,1: Channel scaling supported,?,?,?,?,6: Channel scaling supported,?..."
newline
bitfld.long 0x00 3. "MVI,Multi Vref Implemented" "0: Single voltage reference high (VREFH) input..,1: Multiple voltage reference high (VREFH).."
bitfld.long 0x00 1. "DIFFEN,Differential Supported" "0: Differential operation not supported,1: Differential operation supported"
newline
bitfld.long 0x00 0. "RES,Resolution" "0: Up to 13-bit differential/12-bit single ended..,1: Up to 16-bit differential/16-bit single ended.."
rgroup.long 0x04++0x03
line.long 0x00 "PARAM,Parameter Register"
hexmask.long.byte 0x00 24.--31. 1. "CMD_NUM,Command Buffer Number"
hexmask.long.byte 0x00 16.--23. 1. "CV_NUM,Compare Value Number"
newline
hexmask.long.byte 0x00 8.--15. 1. "FIFOSIZE,Result FIFO Depth"
hexmask.long.byte 0x00 0.--7. 1. "TRIG_NUM,Trigger Number"
group.long 0x10++0x03
line.long 0x00 "CTRL,ADC Control Register"
bitfld.long 0x00 16.--18. "CAL_AVGS,Auto-Calibration Averages" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 9. "RSTFIFO1,Reset FIFO 1" "0: RSTFIFO1_0,1: FIFO 1 is reset"
newline
bitfld.long 0x00 8. "RSTFIFO0,Reset FIFO 0" "0: RSTFIFO0_0,1: FIFO 0 is reset"
bitfld.long 0x00 4. "CALOFS,Configure for offset calibration function" "0: Calibration function disabled,1: Request for offset calibration function"
newline
bitfld.long 0x00 3. "CAL_REQ,Auto-Calibration Request" "0: No request for auto-calibration has been made,1: A request for auto-calibration has been made"
bitfld.long 0x00 2. "DOZEN,Doze Enable" "0: ADC is enabled in Doze mode,1: ADC is disabled in Doze mode"
newline
bitfld.long 0x00 1. "RST,Software Reset" "0: ADC logic is not reset,1: ADC logic is reset"
bitfld.long 0x00 0. "ADCEN,ADC Enable" "0: ADC is disabled,1: ADC is enabled"
group.long 0x14++0x03
line.long 0x00 "STAT,ADC Status Register"
rbitfld.long 0x00 24.--27. "CMDACT,Command Active" "0: No command is currently in progress,1: Command 1 currently being executed,2: Command 2 currently being executed,3: Associated command number is currently being..,4: Associated command number is currently being..,5: Associated command number is currently being..,6: Associated command number is currently being..,7: Associated command number is currently being..,8: Associated command number is currently being..,9: Associated command number is currently being..,?..."
rbitfld.long 0x00 16.--19. "TRGACT,Trigger Active" "0: Command (sequence) associated with Trigger 0..,1: Command (sequence) associated with Trigger 1..,2: Command (sequence) associated with Trigger 2..,3: Command (sequence) from the associated..,4: Command (sequence) from the associated..,5: Command (sequence) from the associated..,6: Command (sequence) from the associated..,7: Command (sequence) from the associated..,8: Command (sequence) from the associated..,9: Command (sequence) from the associated..,?..."
newline
rbitfld.long 0x00 11. "ADC_ACTIVE,ADC Active" "0: The ADC is IDLE,1: The ADC is processing a conversion running.."
rbitfld.long 0x00 10. "CAL_RDY,Calibration Ready" "0: Calibration is incomplete or hasn't been ran,1: The ADC is calibrated"
newline
eventfld.long 0x00 9. "TCOMP_INT,Interrupt Flag For Trigger Completion" "0: Either IE[TCOMP_IE] is set to 0 or no trigger..,1: Trigger sequence has been completed and all.."
eventfld.long 0x00 8. "TEXC_INT,Interrupt Flag For High Priority Trigger Exception" "0: No trigger exceptions have occurred,1: A trigger exception has occurred and is.."
newline
eventfld.long 0x00 3. "FOF1,Result FIFO1 Overflow Flag" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.."
rbitfld.long 0x00 2. "RDY1,Result FIFO1 Ready Flag" "0: Result FIFO1 data level not above watermark..,1: Result FIFO1 holding data above watermark level"
newline
eventfld.long 0x00 1. "FOF0,Result FIFO 0 Overflow Flag" "0: No result FIFO 0 overflow has occurred since..,1: At least one result FIFO 0 overflow has.."
rbitfld.long 0x00 0. "RDY0,Result FIFO 0 Ready Flag" "0: Result FIFO 0 data level not above watermark..,1: Result FIFO 0 holding data above watermark.."
group.long 0x18++0x03
line.long 0x00 "IE,Interrupt Enable Register"
hexmask.long.word 0x00 16.--31. 1. "TCOMP_IE,Trigger Completion Interrupt Enable"
bitfld.long 0x00 8. "TEXC_IE,Trigger Exception Interrupt Enable" "0: Trigger exception interrupts are disabled,1: Trigger exception interrupts are enabled"
newline
bitfld.long 0x00 3. "FOFIE1,Result FIFO1 Overflow Interrupt Enable" "0: No result FIFO1 overflow has occurred since..,1: At least one result FIFO1 overflow has.."
bitfld.long 0x00 2. "FWMIE1,FIFO1 Watermark Interrupt Enable" "0: FIFO1 watermark interrupts are not enabled,1: FIFO1 watermark interrupts are enabled"
newline
bitfld.long 0x00 1. "FOFIE0,Result FIFO 0 Overflow Interrupt Enable" "0: FIFO 0 overflow interrupts are not enabled,1: FIFO 0 overflow interrupts are enabled"
bitfld.long 0x00 0. "FWMIE0,FIFO 0 Watermark Interrupt Enable" "0: FIFO 0 watermark interrupts are not enabled,1: FIFO 0 watermark interrupts are enabled"
group.long 0x1C++0x03
line.long 0x00 "DE,DMA Enable Register"
bitfld.long 0x00 1. "FWMDE1,FIFO1 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled"
bitfld.long 0x00 0. "FWMDE0,FIFO 0 Watermark DMA Enable" "0: DMA request disabled,1: DMA request enabled"
group.long 0x20++0x03
line.long 0x00 "CFG,ADC Configuration Register"
bitfld.long 0x00 28. "PWREN,ADC Analog Pre-Enable" "0: ADC analog circuits are only enabled while..,1: ADC analog circuits are pre-enabled and ready.."
hexmask.long.byte 0x00 16.--23. 1. "PUDLY,Power Up Delay"
newline
bitfld.long 0x00 10. "HPT_EXDI,High Priority Trigger Exception Disable" "0: High priority trigger exceptions are enabled,1: High priority trigger exceptions are disabled"
bitfld.long 0x00 9. "TCMDRES,Trigger Command Resume" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.."
newline
bitfld.long 0x00 8. "TRES,Trigger Resume Enable" "0: Trigger sequences interrupted by a high..,1: Trigger sequences interrupted by a high.."
bitfld.long 0x00 6.--7. "REFSEL,Voltage Reference Selection" "0: (Default) Option 1 setting,1: Option 2 setting,2: Option 3 setting,?..."
newline
bitfld.long 0x00 4.--5. "PWRSEL,Power Configuration Select" "0: Lowest power setting,1: Higher power setting than 0b0,2: Higher power setting than 0b1,3: Highest power setting"
bitfld.long 0x00 0.--1. "TPRICTRL,ADC trigger priority control" "0: If a higher priority trigger is detected..,1: If a higher priority trigger is received..,2: If a higher priority trigger is received..,?..."
group.long 0x24++0x03
line.long 0x00 "PAUSE,ADC Pause Register"
bitfld.long 0x00 31. "PAUSEEN,PAUSE Option Enable" "0: Pause operation disabled,1: Pause operation enabled"
hexmask.long.word 0x00 0.--8. 1. "PAUSEDLY,Pause Delay"
group.long 0x34++0x03
line.long 0x00 "SWTRIG,Software Trigger Register"
bitfld.long 0x00 15. "SWT15,Software trigger 15 event" "0: No trigger 15 event generated,1: Trigger 15 event generated"
bitfld.long 0x00 14. "SWT14,Software trigger 14 event" "0: No trigger 14 event generated,1: Trigger 14 event generated"
newline
bitfld.long 0x00 13. "SWT13,Software trigger 13 event" "0: No trigger 13 event generated,1: Trigger 13 event generated"
bitfld.long 0x00 12. "SWT12,Software trigger 12 event" "0: No trigger 12 event generated,1: Trigger 12 event generated"
newline
bitfld.long 0x00 11. "SWT11,Software trigger 11 event" "0: No trigger 11 event generated,1: Trigger 11 event generated"
bitfld.long 0x00 10. "SWT10,Software trigger 10 event" "0: No trigger 10 event generated,1: Trigger 10 event generated"
newline
bitfld.long 0x00 9. "SWT9,Software trigger 9 event" "0: No trigger 9 event generated,1: Trigger 9 event generated"
bitfld.long 0x00 8. "SWT8,Software trigger 8 event" "0: No trigger 8 event generated,1: Trigger 8 event generated"
newline
bitfld.long 0x00 7. "SWT7,Software trigger 7 event" "0: No trigger 7 event generated,1: Trigger 7 event generated"
bitfld.long 0x00 6. "SWT6,Software trigger 6 event" "0: No trigger 6 event generated,1: Trigger 6 event generated"
newline
bitfld.long 0x00 5. "SWT5,Software trigger 5 event" "0: No trigger 5 event generated,1: Trigger 5 event generated"
bitfld.long 0x00 4. "SWT4,Software trigger 4 event" "0: No trigger 4 event generated,1: Trigger 4 event generated"
newline
bitfld.long 0x00 3. "SWT3,Software trigger 3 event" "0: No trigger 3 event generated,1: Trigger 3 event generated"
bitfld.long 0x00 2. "SWT2,Software trigger 2 event" "0: No trigger 2 event generated,1: Trigger 2 event generated"
newline
bitfld.long 0x00 1. "SWT1,Software trigger 1 event" "0: No trigger 1 event generated,1: Trigger 1 event generated"
bitfld.long 0x00 0. "SWT0,Software trigger 0 event" "0: No trigger 0 event generated,1: Trigger 0 event generated"
group.long 0x38++0x03
line.long 0x00 "TSTAT,Trigger Status Register"
hexmask.long.word 0x00 16.--31. 1. "TCOMP_FLAG,Trigger Completion Flag"
hexmask.long.word 0x00 0.--15. 1. "TEXC_NUM,Trigger Exception Number"
group.long 0x40++0x03
line.long 0x00 "OFSTRIM,ADC Offset Trim Register"
bitfld.long 0x00 16.--20. "OFSTRIM_B,Trim for offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "OFSTRIM_A,Trim for offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0xA0)++0x03
line.long 0x00 "TCTRL[$1],Trigger Control Register $1"
bitfld.long 0x00 24.--27. "TCMD,Trigger command select" "0: Not a valid selection from the command buffer,1: CMD1 is executed,2: Corresponding CMD is executed,3: Corresponding CMD is executed,4: Corresponding CMD is executed,5: Corresponding CMD is executed,6: Corresponding CMD is executed,7: Corresponding CMD is executed,8: Corresponding CMD is executed,9: Corresponding CMD is executed,?,?,?,?,?,15: CMD15 is executed"
bitfld.long 0x00 16.--19. "TDLY,Trigger delay select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 15. "RSYNC,Trigger Resync" "0,1"
bitfld.long 0x00 8.--11. "TPRI,Trigger priority setting" "0: Set to highest priority Level 1,1: Set to corresponding priority level,2: Set to corresponding priority level,3: Set to corresponding priority level,4: Set to corresponding priority level,5: Set to corresponding priority level,6: Set to corresponding priority level,7: Set to corresponding priority level,8: Set to corresponding priority level,9: Set to corresponding priority level,?,?,?,?,?,15: Set to lowest priority Level 16"
newline
bitfld.long 0x00 2. "FIFO_SEL_B,SAR Result Destination For Channel B" "0: Result written to FIFO 0,1: Result written to FIFO 1"
bitfld.long 0x00 1. "FIFO_SEL_A,SAR Result Destination For Channel A" "0: Result written to FIFO 0,1: Result written to FIFO 1"
newline
bitfld.long 0x00 0. "HTEN,Trigger enable" "0: Hardware trigger source disabled,1: Hardware trigger source enabled"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0xE0)++0x03
line.long 0x00 "FCTRL[$1],FIFO Control Register $1"
bitfld.long 0x00 16.--19. "FWMARK,Watermark level selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--4. "FCOUNT,Result FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0xF0)++0x03
line.long 0x00 "GCC[$1],Gain Calibration Control $1"
bitfld.long 0x00 24. "RDY,Gain Calibration Value Valid" "0: The gain calibration value is invalid,1: The gain calibration value is valid"
hexmask.long.word 0x00 0.--15. 1. "GAIN_CAL,Gain Calibration Value"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0xF8)++0x03
line.long 0x00 "GCR[$1],Gain Calculation Result $1"
bitfld.long 0x00 24. "RDY,Gain Calculation Ready" "0: The gain offset calculation value is invalid,1: The gain calibration value is valid"
hexmask.long.word 0x00 0.--15. 1. "GCALR,Gain Calculation Result"
repeat.end
group.long 0x100++0x03
line.long 0x00 "CMDL1,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
newline
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x104++0x03
line.long 0x00 "CMDH1,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x108++0x03
line.long 0x00 "CMDL2,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x10C++0x03
line.long 0x00 "CMDH2,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x110++0x03
line.long 0x00 "CMDL3,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x114++0x03
line.long 0x00 "CMDH3,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x118++0x03
line.long 0x00 "CMDL4,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x11C++0x03
line.long 0x00 "CMDH4,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
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bitfld.long 0x00 0.--1. "CMPEN,Compare Function Enable" "0: Compare disabled,?,2: Compare enabled,3: Compare enabled"
group.long 0x120++0x03
line.long 0x00 "CMDL5,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x124++0x03
line.long 0x00 "CMDH5,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x128++0x03
line.long 0x00 "CMDL6,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x12C++0x03
line.long 0x00 "CMDH6,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x130++0x03
line.long 0x00 "CMDL7,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x134++0x03
line.long 0x00 "CMDH7,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x138++0x03
line.long 0x00 "CMDL8,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x13C++0x03
line.long 0x00 "CMDH8,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x140++0x03
line.long 0x00 "CMDL9,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x144++0x03
line.long 0x00 "CMDH9,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x148++0x03
line.long 0x00 "CMDL10,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x14C++0x03
line.long 0x00 "CMDH10,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x150++0x03
line.long 0x00 "CMDL11,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x154++0x03
line.long 0x00 "CMDH11,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x158++0x03
line.long 0x00 "CMDL12,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x15C++0x03
line.long 0x00 "CMDH12,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x160++0x03
line.long 0x00 "CMDL13,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x164++0x03
line.long 0x00 "CMDH13,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x168++0x03
line.long 0x00 "CMDL14,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x16C++0x03
line.long 0x00 "CMDH14,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
group.long 0x170++0x03
line.long 0x00 "CMDL15,ADC Command Low Buffer Register"
bitfld.long 0x00 7. "MODE,Select resolution of conversions" "0: Standard resolution,1: High resolution"
bitfld.long 0x00 5.--6. "CTYPE,Conversion Type" "0: Single-Ended Mode,1: Single-Ended Mode,2: Differential Mode,3: Dual-Single-Ended Mode"
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bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Select CH0A or CH0B or CH0A/CH0B pair,1: Select CH1A or CH1B or CH1A/CH1B pair,2: Select CH2A or CH2B or CH2A/CH2B pair,3: Select CH3A or CH3B or CH3A/CH3B pair,4: Select corresponding channel CHnA or CHnB or..,5: Select corresponding channel CHnA or CHnB or..,6: Select corresponding channel CHnA or CHnB or..,7: Select corresponding channel CHnA or CHnB or..,8: Select corresponding channel CHnA or CHnB or..,9: Select corresponding channel CHnA or CHnB or..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,30: Select CH30A or CH30B or CH30A/CH30B pair,31: Select CH31A or CH31B or CH31A/CH31B pair"
group.long 0x174++0x03
line.long 0x00 "CMDH15,ADC Command High Buffer Register"
bitfld.long 0x00 24.--27. "NEXT,Next Command Select" "0: No next command defined,1: Select CMD1 command buffer register as next..,2: Select corresponding CMD command buffer..,3: Select corresponding CMD command buffer..,4: Select corresponding CMD command buffer..,5: Select corresponding CMD command buffer..,6: Select corresponding CMD command buffer..,7: Select corresponding CMD command buffer..,8: Select corresponding CMD command buffer..,9: Select corresponding CMD command buffer..,?,?,?,?,?,15: Select CMD15 command buffer register as next.."
bitfld.long 0x00 16.--19. "LOOP,Loop Count Select" "0: Looping not enabled,1: Loop 1 time,2: Loop 2 times,3: Loop corresponding number of times,4: Loop corresponding number of times,5: Loop corresponding number of times,6: Loop corresponding number of times,7: Loop corresponding number of times,8: Loop corresponding number of times,9: Loop corresponding number of times,?,?,?,?,?,15: Loop 15 times"
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bitfld.long 0x00 12.--14. "AVGS,Hardware Average Select" "0: Single conversion,1: 2 conversions averaged,2: 4 conversions averaged,3: 8 conversions averaged,4: 16 conversions averaged,5: 32 conversions averaged,6: 64 conversions averaged,7: 128 conversions averaged"
bitfld.long 0x00 8.--10. "STS,Sample Time Select" "0: Minimum sample time of 3 ADCK cycles,1: 3 + 21 ADCK cycles 5 ADCK cycles total sample..,2: 3 + 22 ADCK cycles 7 ADCK cycles total sample..,3: 3 + 23 ADCK cycles 11 ADCK cycles total..,4: 3 + 24 ADCK cycles 19 ADCK cycles total..,5: 3 + 25 ADCK cycles 35 ADCK cycles total..,6: 3 + 26 ADCK cycles 67 ADCK cycles total..,7: 3 + 27 ADCK cycles 131 ADCK cycles total.."
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bitfld.long 0x00 7. "LWI,Loop with Increment" "0: Auto channel increment disabled,1: Auto channel increment enabled"
bitfld.long 0x00 2. "WAIT_TRIG,Wait for trigger assertion before execution" "0: This command will be automatically executed,1: The active trigger must be asserted again.."
repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x200)++0x03
line.long 0x00 "CV$1,Compare Value Register"
hexmask.long.word 0x00 16.--31. 1. "CVH,Compare Value High"
hexmask.long.word 0x00 0.--15. 1. "CVL,Compare Value Low"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x300)++0x03
line.long 0x00 "RESFIFO[$1],ADC Data Result FIFO Register $1"
bitfld.long 0x00 31. "VALID,FIFO entry is valid" "0: FIFO is empty,1: FIFO record read from RESFIFO is valid"
bitfld.long 0x00 24.--27. "CMDSRC,Command Buffer Source" "0: Not a valid value CMDSRC value for a dataword..,1: CMD1 buffer used as control settings for this..,2: Corresponding command buffer used as control..,3: Corresponding command buffer used as control..,4: Corresponding command buffer used as control..,5: Corresponding command buffer used as control..,6: Corresponding command buffer used as control..,7: Corresponding command buffer used as control..,8: Corresponding command buffer used as control..,9: Corresponding command buffer used as control..,?,?,?,?,?,15: CMD15 buffer used as control settings for.."
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bitfld.long 0x00 20.--23. "LOOPCNT,Loop count value" "0: Result is from initial conversion in command,1: Result is from second conversion in command,2: Result is from LOOPCNT+1 conversion in command,3: Result is from LOOPCNT+1 conversion in command,4: Result is from LOOPCNT+1 conversion in command,5: Result is from LOOPCNT+1 conversion in command,6: Result is from LOOPCNT+1 conversion in command,7: Result is from LOOPCNT+1 conversion in command,8: Result is from LOOPCNT+1 conversion in command,9: Result is from LOOPCNT+1 conversion in command,?,?,?,?,?,15: Result is from 16th conversion in command"
bitfld.long 0x00 16.--19. "TSRC,Trigger Source" "0: Trigger source 0 initiated this conversion,1: Trigger source 1 initiated this conversion,2: Corresponding trigger source initiated this..,3: Corresponding trigger source initiated this..,4: Corresponding trigger source initiated this..,5: Corresponding trigger source initiated this..,6: Corresponding trigger source initiated this..,7: Corresponding trigger source initiated this..,8: Corresponding trigger source initiated this..,9: Corresponding trigger source initiated this..,?,?,?,?,?,15: Trigger source 15 initiated this conversion"
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hexmask.long.word 0x00 0.--15. 1. "D,Data result"
repeat.end
repeat 33. (increment 0 1) (increment 0 0x04)
group.long ($2+0x400)++0x03
line.long 0x00 "CAL_GAR[$1],Calibration General A-Side Registers $1"
hexmask.long.word 0x00 0.--15. 1. "CAL_GAR_VAL,Calibration General A Side Register Element"
repeat.end
repeat 33. (increment 0 1) (increment 0 0x04)
group.long ($2+0x500)++0x03
line.long 0x00 "CAL_GBR[$1],Calibration General B-Side Registers $1"
hexmask.long.word 0x00 0.--15. 1. "CAL_GBR_VAL,Calibration General B Side Register Element"
repeat.end
group.long 0xFFC++0x03
line.long 0x00 "TST,ADC Test Register"
bitfld.long 0x00 23. "TESTEN,Enable test configuration" "0: Normal operation,1: Hardware BIST Test in progress"
bitfld.long 0x00 11. "FOFFP2,Force P-side negative offset" "0: Normal operation,1: Test configuration"
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bitfld.long 0x00 10. "FOFFM2,Force M-side negative offset" "0: Normal operation,1: Test configuration"
bitfld.long 0x00 9. "FOFFP,Force P-side positive offset" "0: Normal operation,1: Test configuration"
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bitfld.long 0x00 8. "FOFFM,Force M-side positive offset" "0: Normal operation,1: Test configuration"
bitfld.long 0x00 0. "CST_LONG,Calibration Sample Time Long" "0: Normal sample time,1: Increased sample time"
tree.end
tree "AHB_SECURE_CTRL (AHB Secure Controller)"
base ad:0x400AC000
group.long 0x00++0x03
line.long 0x00 "SEC_CTRL_FLASH_ROM_SLAVE_RULE,Security access rules for Flash and ROM slaves"
bitfld.long 0x00 4.--5. "ROM_RULE,Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
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sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 0.--1. "FLASH_RULE,Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--1. "FLASH_RULE,Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
group.long 0x10++0x03
line.long 0x00 "SEC_CTRL_FLASH_MEM_RULE0,Security access rules for FLASH sector 0 to sector 20"
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
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bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
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bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x10++0x03
line.long 0x00 "SEC_CTRL_FLASH_MEM_RULE0,Security access rules for FLASH sector 0 to sector 7"
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x14)++0x03
line.long 0x00 "SEC_CTRL_FLASH_MEM_RULE$1,Security access rules for FLASH sector 0 to sector 20"
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x20)++0x03
line.long 0x00 "SEC_CTRL_ROM_MEM_RULE$1,Security access rules for ROM sector 0 to sector 31"
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
repeat.end
group.long 0x30++0x03
line.long 0x00 "SEC_CTRL_RAMX_SLAVE_RULE,Security access rules for RAMX slaves"
bitfld.long 0x00 0.--1. "RAMX_RULE,Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x40++0x03
line.long 0x00 "SEC_CTRL_RAMX_MEM_RULE0,Security access rules for RAMX slaves"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x50++0x03
line.long 0x00 "SEC_CTRL_RAM0_SLAVE_RULE,Security access rules for RAM0 slaves"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 0.--1. "RAM0_RULE,Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--1. "RAM0_RULE,Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0x60)++0x03
line.long 0x00 "SEC_CTRL_RAM0_MEM_RULE$1,Security access rules for RAM0 slaves"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
repeat.end
group.long 0x70++0x03
line.long 0x00 "SEC_CTRL_RAM1_SLAVE_RULE,Security access rules for RAM1 slaves"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--1. "RAM1_RULE,Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF name= 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 0.--1. "RAM1_RULE,Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
group.long 0x80++0x03
line.long 0x00 "SEC_CTRL_RAM1_MEM_RULE0,Security access rules for RAM1 slaves"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x84++0x03
line.long 0x00 "SEC_CTRL_RAM1_MEM_RULE1,Security access rules for RAM1 slaves"
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x90++0x03
line.long 0x00 "SEC_CTRL_RAM2_SLAVE_RULE,Security access rules for RAM2 slaves"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 0.--1. "RAM2_RULE,Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--1. "RAM2_RULE,Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0xA0)++0x03
line.long 0x00 "SEC_CTRL_RAM2_MEM_RULE$1,Security access rules for RAM2 slaves"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
repeat.end
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
group.long 0xB0++0x03
line.long 0x00 "SEC_CTRL_RAM3_SLAVE_RULE,Security access rules for RAM3 slaves"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--1. "RAM3_RULE,Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 0.--1. "RAM3_RULE,Security access rules for the whole RAM3 : 0x2001_0000 - 0x2001_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
endif
group.long 0xB0++0x03
line.long 0x00 "SEC_CTRL_USB_HS_SLAVE_RULE,Security access rules for USB High speed RAM slaves"
bitfld.long 0x00 0.--1. "RAM_USB_HS_RULE,Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xC0++0x03
line.long 0x00 "SEC_CTRL_RAM3_MEM_RULE0,Security access rules for RAM3"
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xC0++0x03
line.long 0x00 "SEC_CTRL_USB_HS_MEM_RULE,Security access rules for RAM_USB_HS"
bitfld.long 0x00 12.--13. "SRAM_SECT_3_RULE,Address space: 0x2001_3000 - 0x2001_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "SRAM_SECT_2_RULE,Address space: 0x2001_2000 - 0x2001_2FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "SRAM_SECT_1_RULE,Address space: 0x2001_1000 - 0x2001_1FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "SRAM_SECT_0_RULE,Address space: 0x2001_0000 - 0x2001_0FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0xC0)++0x03
line.long 0x00 "SEC_CTRL_RAM3_MEM_RULE$1,Security access rules for RAM3 slaves"
bitfld.long 0x00 28.--29. "RULE7,secure control rule7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "RULE6,secure control rule6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "RULE5,secure control rule5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RULE4,secure control rule4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
repeat.end
group.long 0xD0++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE_SLAVE_RULE,Security access rules for both APB Bridges slaves"
bitfld.long 0x00 4.--5. "APBBRIDGE1_RULE,Security access rules for the whole APB Bridge 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "APBBRIDGE0_RULE,Security access rules for the whole APB Bridge 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xD0++0x03
line.long 0x00 "SEC_CTRL_RAM4_SLAVE_RULE,Security access rules for RAM4 slaves"
bitfld.long 0x00 0.--1. "RAM4_RULE,Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xE0++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE0_MEM_CTRL0,Security access rules for APB Bridge 0 peripherals"
bitfld.long 0x00 24.--25. "INPUTMUX_RULE,Peripheral input multiplexing" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "SEC_PINT_RULE,Secure Pin Interrupt and Pattern match" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "PINT_RULE,Pin Interrupt and Pattern match" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "GINT1_RULE,GPIO input Interrupt 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "GINT0_RULE,GPIO input Interrupt 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "IOCON_RULE,I/O Configuration" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "SYSCON_RULE,System Configuration" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xE0++0x03
line.long 0x00 "SEC_CTRL_RAM4_MEM_RULE0,Security access rules for RAM4 slaves"
bitfld.long 0x00 12.--13. "RULE3,secure control rule3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RULE2,secure control rule2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "RULE1,secure control rule1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "RULE0,secure control rule0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xE4++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE0_MEM_CTRL1,Security access rules for APB Bridge 0 peripherals"
bitfld.long 0x00 24.--25. "UTICK_RULE,Micro-Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "MRT_RULE,Multi-rate Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "WWDT_RULE,Windiwed wtachdog Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "CTIMER1_RULE,Standard counter/Timer 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "CTIMER0_RULE,Standard counter/Timer 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xE8++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE0_MEM_CTRL2,Security access rules for APB Bridge 0 peripherals"
bitfld.long 0x00 12.--13. "ANACTRL_RULE,Analog Modules controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xF0++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL0,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 16.--17. "SPI_FILTER_RULE,SPI FILTER control" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "SYSCTRL_RULE,System Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "PMC_RULE,Power Management Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xF4++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL1,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 20.--21. "OSEVENT_RULE,OS Event Timer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "RTC_RULE,Real Time Counter" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "CTIMER4_RULE,Standard counter/Timer 4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "CTIMER3_RULE,Standard counter/Timer 3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "CTIMER2_RULE,Standard counter/Timer 2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xF8++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL2,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 20.--21. "PRINCE_RULE,Prince" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "FLASH_CTRL_RULE,Flash Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0xFC++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL3,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 20.--21. "PLU_RULE,Programmable Look-Up logic" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "PUF_RULE,PUF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "RNG_RULE,True Random Number Generator" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--1. "USBHPHY_RULE,USB High Speed Phy controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
group.long 0x100++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT7_SLAVE0_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "FLEXCOMM1_RULE,Flexcomm interface 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "FLEXCOMM0_RULE,Flexcomm interface 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "SCT_RULE,SCTimer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 16.--17. "FS_USB_DEV_RULE,USB Full-speed device" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
bitfld.long 0x00 8.--9. "DMA0_RULE,DMA Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x104++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT7_SLAVE1_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 16.--17. "GPIO0_RULE,High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "FLEXCOMM4_RULE,Flexcomm interface 4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "FLEXCOMM3_RULE,Flexcomm interface 3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "FLEXCOMM2_RULE,Flexcomm interface 2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x110++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE0_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "FLEXCOMM6_RULE,Flexcomm interface 6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "FLEXCOMM5_RULE,Flexcomm interface 5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "CRC_RULE,CRC engine" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 16.--17. "USB_HS_DEV_RULE,USB high Speed device registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
group.long 0x110++0x03
line.long 0x00 "SEC_CTRL_APB_BRIDGE1_MEM_CTRL0,Security access rules for APB Bridge 1 peripherals"
bitfld.long 0x00 12.--13. "SYSCTRL_RULE,System Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "PMC_RULE,Power Management Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x114++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE1_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "HS_LSPI_RULE,High Speed SPI" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "CAN0_RULE,CAN-FD" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "DBG_MAILBOX_RULE,Debug mailbox (aka ISP-AP)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "FLEXCOMM7_RULE,Flexcomm interface 7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x120++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE0_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "FLEXCOMM1_RULE,Flexcomm interface 1" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "FLEXCOMM0_RULE,Flexcomm interface 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "SCT_RULE,SCTimer" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "FS_USB_DEV_RULE,USB Full-speed device" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "DMA0_RULE,DMA Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x120++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE0_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "DMA1_RULE,DMA Controller (Secure)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "CASPER_RULE,RSA/ECC crypto accelerator" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "HASH_RULE,SHA-2 crypto registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 12.--13. "USB_HS_HOST_RULE,USB High speed host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "USB_FS_HOST_RULE,USB Full Speed Host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
bitfld.long 0x00 0.--1. "ADC_RULE,ADC" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x124++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE1_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 4.--5. "AHB_SEC_CTRL_RULE,AHB Secure Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "GPIO1_RULE,Secure High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x124++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT8_SLAVE1_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 16.--17. "GPIO0_RULE,High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "MAILBOX_RULE,Inter CPU communication Mailbox" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "FLEXCOMM4_RULE,Flexcomm interface 4" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "FLEXCOMM3_RULE,Flexcomm interface 3" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "FLEXCOMM2_RULE,Flexcomm interface 2" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x130++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE0_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "FLEXCOMM6_RULE,Flexcomm interface 6" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "FLEXCOMM5_RULE,Flexcomm interface 5" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "CRC_RULE,CRC engine" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "USB_HS_DEV_RULE,USB high Speed device registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x130++0x03
line.long 0x00 "SEC_CTRL_AHB_SEC_CTRL_MEM_RULE,Security access rules for AHB_SEC_CTRL_AHB"
bitfld.long 0x00 12.--13. "AHB_SEC_CTRL_SECT_3_RULE,Address space: 0x400A_F000 - 0x400A_FFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "AHB_SEC_CTRL_SECT_2_RULE,Address space: 0x400A_E000 - 0x400A_EFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "AHB_SEC_CTRL_SECT_1_RULE,Address space: 0x400A_D000 - 0x400A_DFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "AHB_SEC_CTRL_SECT_0_RULE,Address space: 0x400A_0000 - 0x400A_CFFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x134++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT9_SLAVE1_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "HS_LSPI_RULE,High Speed SPI" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "DBG_MAILBOX_RULE,Debug mailbox (aka ISP-AP)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "SDIO_RULE,SDMMC card interface" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "FLEXCOMM7_RULE,Flexcomm interface 7" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x140++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT10_SLAVE0_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 28.--29. "DMA1_RULE,DMA Controller (Secure)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 24.--25. "PQ_RULE,Power Quad (CPU0 processor hardware accelerator)" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 20.--21. "CASPER_RULE,RSA/ECC crypto accelerator" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "HASH_RULE,SHA-2 crypto registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 12.--13. "USB_HS_HOST_RULE,USB High speed host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "USB_FS_HOST_RULE,USB Full Speed Host registers" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "ADC_RULE,ADC" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x144++0x03
line.long 0x00 "SEC_CTRL_AHB_PORT10_SLAVE1_RULE,Security access rules for AHB peripherals"
bitfld.long 0x00 4.--5. "AHB_SEC_CTRL_RULE,AHB Secure Controller" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "GPIO1_RULE,Secure High Speed GPIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x160++0x03
line.long 0x00 "SEC_CTRL_USB_HS_SLAVE_RULE,Security access rules for USB High speed RAM slaves"
bitfld.long 0x00 0.--1. "RAM_USB_HS_RULE,Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
group.long 0x170++0x03
line.long 0x00 "SEC_CTRL_USB_HS_MEM_RULE,Security access rules for RAM_USB_HS"
bitfld.long 0x00 12.--13. "SRAM_SECT_3_RULE,Address space: 0x4010_3000 - 0x4010_3FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 8.--9. "SRAM_SECT_2_RULE,Address space: 0x4010_2000 - 0x4010_2FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "SRAM_SECT_1_RULE,Address space: 0x4010_1000 - 0x4010_1FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 0.--1. "SRAM_SECT_0_RULE,Address space: 0x4010_0000 - 0x4010_0FFF" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
rgroup.long 0xE00++0x03
line.long 0x00 "sec_vio_addr[0],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer"
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE00)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE04)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE08)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE0C)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE10)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE14)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE18)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port"
repeat.end
rgroup.long 0xE1C++0x03
line.long 0x00 "sec_vio_addr[7],most recent security violation address for AHB layer n"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer"
rgroup.long 0xE20++0x03
line.long 0x00 "sec_vio_addr[8],most recent security violation address for AHB port n"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port"
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE20)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB layer n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB layer"
repeat.end
repeat 3. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE24)++0x03
line.long 0x00 "sec_vio_addr[$1],most recent security violation address for AHB port n $1"
hexmask.long 0x00 0.--31. 1. "SEC_VIO_ADDR,security violation address for AHB port"
repeat.end
rgroup.long 0xE80++0x03
line.long 0x00 "sec_vio_misc_info[0],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE80++0x03
line.long 0x00 "sec_vio_misc_info[0],most recent security violation miscellaneous information for AHB port n"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE84++0x03
line.long 0x00 "sec_vio_misc_info[1],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE84++0x03
line.long 0x00 "sec_vio_misc_info[1],most recent security violation miscellaneous information for AHB port n"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE88++0x03
line.long 0x00 "sec_vio_misc_info[2],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE88)++0x03
line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB port n $1"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE8C)++0x03
line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB layer n $1"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xE90)++0x03
line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB port n $1"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
repeat.end
rgroup.long 0xE94++0x03
line.long 0x00 "sec_vio_misc_info[5],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE98++0x03
line.long 0x00 "sec_vio_misc_info[6],most recent security violation miscellaneous information for AHB port n"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE98++0x03
line.long 0x00 "sec_vio_misc_info[6],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE9C++0x03
line.long 0x00 "sec_vio_misc_info[7],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xE9C++0x03
line.long 0x00 "sec_vio_misc_info[7],most recent security violation miscellaneous information for AHB port n"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xEA0++0x03
line.long 0x00 "sec_vio_misc_info[8],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xEA0++0x03
line.long 0x00 "sec_vio_misc_info[8],most recent security violation miscellaneous information for AHB port n"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
rgroup.long 0xEA4++0x03
line.long 0x00 "sec_vio_misc_info[9],most recent security violation miscellaneous information for AHB layer n"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,4: USB-HS Device,5: VALUE_5,?,?,?,?,10: VALUE_10,11: USB-FS Host,12: VALUE_12,13: VALUE_13,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,?,?,?,5: VALUE_5,?,?,?,?,10: VALUE_10,?,12: VALUE_12,13: VALUE_13,?..."
newline
endif
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
repeat 3. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0xEA4)++0x03
line.long 0x00 "sec_vio_misc_info[$1],most recent security violation miscellaneous information for AHB port n $1"
bitfld.long 0x00 8.--11. "SEC_VIO_INFO_MASTER,security violation master number" "0: CPU0 Code,1: CPU0 System,2: CPU1 Data,3: CPU1 System,4: USB-HS Device,5: VALUE_5,?,?,8: VALUE_8,9: PowerQuad,10: VALUE_10,11: USB-FS Host,12: VALUE_12,?..."
newline
bitfld.long 0x00 4.--7. "SEC_VIO_INFO_MASTER_SEC_LEVEL,bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "SEC_VIO_INFO_DATA_ACCESS,security violation access data/code indicator" "0: Code access,1: Data access"
newline
bitfld.long 0x00 0. "SEC_VIO_INFO_WRITE,security violation access read/write indicator" "0: Read access,1: Write access"
repeat.end
group.long 0xF00++0x03
line.long 0x00 "SEC_VIO_INFO_VALID,security violation address/information registers valid flags"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 11. "VIO_INFO_VALID11,violation information valid flag for AHB port 11" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 10. "VIO_INFO_VALID10,violation information valid flag for AHB port 10" "0: Not valid,1: Valid (violation occurred)"
newline
endif
bitfld.long 0x00 9. "VIO_INFO_VALID9,violation information valid flag for AHB port 9" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 8. "VIO_INFO_VALID8,violation information valid flag for AHB port 8" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 7. "VIO_INFO_VALID7,violation information valid flag for AHB port 7" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 6. "VIO_INFO_VALID6,violation information valid flag for AHB port 6" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 5. "VIO_INFO_VALID5,violation information valid flag for AHB port 5" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 4. "VIO_INFO_VALID4,violation information valid flag for AHB port 4" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 3. "VIO_INFO_VALID3,violation information valid flag for AHB port 3" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 2. "VIO_INFO_VALID2,violation information valid flag for AHB port 2" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 1. "VIO_INFO_VALID1,violation information valid flag for AHB port 1" "0: Not valid,1: Valid (violation occurred)"
newline
bitfld.long 0x00 0. "VIO_INFO_VALID0,violation information valid flag for AHB port 0" "0: Not valid,1: Valid (violation occurred)"
group.long 0xF80++0x03
line.long 0x00 "SEC_GPIO_MASK0,Secure GPIO mask for port 0 pins"
bitfld.long 0x00 31. "PIO0_PIN31_SEC_MASK,Secure mask for pin P0_31" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 30. "PIO0_PIN30_SEC_MASK,Secure mask for pin P0_30" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 29. "PIO0_PIN29_SEC_MASK,Secure mask for pin P0_29" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 28. "PIO0_PIN28_SEC_MASK,Secure mask for pin P0_28" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 27. "PIO0_PIN27_SEC_MASK,Secure mask for pin P0_27" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 26. "PIO0_PIN26_SEC_MASK,Secure mask for pin P0_26" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 25. "PIO0_PIN25_SEC_MASK,Secure mask for pin P0_25" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 24. "PIO0_PIN24_SEC_MASK,Secure mask for pin P0_24" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 23. "PIO0_PIN23_SEC_MASK,Secure mask for pin P0_23" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 22. "PIO0_PIN22_SEC_MASK,Secure mask for pin P0_22" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 21. "PIO0_PIN21_SEC_MASK,Secure mask for pin P0_21" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 20. "PIO0_PIN20_SEC_MASK,Secure mask for pin P0_20" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 19. "PIO0_PIN19_SEC_MASK,Secure mask for pin P0_19" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 18. "PIO0_PIN18_SEC_MASK,Secure mask for pin P0_18" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 17. "PIO0_PIN17_SEC_MASK,Secure mask for pin P0_17" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 16. "PIO0_PIN16_SEC_MASK,Secure mask for pin P0_16" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 15. "PIO0_PIN15_SEC_MASK,Secure mask for pin P0_15" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 14. "PIO0_PIN14_SEC_MASK,Secure mask for pin P0_14" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 13. "PIO0_PIN13_SEC_MASK,Secure mask for pin P0_13" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 12. "PIO0_PIN12_SEC_MASK,Secure mask for pin P0_12" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 11. "PIO0_PIN11_SEC_MASK,Secure mask for pin P0_11" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 10. "PIO0_PIN10_SEC_MASK,Secure mask for pin P0_10" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 9. "PIO0_PIN9_SEC_MASK,Secure mask for pin P0_9" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 8. "PIO0_PIN8_SEC_MASK,Secure mask for pin P0_8" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 7. "PIO0_PIN7_SEC_MASK,Secure mask for pin P0_7" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 6. "PIO0_PIN6_SEC_MASK,Secure mask for pin P0_6" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 5. "PIO0_PIN5_SEC_MASK,Secure mask for pin P0_5" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 4. "PIO0_PIN4_SEC_MASK,Secure mask for pin P0_4" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 3. "PIO0_PIN3_SEC_MASK,Secure mask for pin P0_3" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 2. "PIO0_PIN2_SEC_MASK,Secure mask for pin P0_2" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 1. "PIO0_PIN1_SEC_MASK,Secure mask for pin P0_1" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 0. "PIO0_PIN0_SEC_MASK,Secure mask for pin P0_0" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
group.long 0xF84++0x03
line.long 0x00 "SEC_GPIO_MASK1,Secure GPIO mask for port 1 pins"
bitfld.long 0x00 31. "PIO1_PIN31_SEC_MASK,Secure mask for pin P1_31" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 30. "PIO1_PIN30_SEC_MASK,Secure mask for pin P1_30" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 29. "PIO1_PIN29_SEC_MASK,Secure mask for pin P1_29" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 28. "PIO1_PIN28_SEC_MASK,Secure mask for pin P1_28" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 27. "PIO1_PIN27_SEC_MASK,Secure mask for pin P1_27" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 26. "PIO1_PIN26_SEC_MASK,Secure mask for pin P1_26" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 25. "PIO1_PIN25_SEC_MASK,Secure mask for pin P1_25" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 24. "PIO1_PIN24_SEC_MASK,Secure mask for pin P1_24" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 23. "PIO1_PIN23_SEC_MASK,Secure mask for pin P1_23" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 22. "PIO1_PIN22_SEC_MASK,Secure mask for pin P1_22" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 21. "PIO1_PIN21_SEC_MASK,Secure mask for pin P1_21" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 20. "PIO1_PIN20_SEC_MASK,Secure mask for pin P1_20" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 19. "PIO1_PIN19_SEC_MASK,Secure mask for pin P1_19" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 18. "PIO1_PIN18_SEC_MASK,Secure mask for pin P1_18" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 17. "PIO1_PIN17_SEC_MASK,Secure mask for pin P1_17" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 16. "PIO1_PIN16_SEC_MASK,Secure mask for pin P1_16" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 15. "PIO1_PIN15_SEC_MASK,Secure mask for pin P1_15" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 14. "PIO1_PIN14_SEC_MASK,Secure mask for pin P1_14" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 13. "PIO1_PIN13_SEC_MASK,Secure mask for pin P1_13" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 12. "PIO1_PIN12_SEC_MASK,Secure mask for pin P1_12" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 11. "PIO1_PIN11_SEC_MASK,Secure mask for pin P1_11" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 10. "PIO1_PIN10_SEC_MASK,Secure mask for pin P1_10" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 9. "PIO1_PIN9_SEC_MASK,Secure mask for pin P1_9" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 8. "PIO1_PIN8_SEC_MASK,Secure mask for pin P1_8" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 7. "PIO1_PIN7_SEC_MASK,Secure mask for pin P1_7" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 6. "PIO1_PIN6_SEC_MASK,Secure mask for pin P1_6" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 5. "PIO1_PIN5_SEC_MASK,Secure mask for pin P1_5" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 4. "PIO1_PIN4_SEC_MASK,Secure mask for pin P1_4" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 3. "PIO1_PIN3_SEC_MASK,Secure mask for pin P1_3" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 2. "PIO1_PIN2_SEC_MASK,Secure mask for pin P1_2" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 1. "PIO1_PIN1_SEC_MASK,Secure mask for pin P1_1" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
newline
bitfld.long 0x00 0. "PIO1_PIN0_SEC_MASK,Secure mask for pin P1_0" "0: Pin state is blocked to non-secure world,1: Pin state is readable by non-secure world"
group.long 0xF90++0x03
line.long 0x00 "SEC_CPU_INT_MASK0,Secure Interrupt mask for CPU1"
bitfld.long 0x00 31. "MAILBOX_IRQ,Mailbox interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 30. "RESERVED3,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 29. "RTC_IRQ,RTC_LITE0_ALARM_IRQ RTC_LITE0_WAKEUP_IRQ" "0: no description available,1: no description available"
newline
bitfld.long 0x00 28. "USB0_IRQ,USB Full Speed Controller interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 27. "USB0_NEEDCLK,USB Full Speed Controller Clock request interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 26. "RESERVED2,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 25. "RESERVED1,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 24. "ACMP_IRQ,Analog Comparator interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 23. "RESERVED0,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 22. "ADC_IRQ,General Purpose ADC interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 21. "FLEXCOMM7_IRQ,Flexcomm 7 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 20. "FLEXCOMM6_IRQ,Flexcomm 6 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 19. "FLEXCOMM5_IRQ,Flexcomm 5 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 18. "FLEXCOMM4_IRQ,Flexcomm 4 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 17. "FLEXCOMM3_IRQ,Flexcomm 3 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 16. "FLEXCOMM2_IRQ,Flexcomm 2 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 15. "FLEXCOMM1_IRQ,Flexcomm 1 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 14. "FLEXCOMM0_IRQ,Flexcomm 0 interrupt (USART SPI I2C I2S)" "0: no description available,1: no description available"
newline
bitfld.long 0x00 13. "CTIMER3_IRQ,Standard counter/timer 3 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 12. "SCT_IRQ,SCTimer/PWM interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 11. "CTIMER1_IRQ,Standard counter/timer 1 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 10. "CTIMER0_IRQ,Standard counter/timer 0 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 9. "MRT_IRQ,Multi-Rate Timer interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 8. "UTICK_IRQ,Micro Tick Timer interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 7. "GPIO_INT0_IRQ3,Pin interrupt 3 or pattern match engine slice 3 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 6. "GPIO_INT0_IRQ2,Pin interrupt 2 or pattern match engine slice 2 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 5. "GPIO_INT0_IRQ1,Pin interrupt 1 or pattern match engine slice 1 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 4. "GPIO_INT0_IRQ0,Pin interrupt 0 or pattern match engine slice 0 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 3. "GPIO_GLOBALINT1_IRQ,GPIO Group 1 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 2. "GPIO_GLOBALINT0_IRQ,GPIO Group 0 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 1. "SDMA0_IRQ,System DMA 0 (non-secure) interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 0. "SYS_IRQ,Watchdog Timer Brown Out Detectors and Flash Controller interrupts" "0: no description available,1: no description available"
group.long 0xF94++0x03
line.long 0x00 "SEC_CPU_INT_MASK1,Secure Interrupt mask for CPU1"
bitfld.long 0x00 27. "LSPI_HS_IRQ,High Speed SPI interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 26. "SDMA1_IRQ,System DMA 1 (Secure) interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 25. "PQ_IRQ,Power Quad interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 24. "PUFKEY_IRQ,PUF interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 23. "CASPER_IRQ,CASPER interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 22. "SHA_IRQ,HASH-AES interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 21. "SEC_VIO_IRQ,Security Violation interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 20. "PLU_IRQ,Programmable Look-Up Controller interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 19. "SEC_GPIO_INT0_IRQ1,Secure Pin interrupt 1 or pattern match engine slice 1 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 18. "SEC_GPIO_INT0_IRQ0,Secure Pin interrupt 0 or pattern match engine slice 0 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 17. "SEC_HYPERVISOR_CALL_IRQ,Secure fault Hyper Visor call interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 16. "USB1_NEEDCLK,USB High Speed Controller Clock request interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 15. "USB1_IRQ,USB High Speed Controller interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 14. "USB1_PHY_IRQ,USB High Speed PHY Controller interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 13. "RESERVED5,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 12. "RESERVED4,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 11. "RESERVED3,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 10. "SDIO_IRQ,SDIO Controller interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 9. "RESERVED2,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 8. "RESERVED1,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 7. "RESERVED0,Reserved" "0: no description available,1: no description available"
newline
bitfld.long 0x00 6. "OS_EVENT_TIMER_IRQ,OS Event Timer and OS Event Timer Wakeup interrupts" "0: no description available,1: no description available"
newline
bitfld.long 0x00 5. "CTIMER4_IRQ,Standard counter/timer 4 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 4. "CTIMER2_IRQ,Standard counter/timer 2 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 3. "GPIO_INT0_IRQ7,Pin interrupt 7 or pattern match engine slice 7 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 2. "GPIO_INT0_IRQ6,Pin interrupt 6 or pattern match engine slice 6 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 1. "GPIO_INT0_IRQ5,Pin interrupt 5 or pattern match engine slice 5 interrupt" "0: no description available,1: no description available"
newline
bitfld.long 0x00 0. "GPIO_INT0_IRQ4,Pin interrupt 4 or pattern match engine slice 4 interrupt" "0: no description available,1: no description available"
group.long 0xFBC++0x03
line.long 0x00 "SEC_MASK_LOCK,Security General Purpose register access control"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 10.--11. "SEC_CPU1_INT_MASK1_LOCK,SEC_CPU_INT_MASK1 register write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 8.--9. "SEC_CPU1_INT_MASK0_LOCK,SEC_CPU_INT_MASK0 register write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
endif
bitfld.long 0x00 2.--3. "SEC_GPIO_MASK1_LOCK,SEC_GPIO_MASK1 register write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 0.--1. "SEC_GPIO_MASK0_LOCK,SEC_GPIO_MASK0 register write-lock" "?,1: Restricted mode,2: Writable,?..."
group.long 0xFD0++0x03
line.long 0x00 "MASTER_SEC_LEVEL,master secure level register"
bitfld.long 0x00 30.--31. "MASTER_SEC_LEVEL_LOCK,MASTER_SEC_LEVEL write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 26.--27. "CANFD,CAN FD" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
bitfld.long 0x00 24.--25. "SDMA1,System DMA 1 security level" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 22.--23. "USBFSH,USB Full speed Host" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
bitfld.long 0x00 20.--21. "HASH,Hash" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 18.--19. "PQ,Power Quad" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 16.--17. "SDIO,SDIO" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
bitfld.long 0x00 10.--11. "SDMA0,System DMA 0" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 8.--9. "USBFSD,USB Full Speed Device" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6.--7. "CPU1S,Micro-Cortex M33 (CPU1) System bus" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
newline
bitfld.long 0x00 4.--5. "CPU1C,Micro-Cortex M33 (CPU1) Code bus" "0: Non-secure and Non-priviledge user access..,1: Non-secure and Privilege access allowed,2: Secure and Non-priviledge user access allowed,3: Secure and Priviledge user access allowed"
endif
group.long 0xFD4++0x03
line.long 0x00 "MASTER_SEC_ANTI_POL_REG,master secure level anti-pole register"
bitfld.long 0x00 30.--31. "MASTER_SEC_LEVEL_ANTIPOL_LOCK,MASTER_SEC_ANTI_POL_REG register write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 26.--27. "CANFD,CAN FD" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
endif
bitfld.long 0x00 24.--25. "SDMA1,System DMA 1 security level" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 22.--23. "USBFSH,USB Full speed Host" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
endif
bitfld.long 0x00 20.--21. "HASH,Hash" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 18.--19. "PQ,Power Quad" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
bitfld.long 0x00 16.--17. "SDIO,SDIO" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
endif
bitfld.long 0x00 10.--11. "SDMA0,System DMA 0" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 8.--9. "USBFSD,USB Full Speed Device" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6.--7. "CPU1S,Micro-Cortex M33 (CPU1) System bus" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
newline
bitfld.long 0x00 4.--5. "CPU1C,Micro-Cortex M33 (CPU1) Code bus" "0: Secure and Priviledge user access allowed,1: Secure and Non-priviledge user access allowed,2: Non-secure and Privilege access allowed,3: Non-secure and Non-priviledge user access.."
endif
group.long 0xFEC++0x03
line.long 0x00 "CPU0_LOCK_REG,Miscalleneous control signals for in Cortex M33 (CPU0)"
bitfld.long 0x00 30.--31. "CPU0_LOCK_REG_LOCK,CPU0_LOCK_REG write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 8.--9. "LOCK_SAU,Cortex M33 (CPU0) SAU registers write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 6.--7. "LOCK_S_MPU,Cortex M33 (CPU0) Secure MPU registers write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 4.--5. "LOCK_S_VTAIRCR,Cortex M33 (CPU0) VTOR_S AIRCR.PRIS IRCR.BFHFNMINS registers write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 2.--3. "LOCK_NS_MPU,Cortex M33 (CPU0) non-secure MPU register write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 0.--1. "LOCK_NS_VTOR,Cortex M33 (CPU0) VTOR_NS register write-lock" "?,1: Restricted mode,2: Writable,?..."
group.long 0xFF0++0x03
line.long 0x00 "CPU1_LOCK_REG,Miscalleneous control signals for in micro-Cortex M33 (CPU1)"
bitfld.long 0x00 30.--31. "CPU1_LOCK_REG_LOCK,CPU1_LOCK_REG write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 2.--3. "LOCK_NS_MPU,micro-Cortex M33 (CPU1) non-secure MPU register write-lock" "?,1: Restricted mode,2: Writable,?..."
newline
bitfld.long 0x00 0.--1. "LOCK_NS_VTOR,micro-Cortex M33 (CPU1) VTOR_NS register write-lock" "?,1: Restricted mode,2: Writable,?..."
group.long 0xFF8++0x03
line.long 0x00 "MISC_CTRL_DP_REG,secure control duplicate register"
bitfld.long 0x00 14.--15. "IDAU_ALL_NS,Disable IDAU" "?,1: IDAU is disable,2: IDAU is enabled,?..."
newline
bitfld.long 0x00 12.--13. "DISABLE_SMART_MASTER_STRICT_MODE,Disable smart master strict mode" "?,1: Smart master in tier mode,2: Smart master in strict mode,?..."
newline
bitfld.long 0x00 10.--11. "DISABLE_SIMPLE_MASTER_STRICT_MODE,Disable simple master strict mode" "?,1: Simple master in tier mode,2: Simple master in strict mode,?..."
newline
bitfld.long 0x00 8.--9. "DISABLE_VIOLATION_ABORT,Disable secure violation abort" "?,1: Disable abort fort secure checker,2: Enable abort fort secure checker,?..."
newline
bitfld.long 0x00 6.--7. "ENABLE_NS_PRIV_CHECK,Enable non-secure privilege check for AHB matrix" "?,1: Restricted mode,2: Disable check,?..."
newline
bitfld.long 0x00 4.--5. "ENABLE_S_PRIV_CHECK,Enable secure privilege check for AHB matrix" "?,1: Restricted mode,2: Disable check,?..."
newline
bitfld.long 0x00 2.--3. "ENABLE_SECURE_CHECKING,Enable secure check for AHB matrix" "?,1: Restricted mode,2: Disable check,?..."
newline
bitfld.long 0x00 0.--1. "WRITE_LOCK,Write lock" "?,1: Restricted mode,2: Secure control registers can be written,?..."
group.long 0xFFC++0x03
line.long 0x00 "MISC_CTRL_REG,secure control register"
bitfld.long 0x00 14.--15. "IDAU_ALL_NS,Disable IDAU" "?,1: IDAU is disable,2: IDAU is enabled,?..."
newline
bitfld.long 0x00 12.--13. "DISABLE_SMART_MASTER_STRICT_MODE,Disable smart master strict mode" "?,1: Smart master in tier mode,2: Smart master in strict mode,?..."
newline
bitfld.long 0x00 10.--11. "DISABLE_SIMPLE_MASTER_STRICT_MODE,Disable simple master strict mode" "?,1: Simple master in tier mode,2: Simple master in strict mode,?..."
newline
bitfld.long 0x00 8.--9. "DISABLE_VIOLATION_ABORT,Disable secure violation abort" "?,1: Disable abort fort secure checker,2: Enable abort fort secure checker,?..."
newline
bitfld.long 0x00 6.--7. "ENABLE_NS_PRIV_CHECK,Enable non-secure privilege check for AHB matrix" "?,1: Enabled (restricted mode),2: Disable check,?..."
newline
bitfld.long 0x00 4.--5. "ENABLE_S_PRIV_CHECK,Enable secure privilege check for AHB matrix" "?,1: Enabled (restricted mode),2: Disable check,?..."
newline
bitfld.long 0x00 2.--3. "ENABLE_SECURE_CHECKING,Enable secure check for AHB matrix" "?,1: Enabled (restricted mode),2: Disable check,?..."
newline
bitfld.long 0x00 0.--1. "WRITE_LOCK,Write lock" "?,1: Restricted mode,2: Secure control registers can be written,?..."
tree.end
tree "ANACTRL (ANALOGCTRL)"
base ad:0x40013000
group.long 0x00++0x03
line.long 0x00 "ANALOG_CTRL_CFG,Various Analog blocks configuration (like FRO 192MHz trimmings source ...)"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long 0x00 0.--31. 1. "CONFIG,Analog blocks configuration"
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0. "FRO192M_TRIM_SRC,FRO192M trimming and 'Enable' source" "0: FRO192M trimming and 'Enable' comes from eFUSE,1: FRO192M trimming and 'Enable' comes from.."
endif
rgroup.long 0x04++0x03
line.long 0x00 "ANALOG_CTRL_STATUS,Analog Macroblock Identity registers Flash Status registers"
bitfld.long 0x00 13. "FLASH_INIT_ERROR,Flash initialization error status" "0: No error,1: At least one error occured during flash.."
newline
bitfld.long 0x00 12. "FLASH_PWRDWN,Flash Power Down status" "0: Flash is not in power down mode,1: Flash is in power down mode"
group.long 0x0C++0x03
line.long 0x00 "FREQ_ME_CTRL,Frequency Measure function control register"
bitfld.long 0x00 31. "PROG,Set this bit to one to initiate a frequency measurement cycle" "0,1"
newline
hexmask.long 0x00 0.--30. 1. "CAPVAL_SCALE,Frequency measure result /Frequency measur scale"
group.long 0x10++0x03
line.long 0x00 "FRO192M_CTRL,192MHz Free Running OScillator (FRO) Control register"
bitfld.long 0x00 31. "WRTRIM,This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields" "0,1"
newline
bitfld.long 0x00 30. "ENA_96MHZCLK,96 MHz clock control" "0: 96 MHz clock is disabled,1: 96 MHz clock is enabled"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rbitfld.long 0x00 25. "USBMODCHG,If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1 it should be re-read until it is 0" "0,1"
newline
bitfld.long 0x00 24. "USBCLKADJ,If this bit is set and the USB peripheral is enabled into full speed device mode the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF packets" "0,1"
newline
endif
hexmask.long.byte 0x00 16.--23. 1. "DAC_TRIM,Frequency trim"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 15. "ENA_48MHZCLK,48 MHz clock control" "?,1: 48 MHz clock is enabled"
newline
endif
bitfld.long 0x00 14. "ENA_12MHZCLK,12 MHz clock control" "0: 12 MHz clock is disabled,1: 12 MHz clock is enabled"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long.byte 0x00 7.--13. 1. "TEMP_TRIM,Temperature coefficient trimming bits"
newline
bitfld.long 0x00 0.--5. "BIAS_TRIM,Bias trimming bits (course frequency trimming)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.long 0x14++0x03
line.long 0x00 "FRO192M_STATUS,192MHz Free Running OScillator (FRO) Status register"
rbitfld.long 0x00 1. "ATB_VCTRL,CCO threshold voltage detector output (signal vcco_ok)" "0,1"
newline
rbitfld.long 0x00 0. "CLK_VALID,Output clock valid signal" "0: No output clock present (None of 12 MHz 48..,1: Clock is present (12 MHz 48 MHz or 96 MHz can.."
group.long 0x18++0x03
line.long 0x00 "ADC_CTRL,General Purpose ADC VBAT Divider branch control"
bitfld.long 0x00 0. "VBATDIVENABLE,Switch On/Off VBAT divider branch" "0: VBAT divider branch is disabled,1: VBAT divider branch is enabled"
group.long 0x18++0x03
line.long 0x00 "ADC_CTRL,ADC control static configuration"
hexmask.long 0x00 0.--31. 1. "CONFIG,ADC control static configuration"
group.long 0x20++0x03
line.long 0x00 "XO32M_CTRL,High speed Crystal Oscillator Control register"
bitfld.long 0x00 24. "ENABLE_SYSTEM_CLK_OUT,Enable High speed Crystal oscillator output to CPU system" "0: High speed Crystal oscillator output to CPU..,1: High speed Crystal oscillator output to CPU.."
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 23. "ENABLE_PLL_USB_OUT,Enable High speed Crystal oscillator output to USB HS PLL" "0: High speed Crystal oscillator output to USB..,1: High speed Crystal oscillator output to USB.."
newline
endif
bitfld.long 0x00 22. "ACBUF_PASS_ENABLE,Bypass enable of XO AC buffer enable in pll and top level" "0: XO AC buffer bypass is disabled,1: XO AC buffer bypass is enabled"
newline
hexmask.long.byte 0x00 15.--21. 1. "OSC_CAP_OUT,Tune capa banks of High speed Crystal Oscillator output pin"
newline
hexmask.long.byte 0x00 8.--14. 1. "OSC_CAP_IN,Tune capa banks of High speed Crystal Oscillator input pin"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 5.--7. "AMP,Amplitude selection Min amp : 001 Max amp : 110" "0,1,2,3,4,5,6,7"
newline
endif
bitfld.long 0x00 4. "SLAVE,Xo in slave mode" "0,1"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 1.--3. "GM,Gm value for Xo" "0,1,2,3,4,5,6,7"
endif
rgroup.long 0x24++0x03
line.long 0x00 "XO32M_STATUS,High speed Crystal Oscillator Status register"
bitfld.long 0x00 0. "XO_READY,Indicates XO out frequency statibilty" "0: XO output frequency is not yet stable,1: XO output frequency is stable"
group.long 0x30++0x03
line.long 0x00 "BOD_DCDC_INT_CTRL,Brown Out Detectors (BoDs) & DCDC interrupts generation control register"
bitfld.long 0x00 5. "DCDC_INT_CLEAR,DCDC interrupt clear.1: Clear the interrupt" "0,1"
newline
bitfld.long 0x00 4. "DCDC_INT_ENABLE,DCDC interrupt control" "0: DCDC interrupt is disabled,1: DCDC interrupt is enabled"
newline
bitfld.long 0x00 3. "BODCORE_INT_CLEAR,BOD CORE interrupt clear.1: Clear the interrupt" "0,1"
newline
bitfld.long 0x00 2. "BODCORE_INT_ENABLE,BOD CORE interrupt control" "0: BOD CORE interrupt is disabled,1: BOD CORE interrupt is enabled"
newline
bitfld.long 0x00 1. "BODVBAT_INT_CLEAR,BOD VBAT interrupt clear.1: Clear the interrupt" "0,1"
newline
bitfld.long 0x00 0. "BODVBAT_INT_ENABLE,BOD VBAT interrupt control" "0: BOD VBAT interrupt is disabled,1: BOD VBAT interrupt is enabled"
rgroup.long 0x34++0x03
line.long 0x00 "BOD_DCDC_INT_STATUS,BoDs & DCDC interrupts status register"
bitfld.long 0x00 8. "DCDC_VAL,Current value of DCDC power status output" "0: DCDC output Voltage is below the targeted..,1: DCDC output Voltage is above the targeted.."
newline
bitfld.long 0x00 7. "DCDC_INT_STATUS,DCDC Interrupt status after Interrupt Enable" "0: No interrupt pending,1: Interrupt pending"
newline
bitfld.long 0x00 6. "DCDC_STATUS,DCDC Interrupt status before Interrupt Enable" "0: No interrupt pending,1: Interrupt pending"
newline
bitfld.long 0x00 5. "BODCORE_VAL,Current value of BOD CORE power status output" "0: CORE voltage level is below the threshold,1: CORE voltage level is above the threshold"
newline
bitfld.long 0x00 4. "BODCORE_INT_STATUS,BOD CORE Interrupt status after Interrupt Enable" "0: No interrupt pending,1: Interrupt pending"
newline
bitfld.long 0x00 3. "BODCORE_STATUS,BOD CORE Interrupt status before Interrupt Enable" "0: No interrupt pending,1: Interrupt pending"
newline
bitfld.long 0x00 2. "BODVBAT_VAL,Current value of BOD VBAT power status output" "0: VBAT voltage level is below the threshold,1: VBAT voltage level is above the threshold"
newline
bitfld.long 0x00 1. "BODVBAT_INT_STATUS,BOD VBAT Interrupt status after Interrupt Enable" "0: No interrupt pending,1: Interrupt pending"
newline
bitfld.long 0x00 0. "BODVBAT_STATUS,BOD VBAT Interrupt status before Interrupt Enable" "0: No interrupt pending,1: Interrupt pending"
group.long 0x40++0x03
line.long 0x00 "RINGO0_CTRL,First Ring Oscillator module control register"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long 0x00 0.--31. 1. "CONFIG,First ring oscillator configuration"
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rbitfld.long 0x00 31. "DIV_UPDATE_REQ,Ringo clock out Divider status flag" "0,1"
newline
bitfld.long 0x00 16.--19. "DIVISOR,Ringo out Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "E_PN1,Second PN (P-Transistor and N-Transistor processing) monitor control" "0: Second PN-based ringo is disabled,1: Second PN-based ringo is enabled"
newline
bitfld.long 0x00 11. "E_PN0,First PN (P-Transistor and N-Transistor processing) monitor control" "0: First PN-based ringo is disabled,1: First PN-based ringo is enabled"
newline
bitfld.long 0x00 10. "E_IV1,Second Inverter-based ringo control" "0: Second INV-based ringo is disabled,1: Second INV-based ringo is enabled"
newline
bitfld.long 0x00 9. "E_IV0,First Inverter-based ringo control" "0: First INV-based ringo is disabled,1: First INV-based ringo is enabled"
newline
bitfld.long 0x00 8. "E_NR1,Second NOR2-based ringo control" "0: Second NORD2-based ringo is disabled,1: Second NORD2-based ringo is enabled"
newline
bitfld.long 0x00 7. "E_NR0,First NOR2-based ringo control" "0: First NOR2-based ringo is disabled,1: First NOR2-based ringo is enabled"
newline
bitfld.long 0x00 6. "E_ND1,Second NAND2-based ringo control" "0: Second NAND2-based ringo is disabled,1: Second NAND2-based ringo is enabled"
newline
bitfld.long 0x00 5. "E_ND0,First NAND2-based ringo control" "0: First NAND2-based ringo is disabled,1: First NAND2-based ringo is enabled"
newline
bitfld.long 0x00 4. "PD,Ringo module Power control" "0: The Ringo module is enabled,1: The Ringo module is disabled"
newline
bitfld.long 0x00 2.--3. "SWN_SWP,PN-Ringos (P-Transistor and N-Transistor processing) control" "0: Normal mode,1: P-Monitor mode,2: P-Monitor mode,3: Don't use"
newline
bitfld.long 0x00 1. "FS,Ringo frequency output divider" "0: High frequency output (frequency lower than..,1: Low frequency output (frequency lower than 10.."
newline
bitfld.long 0x00 0. "SL,Select short or long ringo (for all ringos types)" "0: Select short ringo (few elements),1: Select long ringo (many elements)"
endif
group.long 0x44++0x03
line.long 0x00 "RINGO1_CTRL,Second Ring Oscillator module control register"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long 0x00 0.--31. 1. "CONFIG,Second ring oscillator configuration"
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rbitfld.long 0x00 31. "DIV_UPDATE_REQ,Ringo clock out Divider status flag" "0,1"
newline
bitfld.long 0x00 16.--19. "DIVISOR,Ringo out Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "E_M5,Metal 5 (M5) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 7. "E_M4,Metal 4 (M4) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 6. "E_M3,Metal 3 (M3) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 5. "E_M2,Metal 2 (M2) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 4. "E_R35," "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 3. "E_R24," "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 2. "PD,Ringo module Power control" "0: The Ringo module is enabled,1: The Ringo module is disabled"
newline
bitfld.long 0x00 1. "FS,Ringo frequency output divider" "0: High frequency output (frequency lower than..,1: Low frequency output (frequency lower than 10.."
newline
bitfld.long 0x00 0. "S,Select short or long ringo (for all ringos types)" "0: Select short ringo (few elements),1: Select long ringo (many elements)"
endif
group.long 0x48++0x03
line.long 0x00 "RINGO2_CTRL,Third Ring Oscillator module control register"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long 0x00 0.--31. 1. "CONFIG,Third ring oscillator configuration"
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rbitfld.long 0x00 31. "DIV_UPDATE_REQ,Ringo clock out Divider status flag" "0,1"
newline
bitfld.long 0x00 16.--19. "DIVISOR,Ringo out Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8. "E_M5,Metal 5 (M5) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 7. "E_M4,Metal 4 (M4) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 6. "E_M3,Metal 3 (M3) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 5. "E_M2,Metal 2 (M2) monitor control" "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 4. "E_R35," "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 3. "E_R24," "0: Ringo is disabled,1: Ringo is enabled"
newline
bitfld.long 0x00 2. "PD,Ringo module Power control" "0: The Ringo module is enabled,1: The Ringo module is disabled"
newline
bitfld.long 0x00 1. "FS,Ringo frequency output divider" "0: High frequency output (frequency lower than..,1: Low frequency output (frequency lower than 10.."
newline
bitfld.long 0x00 0. "S,Select short or long ringo (for all ringos types)" "0: Select short ringo (few elements),1: Select long ringo (many elements)"
endif
group.long 0xB0++0x03
line.long 0x00 "LDO_XO32M,High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register"
bitfld.long 0x00 8.--9. "STABMODE,Stability configuration" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "IBIAS,Adjust the biasing current" "0,1,2,3"
newline
bitfld.long 0x00 3.--5. "VOUT,Sets the LDO output level" "0: 0.750 V,1: 0.775 V,2: 0.800 V,3: 0.825 V,4: 0.850 V,5: 0.875 V,6: 0.900 V,7: 0.925 V"
newline
bitfld.long 0x00 2. "HIGHZ," "0: Output in High normal state,1: Output in High Impedance state"
newline
bitfld.long 0x00 1. "BYPASS,Activate LDO bypass" "0: Disable bypass mode (for normal operations),1: Activate LDO bypass"
group.long 0xB4++0x03
line.long 0x00 "AUX_BIAS,AUX_BIAS"
bitfld.long 0x00 21. "ITRIMCTRL1,Control bit to configure trimming state of mirror" "0,1"
newline
bitfld.long 0x00 20. "ITRIMCTRL0,Control bit to configure trimming state of mirror" "0,1"
newline
bitfld.long 0x00 17.--19. "VREF1VCURVETRIM,Control bit to configure trimming state of mirror" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--16. "VREF1VTRIM,voltage trimming control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7.--11. "PTATITRIM,current trimming control word for ptat current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 2.--6. "ITRIM,current trimming control word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1. "VREF1VENABLE,Control output of 1V reference voltage" "0: Output of 1V reference voltage buffer is..,1: Output of 1V reference voltage is enabled"
group.long 0xF8++0x03
line.long 0x00 "DUMMY_CTRL,Dummy Control bus to analog modules"
bitfld.long 0x00 10.--11. "XO32M_ADC_CLK_MODE,Control High speed Crystal oscillator mode of the ADC clock" "0: High speed Crystal oscillator output to ADC..,1: High speed Crystal oscillator output to ADC..,?..."
group.long 0x100++0x03
line.long 0x00 "USBHS_PHY_CTRL,USB High Speed Phy Control"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 3. "iso_atx," "0,1"
newline
endif
bitfld.long 0x00 1. "usb_id_ext,Override value for ID if using external detectors" "0,1"
newline
bitfld.long 0x00 0. "usb_vbusvalid_ext,Override value for Vbus if using external detectors" "0,1"
group.long 0x104++0x03
line.long 0x00 "USBHS_PHY_TRIM,USB High Speed Phy Trim values"
bitfld.long 0x00 21.--23. "trim_pll_ctrl0_div_sel," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 18.--20. "trim_usb2_refbias_vbgadj," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--17. "trim_usb2_refbias_tst," "0,1,2,3"
newline
bitfld.long 0x00 11.--15. "trim_usbphy_tx_cal45dm," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "trim_usbphy_tx_cal45dp," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 2.--5. "trim_usbphy_tx_d_cal," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--1. "trim_usb_reg_env_tail_adj_vd,Adjusts time constant of HS RX squelch (envelope) comparator" "0,1,2,3"
tree.end
sif cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")
tree "CAN (Controller Area Network Flexible Data)"
base ad:0x4009D000
group.long 0x0C++0x03
line.long 0x00 "DBTP,Data Bit Timing Prescaler Register"
bitfld.long 0x00 23. "TDC,Transmitter delay compensation" "0,1"
bitfld.long 0x00 16.--20. "DBRP,Data bit rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DSJW,Data (re)synchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "TEST,Test Register"
bitfld.long 0x00 7. "RX,Monitors the actual value of the CAN_RXD" "0,1"
bitfld.long 0x00 5.--6. "TX,Control of transmit pin" "0,1,2,3"
bitfld.long 0x00 4. "LBCK,Loop back mode" "0,1"
group.long 0x18++0x03
line.long 0x00 "CCCR,CC Control Register"
bitfld.long 0x00 15. "NISO,Non ISO operation" "0,1"
bitfld.long 0x00 14. "TXP,Transmit pause" "0,1"
bitfld.long 0x00 13. "EFBI,Edge filtering during bus integration" "0,1"
bitfld.long 0x00 12. "PXHD,Protocol exception handling disable" "0,1"
bitfld.long 0x00 9. "BRSE,When CAN FD operation is disabled this bit is not evaluated" "0,1"
bitfld.long 0x00 8. "FDOE,CAN FD operation enable" "0,1"
bitfld.long 0x00 7. "TEST,Test mode enable" "0,1"
bitfld.long 0x00 6. "DAR,Disable automatic retransmission" "0,1"
bitfld.long 0x00 5. "MON,Bus monitoring mode" "0,1"
bitfld.long 0x00 4. "CSR,Clock Stop Request" "0,1"
bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x00 2. "ASM,Restricted operational mode" "0,1"
newline
bitfld.long 0x00 1. "CCE,Configuration change enable" "0,1"
bitfld.long 0x00 0. "INIT,Initialization" "0,1"
group.long 0x1C++0x03
line.long 0x00 "NBTP,Nominal Bit Timing and Prescaler Register"
hexmask.long.byte 0x00 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
hexmask.long.word 0x00 16.--24. 1. "NBRP,Nominal bit rate prescaler"
hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
hexmask.long.byte 0x00 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
group.long 0x20++0x03
line.long 0x00 "TSCC,Timestamp Counter Configuration"
bitfld.long 0x00 16.--19. "TCP,Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TSS,Timestamp select" "0,1,2,3"
group.long 0x24++0x03
line.long 0x00 "TSCV,Timestamp Counter Value"
hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp counter"
group.long 0x28++0x03
line.long 0x00 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout period"
bitfld.long 0x00 1.--2. "TOS,Timeout select" "0,1,2,3"
bitfld.long 0x00 0. "ETOC,Enable timeout counter" "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "TOCV,Timeout Counter Value"
hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout counter"
rgroup.long 0x40++0x03
line.long 0x00 "ECR,Error Counter Register"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN error logging"
bitfld.long 0x00 15. "RP,Receive error passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive error counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit error counter"
rgroup.long 0x44++0x03
line.long 0x00 "PSR,Protocol Status Register"
hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter delay compensation value"
bitfld.long 0x00 14. "PXE,Protocol exception event" "0,1"
bitfld.long 0x00 13. "RFDF,Received a CAN FD message" "0,1"
bitfld.long 0x00 12. "RBRS,BRS flag of last received CAN FD message" "0,1"
bitfld.long 0x00 11. "RESI,ESI flag of the last received CAN FD message" "0,1"
bitfld.long 0x00 8.--10. "DLEC,Data phase last error code" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "BO,Bus Off Status" "0,1"
bitfld.long 0x00 6. "EW,Warning status" "0,1"
bitfld.long 0x00 5. "EP,Error Passive" "0,1"
bitfld.long 0x00 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x00 0.--2. "LEC,Last error code" "0,1,2,3,4,5,6,7"
group.long 0x48++0x03
line.long 0x00 "TDCR,Transmitter Delay Compensator Register"
hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter delay compensation offset"
hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
group.long 0x50++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 29. "ARA,Access to reserved address" "0,1"
bitfld.long 0x00 28. "PED,Protocol error in data phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol error in arbitration phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog interrupt" "0,1"
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning status" "0,1"
bitfld.long 0x00 23. "EP,Error passive" "0,1"
bitfld.long 0x00 22. "ELO,Error logging overflow" "0,1"
bitfld.long 0x00 21. "BEU,Bit error uncorrected" "0,1"
bitfld.long 0x00 20. "BEC,Bit error corrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored in dedicated Rx buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout occurred" "0,1"
newline
bitfld.long 0x00 17. "MRAF,Message RAM access failure" "0,1"
bitfld.long 0x00 16. "TSW,Timestamp wraparound" "0,1"
bitfld.long 0x00 15. "TEFL,Tx event FIFO element lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx event FIFO full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx event FIFO watermark reached" "0,1"
bitfld.long 0x00 12. "TEFN,Tx event FIFO new entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO empty" "0,1"
bitfld.long 0x00 10. "TCF,Transmission cancellation finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission completed" "0,1"
bitfld.long 0x00 8. "HPM,High priority message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 message lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 full" "0,1"
newline
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 watermark reached" "0,1"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 new message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 message lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 watermark reached" "0,1"
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 new message" "0,1"
group.long 0x54++0x03
line.long 0x00 "IE,Interrupt Enable"
bitfld.long 0x00 29. "ARAE,Access to reserved address interrupt enable" "0,1"
bitfld.long 0x00 28. "PEDE,Protocol error in data phase interrupt enable" "0,1"
bitfld.long 0x00 27. "PEAE,Protocol error in arbitration phase interrupt enable" "0,1"
bitfld.long 0x00 26. "WDIE,Watchdog interrupt enable" "0,1"
bitfld.long 0x00 25. "BOE,Bus_Off Status interrupt enable" "0,1"
bitfld.long 0x00 24. "EWE,Warning status interrupt enable" "0,1"
bitfld.long 0x00 23. "EPE,Error passive interrupt enable" "0,1"
bitfld.long 0x00 22. "ELOE,Error logging overflow interrupt enable" "0,1"
bitfld.long 0x00 21. "BEUE,Bit error uncorrected interrupt enable" "0,1"
bitfld.long 0x00 20. "BECE,Bit error corrected interrupt enable" "0,1"
bitfld.long 0x00 19. "DRXE,Message stored in dedicated Rx buffer interrupt enable" "0,1"
bitfld.long 0x00 18. "TOOE,Timeout occurred interrupt enable" "0,1"
newline
bitfld.long 0x00 17. "MRAFE,Message RAM access failure interrupt enable" "0,1"
bitfld.long 0x00 16. "TSWE,Timestamp wraparound interrupt enable" "0,1"
bitfld.long 0x00 15. "TEFLE,Tx event FIFO element lost interrupt enable" "0,1"
bitfld.long 0x00 14. "TEFFE,Tx event FIFO full interrupt enable" "0,1"
bitfld.long 0x00 13. "TEFWE,Tx event FIFO watermark reached interrupt enable" "0,1"
bitfld.long 0x00 12. "TEFNE,Tx event FIFO new entry interrupt enable" "0,1"
bitfld.long 0x00 11. "TFEE,Tx FIFO empty interrupt enable" "0,1"
bitfld.long 0x00 10. "TCFE,Transmission cancellation finished interrupt enable" "0,1"
bitfld.long 0x00 9. "TCE,Transmission completed interrupt enable" "0,1"
bitfld.long 0x00 8. "HPME,High priority message interrupt enable" "0,1"
bitfld.long 0x00 7. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0,1"
bitfld.long 0x00 6. "RF1FE,Rx FIFO 1 full interrupt enable" "0,1"
newline
bitfld.long 0x00 5. "RF1WE,Rx FIFO 1 watermark reached interrupt enable" "0,1"
bitfld.long 0x00 4. "RF1NE,Rx FIFO 1 new message interrupt enable" "0,1"
bitfld.long 0x00 3. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0,1"
bitfld.long 0x00 2. "RF0FE,Rx FIFO 0 full interrupt enable" "0,1"
bitfld.long 0x00 1. "RF0WE,Rx FIFO 0 watermark reached interrupt enable" "0,1"
bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0,1"
group.long 0x58++0x03
line.long 0x00 "ILS,Interrupt Line Select"
bitfld.long 0x00 29. "ARAL,Access to reserved address interrupt line" "0,1"
bitfld.long 0x00 28. "PEDL,Protocol error in data phase interrupt line" "0,1"
bitfld.long 0x00 27. "PEAL,Protocol error in arbitration phase interrupt line" "0,1"
bitfld.long 0x00 26. "WDIL,Watchdog interrupt line" "0,1"
bitfld.long 0x00 25. "BOL,Bus_Off Status interrupt line" "0,1"
bitfld.long 0x00 24. "EWL,Warning status interrupt line" "0,1"
bitfld.long 0x00 23. "EPL,Error passive interrupt line" "0,1"
bitfld.long 0x00 22. "ELOL,Error logging overflow interrupt line" "0,1"
bitfld.long 0x00 21. "BEUL,Bit error uncorrected interrupt line" "0,1"
bitfld.long 0x00 20. "BECL,Bit error corrected interrupt line" "0,1"
bitfld.long 0x00 19. "DRXL,Message stored in dedicated Rx buffer interrupt line" "0,1"
bitfld.long 0x00 18. "TOOL,Timeout occurred interrupt line" "0,1"
newline
bitfld.long 0x00 17. "MRAFL,Message RAM access failure interrupt line" "0,1"
bitfld.long 0x00 16. "TSWL,Timestamp wraparound interrupt line" "0,1"
bitfld.long 0x00 15. "TEFLL,Tx event FIFO element lost interrupt line" "0,1"
bitfld.long 0x00 14. "TEFFL,Tx event FIFO full interrupt line" "0,1"
bitfld.long 0x00 13. "TEFWL,Tx event FIFO watermark reached interrupt line" "0,1"
bitfld.long 0x00 12. "TEFNL,Tx event FIFO new entry interrupt line" "0,1"
bitfld.long 0x00 11. "TFEL,Tx FIFO empty interrupt line" "0,1"
bitfld.long 0x00 10. "TCFL,Transmission cancellation finished interrupt line" "0,1"
bitfld.long 0x00 9. "TCL,Transmission completed interrupt line" "0,1"
bitfld.long 0x00 8. "HPML,High priority message interrupt line" "0,1"
bitfld.long 0x00 7. "RF1LL,Rx FIFO 1 message lost interrupt line" "0,1"
bitfld.long 0x00 6. "RF1FL,Rx FIFO 1 full interrupt line" "0,1"
newline
bitfld.long 0x00 5. "RF1WL,Rx FIFO 1 watermark reached interrupt line" "0,1"
bitfld.long 0x00 4. "RF1NL,Rx FIFO 1 new message interrupt line" "0,1"
bitfld.long 0x00 3. "RF0LL,Rx FIFO 0 message lost interrupt line" "0,1"
bitfld.long 0x00 2. "RF0FL,Rx FIFO 0 full interrupt line" "0,1"
bitfld.long 0x00 1. "RF0WL,Rx FIFO 0 watermark reached interrupt line" "0,1"
bitfld.long 0x00 0. "RF0NL,Rx FIFO 0 new message interrupt line" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ILE,Interrupt Line Enable"
bitfld.long 0x00 1. "EINT1,Enable interrupt line 1" "0,1"
bitfld.long 0x00 0. "EINT0,Enable interrupt line 0" "0,1"
group.long 0x80++0x03
line.long 0x00 "GFC,Global Filter Configuration"
bitfld.long 0x00 4.--5. "ANFS,Accept non-matching frames standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept non-matching frames extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,Reject remote frames standard" "0,1"
bitfld.long 0x00 0. "RRFE,Reject remote frames extended" "0,1"
group.long 0x84++0x03
line.long 0x00 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x00 16.--23. 1. "LSS,List size standard"
hexmask.long.word 0x00 2.--15. 1. "FLSSA,Filter list standard start address"
group.long 0x88++0x03
line.long 0x00 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x00 16.--23. 1. "LSE,List size extended"
hexmask.long.word 0x00 2.--15. 1. "FLESA,Filter list extended start address"
group.long 0x90++0x03
line.long 0x00 "XIDAM,Extended ID AND Mask"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID mask"
rgroup.long 0x94++0x03
line.long 0x00 "HPMS,High Priority Message Status"
bitfld.long 0x00 15. "FLST,Filter list" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "FIDX,Filter index"
bitfld.long 0x00 6.--7. "MSI,Message storage indicator" "0,1,2,3"
bitfld.long 0x00 0.--5. "BIDX,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x98)++0x03
line.long 0x00 "NDAT$1,New Data $1"
hexmask.long 0x00 0.--31. 1. "ND,New Data"
repeat.end
group.long 0xA0++0x03
line.long 0x00 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x00 31. "F0OM,FIFO 0 operation mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 watermark"
hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 size"
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 start address"
group.long 0xA4++0x03
line.long 0x00 "RXF0S,Rx FIFO 0 Status"
rbitfld.long 0x00 25. "RF0L,Rx FIFO 0 message lost" "0,1"
rbitfld.long 0x00 24. "F0F,Rx FIFO 0 full" "0,1"
rbitfld.long 0x00 16.--21. "F0PI,Rx FIFO 0 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 8.--13. "F0GI,Rx FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--6. 1. "F0FL,Rx FIFO 0 fill level"
group.long 0xA8++0x03
line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge"
bitfld.long 0x00 0.--5. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAC++0x03
line.long 0x00 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x00 2.--15. 1. "RBSA,Rx buffer start address"
group.long 0xB0++0x03
line.long 0x00 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x00 31. "F1OM,FIFO 1 operation mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "F1WM,Rx FIFO 1 watermark"
hexmask.long.byte 0x00 16.--22. 1. "F1S,Rx FIFO 1 size"
hexmask.long.word 0x00 2.--15. 1. "F1SA,Rx FIFO 1 start address"
rgroup.long 0xB4++0x03
line.long 0x00 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x00 25. "RF1L,Rx FIFO 1 message lost" "0,1"
bitfld.long 0x00 24. "F1F,Rx FIFO 1 full" "0,1"
bitfld.long 0x00 16.--21. "F1PI,Rx FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "F1GI,Rx FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--6. 1. "F1FL,Rx FIFO 1 fill level"
group.long 0xB8++0x03
line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge"
bitfld.long 0x00 0.--5. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBC++0x03
line.long 0x00 "RXESC,Rx Buffer and FIFO Element Size Configuration"
bitfld.long 0x00 8.--10. "RBDS," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "F1DS,Rx FIFO 1 data field size" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "F0DS,Rx FIFO 0 data field size" "0,1,2,3,4,5,6,7"
group.long 0xC0++0x03
line.long 0x00 "TXBC,Tx Buffer Configuration"
bitfld.long 0x00 30. "TFQM,Tx FIFO/queue mode" "0,1"
bitfld.long 0x00 24.--29. "TFQS,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "NDTB,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "TBSA,Tx buffers start address"
group.long 0xC4++0x03
line.long 0x00 "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0x00 21. "TFQF,Tx FIFO/queue full" "0,1"
bitfld.long 0x00 16.--20. "TFQPI,Tx FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "TFGI,Tx FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC8++0x03
line.long 0x00 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x00 0.--2. "TBDS,Tx buffer data field size" "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x03
line.long 0x00 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x00 0.--31. 1. "TRP,Transmission request pending"
group.long 0xD0++0x03
line.long 0x00 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x00 0.--31. 1. "AR,Add request"
group.long 0xD4++0x03
line.long 0x00 "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x00 0.--31. 1. "CR,Cancellation request"
rgroup.long 0xD8++0x03
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x00 0.--31. 1. "TO,Transmission occurred"
rgroup.long 0xDC++0x03
line.long 0x00 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x00 0.--31. 1. "TO,Cancellation finished"
group.long 0xE0++0x03
line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x00 0.--31. 1. "TIE,Transmission interrupt enable"
group.long 0xE4++0x03
line.long 0x00 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x00 0.--31. 1. "CFIE,Cancellation finished interrupt enable"
group.long 0xF0++0x03
line.long 0x00 "TXEFC,Tx Event FIFO Configuration"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO start address"
rgroup.long 0xF4++0x03
line.long 0x00 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x00 25. "TEFL,Tx event FIFO element lost" "0,1"
bitfld.long 0x00 24. "EFF,Event FIFO full" "0,1"
bitfld.long 0x00 16.--21. "EFPI,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--12. "EFGI,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF8++0x03
line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge"
bitfld.long 0x00 0.--4. "EFAI,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x200++0x03
line.long 0x00 "MRBA,CAN Message RAM Base Address"
hexmask.long.word 0x00 16.--31. 1. "BA,Base address for the message RAM in the chip memory map"
group.long 0x400++0x03
line.long 0x00 "ETSCC,External Timestamp Counter Configuration"
bitfld.long 0x00 31. "ETCE,External timestamp counter enable" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ETCP,External timestamp prescaler value"
group.long 0x600++0x03
line.long 0x00 "ETSCV,External Timestamp Counter Value"
hexmask.long.word 0x00 0.--15. 1. "ETSC,External timestamp counter"
tree.end
endif
tree "CASPER"
base ad:0x400A5000
group.long 0x00++0x03
line.long 0x00 "CTRL0,Contains the offsets of AB and CD in the RAM"
hexmask.long.word 0x00 18.--28. 1. "CDOFF,Word or DWord Offset of CD with D at [2]=0 and C at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB)"
bitfld.long 0x00 16. "CDBPAIR,Which bank-pair the offset CDOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
hexmask.long.word 0x00 2.--12. 1. "ABOFF,Word or DWord Offset of AB values with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB)"
newline
bitfld.long 0x00 0. "ABBPAIR,Which bank-pair the offset ABOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
group.long 0x04++0x03
line.long 0x00 "CTRL1,Contains the opcode mode iteration count and result offset (in RAM) and also launches the accelerator"
bitfld.long 0x00 30.--31. "CSKIP,Skip rules on Carry if needed" "0: NO_SKIP,1: Skip if Carry is 1,2: Skip if Carry is 0,3: Set CTRLOFF to CDOFF and Skip"
hexmask.long.word 0x00 18.--28. 1. "RESOFF,Word or DWord Offset of result"
bitfld.long 0x00 16. "RESBPAIR,Which bank-pair the offset RESOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
newline
hexmask.long.byte 0x00 8.--15. 1. "MODE,Operation mode to perform"
hexmask.long.byte 0x00 0.--7. 1. "ITER,Iteration counter"
group.long 0x08++0x03
line.long 0x00 "LOADER,Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations"
hexmask.long.word 0x00 18.--28. 1. "CTRLOFF,DWord Offset of CTRL pair to load next"
bitfld.long 0x00 16. "CTRLBPAIR,Which bank-pair the offset CTRLOFF is within" "0: Bank-pair 0 (1st),1: Bank-pair 1 (2nd)"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Number of control pairs to load 0 relative (so 1 means load 1)"
group.long 0x0C++0x03
line.long 0x00 "STATUS,Indicates operational status and would contain the carry bit if used"
rbitfld.long 0x00 5. "BUSY,Indicates if the accelerator is busy performing an operation" "0: Not busy - is idle,1: Is busy"
rbitfld.long 0x00 4. "CARRY,Last carry value if operation produced a carry bit" "0: Carry was 0 or no carry,1: Carry was 1"
bitfld.long 0x00 0. "DONE,Indicates if the accelerator has finished an operation" "0: Busy or just cleared,1: Completed last operation"
group.long 0x10++0x03
line.long 0x00 "INTENSET,Sets interrupts"
bitfld.long 0x00 0. "DONE,Set if the accelerator should interrupt when done" "0: Do not interrupt when done,1: Interrupt when done"
group.long 0x14++0x03
line.long 0x00 "INTENCLR,Clears interrupts"
eventfld.long 0x00 0. "DONE,Written to clear an interrupt set with INTENSET" "0: If written 0 ignored,1: If written 1 do not Interrupt when done"
group.long 0x18++0x03
line.long 0x00 "INTSTAT,Interrupt status bits (mask of INTENSET and STATUS)"
rbitfld.long 0x00 0. "DONE,If set interrupt is caused by accelerator being done" "0: Not caused by accelerator being done,1: Caused by accelerator being done"
group.long 0x20++0x03
line.long 0x00 "AREG,A register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register to be fed into Multiplier"
group.long 0x24++0x03
line.long 0x00 "BREG,B register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register to be fed into Multiplier"
group.long 0x28++0x03
line.long 0x00 "CREG,C register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register to be fed into Multiplier"
group.long 0x2C++0x03
line.long 0x00 "DREG,D register"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register to be fed into Multiplier"
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x30)++0x03
line.long 0x00 "RES$1,Result register $1"
hexmask.long 0x00 0.--31. 1. "REG_VALUE,Register to hold working result (from multiplier adder/xor etc)"
repeat.end
group.long 0x60++0x03
line.long 0x00 "MASK,Optional mask register"
hexmask.long 0x00 0.--31. 1. "MASK,Mask to apply as side channel countermeasure"
group.long 0x64++0x03
line.long 0x00 "REMASK,Optional re-mask register"
hexmask.long 0x00 0.--31. 1. "MASK,Mask to apply as side channel countermeasure"
group.long 0x80++0x03
line.long 0x00 "LOCK,Security lock register"
hexmask.long.word 0x00 4.--16. 1. "KEY,Must be written as 0x73D to change the register"
bitfld.long 0x00 0. "LOCK,Reads back with security level locked to or 0" "0: UNLOCK,1: Lock to current security level"
tree.end
sif cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")
tree "CDOG"
base ad:0x400A1000
group.long 0x00++0x03
line.long 0x00 "CONTROL,The control fields which constitute CONTROL control all controllable attributes of the module including those of CONTROL itself"
bitfld.long 0x00 30.--31. "DEBUG_HALT_CTRL,DEBUG_HALT control field" "0,1,2,3"
bitfld.long 0x00 28.--29. "IRQ_PAUSE,IRQ pause control field" "0,1,2,3"
bitfld.long 0x00 17.--19. "ADDRESS_CTRL,ADDRESS control field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "STATE_CTRL,STATE control field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11.--13. "CONTROL_CTRL,CONTROL control field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "SEQUENCE_CTRL,SEQUENCE control field" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5.--7. "MISCOMPARE_CTRL,MISCOMPARE control field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2.--4. "TIMEOUT_CTRL,TIMEOUT control" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--1. "LOCK_CTRL,Lock control field" "0,1,2,3"
group.long 0x04++0x03
line.long 0x00 "RELOAD,Instruction timer reload"
hexmask.long 0x00 0.--31. 1. "RLOAD,Inst"
group.long 0x08++0x03
line.long 0x00 "INSTRUCTION_TIMER,The INSTRUCTION TIMER itself"
hexmask.long 0x00 0.--31. 1. "INSTIM,INSTRUCTION TIMER 32-bit value"
group.long 0x0C++0x03
line.long 0x00 "SECURE_COUNTER,Also known as SEC_CNT"
hexmask.long 0x00 0.--31. 1. "SECCNT,Secure Counter"
rgroup.long 0x10++0x03
line.long 0x00 "STATUS,Status register (1 of 2)"
bitfld.long 0x00 28.--31. "CURST,Current State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. "NUMILSEQF,Number of illegal sequence faults"
hexmask.long.byte 0x00 8.--15. 1. "NUMMISCOMPF,Number of Miscompare Faults"
hexmask.long.byte 0x00 0.--7. 1. "NUMTOF,Number of Timeout Faults"
rgroup.long 0x14++0x03
line.long 0x00 "STATUS2,STATUS register (2 of 2)"
hexmask.long.byte 0x00 16.--23. 1. "NUMILLA,Number of (illegal) address faults"
hexmask.long.byte 0x00 8.--15. 1. "NUMILLSTF,Number (of) state faults"
hexmask.long.byte 0x00 0.--7. 1. "NUMCNTF,Number (of) control faults"
group.long 0x18++0x03
line.long 0x00 "FLAGS,Hardware flags"
bitfld.long 0x00 16. "POR_FLAG,Power-on reset flag" "0,1"
bitfld.long 0x00 5. "ADDR_FLAG,Address flag" "0,1"
bitfld.long 0x00 4. "STATE_FLAG,State flag" "0,1"
bitfld.long 0x00 3. "CNT_FLAG,Control (fault) flag" "0,1"
bitfld.long 0x00 2. "SEQ_FLAG,Sequence flag" "0,1"
bitfld.long 0x00 1. "MISCOM_FLAG,Miscompare flag" "0,1"
newline
bitfld.long 0x00 0. "TO_FLAG,Timeout flag" "0,1"
group.long 0x1C++0x03
line.long 0x00 "PERSISTENT,Persistent (Ad. Hoc. quasi-NV) data storage"
hexmask.long 0x00 0.--31. 1. "PERSIS,32 regs free for user SW to enjoy"
wgroup.long 0x20++0x03
line.long 0x00 "START,Write address for issuing the START command"
hexmask.long 0x00 0.--31. 1. "STRT,Address of start command access"
wgroup.long 0x24++0x03
line.long 0x00 "STOP,Write address for issuing the STOP command"
hexmask.long 0x00 0.--31. 1. "STP,Address of stop command access"
wgroup.long 0x28++0x03
line.long 0x00 "RESTART,Write address for issuing the RESTART command"
hexmask.long 0x00 0.--31. 1. "RSTRT,Write address for issuing the RESTART command"
wgroup.long 0x2C++0x03
line.long 0x00 "ADD,Write address for issuing the ADD command"
hexmask.long 0x00 0.--31. 1. "AD,Address of ADD command"
wgroup.long 0x30++0x03
line.long 0x00 "ADD1,Write address for issuing the ADD1 command"
hexmask.long 0x00 0.--31. 1. "AD1,Address of ADD1 command"
wgroup.long 0x34++0x03
line.long 0x00 "ADD16,Write address for issuing the ADD16 command"
hexmask.long 0x00 0.--31. 1. "AD16,Address of ADD16"
wgroup.long 0x38++0x03
line.long 0x00 "ADD256,Write address for issuing the ADD16 command"
hexmask.long 0x00 0.--31. 1. "AD256,Address of ADD256 command"
wgroup.long 0x3C++0x03
line.long 0x00 "SUB,Write address for issuing the SUB command"
hexmask.long 0x00 0.--31. 1. "S0B,Address of SUB command"
wgroup.long 0x40++0x03
line.long 0x00 "SUB1,Write address for issuing the SUB1 command"
hexmask.long 0x00 0.--31. 1. "S1B,Address of SUB1 command"
wgroup.long 0x44++0x03
line.long 0x00 "SUB16,Write address for issuing the SUB16 command"
hexmask.long 0x00 0.--31. 1. "SB16,Address of SUB16 command"
wgroup.long 0x48++0x03
line.long 0x00 "SUB256,Write address for issuing the SUB256 command"
hexmask.long 0x00 0.--31. 1. "SB256,Address of (you guessed it) SUB256 command"
tree.end
endif
tree "CRC (CRC engine)"
base ad:0x40095000
group.long 0x00++0x03
line.long 0x00 "MODE,CRC mode register"
bitfld.long 0x00 5. "CMPL_SUM,CRC sum complement" "0: No 1's complement for CRC_SUM,1: 1's complement for CRC_SUM"
bitfld.long 0x00 4. "BIT_RVS_SUM,CRC sum bit order" "0: No bit order reverse for CRC_SUM,1: Bit order reverse for CRC_SUM"
newline
bitfld.long 0x00 3. "CMPL_WR,Data complement" "0: No 1's complement for CRC_WR_DATA,1: 1's complement for CRC_WR_DATA"
bitfld.long 0x00 2. "BIT_RVS_WR,Data bit order" "0: No bit order reverse for CRC_WR_DATA (per byte),1: Bit order reverse for CRC_WR_DATA (per byte)"
newline
bitfld.long 0x00 0.--1. "CRC_POLY,CRC polynomial: 1X = CRC-32 polynomial" "0: CRC-CCITT polynomial,1: CRC-16 polynomial,?..."
group.long 0x04++0x03
line.long 0x00 "SEED,CRC seed register"
hexmask.long 0x00 0.--31. 1. "CRC_SEED,A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes"
rgroup.long 0x08++0x03
line.long 0x00 "SUM,CRC checksum register"
hexmask.long 0x00 0.--31. 1. "CRC_SUM,The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes"
wgroup.long 0x08++0x03
line.long 0x00 "WR_DATA,CRC data register"
hexmask.long 0x00 0.--31. 1. "CRC_WR_DATA,Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process"
tree.end
tree "CTIMER (Standard counter/timers)"
repeat 5. (list 0. 1. 2. 3. 4.) (list ad:0x40008000 ad:0x40009000 ad:0x40028000 ad:0x40029000 ad:0x4002A000)
tree "CTIMER$1"
base $2
group.long 0x00++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 7. "CR3INT,Interrupt flag for capture channel 3 event" "0,1"
bitfld.long 0x00 6. "CR2INT,Interrupt flag for capture channel 2 event" "0,1"
bitfld.long 0x00 5. "CR1INT,Interrupt flag for capture channel 1 event" "0,1"
bitfld.long 0x00 4. "CR0INT,Interrupt flag for capture channel 0 event" "0,1"
newline
bitfld.long 0x00 3. "MR3INT,Interrupt flag for match channel 3" "0,1"
bitfld.long 0x00 2. "MR2INT,Interrupt flag for match channel 2" "0,1"
bitfld.long 0x00 1. "MR1INT,Interrupt flag for match channel 1" "0,1"
bitfld.long 0x00 0. "MR0INT,Interrupt flag for match channel 0" "0,1"
group.long 0x04++0x03
line.long 0x00 "TCR,Timer Control Register"
bitfld.long 0x00 1. "CRST,Counter reset" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "CEN,Counter enable" "0: Disabled.The counters are disabled,1: Enabled"
group.long 0x08++0x03
line.long 0x00 "TC,Timer Counter"
hexmask.long 0x00 0.--31. 1. "TCVAL,Timer counter value"
group.long 0x0C++0x03
line.long 0x00 "PR,Prescale Register"
hexmask.long 0x00 0.--31. 1. "PRVAL,Prescale counter value"
group.long 0x10++0x03
line.long 0x00 "PC,Prescale Counter"
hexmask.long 0x00 0.--31. 1. "PCVAL,Prescale counter value"
group.long 0x14++0x03
line.long 0x00 "MCR,Match Control Register"
bitfld.long 0x00 27. "MR3RL,Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)" "0,1"
bitfld.long 0x00 26. "MR2RL,Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)" "0,1"
bitfld.long 0x00 25. "MR1RL,Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)" "0,1"
bitfld.long 0x00 24. "MR0RL,Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero (either via a match event or a write to bit 1 of the TCR)" "0,1"
newline
bitfld.long 0x00 11. "MR3S,Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC" "0,1"
bitfld.long 0x00 10. "MR3R,Reset on MR3: the TC will be reset if MR3 matches it" "0,1"
bitfld.long 0x00 9. "MR3I,Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC" "0,1"
bitfld.long 0x00 8. "MR2S,Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" "0,1"
newline
bitfld.long 0x00 7. "MR2R,Reset on MR2: the TC will be reset if MR2 matches it" "0,1"
bitfld.long 0x00 6. "MR2I,Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC" "0,1"
bitfld.long 0x00 5. "MR1S,Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC" "0,1"
bitfld.long 0x00 4. "MR1R,Reset on MR1: the TC will be reset if MR1 matches it" "0,1"
newline
bitfld.long 0x00 3. "MR1I,Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC" "0,1"
bitfld.long 0x00 2. "MR0S,Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC" "0,1"
bitfld.long 0x00 1. "MR0R,Reset on MR0: the TC will be reset if MR0 matches it" "0,1"
bitfld.long 0x00 0. "MR0I,Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC" "0,1"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x18)++0x03
line.long 0x00 "MR[$1],Match Register"
hexmask.long 0x00 0.--31. 1. "MATCH,Timer counter match value"
repeat.end
group.long 0x28++0x03
line.long 0x00 "CCR,Capture Control Register"
bitfld.long 0x00 11. "CAP3I,Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt" "0,1"
bitfld.long 0x00 10. "CAP3FE,Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC" "0: disabled,1: enabled"
bitfld.long 0x00 9. "CAP3RE,Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC" "0: disabled,1: enabled"
bitfld.long 0x00 8. "CAP2I,Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt" "0,1"
newline
bitfld.long 0x00 7. "CAP2FE,Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC" "0: disabled,1: enabled"
bitfld.long 0x00 6. "CAP2RE,Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC" "0: disabled,1: enabled"
bitfld.long 0x00 5. "CAP1I,Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt" "0,1"
bitfld.long 0x00 4. "CAP1FE,Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC" "0: disabled,1: enabled"
newline
bitfld.long 0x00 3. "CAP1RE,Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC" "0: disabled,1: enabled"
bitfld.long 0x00 2. "CAP0I,Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt" "0,1"
bitfld.long 0x00 1. "CAP0FE,Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC" "0: disabled,1: enabled"
bitfld.long 0x00 0. "CAP0RE,Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC" "0: disabled,1: enabled"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x2C)++0x03
line.long 0x00 "CR[$1],Capture Register"
hexmask.long 0x00 0.--31. 1. "CAP,Timer counter capture value"
repeat.end
group.long 0x3C++0x03
line.long 0x00 "EMR,External Match Register"
bitfld.long 0x00 10.--11. "EMC3,External Match Control 3" "0: Do Nothing,1: Clear,2: Set,3: Toggle"
bitfld.long 0x00 8.--9. "EMC2,External Match Control 2" "0: Do Nothing,1: Clear,2: Set,3: Toggle"
bitfld.long 0x00 6.--7. "EMC1,External Match Control 1" "0: Do Nothing,1: Clear,2: Set,3: Toggle"
bitfld.long 0x00 4.--5. "EMC0,External Match Control 0" "0: Do Nothing,1: Clear,2: Set,3: Toggle"
newline
bitfld.long 0x00 3. "EM3,External Match 3" "0: LOW,1: HIGH"
bitfld.long 0x00 2. "EM2,External Match 2" "0: LOW,1: HIGH"
bitfld.long 0x00 1. "EM1,External Match 1" "0: LOW,1: HIGH"
bitfld.long 0x00 0. "EM0,External Match 0" "0: LOW,1: HIGH"
group.long 0x70++0x03
line.long 0x00 "CTCR,Count Control Register"
bitfld.long 0x00 5.--7. "SELCC,Edge select" "0: Channel 0 Rising Edge,1: Channel 0 Falling Edge,2: Channel 1 Rising Edge,3: Channel 1 Falling Edge,4: Channel 2 Rising Edge,5: Channel 2 Falling Edge,?..."
bitfld.long 0x00 4. "ENCC,Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs" "0,1"
bitfld.long 0x00 2.--3. "CINSEL,Count Input Select When bits 1:0 in this register are not 00 these bits select which CAP pin is sampled for clocking" "0: Channel 0,1: Channel 1,2: Channel 2,3: Channel 3"
bitfld.long 0x00 0.--1. "CTMODE,Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC) or clear PC and increment Timer Counter (TC)" "0: Timer Mode,1: Counter Mode rising edge,2: Counter Mode falling edge,3: Counter Mode dual edge"
group.long 0x74++0x03
line.long 0x00 "PWMC,PWM Control Register"
bitfld.long 0x00 3. "PWMEN3,PWM mode enable for channel3" "0: Match,1: PWM"
bitfld.long 0x00 2. "PWMEN2,PWM mode enable for channel2" "0: Match,1: PWM"
bitfld.long 0x00 1. "PWMEN1,PWM mode enable for channel1" "0: Match,1: PWM"
bitfld.long 0x00 0. "PWMEN0,PWM mode enable for channel0" "0: Match,1: PWM"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x78)++0x03
line.long 0x00 "MSR[$1],Match Shadow Register $1"
hexmask.long 0x00 0.--31. 1. "SHADOW,Timer counter match shadow value"
repeat.end
tree.end
repeat.end
tree.end
tree "DBGMAILBOX (MCU Debugger Mailbox)"
base ad:0x4009C000
group.long 0x00++0x03
line.long 0x00 "CSW,CRC mode register"
bitfld.long 0x00 5. "CHIP_RESET_REQ,Write only bit" "0,1"
bitfld.long 0x00 4. "SOFT_RESET,Soft Reset for DM (write-only from AHB not readable and selfclearing)" "0,1"
bitfld.long 0x00 3. "AHB_OR_ERR,AHB overrun Error (Return value overwritten by ROM)" "0,1"
bitfld.long 0x00 2. "DBG_OR_ERR,Debugger overrun error (previous REQUEST overwritten before being picked up by ROM)" "0,1"
bitfld.long 0x00 1. "REQ_PENDING,Request is pending from debugger (i.e unread value in REQUEST)" "0,1"
bitfld.long 0x00 0. "RESYNCH_REQ,Debugger will set this bit to 1 to request a resynchronrisation" "0,1"
group.long 0x04++0x03
line.long 0x00 "REQUEST,CRC seed register"
hexmask.long 0x00 0.--31. 1. "REQ,Request Value"
group.long 0x08++0x03
line.long 0x00 "RETURN,Return value from ROM"
hexmask.long 0x00 0.--31. 1. "RET,The Return value from ROM"
rgroup.long 0xFC++0x03
line.long 0x00 "ID,Identification register"
hexmask.long 0x00 0.--31. 1. "ID,Identification value"
tree.end
tree "DMA (DMA controller)"
repeat 2. (list 0. 1.) (list ad:0x40082000 ad:0x400A7000)
tree "DMA$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTRL,DMA control"
bitfld.long 0x00 0. "ENABLE,DMA controller master enable" "0: Disabled,1: Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "INTSTAT,Interrupt status"
bitfld.long 0x00 2. "ACTIVEERRINT,Summarizes whether any error interrupts are pending" "0: Not pending,1: Pending"
bitfld.long 0x00 1. "ACTIVEINT,Summarizes whether any enabled interrupts (other than error interrupts) are pending" "0: Not pending,1: Pending"
group.long 0x08++0x03
line.long 0x00 "SRAMBASE,SRAM address of the channel configuration table"
hexmask.long.tbyte 0x00 9.--31. 1. "OFFSET,Address bits 31:9 of the beginning of the DMA descriptor table"
group.long 0x20++0x03
line.long 0x00 "ENABLESET0,Channel Enable read and Set for all DMA channels"
abitfld.long 0x00 0.--31. "ENA,Enable for DMA channels" "0x00000000=0: disabled,0x00000001=1: enabled"
wgroup.long 0x28++0x03
line.long 0x00 "ENABLECLR0,Channel Enable Clear for all DMA channels"
hexmask.long 0x00 0.--31. 1. "CLR,Writing ones to this register clears the corresponding bits in ENABLESET0"
rgroup.long 0x30++0x03
line.long 0x00 "ACTIVE0,Channel Active status for all DMA channels"
abitfld.long 0x00 0.--31. "ACT,Active flag for DMA channel n" "0x00000000=0: not active,0x00000001=1: active"
rgroup.long 0x38++0x03
line.long 0x00 "BUSY0,Channel Busy status for all DMA channels"
abitfld.long 0x00 0.--31. "BSY,Busy flag for DMA channel n" "0x00000000=0: not busy,0x00000001=1: busy"
group.long 0x40++0x03
line.long 0x00 "ERRINT0,Error Interrupt status for all DMA channels"
abitfld.long 0x00 0.--31. "ERR,Error Interrupt flag for DMA channel n" "0x00000000=0: error interrupt is not active,0x00000001=1: error interrupt is active"
group.long 0x48++0x03
line.long 0x00 "INTENSET0,Interrupt Enable read and Set for all DMA channels"
abitfld.long 0x00 0.--31. "INTEN,Interrupt Enable read and set for DMA channel n" "0x00000000=0: interrupt for DMA channel is..,0x00000001=1: interrupt for DMA channel is enabled"
wgroup.long 0x50++0x03
line.long 0x00 "INTENCLR0,Interrupt Enable Clear for all DMA channels"
hexmask.long 0x00 0.--31. 1. "CLR,Writing ones to this register clears corresponding bits in the INTENSET0"
group.long 0x58++0x03
line.long 0x00 "INTA0,Interrupt A status for all DMA channels"
abitfld.long 0x00 0.--31. "IA,Interrupt A status for DMA channel n" "0x00000000=0: the DMA channel interrupt A is not..,0x00000001=1: the DMA channel interrupt A is.."
group.long 0x60++0x03
line.long 0x00 "INTB0,Interrupt B status for all DMA channels"
abitfld.long 0x00 0.--31. "IB,Interrupt B status for DMA channel n" "0x00000000=0: the DMA channel interrupt B is not..,0x00000001=1: the DMA channel interrupt B is.."
wgroup.long 0x68++0x03
line.long 0x00 "SETVALID0,Set ValidPending control bits for all DMA channels"
abitfld.long 0x00 0.--31. "SV,SETVALID control for DMA channel n" "0x00000000=0: no effect,0x00000001=1: sets the VALIDPENDING"
wgroup.long 0x70++0x03
line.long 0x00 "SETTRIG0,Set Trigger control bits for all DMA channels"
abitfld.long 0x00 0.--31. "TRIG,Set Trigger control bit for DMA channel 0" "0x00000000=0: no effect,0x00000001=1: sets the TRIG bit for DMA"
wgroup.long 0x78++0x03
line.long 0x00 "ABORT0,Channel Abort control for all DMA channels"
abitfld.long 0x00 0.--31. "ABORTCTRL,Abort control for DMA channel 0" "0x00000000=0: no effect,0x00000001=1: aborts DMA operations on"
repeat 23. (increment 0 1)(increment  0 0x10)
tree "CHANNEL[$1]"
group.long ($2+0x400)++0x03
line.long 0x00 "CFG,Configuration register for DMA channel"
bitfld.long 0x00 16.--18. "CHPRIORITY,Priority of this channel when multiple DMA requests are pending" "0: highest priority,?,?,?,?,?,?,7: lowest priority"
bitfld.long 0x00 15. "DSTBURSTWRAP,Destination Burst Wrap" "0: Disabled,1: Enabled"
bitfld.long 0x00 14. "SRCBURSTWRAP,Source Burst Wrap" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 8.--11. "BURSTPOWER,Burst Power is used in two ways" "0: Burst size = 1 (20),1: Burst size = 2 (21),2: Burst size = 4 (22),?,?,?,?,?,?,?,10: Burst size = 1024 (210),?..."
bitfld.long 0x00 6. "TRIGBURST,Trigger Burst" "0: Single transfer,1: Burst transfer"
bitfld.long 0x00 5. "TRIGTYPE,Trigger Type" "0: Edge,1: Level"
newline
bitfld.long 0x00 4. "TRIGPOL,Trigger Polarity" "0: Active low - falling edge,1: Active high - rising edge"
bitfld.long 0x00 1. "HWTRIGEN,Hardware Triggering Enable for this channel" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "PERIPHREQEN,Peripheral request Enable" "0: Disabled,1: Enabled"
rgroup.long ($2+0x404)++0x03
line.long 0x00 "CTLSTAT,Control and status register for DMA channel"
bitfld.long 0x00 2. "TRIG,Trigger flag" "0: Not triggered,1: Triggered"
bitfld.long 0x00 0. "VALIDPENDING,Valid pending flag for this channel" "0: No effect,1: Valid pending"
group.long ($2+0x408)++0x03
line.long 0x00 "XFERCFG,Transfer configuration register for DMA channel"
abitfld.long 0x00 16.--25. "XFERCOUNT,Total number of transfers to be performed minus 1 encoded" "0x000=0: a total of 1 transfer will be performed,0x001=1: a total of 2 transfers will be performed,0x3FF=1023: a total of 1 024 transfers will be.."
bitfld.long 0x00 14.--15. "DSTINC,Determines whether the destination address is incremented for each DMA transfer" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width"
bitfld.long 0x00 12.--13. "SRCINC,Determines whether the source address is incremented for each DMA transfer" "0: No increment,1: 1 x width,2: 2 x width,3: 4 x width"
newline
bitfld.long 0x00 8.--9. "WIDTH,Transfer width used for this DMA channel" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
bitfld.long 0x00 5. "SETINTB,Set Interrupt flag B for this channel" "0: No effect,1: Set"
bitfld.long 0x00 4. "SETINTA,Set Interrupt flag A for this channel" "0: No effect,1: Set"
newline
bitfld.long 0x00 3. "CLRTRIG,Clear Trigger" "0: Not cleared,1: Cleared"
bitfld.long 0x00 2. "SWTRIG,Software Trigger" "0: Not set,1: Set"
bitfld.long 0x00 1. "RELOAD,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "CFGVALID,Configuration Valid flag" "0: Not valid,1: Valid"
tree.end
repeat.end
tree.end
repeat.end
tree.end
tree "FLASH"
base ad:0x40034000
wgroup.long 0x00++0x03
line.long 0x00 "CMD,command register"
hexmask.long 0x00 0.--31. 1. "CMD,command register"
wgroup.long 0x04++0x03
line.long 0x00 "EVENT,event register"
bitfld.long 0x00 2. "ABORT,When bit is set a running program/erase command is aborted" "0,1"
bitfld.long 0x00 1. "WAKEUP,When bit is set the controller wakes up from whatever low power or powerdown mode was active" "0,1"
bitfld.long 0x00 0. "RST,When bit is set the controller and flash are reset" "0,1"
group.long 0x10++0x03
line.long 0x00 "STARTA,start (or only) address for next flash command"
hexmask.long.tbyte 0x00 0.--17. 1. "STARTA,Address / Start address for commands that take an address (range) as a parameter"
group.long 0x14++0x03
line.long 0x00 "STOPA,end address for next flash command if command operates on address ranges"
hexmask.long.tbyte 0x00 0.--17. 1. "STOPA,Stop address for commands that take an address range as a parameter (the word specified by STOPA is included in the address range)"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "DATAW[$1],data register word 0-7 Memory data or command parameter or command result $1"
hexmask.long 0x00 0.--31. 1. "DATAW,no description available"
repeat.end
wgroup.long 0xFD8++0x03
line.long 0x00 "INT_CLR_ENABLE,Clear interrupt enable bits"
bitfld.long 0x00 3. "ECC_ERR,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
bitfld.long 0x00 2. "DONE,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
bitfld.long 0x00 1. "ERR,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
bitfld.long 0x00 0. "FAIL,When a CLR_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is cleared" "0,1"
wgroup.long 0xFDC++0x03
line.long 0x00 "INT_SET_ENABLE,Set interrupt enable bits"
bitfld.long 0x00 3. "ECC_ERR,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
bitfld.long 0x00 2. "DONE,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
bitfld.long 0x00 1. "ERR,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
bitfld.long 0x00 0. "FAIL,When a SET_ENABLE bit is written to 1 the corresponding INT_ENABLE bit is set" "0,1"
group.long 0xFE0++0x03
line.long 0x00 "INT_STATUS,Interrupt status bits"
rbitfld.long 0x00 3. "ECC_ERR,This status bit is set if during a memory read operation (either a user-requested read or a speculative read or reads performed by a controller command) a correctable or uncorrectable error is detected by ECC decoding logic" "0,1"
rbitfld.long 0x00 2. "DONE,This status bit is set at the end of command execution" "0,1"
rbitfld.long 0x00 1. "ERR,This status bit is set if execution of an illegal command is detected" "0,1"
rbitfld.long 0x00 0. "FAIL,This status bit is set if execution of a (legal) command failed" "0,1"
group.long 0xFE4++0x03
line.long 0x00 "INT_ENABLE,Interrupt enable bits"
rbitfld.long 0x00 3. "ECC_ERR,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1"
rbitfld.long 0x00 2. "DONE,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1"
rbitfld.long 0x00 1. "ERR,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1"
rbitfld.long 0x00 0. "FAIL,If an INT_ENABLE bit is set an interrupt request will be generated if the corresponding INT_STATUS bit is high" "0,1"
wgroup.long 0xFE8++0x03
line.long 0x00 "INT_CLR_STATUS,Clear interrupt status bits"
bitfld.long 0x00 3. "ECC_ERR,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
bitfld.long 0x00 2. "DONE,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
bitfld.long 0x00 1. "ERR,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
bitfld.long 0x00 0. "FAIL,When a CLR_STATUS bit is written to 1 the corresponding INT_STATUS bit is cleared" "0,1"
wgroup.long 0xFEC++0x03
line.long 0x00 "INT_SET_STATUS,Set interrupt status bits"
bitfld.long 0x00 3. "ECC_ERR,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
bitfld.long 0x00 2. "DONE,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
bitfld.long 0x00 1. "ERR,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
bitfld.long 0x00 0. "FAIL,When a SET_STATUS bit is written to 1 the corresponding INT_STATUS bit is set" "0,1"
rgroup.long 0xFFC++0x03
line.long 0x00 "MODULE_ID,Controller+Memory module identification"
hexmask.long.word 0x00 16.--31. 1. "ID,Identifier"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture i"
tree.end
tree "FLASH_CFPA"
repeat 2. (list 0. 1.) (list ad:0x3E000 ad:0x3E200) (list ad:0x9E000 ad:0x9E200)
tree "FLASH_CFPA$1"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
base $2
elif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
base $3
endif
group.long 0x00++0x03
line.long 0x00 "HEADER,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x04++0x03
line.long 0x00 "VERSION,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x08++0x03
line.long 0x00 "S_FW_Version,Secure firmware version (Monotonic counter)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x0C++0x03
line.long 0x00 "NS_FW_Version,Non-Secure firmware version (Monotonic counter)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x10++0x03
line.long 0x00 "IMAGE_KEY_REVOKE,Image key revocation ID (Monotonic counter)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x18++0x03
line.long 0x00 "ROTKH_REVOKE,no description available"
bitfld.long 0x00 6.--7. "RoTK3_EN,RoT Key 3 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
bitfld.long 0x00 4.--5. "RoTK2_EN,RoT Key 2 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
bitfld.long 0x00 2.--3. "RoTK1_EN,RoT Key 1 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
newline
bitfld.long 0x00 0.--1. "RoTK0_EN,RoT Key 0 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
group.long 0x1C++0x03
line.long 0x00 "VENDOR_USAGE,no description available"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
hexmask.long.word 0x00 0.--15. 1. "DBG_VENDOR_USAGE,DBG_VENDOR_USAGE"
group.long 0x20++0x03
line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1"
bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 7. "FA_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
group.long 0x20++0x03
line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1"
bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
group.long 0x24++0x03
line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
group.long 0x24++0x03
line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 7. "FA_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
group.long 0x28++0x03
line.long 0x00 "ENABLE_FA_MODE,Enable FA mode"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x2C++0x03
line.long 0x00 "CMPA_PROG_IN_PROGRESS,CMPA Page programming on going"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x30++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x30++0x03
line.long 0x00 "PRINCE_REGION0_IV_HEADER0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x34++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x34++0x03
line.long 0x00 "PRINCE_REGION0_IV_HEADER1,no description available"
bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3"
group.long 0x38++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x38++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x3C++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x3C)++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x40++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE4,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x44++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x44++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x48++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY4,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x48++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x4C++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
group.long ($2+0x4C)++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "6" "7" )(list 0x0 0x4 )
group.long ($2+0x50)++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x54++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x58++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY8,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x58++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x5C++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "11" "12" )(list 0x0 0x4 )
group.long ($2+0x5C)++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x60++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x64++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE13,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x64++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x68++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x68++0x03
line.long 0x00 "PRINCE_REGION1_IV_HEADER0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x6C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x6C++0x03
line.long 0x00 "PRINCE_REGION1_IV_HEADER1,no description available"
bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3"
group.long 0x70++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x70++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x74++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "3" "4" )(list 0x0 0x4 )
group.long ($2+0x74)++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
group.long ($2+0x78)++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x7C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x80++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY4,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x80++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x84++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
group.long ($2+0x84)++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x88++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x8C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
group.long ($2+0x8C)++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x90++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x94++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x94++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x98++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x98++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE12,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x9C++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x9C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE13,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xA0++0x03
line.long 0x00 "PRINCE_REGION2_IV_HEADER0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0xA0)++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0xA4++0x03
line.long 0x00 "PRINCE_REGION2_IV_HEADER1,no description available"
bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3"
group.long 0xA8++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xA8++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xAC++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xAC++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xB0++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "4" "5" )(list 0x0 0x4 )
group.long ($2+0xB0)++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "3" "4" )(list 0x0 0x4 )
group.long ($2+0xB4)++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0xB8++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xBC++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xBC++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE7,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xC0++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xC0++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE8,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xC4++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY7,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "9" "10" )(list 0x0 0x4 )
group.long ($2+0xC4)++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
group.long ($2+0xC8)++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0xCC++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD0++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD0++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE12,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD4++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD4++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE13,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 56. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "CUSTOMER_DEFINED[$1],Customer Defined (Programable through ROM API $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1E0)++0x03
line.long 0x00 "SHA256_DIGEST[$1],SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
tree.end
repeat.end
tree "FLASH_CFPA_SCRATCH"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
base ad:0x3DE00
elif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
base ad:0x9DE00
endif
group.long 0x00++0x03
line.long 0x00 "HEADER,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x04++0x03
line.long 0x00 "VERSION,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x08++0x03
line.long 0x00 "S_FW_Version,Secure firmware version (Monotonic counter)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x0C++0x03
line.long 0x00 "NS_FW_Version,Non-Secure firmware version (Monotonic counter)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x10++0x03
line.long 0x00 "IMAGE_KEY_REVOKE,Image key revocation ID (Monotonic counter)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x18++0x03
line.long 0x00 "ROTKH_REVOKE,no description available"
bitfld.long 0x00 6.--7. "RoTK3_EN,RoT Key 3 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
bitfld.long 0x00 4.--5. "RoTK2_EN,RoT Key 2 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
bitfld.long 0x00 2.--3. "RoTK1_EN,RoT Key 1 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
newline
bitfld.long 0x00 0.--1. "RoTK0_EN,RoT Key 0 enable" "0: Invalid,1: Enabled 10,?,3: Key revoked"
group.long 0x1C++0x03
line.long 0x00 "VENDOR_USAGE,no description available"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
hexmask.long.word 0x00 0.--15. 1. "DBG_VENDOR_USAGE,DBG_VENDOR_USAGE"
group.long 0x20++0x03
line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1"
bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 7. "FA_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
group.long 0x20++0x03
line.long 0x00 "DCFG_CC_SOCU_PIN,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1"
bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
group.long 0x24++0x03
line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
group.long 0x24++0x03
line.long 0x00 "DCFG_CC_SOCU_DFLT,With TZ-M the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 7. "FA_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE"
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
group.long 0x28++0x03
line.long 0x00 "ENABLE_FA_MODE,Enable FA mode"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x2C++0x03
line.long 0x00 "CMPA_PROG_IN_PROGRESS,CMPA Page programming on going"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x30++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x30++0x03
line.long 0x00 "PRINCE_REGION0_IV_HEADER0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x34++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x34++0x03
line.long 0x00 "PRINCE_REGION0_IV_HEADER1,no description available"
bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3"
group.long 0x38++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x38++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x3C++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x3C)++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x40++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE4,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x44++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x44++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x48++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY4,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x48++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x4C++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
group.long ($2+0x4C)++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "6" "7" )(list 0x0 0x4 )
group.long ($2+0x50)++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x54++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x58++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY8,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x58++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x5C++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "11" "12" )(list 0x0 0x4 )
group.long ($2+0x5C)++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x60++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x64++0x03
line.long 0x00 "PRINCE_REGION0_IV_CODE13,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x64++0x03
line.long 0x00 "PRINCE_REGION0_IV_BODY11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x68++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x68++0x03
line.long 0x00 "PRINCE_REGION1_IV_HEADER0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x6C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x6C++0x03
line.long 0x00 "PRINCE_REGION1_IV_HEADER1,no description available"
bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3"
group.long 0x70++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x70++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x74++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "3" "4" )(list 0x0 0x4 )
group.long ($2+0x74)++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "2" "3" )(list 0x0 0x4 )
group.long ($2+0x78)++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x7C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x80++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY4,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x80++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x84++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
group.long ($2+0x84)++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x88++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x8C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
group.long ($2+0x8C)++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x90++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x94++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY9,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x94++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x98++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x98++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE12,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x9C++0x03
line.long 0x00 "PRINCE_REGION1_IV_BODY11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x9C++0x03
line.long 0x00 "PRINCE_REGION1_IV_CODE13,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xA0++0x03
line.long 0x00 "PRINCE_REGION2_IV_HEADER0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0xA0)++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0xA4++0x03
line.long 0x00 "PRINCE_REGION2_IV_HEADER1,no description available"
bitfld.long 0x00 24.--29. "SIZE,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE,no description available" "0,1,2,3"
group.long 0xA8++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xA8++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xAC++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xAC++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xB0++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "4" "5" )(list 0x0 0x4 )
group.long ($2+0xB0)++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "3" "4" )(list 0x0 0x4 )
group.long ($2+0xB4)++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0xB8++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xBC++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY5,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xBC++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE7,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xC0++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY6,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xC0++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE8,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xC4++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY7,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "9" "10" )(list 0x0 0x4 )
group.long ($2+0xC4)++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
group.long ($2+0xC8)++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY$1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0xCC++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD0++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY10,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD0++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE12,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD4++0x03
line.long 0x00 "PRINCE_REGION2_IV_BODY11,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xD4++0x03
line.long 0x00 "PRINCE_REGION2_IV_CODE13,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 56. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "CUSTOMER_DEFINED[$1],Customer Defined (Programable through ROM API $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1E0)++0x03
line.long 0x00 "SHA256_DIGEST[$1],SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
tree.end
tree.end
tree "FLASH_CMPA"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
base ad:0x3E400
elif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
base ad:0x9E400
endif
group.long 0x00++0x03
line.long 0x00 "BOOT_CFG,no description available"
hexmask.long.byte 0x00 24.--31. 1. "BOOT_FAILURE_PIN,GPIO port and pin number to use for indicating failure reason"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 7.--8. "BOOT_SPEED,Core clock" "0: Defined by NMPA.SYSTEM_SPEED_CODE,?,2: 48MHz FRO,?..."
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 7.--8. "BOOT_SPEED,Core clock" "0: Defined by NMPA.SYSTEM_SPEED_CODE,1: 96MHz FRO,2: 48MHz FRO,?..."
newline
endif
bitfld.long 0x00 4.--6. "DEFAULT_ISP_MODE,Default ISP mode" "0: AUTO_ISP,1: USB_HID_ISP,2: UART_ISP,3: SPI Slave ISP,4: I2C Slave ISP,?,?,7: Disable ISP fall through"
group.long 0x04++0x03
line.long 0x00 "SPI_FLASH_CFG,no description available"
bitfld.long 0x00 0.--4. "SPI_RECOVERY_BOOT_EN,SPI flash recovery boot is enabled if non-zero value is written to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x08++0x03
line.long 0x00 "USB_ID,no description available"
hexmask.long.word 0x00 16.--31. 1. "USB_PRODUCT_ID,no description available"
newline
hexmask.long.word 0x00 0.--15. 1. "USB_VENDOR_ID,no description available"
group.long 0x0C++0x03
line.long 0x00 "SDIO_CFG,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x10++0x03
line.long 0x00 "CC_SOCU_PIN,no description available"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
newline
bitfld.long 0x00 15. "UUID_CHECK,Enforce UUID match during Debug authentication" "0,1"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command enable" "0: Use DAP to enable,1: Fixed state"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 7. "FA_CMD_EN,FA Command enable" "0: Use DAP to enable,1: Fixed state"
newline
endif
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command enable" "0: Use DAP to enable,1: Fixed state"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
endif
bitfld.long 0x00 4. "TAPEN,JTAG TAP enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 1. "DBGEN,Non Secure debug enable" "0: Use DAP to enable,1: Fixed state"
newline
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug enable" "0: Use DAP to enable,1: Fixed state"
group.long 0x14++0x03
line.long 0x00 "CC_SOCU_DFLT,no description available"
hexmask.long.word 0x00 16.--31. 1. "INVERSE_VALUE,inverse value of bits [15:0]"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 9. "CPU1_NIDEN,CPU1 (Micro cortex M33) non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 8. "ME_CMD_EN,Flash Mass Erase Command fixed state" "0: DISABLE,1: ENABLE"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 7. "FA_ME_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 7. "FA_CMD_EN,FA Command fixed state" "0: DISABLE,1: ENABLE"
newline
endif
bitfld.long 0x00 6. "ISP_CMD_EN,ISP Boot Command fixed state" "0: DISABLE,1: ENABLE"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 5. "CPU1_DBGEN,CPU1 (Micro cortex M33) invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
endif
bitfld.long 0x00 4. "TAPEN,JTAG TAP fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 3. "SPIDEN,Secure invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 2. "SPNIDEN,Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 1. "DBGEN,Non Secure debug fixed state" "0: DISABLE,1: ENABLE"
newline
bitfld.long 0x00 0. "NIDEN,Non Secure non-invasive debug fixed state" "0: DISABLE,1: ENABLE"
group.long 0x18++0x03
line.long 0x00 "VENDOR_USAGE,no description available"
hexmask.long.word 0x00 16.--31. 1. "VENDOR_USAGE,Upper 16 bits of vendor usage field defined in DAP"
group.long 0x1C++0x03
line.long 0x00 "SECURE_BOOT_CFG,Secure boot configuration flags"
bitfld.long 0x00 30.--31. "SEC_BOOT_EN,Secure boot enable" "0: Plain image (internal flash with or without..,1: Boot signed images,2: Boot signed images,3: Boot signed images"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 22.--23. "BOOT_SEED_INC_EPOCH,Include security epoch area in BOOT_SEED computation" "0: not included,1: included,2: included,3: included"
newline
bitfld.long 0x00 20.--21. "BOOT_SEED_CUST_CFG,Include CMPA area in BOOT SEED computation" "0: not included,1: included,2: included,3: included"
newline
bitfld.long 0x00 18.--19. "BOOT_SEED_INC_NXP_CFG,Include NXP area in BOOT SEED computation" "0: not included,1: included,2: included,3: included"
newline
bitfld.long 0x00 16.--17. "SKIP_BOOT_SEED,Skip boot seed computation" "0: Enable BOOT_SEED,1: Disable BOOT_SEED,2: Disable BOOT_SEED,3: Disable BOOT_SEED"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 14.--15. "DICE_INC_SEC_EPOCH,Include security EPOCH in DICE" "0,1,2,3"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 14.--15. "DICE_INC_SEC_EPOCH,Include security EPOCH in DICE" "0: not included,1: included,2: included,3: included"
newline
endif
bitfld.long 0x00 12.--13. "BLOCK_ENROLL,Block PUF enrollement" "0: Allow PUF enroll operation,1: Disable PUF enroll operation,2: Disable PUF enroll operation,3: Disable PUF enroll operation"
newline
bitfld.long 0x00 10.--11. "BLOCK_SET_KEY,Block PUF key code generation" "0: Allow PUF Key Code generation,1: Disable PUF Key Code generation,2: Disable PUF Key Code generation,3: Disable PUF Key Code generation"
newline
bitfld.long 0x00 8.--9. "TZM_IMAGE_TYPE,TrustZone-M mode" "0: TZ-M image mode is taken from application..,1: TZ-M disabled image boots to non-secure mode,2: TZ-M enabled image boots to secure mode,3: TZ-M enabled image with TZ-M preset boot to.."
newline
bitfld.long 0x00 6.--7. "SKIP_DICE,Skip DICE computation" "0: Enable DICE,1: Disable DICE,2: Disable DICE,3: Disable DICE"
newline
bitfld.long 0x00 4.--5. "DICE_CUST_CFG,Include Customer factory area (including keys) in DICE computation" "0: not included,1: included,2: included,3: included"
newline
bitfld.long 0x00 2.--3. "DICE_INC_NXP_CFG,Include NXP area in DICE computation" "0: not included,1: included,2: included,3: included"
newline
bitfld.long 0x00 0.--1. "RSA4K,Use RSA4096 keys only" "0: Allow RSA2048 and higher,1: RSA4096 only,2: RSA4096 only,3: RSA4096 only"
group.long 0x20++0x03
line.long 0x00 "PRINCE_BASE_ADDR,no description available"
bitfld.long 0x00 28.--29. "REG2_ERASE_CHECK_EN,For PRINCE region2 enable checking whether all encrypted pages are erased together" "0: Region is disabled,1: Region is enabled,2: Region is enabled,3: Region is enabled"
newline
bitfld.long 0x00 26.--27. "REG1_ERASE_CHECK_EN,For PRINCE region1 enable checking whether all encrypted pages are erased together" "0: Region is disabled,1: Region is enabled,2: Region is enabled,3: Region is enabled"
newline
bitfld.long 0x00 24.--25. "REG0_ERASE_CHECK_EN,For PRINCE region0 enable checking whether all encrypted pages are erased together" "0: Region is disabled,1: Region is enabled,2: Region is enabled,3: Region is enabled"
newline
bitfld.long 0x00 20.--21. "LOCK_REG1,Lock PRINCE region1 settings" "0: Region is not locked,1: Region is locked,2: Region is locked,3: Region is locked"
newline
bitfld.long 0x00 18.--19. "LOCK_REG0,Lock PRINCE region0 settings" "0: Region is not locked,1: Region is locked,2: Region is locked,3: Region is locked"
newline
bitfld.long 0x00 8.--11. "ADDR2_PRG,Programmable portion of the base address of region 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "ADDR1_PRG,Programmable portion of the base address of region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "ADDR0_PRG,Programmable portion of the base address of region 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "PRINCE_SR_0,Region 0 sub-region enable"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x28++0x03
line.long 0x00 "PRINCE_SR_1,Region 1 sub-region enable"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x2C++0x03
line.long 0x00 "PRINCE_SR_2,Region 2 sub-region enable"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x30++0x03
line.long 0x00 "XTAL_32KHZ_CAPABANK_TRIM,Xtal 32kHz capabank triming"
hexmask.long.word 0x00 21.--30. 1. "PCB_XOUT_PARA_CAP_PF_X100,PCB XOUT parasitic capacitance pF x 100"
newline
hexmask.long.word 0x00 11.--20. 1. "PCB_XIN_PARA_CAP_PF_X100,PCB XIN parasitic capacitance pF x 100"
newline
hexmask.long.word 0x00 1.--10. 1. "XTAL_LOAD_CAP_IEC_PF_X100,Load capacitance pF x 100"
newline
bitfld.long 0x00 0. "TRIM_VALID,XTAL 32kHz capa bank trimmings" "0: Capa Bank trimmings not valid,1: Capa Bank trimmings valid"
group.long 0x34++0x03
line.long 0x00 "XTAL_16MHZ_CAPABANK_TRIM,Xtal 16MHz capabank triming"
hexmask.long.word 0x00 21.--30. 1. "PCB_XOUT_PARA_CAP_PF_X100,PCB XOUT parasitic capacitance pF x 100"
newline
hexmask.long.word 0x00 11.--20. 1. "PCB_XIN_PARA_CAP_PF_X100,PCB XIN parasitic capacitance pF x 100"
newline
hexmask.long.word 0x00 1.--10. 1. "XTAL_LOAD_CAP_IEC_PF_X100,Load capacitance pF x 100"
newline
bitfld.long 0x00 0. "TRIM_VALID,XTAL 16MHz capa bank trimmings" "0: Capa Bank trimmings not valid,1: Capa Bank trimmings valid"
group.long 0x38++0x03
line.long 0x00 "FLASH_REMAP_SIZE,This 32-bit register contains the size of the image to remap in bytes"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x3C++0x03
line.long 0x00 "FLASH_REMAP_OFFSET,This 32-bit register contains the offset by which the image is to be remapped"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0x50)++0x03
line.long 0x00 "ROTKH[$1],ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 56. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "CUSTOMER_DEFINED[$1],Customer Defined (Programable through ROM API $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1E0)++0x03
line.long 0x00 "SHA256_DIGEST[$1],SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
tree.end
tree "FLASH_KEY_STORE"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
base ad:0x3E600
elif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
base ad:0x9E600
endif
group.long 0x00++0x03
line.long 0x00 "HEADER,Valid Key Sore Header : 0x95959595"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x04++0x03
line.long 0x00 "puf_discharge_time_in_ms,puf discharge time in ms"
hexmask.long 0x00 0.--31. 1. "FIELD,"
repeat 298. (increment 0 1) (increment 0 0x4)
group.long ($2+0x08)++0x03
line.long 0x00 "ACTIVATION_CODE[$1],$1"
hexmask.long 0x00 0.--31. 1. "FIELD,"
repeat.end
group.long 0x4B0++0x03
line.long 0x00 "SBKEY_HEADER0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4B0++0x03
line.long 0x00 "SBKEY_KEY_CODE0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4B4++0x03
line.long 0x00 "SBKEY_HEADER1,"
bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3"
group.long 0x4B4++0x03
line.long 0x00 "SBKEY_KEY_CODE1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4B8++0x03
line.long 0x00 "SBKEY_BODY0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4B8++0x03
line.long 0x00 "SBKEY_KEY_CODE2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4BC++0x03
line.long 0x00 "SBKEY_BODY1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4BC++0x03
line.long 0x00 "SBKEY_KEY_CODE3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4C0++0x03
line.long 0x00 "SBKEY_BODY2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4C0++0x03
line.long 0x00 "SBKEY_KEY_CODE4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4C4++0x03
line.long 0x00 "SBKEY_BODY3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4C4++0x03
line.long 0x00 "SBKEY_KEY_CODE5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4C8++0x03
line.long 0x00 "SBKEY_BODY4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4C8++0x03
line.long 0x00 "SBKEY_KEY_CODE6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4CC++0x03
line.long 0x00 "SBKEY_BODY5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4CC++0x03
line.long 0x00 "SBKEY_KEY_CODE7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4D0++0x03
line.long 0x00 "SBKEY_BODY6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4D0++0x03
line.long 0x00 "SBKEY_KEY_CODE8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4D4++0x03
line.long 0x00 "SBKEY_BODY7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4D4++0x03
line.long 0x00 "SBKEY_KEY_CODE9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4D8++0x03
line.long 0x00 "SBKEY_BODY8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4D8++0x03
line.long 0x00 "SBKEY_KEY_CODE10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4DC++0x03
line.long 0x00 "SBKEY_BODY9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4DC++0x03
line.long 0x00 "SBKEY_KEY_CODE11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4E0++0x03
line.long 0x00 "SBKEY_BODY10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4E0++0x03
line.long 0x00 "SBKEY_KEY_CODE12,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4E4++0x03
line.long 0x00 "SBKEY_BODY11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4E4++0x03
line.long 0x00 "SBKEY_KEY_CODE13,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4E8++0x03
line.long 0x00 "USER_KEK_HEADER0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4E8++0x03
line.long 0x00 "USER_KEK_KEY_CODE0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4EC++0x03
line.long 0x00 "USER_KEK_HEADER1,"
bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3"
group.long 0x4EC++0x03
line.long 0x00 "USER_KEK_KEY_CODE1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4F0++0x03
line.long 0x00 "USER_KEK_BODY0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4F0++0x03
line.long 0x00 "USER_KEK_KEY_CODE2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4F4++0x03
line.long 0x00 "USER_KEK_BODY1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4F4++0x03
line.long 0x00 "USER_KEK_KEY_CODE3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4F8++0x03
line.long 0x00 "USER_KEK_BODY2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4F8++0x03
line.long 0x00 "USER_KEK_KEY_CODE4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4FC++0x03
line.long 0x00 "USER_KEK_BODY3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x4FC++0x03
line.long 0x00 "USER_KEK_KEY_CODE5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x500++0x03
line.long 0x00 "USER_KEK_BODY4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x500++0x03
line.long 0x00 "USER_KEK_KEY_CODE6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x504++0x03
line.long 0x00 "USER_KEK_BODY5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x504++0x03
line.long 0x00 "USER_KEK_KEY_CODE7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x508++0x03
line.long 0x00 "USER_KEK_BODY6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x508++0x03
line.long 0x00 "USER_KEK_KEY_CODE8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x50C++0x03
line.long 0x00 "USER_KEK_BODY7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x50C++0x03
line.long 0x00 "USER_KEK_KEY_CODE9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x510++0x03
line.long 0x00 "USER_KEK_BODY8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x510++0x03
line.long 0x00 "USER_KEK_KEY_CODE10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x514++0x03
line.long 0x00 "USER_KEK_BODY9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x514++0x03
line.long 0x00 "USER_KEK_KEY_CODE11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x518++0x03
line.long 0x00 "USER_KEK_BODY10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x518++0x03
line.long 0x00 "USER_KEK_KEY_CODE12,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x51C++0x03
line.long 0x00 "USER_KEK_BODY11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x51C++0x03
line.long 0x00 "USER_KEK_KEY_CODE13,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x520++0x03
line.long 0x00 "UDS_HEADER0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x520++0x03
line.long 0x00 "UDS_KEY_CODE0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x524++0x03
line.long 0x00 "UDS_HEADER1,"
bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3"
group.long 0x524++0x03
line.long 0x00 "UDS_KEY_CODE1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x528++0x03
line.long 0x00 "UDS_BODY0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x528++0x03
line.long 0x00 "UDS_KEY_CODE2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x52C++0x03
line.long 0x00 "UDS_BODY1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x52C++0x03
line.long 0x00 "UDS_KEY_CODE3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x530++0x03
line.long 0x00 "UDS_BODY2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x530++0x03
line.long 0x00 "UDS_KEY_CODE4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x534++0x03
line.long 0x00 "UDS_BODY3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x534++0x03
line.long 0x00 "UDS_KEY_CODE5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x538++0x03
line.long 0x00 "UDS_BODY4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x538++0x03
line.long 0x00 "UDS_KEY_CODE6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x53C++0x03
line.long 0x00 "UDS_BODY5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x53C++0x03
line.long 0x00 "UDS_KEY_CODE7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x540++0x03
line.long 0x00 "UDS_BODY6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x540++0x03
line.long 0x00 "UDS_KEY_CODE8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x544++0x03
line.long 0x00 "UDS_BODY7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x544++0x03
line.long 0x00 "UDS_KEY_CODE9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x548++0x03
line.long 0x00 "UDS_BODY8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x548++0x03
line.long 0x00 "UDS_KEY_CODE10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x54C++0x03
line.long 0x00 "UDS_BODY9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x54C++0x03
line.long 0x00 "UDS_KEY_CODE11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x550++0x03
line.long 0x00 "UDS_BODY10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x550++0x03
line.long 0x00 "UDS_KEY_CODE12,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x554++0x03
line.long 0x00 "UDS_BODY11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x554++0x03
line.long 0x00 "UDS_KEY_CODE13,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x558++0x03
line.long 0x00 "PRINCE_REGION0_HEADER0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x558++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x55C++0x03
line.long 0x00 "PRINCE_REGION0_HEADER1,"
bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3"
group.long 0x55C++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x560++0x03
line.long 0x00 "PRINCE_REGION0_BODY0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x560++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x564++0x03
line.long 0x00 "PRINCE_REGION0_BODY1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x564++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x568++0x03
line.long 0x00 "PRINCE_REGION0_BODY2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x568++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x56C++0x03
line.long 0x00 "PRINCE_REGION0_BODY3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x56C++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x570++0x03
line.long 0x00 "PRINCE_REGION0_BODY4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x570++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x574++0x03
line.long 0x00 "PRINCE_REGION0_BODY5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x574++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x578++0x03
line.long 0x00 "PRINCE_REGION0_BODY6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x578++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x57C++0x03
line.long 0x00 "PRINCE_REGION0_BODY7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x57C++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x580++0x03
line.long 0x00 "PRINCE_REGION0_BODY8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x580++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x584++0x03
line.long 0x00 "PRINCE_REGION0_BODY9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x584++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x588++0x03
line.long 0x00 "PRINCE_REGION0_BODY10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x588++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE12,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x58C++0x03
line.long 0x00 "PRINCE_REGION0_BODY11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x58C++0x03
line.long 0x00 "PRINCE_REGION0_KEY_CODE13,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x590++0x03
line.long 0x00 "PRINCE_REGION1_HEADER0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x590++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x594++0x03
line.long 0x00 "PRINCE_REGION1_HEADER1,"
bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3"
group.long 0x594++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x598++0x03
line.long 0x00 "PRINCE_REGION1_BODY0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x598++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x59C++0x03
line.long 0x00 "PRINCE_REGION1_BODY1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x59C++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5A0++0x03
line.long 0x00 "PRINCE_REGION1_BODY2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5A0++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5A4++0x03
line.long 0x00 "PRINCE_REGION1_BODY3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5A4++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5A8++0x03
line.long 0x00 "PRINCE_REGION1_BODY4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5A8++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5AC++0x03
line.long 0x00 "PRINCE_REGION1_BODY5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5AC++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5B0++0x03
line.long 0x00 "PRINCE_REGION1_BODY6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5B0++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5B4++0x03
line.long 0x00 "PRINCE_REGION1_BODY7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5B4++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5B8++0x03
line.long 0x00 "PRINCE_REGION1_BODY8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5B8++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5BC++0x03
line.long 0x00 "PRINCE_REGION1_BODY9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5BC++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5C0++0x03
line.long 0x00 "PRINCE_REGION1_BODY10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5C0++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE12,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5C4++0x03
line.long 0x00 "PRINCE_REGION1_BODY11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5C4++0x03
line.long 0x00 "PRINCE_REGION1_KEY_CODE13,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5C8++0x03
line.long 0x00 "PRINCE_REGION2_HEADER0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5C8++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5CC++0x03
line.long 0x00 "PRINCE_REGION2_HEADER1,"
bitfld.long 0x00 24.--29. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--11. "INDEX," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TYPE," "0,1,2,3"
group.long 0x5CC++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5D0++0x03
line.long 0x00 "PRINCE_REGION2_BODY0,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5D0++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5D4++0x03
line.long 0x00 "PRINCE_REGION2_BODY1,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5D4++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5D8++0x03
line.long 0x00 "PRINCE_REGION2_BODY2,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5D8++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5DC++0x03
line.long 0x00 "PRINCE_REGION2_BODY3,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5DC++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5E0++0x03
line.long 0x00 "PRINCE_REGION2_BODY4,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5E0++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5E4++0x03
line.long 0x00 "PRINCE_REGION2_BODY5,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5E4++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5E8++0x03
line.long 0x00 "PRINCE_REGION2_BODY6,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5E8++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5EC++0x03
line.long 0x00 "PRINCE_REGION2_BODY7,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5EC++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5F0++0x03
line.long 0x00 "PRINCE_REGION2_BODY8,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5F0++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5F4++0x03
line.long 0x00 "PRINCE_REGION2_BODY9,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5F4++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5F8++0x03
line.long 0x00 "PRINCE_REGION2_BODY10,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5F8++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE12,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5FC++0x03
line.long 0x00 "PRINCE_REGION2_BODY11,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
group.long 0x5FC++0x03
line.long 0x00 "PRINCE_REGION2_KEY_CODE13,"
hexmask.long 0x00 0.--31. 1. "FIELD,"
tree.end
sif cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")
tree "FLASH_NMPA"
base ad:0x3FC00
group.long 0x00++0x03
line.long 0x00 "GPO0_0,GPO0 register 0 description"
hexmask.long.word 0x00 16.--31. 1. "FIELD,no description available"
newline
hexmask.long.word 0x00 7.--15. 1. "FRO32K_CAPCAL,no description available"
newline
bitfld.long 0x00 4.--6. "FRO32K_PTAT,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 1.--3. "FRO32K_NTAT,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "FRO_TRIM_VALID,no description available" "0,1"
group.long 0x00++0x03
line.long 0x00 "GPO0_ARRAY0,GPO0 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x04++0x03
line.long 0x00 "GPO0_1,GPO0 register 1 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x04++0x03
line.long 0x00 "GPO0_ARRAY1,GPO0 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x08++0x03
line.long 0x00 "GPO0_2,GPO0 register 2 description"
hexmask.long 0x00 4.--31. 1. "FIELD,no description available"
newline
bitfld.long 0x00 2.--3. "FLASH_CTRL_OPMODE," "?,1: RCLK (back up clock),2: PCLK (back up clock),?..."
newline
bitfld.long 0x00 0.--1. "SYSTEM_SPEED_CODE," "?,1: FRO24MHz,2: FRO48MHz,3: FRO96MHz"
group.long 0x08++0x03
line.long 0x00 "GPO0_ARRAY2,GPO0 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x0C++0x03
line.long 0x00 "GPO0_3,GPO0 register 3 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x0C++0x03
line.long 0x00 "GPO0_ARRAY3,GPO0 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x10++0x03
line.long 0x00 "GPO1_0,GPO1 register 0 description"
bitfld.long 0x00 28.--31. "METAL_REVISION_ID,METAL REVISION ID[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24.--27. "ROM_REVISION_MINOR,ROM Revision-Minor [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "FIELD,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "CPU0_SECURITY_EXTENSION_DISABLE,CPU0_SECURITY_EXTENSION_DISABLE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "SRAM_SIZE,SRAM_SIZE[3:0]: (For Niobe4)" "0: 320 KB,1: 256 KB,2: 144 KB,3: 80 KB (For Niobe4 Mini),4: 96 KB,5: 80 KB,6: 64 KB,7: 48 KB All others,?..."
newline
bitfld.long 0x00 11. "DEVICE_TYPE_SEC,Security device type" "0: LPC55xxx (Non Secure Familly),1: LPC55Sxxx (Secure Familly)"
newline
hexmask.long.byte 0x00 4.--10. 1. "PARTCONFIG,Device type number"
newline
bitfld.long 0x00 0.--3. "FINAL_TEST_NOT_DONE,FINAL_TEST_NOT_DONE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "GPO1_ARRAY0,GPO1 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x14++0x03
line.long 0x00 "GPO1_1,GPO1 register 1 description"
hexmask.long.tbyte 0x00 8.--31. 1. "FIELD,no description available"
newline
bitfld.long 0x00 4.--7. "CUSTOMER_REVISION_ID,CUSTOMER REVISION ID[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "ROM_PATCH_VERSION,ROM Patch Version [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "GPO1_ARRAY1,GPO1 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x18++0x03
line.long 0x00 "GPO1_2,GPO1 register 2 description"
hexmask.long 0x00 1.--31. 1. "FIELD,no description available"
newline
bitfld.long 0x00 0. "HVST,High Voltage Stress" "0: not done,1: done"
group.long 0x18++0x03
line.long 0x00 "GPO1_ARRAY2,GPO1 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x1C++0x03
line.long 0x00 "GPO1_3,GPO1 register 3 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x1C++0x03
line.long 0x00 "GPO1_ARRAY3,GPO1 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x20++0x03
line.long 0x00 "GPO2_0,GPO2 register 0 description"
bitfld.long 0x00 28.--31. "CPU0_SECURITY_EXTENSION_DISABLE,CPU0_SECURITY_EXTENSION_DISABLE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 25.--27. "FLASH_SIZE,(For Niobe4)" "0: 256 KB,1: 128 KB,2: 80 KB (reserved),3: 64 KB,4: 0 kB (reserved) All,?..."
newline
bitfld.long 0x00 22.--24. "TRIM_PLL_CTRL0_DIV_SEL,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19.--21. "TRIM_USB2_REFBIAS_VBGADJ,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--18. "TRIM_USB2_REFBIAS_TST,no description available" "0,1,2,3"
newline
bitfld.long 0x00 12.--16. "TRIM_USBPHY_TX_CAL45DN,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7.--11. "TRIM_USBPHY_TX_CAL45DP,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 3.--6. "TRIM_USBPHY_TX_D_CAL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--2. "TRIM_USB_REG_ENV_TAIL_ADJ_VD,no description available" "0,1,2,3"
newline
bitfld.long 0x00 0. "USBHS_PHY_TRIM_VALID,no description available" "0,1"
group.long 0x20++0x03
line.long 0x00 "GPO2_ARRAY0,GPO2 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x24++0x03
line.long 0x00 "GPO2_1,GPO2 register 1 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x24++0x03
line.long 0x00 "GPO2_ARRAY1,GPO2 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x28++0x03
line.long 0x00 "GPO2_2,GPO2 register 2 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x28++0x03
line.long 0x00 "GPO2_ARRAY2,GPO2 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x2C++0x03
line.long 0x00 "GPO2_3,GPO2 register 3 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x2C++0x03
line.long 0x00 "GPO2_ARRAY3,GPO2 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x30++0x03
line.long 0x00 "GPO3_0,GPO3 register 0 description"
bitfld.long 0x00 28.--31. "FINAL_TEST_NOT_DONE,FINAL_TEST_NOT_DONE[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 25.--27. "MODELNUM_EXTENSION,ModelNumber extension[2:0]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19.--24. "FIELD,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 16.--18. "AUX_BIAS_VREF1_VCURVE_TRIM,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11.--15. "AUX_BIAS_VREF1_VTRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 6.--10. "AUX_BIAS_PTAT_ITRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--5. "AUX_BIAS_ITRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "AUX_BIAS_TRIM_VALID,no description available" "0,1"
group.long 0x30++0x03
line.long 0x00 "GPO3_ARRAY0,GPO3 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x34++0x03
line.long 0x00 "GPO3_1,GPO3 register 1 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x34++0x03
line.long 0x00 "GPO3_ARRAY1,GPO3 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x38++0x03
line.long 0x00 "GPO3_2,GPO3 register 2 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x38++0x03
line.long 0x00 "GPO3_ARRAY2,GPO3 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x3C++0x03
line.long 0x00 "GPO3_3,GPO3 register 3 description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x3C++0x03
line.long 0x00 "GPO3_ARRAY3,GPO3 array description"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x40++0x03
line.long 0x00 "GPO_CHECKSUM_0,checksum of the GPO data in words 0"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x40++0x03
line.long 0x00 "GPO_CHECKSUM_ARRAY0,checksum of the GPO data in words [3:0]"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x44++0x03
line.long 0x00 "GPO_CHECKSUM_1,checksum of the GPO data in words 1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x44++0x03
line.long 0x00 "GPO_CHECKSUM_ARRAY1,checksum of the GPO data in words [3:0]"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x48++0x03
line.long 0x00 "GPO_CHECKSUM_2,checksum of the GPO data in words 2"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x48++0x03
line.long 0x00 "GPO_CHECKSUM_ARRAY2,checksum of the GPO data in words [3:0]"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x4C++0x03
line.long 0x00 "GPO_CHECKSUM_3,checksum of the GPO data in words 3"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x4C++0x03
line.long 0x00 "GPO_CHECKSUM_ARRAY3,checksum of the GPO data in words [3:0]"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x50++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x50++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x54++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x54++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x58++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x58++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x5C++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x5C++0x03
line.long 0x00 "FINAL_TEST_BATCH_ID_ARRAY3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x60++0x03
line.long 0x00 "DEVICE_TYPE,no description available"
hexmask.long.byte 0x00 24.--31. 1. "DEVICE_TYPE_PIN,Number of pins on the package"
newline
bitfld.long 0x00 20.--23. "DEVICE_TYPE_PKG,Device package type" "0: HLQFP,1: HTQFP,2: HVQFN,?,4: VFBGA,?,?,?,8: WLCSP,?..."
newline
bitfld.long 0x00 16. "DEVICE_TYPE_SEC,Security device type" "0: LPC55xxx (Non Secure Familly),1: LPC55Sxxx (Secure Familly)"
newline
hexmask.long.word 0x00 0.--15. 1. "DEVICE_TYPE_NUM,Device type number"
group.long 0x64++0x03
line.long 0x00 "FINAL_TEST_PROGRAM_VERSION,no description available"
hexmask.long 0x00 0.--31. 1. "PROGRAM_VERSION,PROGRAM_VERSION [xx.yy stored as : 100*x+y]"
group.long 0x68++0x03
line.long 0x00 "FINAL_TEST_DATE,no description available"
hexmask.long 0x00 0.--31. 1. "DATE,DATE [stored as : year*10000+month*100+day]"
group.long 0x6C++0x03
line.long 0x00 "FINAL_TEST_TIME,no description available"
hexmask.long 0x00 0.--31. 1. "TIME,TIME [stored as : hour*10000+minute*100+seconde]"
group.long 0x70++0x03
line.long 0x00 "UUID_0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x70++0x03
line.long 0x00 "UUID_ARRAY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x74++0x03
line.long 0x00 "UUID_1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x74++0x03
line.long 0x00 "UUID_ARRAY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x78++0x03
line.long 0x00 "UUID_2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x78++0x03
line.long 0x00 "UUID_ARRAY2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x7C++0x03
line.long 0x00 "UUID_3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x7C++0x03
line.long 0x00 "UUID_ARRAY3,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x80++0x03
line.long 0x00 "WAFER_TEST1_PROGRAM_VERSION,no description available"
hexmask.long 0x00 0.--31. 1. "WT1_PROGRAM_VERSION,WT1_PROGRAM_VERSION [xx.yy stored as : 100*x+y]"
group.long 0x84++0x03
line.long 0x00 "WAFER_TEST1_DATE,no description available"
hexmask.long 0x00 0.--31. 1. "WT1_DATE,WT1_DATE [stored as : year*10000+month*100+day]"
group.long 0x88++0x03
line.long 0x00 "WAFER_TEST1_TIME,no description available"
hexmask.long 0x00 0.--31. 1. "WT1_TIME,WT1_TIME [stored as : hour*10000+minute*100+seconde]"
group.long 0x90++0x03
line.long 0x00 "WAFER_TEST2_PROGRAM_VERSION,no description available"
hexmask.long 0x00 0.--31. 1. "WT2_PROGRAM_VERSION,WT2_PROGRAM_VERSION [xx.yy stored as : 100*x+y]"
group.long 0x94++0x03
line.long 0x00 "WAFER_TEST2_DATE,no description available"
hexmask.long 0x00 0.--31. 1. "WT2_DATE,WT2_DATE [stored as : year*10000+month*100+day]"
group.long 0x98++0x03
line.long 0x00 "WAFER_TEST2_TIME,no description available"
hexmask.long 0x00 0.--31. 1. "WT2_TIME,WT2_TIME [stored as : hour*10000+minute*100+seconde]"
group.long 0x9C++0x03
line.long 0x00 "USBCFG,no description available"
bitfld.long 0x00 16. "USB_USE_XO32M_CAPA_BANKS,Enable the use of Crystal 32 MHz internal Capa Banks during the configuration of the High Speed USB for ISP" "0: Disable Crystal 32 MHz CapaBanks,1: Enable Crystal 32 MHz CapaBanks"
newline
abitfld.long 0x00 8.--15. "USB_SPEED,USB_SPEED[7:0]=" "0x00=0: USB High Speed Module used for ISP,0x01=1: USB Full SPeed Module used for ISP,0x02=2: Neither USB High Speed module nor USB..,0xFF=255: RESERVED"
newline
hexmask.long.byte 0x00 0.--7. 1. "XO32M_READY_TIME_OUT_MS,no description available"
group.long 0xA0++0x03
line.long 0x00 "PERIPHENCFG,no description available"
bitfld.long 0x00 31. "CPU1_ENABLE,no description available" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "PERIPHERAL_CONFIGURATION,no description available"
group.long 0xA4++0x03
line.long 0x00 "RAMSIZECFG,no description available"
hexmask.long 0x00 0.--31. 1. "SRAM_CONFIGURATION,no description available"
group.long 0xA8++0x03
line.long 0x00 "FLASHSIZECFG,no description available"
hexmask.long 0x00 0.--31. 1. "FLASH_CONFIGURATION,no description available"
group.long 0xB0++0x03
line.long 0x00 "RINGO_0,no description available"
hexmask.long 0x00 1.--31. 1. "RINGO_0_CTRL,To copy RINGO_0_CTRL = ANACTRL->RINGO0_CTRL[30:0]"
newline
bitfld.long 0x00 0. "RINGO_0_CTRL_VALID," "0,1"
group.long 0xB4++0x03
line.long 0x00 "RINGO_1,no description available"
hexmask.long 0x00 1.--31. 1. "RINGO_1_CTRL,To copy RINGO_1_CTRL = ANACTRL->RINGO1_CTRL[30:0]"
newline
bitfld.long 0x00 0. "RINGO_1_CTRL_VALID," "0,1"
group.long 0xB8++0x03
line.long 0x00 "RINGO_2,no description available"
hexmask.long 0x00 1.--31. 1. "RINGO_2_CTRL,To copy RINGO_2_CTRL = ANACTRL->RINGO2_CTRL[30:0]"
newline
bitfld.long 0x00 0. "RINGO_2_CTRL_VALID," "0,1"
group.long 0xC0++0x03
line.long 0x00 "FRO_192MHZ,no description available"
hexmask.long.byte 0x00 17.--24. 1. "FRO192M_DACTRIM,FRO192M_DACTRIM[7:0]"
newline
hexmask.long.byte 0x00 8.--14. 1. "FRO192M_TEMPTRIM,FRO192M_TEMPTRIM[6:0]"
newline
bitfld.long 0x00 1.--6. "FRO192M_BIASTRIM,FRO192M_BIASTRIM[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "FRO192M_TRIM_VALID,no description available" "0,1"
group.long 0xC8++0x03
line.long 0x00 "XO_32MHZ,no description available"
bitfld.long 0x00 31. "XO32M_XO_AC_BUF_STATUS,no description available" "0,1"
newline
bitfld.long 0x00 30. "XO32M_XO_SLAVE_STATUS,no description available" "0,1"
newline
hexmask.long.byte 0x00 23.--29. 1. "XO32M_XOUT_CAPCAL_8PF,no description available"
newline
hexmask.long.byte 0x00 16.--22. 1. "XO32M_XOUT_CAPCAL_6PF,no description available"
newline
bitfld.long 0x00 15. "XO32M_XOUT_TRIM_VALID,no description available" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "XO32M_XIN_CAPCAL_8PF,no description available"
newline
hexmask.long.byte 0x00 1.--7. 1. "XO32M_XIN_CAPCAL_6PF,no description available"
newline
bitfld.long 0x00 0. "XO32M_XIN_TRIM_VALID,no description available" "0,1"
group.long 0xCC++0x03
line.long 0x00 "XO_32KHZ,no description available"
hexmask.long.byte 0x00 23.--29. 1. "XO32K_XOUT_CAPCAL_8PF,no description available"
newline
hexmask.long.byte 0x00 16.--22. 1. "XO32K_XOUT_CAPCAL_6PF,no description available"
newline
bitfld.long 0x00 15. "XO32K_XOUT_TRIM_VALID,no description available" "0,1"
newline
hexmask.long.byte 0x00 8.--14. 1. "XO32K_XIN_CAPCAL_8PF,no description available"
newline
hexmask.long.byte 0x00 1.--7. 1. "XO32K_XIN_CAPCAL_6PF,no description available"
newline
bitfld.long 0x00 0. "XO32K_XIN_TRIM_VALID,no description available" "0,1"
group.long 0xD0++0x03
line.long 0x00 "FRO_1MHZ,no description available"
hexmask.long.byte 0x00 1.--7. 1. "FRO1M_FREQSEL,Frequency trimming bits"
newline
bitfld.long 0x00 0. "FRO1M_TRIM_VALID,no description available" "0,1"
group.long 0xD8++0x03
line.long 0x00 "DCDC_POWER_PROFILE_HIGH_0,no description available"
bitfld.long 0x00 24.--27. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 23. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1"
newline
bitfld.long 0x00 22. "SLICINGENABLE,Enable staggered switching of power switches" "0,1"
newline
bitfld.long 0x00 18.--21. "VOUT,Set output regulation voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 17. "DISABLEISENSE,Disable Current sensing" "0,1"
newline
bitfld.long 0x00 12.--16. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 11. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1"
newline
bitfld.long 0x00 9.--10. "ISEL,Alter Internal biasing currents" "0,1,2,3"
newline
bitfld.long 0x00 7.--8. "ICOMP,Select the type of ZCD comparator" "0,1,2,3"
newline
bitfld.long 0x00 1.--6. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "DCDC_TRIM_VALID,DCDC is trimed" "0,1"
group.long 0xD8++0x03
line.long 0x00 "DCDC_POWER_PROFILE_HIGH_ARRAY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xDC++0x03
line.long 0x00 "DCDC_POWER_PROFILE_HIGH_1,no description available"
bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1"
newline
bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1"
newline
bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1"
newline
bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1"
newline
bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1"
newline
bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3"
newline
bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1"
newline
bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xDC++0x03
line.long 0x00 "DCDC_POWER_PROFILE_HIGH_ARRAY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xE0++0x03
line.long 0x00 "DCDC_POWER_PROFILE_LOW_0,no description available"
bitfld.long 0x00 24.--27. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 23. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1"
newline
bitfld.long 0x00 22. "SLICINGENABLE,Enable staggered switching of power switches" "0,1"
newline
bitfld.long 0x00 18.--21. "VOUT,Set output regulation voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 17. "DISABLEISENSE,Disable Current sensing" "0,1"
newline
bitfld.long 0x00 12.--16. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 11. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1"
newline
bitfld.long 0x00 9.--10. "ISEL,Alter Internal biasing currents" "0,1,2,3"
newline
bitfld.long 0x00 7.--8. "ICOMP,Select the type of ZCD comparator" "0,1,2,3"
newline
bitfld.long 0x00 1.--6. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "DCDC_TRIM_VALID,DCDC is trimed" "0,1"
group.long 0xE0++0x03
line.long 0x00 "DCDC_POWER_PROFILE_LOW_ARRAY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xE4++0x03
line.long 0x00 "DCDC_POWER_PROFILE_LOW_1,no description available"
bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1"
newline
bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1"
newline
bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1"
newline
bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1"
newline
bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1"
newline
bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3"
newline
bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1"
newline
bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xE4++0x03
line.long 0x00 "DCDC_POWER_PROFILE_LOW_ARRAY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xE8++0x03
line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_0,no description available"
bitfld.long 0x00 24.--27. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 23. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1"
newline
bitfld.long 0x00 22. "SLICINGENABLE,Enable staggered switching of power switches" "0,1"
newline
bitfld.long 0x00 18.--21. "VOUT,Set output regulation voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 17. "DISABLEISENSE,Disable Current sensing" "0,1"
newline
bitfld.long 0x00 12.--16. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 11. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1"
newline
bitfld.long 0x00 9.--10. "ISEL,Alter Internal biasing currents" "0,1,2,3"
newline
bitfld.long 0x00 7.--8. "ICOMP,Select the type of ZCD comparator" "0,1,2,3"
newline
bitfld.long 0x00 1.--6. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "DCDC_TRIM_VALID,DCDC is trimed" "0,1"
group.long 0xE8++0x03
line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_ARRAY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xEC++0x03
line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_1,no description available"
bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1"
newline
bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1"
newline
bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1"
newline
bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1"
newline
bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1"
newline
bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3"
newline
bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1"
newline
bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEC++0x03
line.long 0x00 "DCDC_POWER_PROFILE_MEDIUM_ARRAY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0xF0++0x03
line.long 0x00 "BOD,no description available"
bitfld.long 0x00 21.--22. "BOD_CORE_HYST,no description available" "0,1,2,3"
newline
bitfld.long 0x00 17.--19. "BOD_CORE_TRIGLVL,no description available" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "BOD_CORE_TRIM_VALID,no description available" "0,1"
newline
bitfld.long 0x00 6.--7. "BOD_VBAT_HYST,no description available" "0,1,2,3"
newline
bitfld.long 0x00 1.--5. "BOD_VBAT_TRIGLVL,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "BOD_VBAT_TRIM_VALID,no description available" "0,1"
group.long 0xF4++0x03
line.long 0x00 "LDO_AO,no description available"
bitfld.long 0x00 25.--29. "DPDW_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 24. "DPDW_TRIM_VALID,no description available" "0,1"
newline
bitfld.long 0x00 17.--21. "PDWN_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16. "PDWN_TRIM_VALID,no description available" "0,1"
newline
bitfld.long 0x00 9.--13. "DSLP_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8. "DSLP_TRIM_VALID,no description available" "0,1"
newline
bitfld.long 0x00 1.--5. "ACTIVE_TRIM,no description available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "ACTIVE_TRIM_VALID,no description available" "0,1"
group.long 0xF8++0x03
line.long 0x00 "SDIO_DELAY,no description available"
hexmask.long.word 0x00 1.--10. 1. "SDIO_0_DELAY,SDIO_0_DELAY (unit: 100 ps)"
newline
bitfld.long 0x00 0. "SDIO_0_VALID,no description available" "0,1"
group.long 0x100++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_0,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_1,VREF1VCURVETRIM_1 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_0,VREF1VCURVETRIM_0 (unit: 100uV)"
group.long 0x100++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY0,Aux Bias Curve Ambient (30degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x104++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_1,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_3,VREF1VCURVETRIM_3 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_2,VREF1VCURVETRIM_2 (unit: 100uV)"
group.long 0x104++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY1,Aux Bias Curve Ambient (30degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x108++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_2,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_5,VREF1VCURVETRIM_5 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_4,VREF1VCURVETRIM_4 (unit: 100uV)"
group.long 0x108++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY2,Aux Bias Curve Ambient (30degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x10C++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_3,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_7,VREF1VCURVETRIM_7 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_6,VREF1VCURVETRIM_6 (unit: 100uV)"
group.long 0x10C++0x03
line.long 0x00 "AUX_BIAS_CURVE_AMBIENT_ARRAY3,Aux Bias Curve Ambient (30degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x110++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_0,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_1,VREF1VCURVETRIM_1 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_0,VREF1VCURVETRIM_0 (unit: 100uV)"
group.long 0x110++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY0,Aux Bias Curve TEMP (105degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x114++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_1,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_3,VREF1VCURVETRIM_3 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_2,VREF1VCURVETRIM_2 (unit: 100uV)"
group.long 0x114++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY1,Aux Bias Curve TEMP (105degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x118++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_2,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_5,VREF1VCURVETRIM_5 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_4,VREF1VCURVETRIM_4 (unit: 100uV)"
group.long 0x118++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY2,Aux Bias Curve TEMP (105degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x11C++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_3,no description available"
hexmask.long.word 0x00 16.--31. 1. "VREF1VCURVETRIM_7,VREF1VCURVETRIM_7 (unit: 100uV)"
newline
hexmask.long.word 0x00 0.--15. 1. "VREF1VCURVETRIM_6,VREF1VCURVETRIM_6 (unit: 100uV)"
group.long 0x11C++0x03
line.long 0x00 "AUX_BIAS_CURVE_TEMP_ARRAY3,Aux Bias Curve TEMP (105degC)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
group.long ($2+0x120)++0x03
line.long 0x00 "TEMP_SENS_VBE1VBE8_REF_$1,no description available"
hexmask.long.word 0x00 16.--31. 1. "VBE8,no description available"
newline
hexmask.long.word 0x00 0.--15. 1. "VBE1,no description available"
repeat.end
group.long 0x128++0x03
line.long 0x00 "TEMP_SENS_SLOPE,no description available"
hexmask.long 0x00 1.--31. 1. "SLOPE_x1024,SLOPE_x1024[30:0]"
newline
bitfld.long 0x00 0. "VALID,no description available" "0,1"
group.long 0x12C++0x03
line.long 0x00 "TEMP_SENS_OFFSET,no description available"
hexmask.long 0x00 1.--31. 1. "OFFSET_x1024,OFFSET_x1024[30:0]"
newline
bitfld.long 0x00 0. "VALID,no description available" "0,1"
group.long 0x130++0x03
line.long 0x00 "PVT_MONITOR_0_ARRAY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x130++0x03
line.long 0x00 "PVT_MONITOR_0_RINGO,no description available"
hexmask.long 0x00 1.--31. 1. "RINGO_FREQ_HZ,no description available"
newline
bitfld.long 0x00 0. "RINGO_VALID,no description available" "0,1"
group.long 0x134++0x03
line.long 0x00 "PVT_MONITOR_0_ARRAY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x134++0x03
line.long 0x00 "PVT_MONITOR_0_DELAYS_LSB,no description available"
hexmask.long.word 0x00 21.--30. 1. "DELAY_2,Delay in us"
newline
hexmask.long.word 0x00 11.--20. 1. "DELAY_1,Delay in us"
newline
hexmask.long.word 0x00 1.--10. 1. "DELAY_0,Delay in us"
newline
bitfld.long 0x00 0. "DELAY_VALID,no description available" "0,1"
group.long 0x138++0x03
line.long 0x00 "PVT_MONITOR_0_ARRAY2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x138++0x03
line.long 0x00 "PVT_MONITOR_0_DELAYS_MSB,no description available"
hexmask.long.word 0x00 20.--29. 1. "DELAY_5,Delay in us"
newline
hexmask.long.word 0x00 10.--19. 1. "DELAY_4,Delay in us"
newline
hexmask.long.word 0x00 0.--9. 1. "DELAY_3,Delay in us"
group.long 0x140++0x03
line.long 0x00 "PVT_MONITOR_1_ARRAY0,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x140++0x03
line.long 0x00 "PVT_MONITOR_1_RINGO,no description available"
hexmask.long 0x00 1.--31. 1. "RINGO_FREQ_HZ,no description available"
newline
bitfld.long 0x00 0. "RINGO_VALID,no description available" "0,1"
group.long 0x144++0x03
line.long 0x00 "PVT_MONITOR_1_ARRAY1,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x144++0x03
line.long 0x00 "PVT_MONITOR_1_DELAYS_LSB,no description available"
hexmask.long.word 0x00 21.--30. 1. "DELAY_2,Delay in us"
newline
hexmask.long.word 0x00 11.--20. 1. "DELAY_1,Delay in us"
newline
hexmask.long.word 0x00 1.--10. 1. "DELAY_0,Delay in us"
newline
bitfld.long 0x00 0. "DELAY_VALID,no description available" "0,1"
group.long 0x148++0x03
line.long 0x00 "PVT_MONITOR_1_ARRAY2,no description available"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x148++0x03
line.long 0x00 "PVT_MONITOR_1_DELAYS_MSB,no description available"
hexmask.long.word 0x00 20.--29. 1. "DELAY_5,Delay in us"
newline
hexmask.long.word 0x00 10.--19. 1. "DELAY_4,Delay in us"
newline
hexmask.long.word 0x00 0.--9. 1. "DELAY_3,Delay in us"
repeat 13. (increment 0 1) (increment 0 0x04)
group.long ($2+0x14C)++0x03
line.long 0x00 "NXP_DEVICE_PRIVATE_KEY[$1],no description available $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x180)++0x03
line.long 0x00 "NXP_DEVICE_CERTIFICATE_[$1],NXP Device Certificate (ECDSA_sign - r $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1A0)++0x03
line.long 0x00 "NXP_DEVICE_CERTIFICATE_[$1],NXP Device Certificate (ECDSA_sign - s $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1C0)++0x03
line.long 0x00 "SHA256_DIGEST[$1],SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index $1"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat.end
group.long 0x1E0++0x03
line.long 0x00 "ECID_BACKUP_0,no description available"
hexmask.long.word 0x00 16.--31. 1. "COORD_X,no description available"
newline
hexmask.long.word 0x00 0.--15. 1. "COORD_Y,no description available"
group.long 0x1E0++0x03
line.long 0x00 "ECID_BACKUP_ARRAY0,ECID backup (the original is in page n-1)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x1E4++0x03
line.long 0x00 "ECID_BACKUP_1,no description available"
hexmask.long.byte 0x00 0.--7. 1. "WAFER,no description available"
group.long 0x1E4++0x03
line.long 0x00 "ECID_BACKUP_ARRAY1,ECID backup (the original is in page n-1)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x1E8++0x03
line.long 0x00 "ECID_BACKUP_2,no description available"
hexmask.long 0x00 0.--31. 1. "LOTID_LSB,no description available"
group.long 0x1E8++0x03
line.long 0x00 "ECID_BACKUP_ARRAY2,ECID backup (the original is in page n-1)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
group.long 0x1EC++0x03
line.long 0x00 "ECID_BACKUP_3,no description available"
hexmask.long 0x00 0.--31. 1. "LOTID_MSB,no description available"
group.long 0x1EC++0x03
line.long 0x00 "ECID_BACKUP_ARRAY3,ECID backup (the original is in page n-1)"
hexmask.long 0x00 0.--31. 1. "FIELD,no description available"
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1F0)++0x03
line.long 0x00 "CHECKSUM[$1],Checksum of the whole page $1"
repeat.end
group.long 0xCAC++0x03
line.long 0x00 "DIS_ROM_HIDING,no description available"
hexmask.long 0x00 0.--31. 1. "DIS_ROM_HIDING,When 0x3CC35AA5 ROM hiding feture is disabled"
group.long 0xCBC++0x03
line.long 0x00 "PUF_SRAM,no description available"
bitfld.long 0x00 25. "STBP,STBP" "0,1"
newline
bitfld.long 0x00 23.--24. "WAM,SRAM Write Assist settings" "0,1,2,3"
newline
bitfld.long 0x00 22. "WAEN,SRAM Write Assist Enable" "0,1"
newline
bitfld.long 0x00 18.--21. "RAM,SRAM Read Assist settings" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 17. "RAEN,SRAM Read Assist Enable" "0,1"
newline
bitfld.long 0x00 16. "WRME,Write read margin enable" "0,1"
newline
bitfld.long 0x00 13.--15. "WM,Write Margin control settings" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--12. "RM,Read Margin control settings" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--9. "SMB,Source Biasing voltage" "0: Low leakage,1: Medium leakage,2: Highest leakage,3: Disable"
newline
bitfld.long 0x00 2. "ckgating,PUF SRAM Clock Gating control" "0,1"
newline
bitfld.long 0x00 1. "mode,PUF SRAM Controller operating mode" "0,1"
newline
bitfld.long 0x00 0. "PUF_SRAM_VALID," "0,1"
tree.end
tree "FLASH_ROMPATCH"
base ad:0x3EC00
group.long 0x00++0x03
line.long 0x00 "HEADER,"
hexmask.long.byte 0x00 24.--31. 1. "IDENTIFIER,"
hexmask.long.byte 0x00 16.--23. 1. "TYPE,"
hexmask.long.byte 0x00 8.--15. 1. "SUB_TYPE,"
hexmask.long.byte 0x00 0.--7. 1. "ENTRIES,"
repeat 255. (increment 0 1) (increment 0 0x4)
group.long ($2+0x04)++0x03
line.long 0x00 "PATCH[$1],$1"
hexmask.long 0x00 0.--31. 1. "PATCH,"
repeat.end
tree.end
endif
tree "FLEXCOMM (Flexcomm serial communication)"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8.) (list ad:0x40086000 ad:0x40087000 ad:0x40088000 ad:0x40089000 ad:0x4008A000 ad:0x40096000 ad:0x40097000 ad:0x40098000 ad:0x4009F000)
tree "FLEXCOMM$1"
base $2
group.long 0xFF8++0x03
line.long 0x00 "PSELID,Peripheral Select and Flexcomm ID register"
hexmask.long.tbyte 0x00 12.--31. 1. "ID,Flexcomm ID"
rbitfld.long 0x00 7. "I2SPRESENT,I 2S present indicator" "0: This Flexcomm does not include the I2S function,1: This Flexcomm includes the I2S function"
newline
rbitfld.long 0x00 6. "I2CPRESENT,I2C present indicator" "0: This Flexcomm does not include the I2C function,1: This Flexcomm includes the I2C function"
rbitfld.long 0x00 5. "SPIPRESENT,SPI present indicator" "0: This Flexcomm does not include the SPI function,1: This Flexcomm includes the SPI function"
newline
rbitfld.long 0x00 4. "USARTPRESENT,USART present indicator" "0: This Flexcomm does not include the USART..,1: This Flexcomm includes the USART function"
bitfld.long 0x00 3. "LOCK,Lock the peripheral select" "0: Peripheral select can be changed by software,1: Peripheral select is locked and cannot be.."
newline
bitfld.long 0x00 0.--2. "PERSEL,Peripheral Select" "0: No peripheral selected,1: USART function selected,2: SPI function selected,3: I2C function selected,4: I2S transmit function selected,5: I2S receive function selected,?..."
group.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFC++0x03
line.long 0x00 "PID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,size aperture for the register port on the bus (APB or AHB)"
tree.end
repeat.end
tree.end
tree "GINT (Group GPIO input interrupt (GINT0/1))"
repeat 2. (list 0. 1.) (list ad:0x40002000 ad:0x40003000)
tree "GINT$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTRL,GPIO grouped interrupt control register"
bitfld.long 0x00 2. "TRIG,Group interrupt trigger" "0: Edge-triggered,1: Level-triggered"
bitfld.long 0x00 1. "COMB,Combine enabled inputs for group interrupt" "0: Or,1: And"
bitfld.long 0x00 0. "INT,Group interrupt status" "0: No request,1: Request active"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x20)++0x03
line.long 0x00 "PORT_POL[$1],GPIO grouped interrupt port 0 polarity register $1"
abitfld.long 0x00 0.--31. "POL,Configure pin polarity of port m pins for group interrupt" "0x00000000=0: the pin is active LOW,0x00000001=1: the pin is active HIGH"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x40)++0x03
line.long 0x00 "PORT_ENA[$1],GPIO grouped interrupt port 0 enable register $1"
abitfld.long 0x00 0.--31. "ENA,Enable port 0 pin for group interrupt" "0x00000000=0: the port 0 pin is disabled and..,0x00000001=1: the port 0 pin is enabled and.."
repeat.end
tree.end
repeat.end
tree.end
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
tree "GPIO"
base ad:0x4008C000
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2000)++0x03
line.long 0x00 "DIR[$1],Direction registers for all port GPIO pins $1"
abitfld.long 0x00 0.--31. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: input,0x00000001=1: output"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2080)++0x03
line.long 0x00 "MASK[$1],Mask register for all port GPIO pins $1"
abitfld.long 0x00 0.--31. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: PIOn_0 bit,0x00000001=1: Read MPORT"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2100)++0x03
line.long 0x00 "PIN[$1],Port pin register for all port GPIO pins $1"
abitfld.long 0x00 0.--31. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: Read: pin is low write: clear..,0x00000001=1: Read: pin is high write: set.."
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2180)++0x03
line.long 0x00 "MPIN[$1],Masked port register for all port GPIO pins $1"
abitfld.long 0x00 0.--31. "MPORTP,Masked port register (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: Read: pin is LOW and/or the..,0x00000001=1: Read: pin is HIGH and the.."
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2200)++0x03
line.long 0x00 "SET[$1],Write: Set register for port"
abitfld.long 0x00 0.--31. "SETP,Read or set output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: Read: output bit,0x00000001=1: Read: output bit write: set output.."
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2280)++0x03
line.long 0x00 "CLR[$1],Clear port for all port GPIO pins $1"
abitfld.long 0x00 0.--31. "CLRP,Clear output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: No operation,0x00000001=1: Clear output bit"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2300)++0x03
line.long 0x00 "NOT[$1],Toggle port for all port GPIO pins $1"
abitfld.long 0x00 0.--31. "NOTP,Toggle output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: no operation,0x00000001=1: Toggle output bit"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2380)++0x03
line.long 0x00 "DIRSET[$1],Set pin direction bits for port $1"
abitfld.long 0x00 0.--31. "DIRSETP,Set direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: No operation,0x00000001=1: Set direction bit"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2400)++0x03
line.long 0x00 "DIRCLR[$1],Clear pin direction bits for port $1"
abitfld.long 0x00 0.--31. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: No operation,0x00000001=1: Clear direction bit"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x2480)++0x03
line.long 0x00 "DIRNOT[$1],Toggle pin direction bits for port $1"
abitfld.long 0x00 0.--31. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: no operation,0x00000001=1: Toggle direction bit"
repeat.end
repeat 2. (increment 0 1)(increment  0 0x20)
tree "B[$1]"
group.byte ($2+0x00)++0x00
line.byte 0x00 "B_[0],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x01)++0x00
line.byte 0x00 "B_[1],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x02)++0x00
line.byte 0x00 "B_[2],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x03)++0x00
line.byte 0x00 "B_[3],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x04)++0x00
line.byte 0x00 "B_[4],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x05)++0x00
line.byte 0x00 "B_[5],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x06)++0x00
line.byte 0x00 "B_[6],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x07)++0x00
line.byte 0x00 "B_[7],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x08)++0x00
line.byte 0x00 "B_[8],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x09)++0x00
line.byte 0x00 "B_[9],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x0A)++0x00
line.byte 0x00 "B_[10],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x0B)++0x00
line.byte 0x00 "B_[11],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x0C)++0x00
line.byte 0x00 "B_[12],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x0D)++0x00
line.byte 0x00 "B_[13],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x0E)++0x00
line.byte 0x00 "B_[14],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x0F)++0x00
line.byte 0x00 "B_[15],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x10)++0x00
line.byte 0x00 "B_[16],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x11)++0x00
line.byte 0x00 "B_[17],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x12)++0x00
line.byte 0x00 "B_[18],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x13)++0x00
line.byte 0x00 "B_[19],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x14)++0x00
line.byte 0x00 "B_[20],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x15)++0x00
line.byte 0x00 "B_[21],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x16)++0x00
line.byte 0x00 "B_[22],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x17)++0x00
line.byte 0x00 "B_[23],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x18)++0x00
line.byte 0x00 "B_[24],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x19)++0x00
line.byte 0x00 "B_[25],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x1A)++0x00
line.byte 0x00 "B_[26],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x1B)++0x00
line.byte 0x00 "B_[27],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x1C)++0x00
line.byte 0x00 "B_[28],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x1D)++0x00
line.byte 0x00 "B_[29],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x1E)++0x00
line.byte 0x00 "B_[30],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
group.byte ($2+0x1F)++0x00
line.byte 0x00 "B_[31],Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
tree.end
repeat.end
repeat 2. (increment 0 1)(increment  0 0x1080)
tree "W[$1]"
group.long ($2+0x1000)++0x03
line.long 0x00 "W_[0],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1004)++0x03
line.long 0x00 "W_[1],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1008)++0x03
line.long 0x00 "W_[2],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x100C)++0x03
line.long 0x00 "W_[3],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1010)++0x03
line.long 0x00 "W_[4],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1014)++0x03
line.long 0x00 "W_[5],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1018)++0x03
line.long 0x00 "W_[6],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x101C)++0x03
line.long 0x00 "W_[7],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1020)++0x03
line.long 0x00 "W_[8],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1024)++0x03
line.long 0x00 "W_[9],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1028)++0x03
line.long 0x00 "W_[10],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x102C)++0x03
line.long 0x00 "W_[11],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1030)++0x03
line.long 0x00 "W_[12],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1034)++0x03
line.long 0x00 "W_[13],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1038)++0x03
line.long 0x00 "W_[14],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x103C)++0x03
line.long 0x00 "W_[15],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1040)++0x03
line.long 0x00 "W_[16],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1044)++0x03
line.long 0x00 "W_[17],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1048)++0x03
line.long 0x00 "W_[18],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x104C)++0x03
line.long 0x00 "W_[19],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1050)++0x03
line.long 0x00 "W_[20],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1054)++0x03
line.long 0x00 "W_[21],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1058)++0x03
line.long 0x00 "W_[22],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x105C)++0x03
line.long 0x00 "W_[23],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1060)++0x03
line.long 0x00 "W_[24],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1064)++0x03
line.long 0x00 "W_[25],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1068)++0x03
line.long 0x00 "W_[26],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x106C)++0x03
line.long 0x00 "W_[27],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1070)++0x03
line.long 0x00 "W_[28],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1074)++0x03
line.long 0x00 "W_[29],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x1078)++0x03
line.long 0x00 "W_[30],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
group.long ($2+0x107C)++0x03
line.long 0x00 "W_[31],Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
tree.end
repeat.end
tree.end
tree "SECGPIO"
base ad:0x400A8000
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "B0_$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "B0_$1,Byte pin registers for all port GPIO pins"
bitfld.byte 0x00 0. "PBYTE,Read: state of the pin PIOm_n regardless of direction masking or alternate function except that pins configured as analog I/O always read as 0" "0,1"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1000)++0x03
line.long 0x00 "W0_$1,Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1040)++0x03
line.long 0x00 "W0_$1,Word pin registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "PWORD," "0x00000000=0: clear output bit,0xFFFFFFFF=4294967295: set output bit"
repeat.end
group.long 0x2000++0x03
line.long 0x00 "DIR0,Direction registers for all port GPIO pins"
abitfld.long 0x00 0.--31. "DIRP,Selects pin direction for pin PIOm_n (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: input,0x00000001=1: output"
group.long 0x2080++0x03
line.long 0x00 "MASK0,Mask register for all port GPIO pins"
abitfld.long 0x00 0.--31. "MASKP,Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: PIOn_0 bit,0x00000001=1: Read MPORT"
group.long 0x2100++0x03
line.long 0x00 "PIN0,Port pin register for all port GPIO pins"
abitfld.long 0x00 0.--31. "PORT,Reads pin states or loads output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: Read: pin is low write: clear..,0x00000001=1: Read: pin is high write: set.."
group.long 0x2180++0x03
line.long 0x00 "MPIN0,Masked port register for all port GPIO pins"
abitfld.long 0x00 0.--31. "MPORTP,Masked port register (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: Read: pin is LOW and/or the..,0x00000001=1: Read: pin is HIGH and the.."
group.long 0x2200++0x03
line.long 0x00 "SET0,Write: Set register for port"
abitfld.long 0x00 0.--31. "SETP,Read or set output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: Read: output bit,0x00000001=1: Read: output bit write: set output.."
wgroup.long 0x2280++0x03
line.long 0x00 "CLR0,Clear port for all port GPIO pins"
abitfld.long 0x00 0.--31. "CLRP,Clear output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: No operation,0x00000001=1: Clear output bit"
wgroup.long 0x2300++0x03
line.long 0x00 "NOT0,Toggle port for all port GPIO pins"
abitfld.long 0x00 0.--31. "NOTP,Toggle output bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: no operation,0x00000001=1: Toggle output bit"
wgroup.long 0x2380++0x03
line.long 0x00 "DIRSET0,Set pin direction bits for port"
abitfld.long 0x00 0.--31. "DIRSETP,Set direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: No operation,0x00000001=1: Set direction bit"
wgroup.long 0x2400++0x03
line.long 0x00 "DIRCLR0,Clear pin direction bits for port"
abitfld.long 0x00 0.--31. "DIRCLRP,Clear direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: No operation,0x00000001=1: Clear direction bit"
wgroup.long 0x2480++0x03
line.long 0x00 "DIRNOT0,Toggle pin direction bits for port"
abitfld.long 0x00 0.--31. "DIRNOTP,Toggle direction bits (bit 0 = PIOn_0 bit 1 = PIOn_1 etc.)" "0x00000000=0: no operation,0x00000001=1: Toggle direction bit"
tree.end
tree.end
tree "HASHCRYPT (Hash-Crypt peripheral)"
base ad:0x400A4000
group.long 0x00++0x03
line.long 0x00 "CTRL,Control register to enable and operate Hash and Crypto"
bitfld.long 0x00 12. "HASHSWPB,If 1 will swap bytes in the word for SHA hashing" "0,1"
bitfld.long 0x00 9. "DMA_O,Written to 1 to use DMA to drain the digest/output" "0: DMA is not used,?..."
newline
bitfld.long 0x00 8. "DMA_I,Written with 1 to use DMA to fill INDATA" "0: DMA is not used,1: DMA will push in the data"
bitfld.long 0x00 4. "New_Hash,Written with 1 when starting a new Hash/Crypto" "?,1: Starts a new Hash/Crypto and initializes the.."
newline
bitfld.long 0x00 0.--2. "Mode,The operational mode to use or 0 if none" "0: DISABLED,1: SHA1 is enabled,2: SHA2-256 is enabled,?,4: AES if available (see also CRYPTCFG register..,5: ICB-AES if available (see also CRYPTCFG..,?..."
group.long 0x00++0x03
line.long 0x00 "CTRL,Control register to enable and operate Hash and Crypto"
bitfld.long 0x00 13. "AESFLUSH,Flushes the AES engine registers" "0: Do not flush the AES engine registers,1: Flush the AES engine registers"
bitfld.long 0x00 12. "HASHSWPB,If 1 will swap bytes in the word for SHA hashing" "0,1"
newline
bitfld.long 0x00 9. "DMA_O,Written to 1 to use DMA to drain the digest/output" "0: DMA is not used,?..."
bitfld.long 0x00 8. "DMA_I,Written with 1 to use DMA to fill INDATA" "0: DMA is not used,1: DMA will push in the data"
newline
bitfld.long 0x00 5. "Reload,If 1 allows the SHA RELOAD registers to be used" "?,1: Allow RELOAD registers to be used"
bitfld.long 0x00 4. "New_Hash,Written with 1 when starting a new Hash/Crypto" "?,1: Starts a new Hash/Crypto and initializes the.."
newline
bitfld.long 0x00 0.--2. "Mode,The operational mode to use or 0 if none" "0: DISABLED,1: SHA1 is enabled,2: SHA2-256 is enabled,?,4: AES if available (see also CRYPTCFG register..,?..."
group.long 0x04++0x03
line.long 0x00 "STATUS,Indicates status of Hash peripheral"
rbitfld.long 0x00 16.--21. "ICBIDX,If ICB-AES is selected then reads as the ICB index count based on ICBSTRM (from CRYPTCFG)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 5. "NEEDIV,Indicates the block wants an IV/NONE to be written in (set along with WAITING)" "0: No IV/Nonce is needed either because written..,1: IV/Nonce is needed and INDATA/ALIAS will be.."
newline
rbitfld.long 0x00 4. "NEEDKEY,Indicates the block wants the key to be written in (set along with WAITING)" "0: No Key is needed and writes will not be..,1: Key is needed and INDATA/ALIAS will be.."
eventfld.long 0x00 2. "ERROR,If 1 an error occurred" "0: No error,1: An error occurred since last cleared (written.."
newline
rbitfld.long 0x00 1. "DIGEST,For Hash if 1 then a DIGEST is ready and waiting and there is no active next block already started" "0: No Digest is ready,1: Digest is ready"
rbitfld.long 0x00 0. "WAITING,If 1 the block is waiting for more data to process" "0: Not waiting for data - may be disabled or may..,1: Waiting for data to be written in (16 words)"
group.long 0x04++0x03
line.long 0x00 "STATUS,Indicates status of Hash peripheral"
rbitfld.long 0x00 9. "PRNGFAULT,PRNG fault status" "0: No PRNG fault has occurred,1: A PRNG fault has occurred"
rbitfld.long 0x00 8. "AESFAULT,AES fault status" "0: No AES fault has occurred,1: An AES fault has occurred"
newline
rbitfld.long 0x00 5. "NEEDIV,Indicates the block wants an IV/NONE to be written in (set along with WAITING)" "0: No IV/Nonce is needed either because written..,1: IV/Nonce is needed and INDATA/ALIAS will be.."
rbitfld.long 0x00 4. "NEEDKEY,Indicates the block wants the key to be written in (set along with WAITING)" "0: No Key is needed and writes will not be..,1: Key is needed and INDATA/ALIAS will be.."
newline
rbitfld.long 0x00 3. "FAULT,Indicates if an AES or PRNG fault has occurred" "0: No AES or PRNG fault has occurred,1: An AES or PRNG fault has occurred"
eventfld.long 0x00 2. "ERROR,If 1 an error occurred" "0: No error,1: An error occurred since last cleared (written.."
newline
rbitfld.long 0x00 1. "DIGEST,For Hash if 1 then a DIGEST is ready and waiting and there is no active next block already started" "0: No Digest is ready,1: Digest is ready"
rbitfld.long 0x00 0. "WAITING,If 1 the block is waiting for more data to process" "0: Not waiting for data - may be disabled or may..,1: Waiting for data to be written in (16 words)"
group.long 0x08++0x03
line.long 0x00 "INTENSET,Write 1 to enable interrupts reads back with which are set"
bitfld.long 0x00 2. "ERROR,Indicates if should interrupt on an ERROR (as defined in Status)" "0: Will not interrupt on Error,1: Will interrupt on Error (until cleared)"
bitfld.long 0x00 1. "DIGEST,Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence)" "0: Will not interrupt when Digest is ready,1: Will interrupt when Digest is ready"
newline
bitfld.long 0x00 0. "WAITING,Indicates if should interrupt when waiting for data input" "0: Will not interrupt when waiting,1: Will interrupt when waiting"
group.long 0x08++0x03
line.long 0x00 "INTENSET,Write 1 to enable interrupts reads back with which are set"
bitfld.long 0x00 3. "FAULT,Indicates if should interrupt on an AES or PRNG fault as indicated in the STATUS register" "0: No interrupt on an AES or PRNG fault,1: Interrupt on an AES or PRNG fault"
bitfld.long 0x00 2. "ERROR,Indicates if should interrupt on an ERROR (as defined in Status)" "0: Will not interrupt on Error,1: Will interrupt on Error (until cleared)"
newline
bitfld.long 0x00 1. "DIGEST,Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence)" "0: Will not interrupt when Digest is ready,1: Will interrupt when Digest is ready"
bitfld.long 0x00 0. "WAITING,Indicates if should interrupt when waiting for data input" "0: Will not interrupt when waiting,1: Will interrupt when waiting"
group.long 0x0C++0x03
line.long 0x00 "INTENCLR,Write 1 to clear interrupts"
eventfld.long 0x00 2. "ERROR,Write 1 to clear mask" "0,1"
eventfld.long 0x00 1. "DIGEST,Write 1 to clear mask" "0,1"
newline
eventfld.long 0x00 0. "WAITING,Write 1 to clear mask" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENCLR,Write 1 to clear interrupts"
eventfld.long 0x00 3. "FAULT,Write 1 to clear mask" "0,1"
eventfld.long 0x00 2. "ERROR,Write 1 to clear mask" "0,1"
newline
eventfld.long 0x00 1. "DIGEST,Write 1 to clear mask" "0,1"
eventfld.long 0x00 0. "WAITING,Write 1 to clear mask" "0,1"
group.long 0x10++0x03
line.long 0x00 "MEMCTRL,Setup Master to access memory (if available)"
hexmask.long.word 0x00 16.--26. 1. "COUNT,Number of 512-bit (128-bit if AES except 1st block which may include key and IV) blocks to copy starting at MEMADDR"
bitfld.long 0x00 0. "MASTER,Enables mastering" "0: Mastering is not used and the normal DMA or..,1: Mastering is enabled and DMA and INDATA.."
group.long 0x14++0x03
line.long 0x00 "MEMADDR,Address to start memory access from (if available)"
hexmask.long 0x00 0.--31. 1. "BASE,Address base to start copying from word aligned (so bits 1:0 must be 0)"
wgroup.long 0x20++0x03
line.long 0x00 "INDATA,Input of 16 words at a time to load up buffer"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x24++0x03
line.long 0x00 "ALIAS[0],Aliases to allow writing words in a burst"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x24++0x03
line.long 0x00 "ALIAS[0],no description available"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x28++0x03
line.long 0x00 "ALIAS[1],Aliases to allow writing words in a burst"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x28++0x03
line.long 0x00 "ALIAS[1],no description available"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x2C++0x03
line.long 0x00 "ALIAS[2],Aliases to allow writing words in a burst"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x2C++0x03
line.long 0x00 "ALIAS[2],no description available"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x30++0x03
line.long 0x00 "ALIAS[3],Aliases to allow writing words in a burst"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x30++0x03
line.long 0x00 "ALIAS[3],no description available"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x34++0x03
line.long 0x00 "ALIAS[4],Aliases to allow writing words in a burst"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x34++0x03
line.long 0x00 "ALIAS[4],no description available"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x38++0x03
line.long 0x00 "ALIAS[5],Aliases to allow writing words in a burst"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x38++0x03
line.long 0x00 "ALIAS[5],no description available"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x3C++0x03
line.long 0x00 "ALIAS[6],Aliases to allow writing words in a burst"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
wgroup.long 0x3C++0x03
line.long 0x00 "ALIAS[6],no description available"
hexmask.long 0x00 0.--31. 1. "DATA,Write next word in little-endian form"
rgroup.long 0x40++0x03
line.long 0x00 "DIGEST0[0],Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
rgroup.long 0x40++0x03
line.long 0x00 "DIGEST0[0],no description available"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
rgroup.long 0x44++0x03
line.long 0x00 "DIGEST0[1],Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
repeat 2. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x44)++0x03
line.long 0x00 "DIGEST[$1],no description available $1"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x48)++0x03
line.long 0x00 "DIGEST[$1],Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
repeat.end
rgroup.long 0x4C++0x03
line.long 0x00 "DIGEST0[3],no description available"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
rgroup.long 0x50++0x03
line.long 0x00 "DIGEST0[4],Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
rgroup.long 0x50++0x03
line.long 0x00 "DIGEST0[4],no description available"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
rgroup.long 0x54++0x03
line.long 0x00 "DIGEST0[5],Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
rgroup.long 0x54++0x03
line.long 0x00 "DIGEST0[5],no description available"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
rgroup.long 0x58++0x03
line.long 0x00 "DIGEST0[6],Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
repeat 2. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x58)++0x03
line.long 0x00 "DIGEST[$1],no description available $1"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
repeat.end
rgroup.long 0x5C++0x03
line.long 0x00 "DIGEST0[7],Result digest (when status says so): Is 1st 5 words if SHA1 used Is all 8 words if SHA2 used Is all 8 words if crypto or SHA512"
hexmask.long 0x00 0.--31. 1. "DIGEST,One word of the Digest or output"
group.long 0x80++0x03
line.long 0x00 "CRYPTCFG,Crypto settings for AES and Salsa and ChaCha"
bitfld.long 0x00 22.--23. "ICBSTRM,The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start)" "0: BLOCKS_8,1: BLOCKS_16,2: BLOCKS_32,3: BLOCKS_64"
bitfld.long 0x00 20.--21. "ICBSZ,This sets the ICB size between 32 and 128 bits using the following rules" "0: 32 bits of the IV/ctr are used (from 127:96),1: 64 bits of the IV/ctr are used (from 127:64),2: 96 bits of the IV/ctr are used (from 127:32),3: All 128 bits of the IV/ctr are used"
newline
bitfld.long 0x00 16. "STREAMLAST,Is 1 if last stream block" "0,1"
bitfld.long 0x00 10.--12. "AESCTRPOS,Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--9. "AESKEYSZ,Sets the AES key size" "0: 128 bit key,1: 192 bit key,2: 256 bit key,?..."
bitfld.long 0x00 7. "AESSECRET,Selects the Hidden Secret key vs" "0: User key provided in normal way,1: Secret key provided in hidden way by HW"
newline
bitfld.long 0x00 6. "AESDECRYPT,AES ECB direction" "0: ENCRYPT,1: DECRYPT"
bitfld.long 0x00 4.--5. "AESMODE,AES Cipher mode to use if plain AES" "0: ECB - used as is,1: CBC mode (see details on IV/nonce),2: CTR mode (see details on IV/nonce),?..."
newline
bitfld.long 0x00 3. "MSW1ST,If 1 load of key IV and data is MSW 1st for AES" "0,1"
bitfld.long 0x00 2. "SWAPDAT,If 1 will SWAP the data and IV inputs (bytes in each word)" "0,1"
newline
bitfld.long 0x00 1. "SWAPKEY,If 1 will Swap the key input (bytes in each word)" "0,1"
bitfld.long 0x00 0. "MSW1ST_OUT,If 1 OUTDATA0 will be read Most significant word 1st for AES" "0,1"
group.long 0x80++0x03
line.long 0x00 "CRYPTCFG,Crypto settings for AES and Salsa and ChaCha"
bitfld.long 0x00 16. "STREAMLAST,Is 1 if last stream block" "0,1"
bitfld.long 0x00 10.--12. "AESCTRPOS,Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for Salsa and ChaCha)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--9. "AESKEYSZ,Sets the AES key size" "0: 128 bit key,1: 192 bit key,2: 256 bit key,?..."
bitfld.long 0x00 7. "AESSECRET,Selects the Hidden Secret key vs" "0: User key provided in normal way,1: Secret key provided in hidden way by HW"
newline
bitfld.long 0x00 6. "AESDECRYPT,AES ECB direction" "0: ENCRYPT,1: DECRYPT"
bitfld.long 0x00 4.--5. "AESMODE,AES Cipher mode to use if plain AES" "0: ECB - used as is,1: CBC mode (see details on IV/nonce),2: CTR mode (see details on IV/nonce),?..."
newline
bitfld.long 0x00 3. "MSW1ST,If 1 load of key IV and data is MSW 1st for AES" "0,1"
bitfld.long 0x00 2. "SWAPDAT,If 1 will SWAP the data and IV inputs (bytes in each word)" "0,1"
newline
bitfld.long 0x00 1. "SWAPKEY,If 1 will Swap the key input (bytes in each word)" "0,1"
bitfld.long 0x00 0. "MSW1ST_OUT,If 1 OUTDATA0 will be read Most significant word 1st for AES" "0,1"
group.long 0x84++0x03
line.long 0x00 "CONFIG,Returns the configuration of this block in this chip - indicates what services are available"
rbitfld.long 0x00 11. "ICB,1 if ICB over AES included" "0,1"
rbitfld.long 0x00 8. "SECRET,1 if AES Secret key available" "0,1"
newline
rbitfld.long 0x00 7. "AESKEY,1 if AES 192 and 256 also included" "0,1"
rbitfld.long 0x00 6. "AES,1 if AES 128 included" "0,1"
newline
rbitfld.long 0x00 3. "AHB,1 if AHB Master is enabled" "0,1"
rbitfld.long 0x00 1. "DMA,1 if DMA is connected" "0,1"
newline
rbitfld.long 0x00 0. "DUAL,1 if 2 x 512 bit buffers 0 if only 1 x 512 bit" "0,1"
group.long 0x84++0x03
line.long 0x00 "CONFIG,Returns the configuration of this block in this chip - indicates what services are available"
rbitfld.long 0x00 8. "SECRET,1 if AES Secret key available" "0,1"
rbitfld.long 0x00 7. "AESKEY,1 if AES 192 and 256 also included" "0,1"
newline
rbitfld.long 0x00 6. "AES,1 if AES 128 included" "0,1"
rbitfld.long 0x00 3. "AHB,1 if AHB Master is enabled" "0,1"
newline
rbitfld.long 0x00 1. "DMA,1 if DMA is connected" "0,1"
rbitfld.long 0x00 0. "DUAL,1 if 2 x 512 bit buffers 0 if only 1 x 512 bit" "0,1"
group.long 0x8C++0x03
line.long 0x00 "LOCK,Lock register allows locking to the current security level or unlocking by the lock holding level"
hexmask.long.word 0x00 4.--15. 1. "PATTERN,Must write 0xA75 to change lock state"
bitfld.long 0x00 0.--1. "SECLOCK,Write 1 to secure-lock this block (if running in a security state)" "0: Unlocks so block is open to all,1: Locks to the current security level,?..."
wgroup.long 0x90++0x03
line.long 0x00 "MASK[0],no description available"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
wgroup.long 0x90++0x03
line.long 0x00 "MASK[0],Allows Application to write a random mask for ICB use"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
wgroup.long 0x94++0x03
line.long 0x00 "MASK[1],no description available"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
repeat 2. (increment 0 1) (increment 0 0x4)
wgroup.long ($2+0x94)++0x03
line.long 0x00 "MASK[$1],Allows Application to write a random mask for ICB use"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
repeat.end
wgroup.long 0x98++0x03
line.long 0x00 "MASK[2],no description available"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
wgroup.long 0x9C++0x03
line.long 0x00 "MASK[3],Allows Application to write a random mask for ICB use"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
wgroup.long 0x9C++0x03
line.long 0x00 "MASK[3],no description available"
hexmask.long 0x00 0.--31. 1. "MASK,A random word"
repeat 8. (increment 0 1) (increment 0 0x4)
wgroup.long ($2+0xA0)++0x03
line.long 0x00 "RELOAD[$1],The WO digest-reload registers may be written with a saved Hash digest to allow continuation from where left off"
hexmask.long 0x00 0.--31. 1. "DIGEST,SHA Digest word to reload"
repeat.end
wgroup.long 0xD0++0x03
line.long 0x00 "PRNG_SEED,PRNG random input value used as an entropy source"
hexmask.long 0x00 0.--31. 1. "PRNG_SEED,Random input value used as an entropy source"
rgroup.long 0xD8++0x03
line.long 0x00 "PRNG_OUT,Provide random number"
hexmask.long 0x00 0.--31. 1. "PRNG_OUT,Provide random number"
tree.end
tree "I2C (Inter-Integrated Circuit)"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0x40086000 ad:0x40087000 ad:0x40088000 ad:0x40089000 ad:0x4008A000 ad:0x40096000 ad:0x40097000 ad:0x40098000)
tree "I2C$1"
base $2
group.long 0x800++0x03
line.long 0x00 "CFG,Configuration for shared functions"
bitfld.long 0x00 5. "HSCAPABLE,High-speed mode Capable enable" "0: Fast-mode plus,1: High-speed"
bitfld.long 0x00 4. "MONCLKSTR,Monitor function Clock Stretching" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 3. "TIMEOUTEN,I2C bus Time-out Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "MONEN,Monitor Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 1. "SLVEN,Slave Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "MSTEN,Master Enable" "0: Disabled,1: Enabled"
group.long 0x804++0x03
line.long 0x00 "STAT,Status register for Master Slave and Monitor functions"
bitfld.long 0x00 25. "SCLTIMEOUT,SCL Time-out Interrupt flag" "0: No time-out,1: Time-out"
bitfld.long 0x00 24. "EVENTTIMEOUT,Event Time-out Interrupt flag" "0: No time-out,1: Event time-out"
newline
bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0: Not idle,1: Idle"
rbitfld.long 0x00 18. "MONACTIVE,Monitor Active flag" "0: Inactive,1: Active"
newline
bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0: No overrun,1: Overrun"
rbitfld.long 0x00 16. "MONRDY,Monitor Ready" "0: No data,1: Data waiting"
newline
bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0: Not deselected,1: Deselected"
rbitfld.long 0x00 14. "SLVSEL,Slave selected flag" "0: Not selected,1: Selected"
newline
rbitfld.long 0x00 12.--13. "SLVIDX,Slave address match Index" "0: Address 0,1: Address 1,2: Address 2,3: Address 3"
rbitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching" "0: Stretching,1: Not stretching"
newline
rbitfld.long 0x00 9.--10. "SLVSTATE,Slave State code" "0: Slave address,1: Slave receive,2: Slave transmit,?..."
rbitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0: In progress,1: Pending"
newline
bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0: No Start/Stop Error has occurred,1: The Master function has experienced a.."
bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0: No Arbitration Loss has occurred,1: Arbitration loss"
newline
rbitfld.long 0x00 1.--3. "MSTSTATE,Master State code" "0: Idle,1: Receive ready,2: Transmit ready,3: NACK Address,4: NACK Data,?..."
rbitfld.long 0x00 0. "MSTPENDING,Master Pending" "0: In progress,1: Pending"
group.long 0x808++0x03
line.long 0x00 "INTENSET,Interrupt Enable Set and read register"
bitfld.long 0x00 25. "SCLTIMEOUTEN,SCL time-out interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 24. "EVENTTIMEOUTEN,Event time-out interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 19. "MONIDLEEN,Monitor Idle interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 17. "MONOVEN,Monitor Overrun interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 16. "MONRDYEN,Monitor data Ready interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 15. "SLVDESELEN,Slave Deselect interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 11. "SLVNOTSTREN,Slave Not Stretching interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "SLVPENDINGEN,Slave Pending interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "MSTSTSTPERREN,Master Start/Stop Error interrupt Enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 4. "MSTARBLOSSEN,Master Arbitration Loss interrupt Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "MSTPENDINGEN,Master Pending interrupt Enable" "0: Disabled,1: Enabled"
wgroup.long 0x80C++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 25. "SCLTIMEOUTCLR,SCL time-out interrupt clear" "0,1"
bitfld.long 0x00 24. "EVENTTIMEOUTCLR,Event time-out interrupt clear" "0,1"
newline
bitfld.long 0x00 19. "MONIDLECLR,Monitor Idle interrupt clear" "0,1"
bitfld.long 0x00 17. "MONOVCLR,Monitor Overrun interrupt clear" "0,1"
newline
bitfld.long 0x00 16. "MONRDYCLR,Monitor data Ready interrupt clear" "0,1"
bitfld.long 0x00 15. "SLVDESELCLR,Slave Deselect interrupt clear" "0,1"
newline
bitfld.long 0x00 11. "SLVNOTSTRCLR,Slave Not Stretching interrupt clear" "0,1"
bitfld.long 0x00 8. "SLVPENDINGCLR,Slave Pending interrupt clear" "0,1"
newline
bitfld.long 0x00 6. "MSTSTSTPERRCLR,Master Start/Stop Error interrupt clear" "0,1"
bitfld.long 0x00 4. "MSTARBLOSSCLR,Master Arbitration Loss interrupt clear" "0,1"
newline
bitfld.long 0x00 0. "MSTPENDINGCLR,Master Pending interrupt clear" "0,1"
group.long 0x810++0x03
line.long 0x00 "TIMEOUT,Time-out value register"
abitfld.long 0x00 4.--15. "TO,Time-out time value" "0x000=0: A time-out will occur after 16 counts..,0x001=1: A time-out will occur after 32 counts..,0xFFF=4095: A time-out will occur after 65 536.."
bitfld.long 0x00 0.--3. "TOMIN,Time-out time value bottom four bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x814++0x03
line.long 0x00 "CLKDIV,Clock pre-divider for the entire I2C interface"
abitfld.long 0x00 0.--15. "DIVVAL,This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that need an internal clock in order to operate" "0x0000=0: FCLK is used directly by the I2C,0x0001=1: FCLK is divided by 2 before use,0x0002=2: FCLK is divided by 3 before use,0xFFFF=65535: FCLK is divided by 65 536 before use"
rgroup.long 0x818++0x03
line.long 0x00 "INTSTAT,Interrupt Status register for Master Slave and Monitor functions"
bitfld.long 0x00 25. "SCLTIMEOUT,SCL time-out Interrupt flag" "0,1"
bitfld.long 0x00 24. "EVENTTIMEOUT,Event time-out Interrupt flag" "0,1"
newline
bitfld.long 0x00 19. "MONIDLE,Monitor Idle flag" "0,1"
bitfld.long 0x00 17. "MONOV,Monitor Overflow flag" "0,1"
newline
bitfld.long 0x00 16. "MONRDY,Monitor Ready" "0,1"
bitfld.long 0x00 15. "SLVDESEL,Slave Deselected flag" "0,1"
newline
bitfld.long 0x00 11. "SLVNOTSTR,Slave Not Stretching status" "0,1"
bitfld.long 0x00 8. "SLVPENDING,Slave Pending" "0,1"
newline
bitfld.long 0x00 6. "MSTSTSTPERR,Master Start/Stop Error flag" "0,1"
bitfld.long 0x00 4. "MSTARBLOSS,Master Arbitration Loss flag" "0,1"
newline
bitfld.long 0x00 0. "MSTPENDING,Master Pending" "0,1"
group.long 0x820++0x03
line.long 0x00 "MSTCTL,Master control register"
bitfld.long 0x00 3. "MSTDMA,Master DMA enable" "0: Disable,1: Enable"
bitfld.long 0x00 2. "MSTSTOP,Master Stop control" "0: No effect,1: Stop"
newline
bitfld.long 0x00 1. "MSTSTART,Master Start control" "0: No effect,1: Start"
bitfld.long 0x00 0. "MSTCONTINUE,Master Continue" "0: No effect,1: Continue"
group.long 0x824++0x03
line.long 0x00 "MSTTIME,Master timing configuration"
bitfld.long 0x00 4.--6. "MSTSCLHIGH,Master SCL High time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks"
bitfld.long 0x00 0.--2. "MSTSCLLOW,Master SCL Low time" "0: 2 clocks,1: 3 clocks,2: 4 clocks,3: 5 clocks,4: 6 clocks,5: 7 clocks,6: 8 clocks,7: 9 clocks"
group.long 0x828++0x03
line.long 0x00 "MSTDAT,Combined Master receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Master function data register"
group.long 0x840++0x03
line.long 0x00 "SLVCTL,Slave control register"
bitfld.long 0x00 9. "AUTOMATCHREAD,When AUTOACK is set this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0" "0: The expected next operation in Automatic Mode..,1: The expected next operation in Automatic Mode.."
bitfld.long 0x00 8. "AUTOACK,Automatic Acknowledge.When this bit is set it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately this is used with DMA to allow processing of the data without intervention" "0: Normal non-automatic operation,1: A header with matching SLVADR0 and matching.."
newline
bitfld.long 0x00 3. "SLVDMA,Slave DMA enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "SLVNACK,Slave NACK" "0: No effect,1: NACK"
newline
bitfld.long 0x00 0. "SLVCONTINUE,Slave Continue" "0: No effect,1: Continue"
group.long 0x844++0x03
line.long 0x00 "SLVDAT,Combined Slave receiver and transmitter data register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Slave function data register"
group.long 0x848++0x03
line.long 0x00 "SLVADR0,Slave address register"
bitfld.long 0x00 15. "AUTONACK,Automatic NACK operation" "0: Normal operation matching I2C addresses are..,1: Automatic-only mode"
hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address"
newline
bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored Slave Address n is ignored"
repeat 3. (strings "1" "2" "3" )(list 0x00 0x04 0x08 )
group.long ($2+0x84C)++0x03
line.long 0x00 "SLVADR$1,Slave address register"
hexmask.long.byte 0x00 1.--7. 1. "SLVADR,Slave Address"
bitfld.long 0x00 0. "SADISABLE,Slave Address n Disable" "0: Enabled,1: Ignored Slave Address n is ignored"
repeat.end
group.long 0x858++0x03
line.long 0x00 "SLVQUAL0,Slave Qualification for address 0"
hexmask.long.byte 0x00 1.--7. 1. "SLVQUAL0,Slave address Qualifier for address 0"
bitfld.long 0x00 0. "QUALMODE0,Qualify mode for slave address 0" "0: Mask,1: Extend"
rgroup.long 0x880++0x03
line.long 0x00 "MONRXDAT,Monitor receiver data register"
bitfld.long 0x00 10. "MONNACK,Monitor Received NACK" "0: Acknowledged,1: Not acknowledged"
bitfld.long 0x00 9. "MONRESTART,Monitor Received Repeated Start" "0: No repeated start detected,1: Repeated start detected"
newline
bitfld.long 0x00 8. "MONSTART,Monitor Received Start" "0: No start detected,1: Start detected"
hexmask.long.byte 0x00 0.--7. 1. "MONRXDAT,Monitor function Receiver Data"
group.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
tree.end
repeat.end
tree.end
tree "I2S (Inter-Integrated Sound Bus Controller)"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0x40086000 ad:0x40087000 ad:0x40088000 ad:0x40089000 ad:0x4008A000 ad:0x40096000 ad:0x40097000 ad:0x40098000)
tree "I2S$1"
base $2
group.long 0xC00++0x03
line.long 0x00 "CFG1,Configuration register 1 for the primary channel pair"
bitfld.long 0x00 16.--20. "DATALEN,Data Length minus 1 encoded defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm" "?,?,2: not supported,3: data is 4 bits in length,4: data is 5 bits in length,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: data is 32 bits in length"
bitfld.long 0x00 13. "WS_POL,WS polarity" "0: Data frames begin at a falling edge of WS..,1: WS is inverted resulting in a data frame.."
newline
bitfld.long 0x00 12. "SCK_POL,SCK polarity" "0: Data is launched on SCK falling edges and..,1: Data is launched on SCK rising edges and.."
bitfld.long 0x00 10. "ONECHANNEL,Single channel mode" "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as.."
newline
bitfld.long 0x00 9. "LEFTJUST,Left Justify data" "0: Data is transferred between the FIFO and the..,1: Data is transferred between the FIFO and the.."
bitfld.long 0x00 8. "RIGHTLOW,Right channel data is in the Low portion of FIFO data" "0: The right channel is taken from the high part..,1: The right channel is taken from the low part.."
newline
bitfld.long 0x00 6.--7. "MODE,Selects the basic I2S operating mode" "0: I2S mode a.k.a,1: DSP mode where WS has a 50% duty cycle,2: DSP mode where WS has a one clock long pulse..,3: DSP mode where WS has a one data slot long.."
bitfld.long 0x00 4.--5. "MSTSLVCFG,Master / slave configuration selection determining how SCK and WS are used by all channel pairs in this Flexcomm" "0: Normal slave mode the default mode,1: WS synchronized master,2: Master using an existing SCK,3: Normal master mode"
newline
bitfld.long 0x00 2.--3. "PAIRCOUNT,Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms" "0: 1 I2S channel pairs in this flexcomm,1: 2 I2S channel pairs in this flexcomm,2: 3 I2S channel pairs in this flexcomm,3: 4 I2S channel pairs in this flexcomm"
bitfld.long 0x00 1. "DATAPAUSE,Data flow Pause" "0: Normal operation or resuming normal operation..,1: A pause in the data flow is being requested"
newline
bitfld.long 0x00 0. "MAINENABLE,Main enable for I 2S function in this Flexcomm" "0: All I 2S channel pairs in this Flexcomm are..,1: This I 2S channel pair is enabled"
group.long 0xC04++0x03
line.long 0x00 "CFG2,Configuration register 2 for the primary channel pair"
abitfld.long 0x00 16.--24. "POSITION,Data Position" "0x000=0: data begins at bit position 0 (the..,0x001=1: data begins at bit position 1 within..,0x002=2: data begins at bit position 2 within.."
abitfld.long 0x00 0.--10. "FRAMELEN,Frame Length minus 1 encoded defines the number of clocks and data bits in the frames that this channel pair participates in" "0x002=2: not supported,0x003=3: frame is 4 bits in total length,0x004=4: frame is 5 bits in total length,0x7FF=2047: frame is 2048 bits in total length.."
group.long 0xC08++0x03
line.long 0x00 "STAT,Status register for the primary channel pair"
rbitfld.long 0x00 3. "DATAPAUSED,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in.."
rbitfld.long 0x00 2. "LR,Left/Right indication" "0: Left channel,1: Right channel"
newline
bitfld.long 0x00 1. "SLVFRMERR,Slave Frame Error flag" "0: No error has been recorded,1: An error has been recorded for some channel.."
rbitfld.long 0x00 0. "BUSY,Busy status for the primary channel pair" "0: The transmitter/receiver for channel pair is..,1: The transmitter/receiver for channel pair is.."
group.long 0xC1C++0x03
line.long 0x00 "DIV,Clock divider used by all channel pairs"
abitfld.long 0x00 0.--11. "DIV,This field controls how this I2S block uses the Flexcomm function clock" "0x000=0: The Flexcomm function clock is used..,0x001=1: The Flexcomm function clock is divided..,0x002=2: The Flexcomm function clock is divided..,0xFFF=4095: The Flexcomm function clock is.."
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
newline
bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.."
bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x00 3. "PACK48,Packing format for 48-bit data" "0: 48-bit I2S FIFO entries are handled as all..,1: 48-bit I2S FIFO entries are handled as.."
newline
bitfld.long 0x00 2. "TXI2SE0,Transmit I2S empty 0" "0: If the TX FIFO becomes empty the last value..,1: If the TX FIFO becomes empty 0 is sent"
bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1"
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1"
newline
rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15"
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
newline
bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long 0x00 0.--31. 1. "TXDATA,Transmit data to the FIFO"
wgroup.long 0xE24++0x03
line.long 0x00 "FIFOWR48H,FIFO write data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
hexmask.long 0x00 0.--31. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE34++0x03
line.long 0x00 "FIFORD48H,FIFO read data for upper data bits"
hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
hexmask.long 0x00 0.--31. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE44++0x03
line.long 0x00 "FIFORD48HNOPOP,FIFO data read for upper data bits with no FIFO pop"
hexmask.long.tbyte 0x00 0.--23. 1. "RXDATA,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,I2S Module identification"
hexmask.long.word 0x00 16.--31. 1. "ID,Unique module identifier for this IP block"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation starting at 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
repeat 3. (increment 0 1)(increment  0 0x20)
tree "SECCHANNEL[$1]"
group.long ($2+0xC20)++0x03
line.long 0x00 "PCFG1,Configuration register 1 for channel pair"
bitfld.long 0x00 10. "ONECHANNEL,Single channel mode" "0: I2S data for this channel pair is treated as..,1: I2S data for this channel pair is treated as.."
bitfld.long 0x00 0. "PAIRENABLE,Enable for this channel pair" "0: This I2S channel pair is disabled,1: This I2S channel pair is enabled"
group.long ($2+0xC24)++0x03
line.long 0x00 "PCFG2,Configuration register 2 for channel pair"
hexmask.long.word 0x00 16.--24. 1. "POSITION,Data Position"
group.long ($2+0xC28)++0x03
line.long 0x00 "PSTAT,Status register for channel pair"
rbitfld.long 0x00 3. "DATAPAUSED,Data Paused status flag" "0: Data is not currently paused,1: A data pause has been requested and is now in.."
bitfld.long 0x00 2. "LR,Left/Right indication" "0,1"
newline
bitfld.long 0x00 1. "SLVFRMERR,Save Frame Error flag" "0,1"
bitfld.long 0x00 0. "BUSY,Busy status for this channel pair" "0: The transmitter/receiver for this channel..,1: The transmitter/receiver for this channel.."
tree.end
repeat.end
tree.end
repeat.end
tree.end
tree "INPUTMUX (Input multiplexing)"
base ad:0x40006000
group.long 0x00++0x03
line.long 0x00 "SCT0_INMUX[0],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24,25: val24,26: val24,27: val24,28: val24,29: val24,30: val24,31: val24"
group.long 0x00++0x03
line.long 0x00 "SCT0_INMUX[0],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: val15,16: val16,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x00++0x03
line.long 0x00 "SCT0_INMUX[0],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x04++0x03
line.long 0x00 "SCT0_INMUX[1],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24,25: val24,26: val24,27: val24,28: val24,29: val24,30: val24,31: val24"
group.long 0x04++0x03
line.long 0x00 "SCT0_INMUX[1],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x04++0x03
line.long 0x00 "SCT0_INMUX[1],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: val15,16: val16,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x08++0x03
line.long 0x00 "SCT0_INMUX[2],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24,25: val24,26: val24,27: val24,28: val24,29: val24,30: val24,31: val24"
group.long 0x08++0x03
line.long 0x00 "SCT0_INMUX[2],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x08++0x03
line.long 0x00 "SCT0_INMUX[2],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: val15,16: val16,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x0C++0x03
line.long 0x00 "SCT0_INMUX[3],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24,25: val24,26: val24,27: val24,28: val24,29: val24,30: val24,31: val24"
group.long 0x0C++0x03
line.long 0x00 "SCT0_INMUX[3],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x0C)++0x03
line.long 0x00 "SCT0_INMUX[$1],Input mux register for SCT0 input $1"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: val15,16: val16,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
repeat.end
group.long 0x10++0x03
line.long 0x00 "SCT0_INMUX[4],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x10)++0x03
line.long 0x00 "SCT0_INMUX[$1],Input mux register for SCT0 input $1"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24,25: val24,26: val24,27: val24,28: val24,29: val24,30: val24,31: val24"
repeat.end
group.long 0x14++0x03
line.long 0x00 "SCT0_INMUX[5],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x14++0x03
line.long 0x00 "SCT0_INMUX[5],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: val15,16: val16,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x18++0x03
line.long 0x00 "SCT0_INMUX[6],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24,25: val24,26: val24,27: val24,28: val24,29: val24,30: val24,31: val24"
group.long 0x18++0x03
line.long 0x00 "SCT0_INMUX[6],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: USB0_FRAME_TOGGLE,16: USB1_FRAME_TOGGLE,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x18++0x03
line.long 0x00 "SCT0_INMUX[6],Input mux register for SCT0 input"
bitfld.long 0x00 0.--4. "INP_N,Input number to SCT0 inputs 0 to 6" "0: SCT_GPI0 function selected from IOCON register,1: SCT_GPI1 function selected from IOCON register,2: SCT_GPI2 function selected from IOCON register,3: SCT_GPI3 function selected from IOCON register,4: SCT_GPI4 function selected from IOCON register,5: SCT_GPI5 function selected from IOCON register,6: SCT_GPI6 function selected from IOCON register,7: SCT_GPI7 function selected from IOCON register,8: T0_OUT0 ctimer 0 match[0] output,9: T1_OUT0 ctimer 1 match[0] output,10: T2_OUT0 ctimer 2 match[0] output,11: T3_OUT0 ctimer 3 match[0] output,12: T4_OUT0 ctimer 4 match[0] output,13: ADC_IRQ interrupt request from ADC,14: GPIOINT_BMATCH,15: val15,16: val16,17: COMP_OUTPUT output from analog comparator,18: I2S_SHARED_SCK[0] output from I2S pin sharing,19: I2S_SHARED_SCK[1] output from I2S pin sharing,20: I2S_SHARED_WS[0] output from I2S pin sharing,21: I2S_SHARED_WS[1] output from I2S pin sharing,22: ARM_TXEV interrupt event from cpu0 or cpu1,23: DEBUG_HALTED from cpu0 or cpu1,24: val24_24,25: val24_25,26: val24_26,27: val24_27,28: val24_28,29: val24_29,30: val24_30,31: val24_31"
group.long 0x20++0x03
line.long 0x00 "TIMER0CAPTSEL[0],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x20++0x03
line.long 0x00 "TIMER0CAPTSEL[0],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x20++0x03
line.long 0x00 "TIMER0CAPTSEL[0],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x24++0x03
line.long 0x00 "TIMER0CAPTSEL[1],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x24++0x03
line.long 0x00 "TIMER0CAPTSEL[1],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x24)++0x03
line.long 0x00 "TIMER0CAPTSEL[$1],Capture select registers for TIMER0 inputs $1"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
repeat.end
group.long 0x28++0x03
line.long 0x00 "TIMER0CAPTSEL[2],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x28)++0x03
line.long 0x00 "TIMER0CAPTSEL[$1],Capture select registers for TIMER0 inputs $1"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat.end
group.long 0x2C++0x03
line.long 0x00 "TIMER0CAPTSEL[3],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x2C++0x03
line.long 0x00 "TIMER0CAPTSEL[3],Capture select registers for TIMER0 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER0 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x40++0x03
line.long 0x00 "TIMER1CAPTSEL[0],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x40++0x03
line.long 0x00 "TIMER1CAPTSEL[0],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x40++0x03
line.long 0x00 "TIMER1CAPTSEL[0],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x44++0x03
line.long 0x00 "TIMER1CAPTSEL[1],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x44++0x03
line.long 0x00 "TIMER1CAPTSEL[1],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x44)++0x03
line.long 0x00 "TIMER1CAPTSEL[$1],Capture select registers for TIMER1 inputs $1"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat.end
group.long 0x48++0x03
line.long 0x00 "TIMER1CAPTSEL[2],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0x48)++0x03
line.long 0x00 "TIMER1CAPTSEL[$1],Capture select registers for TIMER1 inputs $1"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat.end
group.long 0x4C++0x03
line.long 0x00 "TIMER1CAPTSEL[3],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x4C++0x03
line.long 0x00 "TIMER1CAPTSEL[3],Capture select registers for TIMER1 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER1 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x60++0x03
line.long 0x00 "TIMER2CAPTSEL[0],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x60++0x03
line.long 0x00 "TIMER2CAPTSEL[0],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x60++0x03
line.long 0x00 "TIMER2CAPTSEL[0],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x64++0x03
line.long 0x00 "TIMER2CAPTSEL[1],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x64++0x03
line.long 0x00 "TIMER2CAPTSEL[1],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x64++0x03
line.long 0x00 "TIMER2CAPTSEL[1],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x68++0x03
line.long 0x00 "TIMER2CAPTSEL[2],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x68++0x03
line.long 0x00 "TIMER2CAPTSEL[2],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x68++0x03
line.long 0x00 "TIMER2CAPTSEL[2],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x6C++0x03
line.long 0x00 "TIMER2CAPTSEL[3],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x6C++0x03
line.long 0x00 "TIMER2CAPTSEL[3],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x6C++0x03
line.long 0x00 "TIMER2CAPTSEL[3],Capture select registers for TIMER2 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER2 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0xC0)++0x03
line.long 0x00 "PINTSEL[$1],Pin interrupt select register $1"
hexmask.long.byte 0x00 0.--6. 1. "INTPIN,Pin number select for pin interrupt or pattern match engine input"
repeat.end
group.long 0xE0++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[0],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
group.long 0xE0++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[0],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
group.long 0xE4++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[1],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
group.long 0xE4++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[1],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
group.long 0xE8++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[2],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
group.long 0xE8++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[2],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
group.long 0xEC++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[3],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
group.long 0xEC++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[3],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
group.long 0xF0++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[4],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0xF0)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x4)
group.long ($2+0xF4)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat.end
group.long 0xF8++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[6],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
group.long 0xFC++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[7],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0xFC)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat.end
group.long 0x100++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[8],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
group.long 0x104++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[9],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x104)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat.end
group.long 0x108++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[10],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
group.long 0x10C++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[11],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x10C)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat.end
group.long 0x110++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[12],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
group.long 0x114++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[13],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x114)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x118)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x11C)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x120)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat.end
group.long 0x124++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[17],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
group.long 0x128++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[18],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x128)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x12C)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x130)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat.end
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x134)++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[$1],Trigger select register for DMA0 channel $1"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22,23: val22,24: val22,25: val22,26: val22,27: val22,28: val22,29: val22,30: val22,31: val22"
repeat.end
group.long 0x138++0x03
line.long 0x00 "DMA0_ITRIG_INMUX[22],Trigger select register for DMA0 channel"
bitfld.long 0x00 0.--4. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 22)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER1 Match 0,7: Timer CTIMER1 Match 1,8: Timer CTIMER2 Match 0,9: Timer CTIMER2 Match 1,10: Timer CTIMER3 Match 0,11: Timer CTIMER3 Match 1,12: Timer CTIMER4 Match 0,13: Timer CTIMER4 Match 1,14: COMP_OUTPUT,15: DMA0 output trigger mux 0,16: DMA0 output trigger mux 1,17: DMA0 output trigger mux 1,18: DMA0 output trigger mux 3,19: SCT0 DMA request 0,20: SCT0 DMA request 1,21: HASH DMA RX trigger,22: val22_22,23: val22_23,24: val22_24,25: val22_25,26: val22_26,27: val22_27,28: val22_28,29: val22_29,30: val22_30,31: val22_31"
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x160)++0x03
line.long 0x00 "DMA0_OTRIG_INMUX[$1],DMA0 output trigger selection to become DMA0 trigger $1"
bitfld.long 0x00 0.--4. "INP,DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
group.long 0x180++0x03
line.long 0x00 "FREQMEAS_REF,Selection for frequency measurement reference clock"
bitfld.long 0x00 0.--4. "CLKIN,Clock source number (decimal value) for frequency measure function reference clock" "0: External main crystal oscilator (Clock_in),1: FRO 12MHz clock,2: FRO 96MHz clock,3: Watchdog oscillator / FRO1MHz clock,4: 32 kHz oscillator (32k_clk) clock,5: main clock (main_clock),6: FREQME_GPIO_CLK_A,7: FREQME_GPIO_CLK_B,?..."
group.long 0x184++0x03
line.long 0x00 "FREQMEAS_TARGET,Selection for frequency measurement target clock"
bitfld.long 0x00 0.--4. "CLKIN,Clock source number (decimal value) for frequency measure function target clock" "0: External main crystal oscilator (Clock_in),1: FRO 12MHz clock,2: FRO 96MHz clock,3: Watchdog oscillator / FRO1MHz clock,4: 32 kHz oscillator (32k_clk) clock,5: main clock (main_clock),6: FREQME_GPIO_CLK_A,7: FREQME_GPIO_CLK_B,?..."
group.long 0x1A0++0x03
line.long 0x00 "TIMER3CAPTSEL[0],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1A0++0x03
line.long 0x00 "TIMER3CAPTSEL[0],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1A0)++0x03
line.long 0x00 "TIMER3CAPTSEL[$1],Capture select registers for TIMER3 inputs $1"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: CT_INP17 function selected from IOCON register,18: CT_INP18 function selected from IOCON register,19: CT_INP19 function selected from IOCON register,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
repeat.end
group.long 0x1A4++0x03
line.long 0x00 "TIMER3CAPTSEL[1],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1A4)++0x03
line.long 0x00 "TIMER3CAPTSEL[$1],Capture select registers for TIMER3 inputs $1"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat.end
group.long 0x1A8++0x03
line.long 0x00 "TIMER3CAPTSEL[2],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: CT_INP17 function selected from IOCON register,18: CT_INP18 function selected from IOCON register,19: CT_INP19 function selected from IOCON register,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x1A8++0x03
line.long 0x00 "TIMER3CAPTSEL[2],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1AC++0x03
line.long 0x00 "TIMER3CAPTSEL[3],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: CT_INP17 function selected from IOCON register,18: CT_INP18 function selected from IOCON register,19: CT_INP19 function selected from IOCON register,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x1AC++0x03
line.long 0x00 "TIMER3CAPTSEL[3],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1AC++0x03
line.long 0x00 "TIMER3CAPTSEL[3],Capture select registers for TIMER3 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER3 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1C0++0x03
line.long 0x00 "TIMER4CAPTSEL[0],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1C0++0x03
line.long 0x00 "TIMER4CAPTSEL[0],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1C0++0x03
line.long 0x00 "TIMER4CAPTSEL[0],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: CT_INP17 function selected from IOCON register,18: CT_INP18 function selected from IOCON register,19: CT_INP19 function selected from IOCON register,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x1C4++0x03
line.long 0x00 "TIMER4CAPTSEL[1],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1C4++0x03
line.long 0x00 "TIMER4CAPTSEL[1],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: CT_INP17 function selected from IOCON register,18: CT_INP18 function selected from IOCON register,19: CT_INP19 function selected from IOCON register,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1C4)++0x03
line.long 0x00 "TIMER4CAPTSEL[$1],Capture select registers for TIMER4 inputs $1"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
repeat.end
group.long 0x1C8++0x03
line.long 0x00 "TIMER4CAPTSEL[2],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1C8++0x03
line.long 0x00 "TIMER4CAPTSEL[2],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: CT_INP17 function selected from IOCON register,18: CT_INP18 function selected from IOCON register,19: CT_INP19 function selected from IOCON register,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
group.long 0x1CC++0x03
line.long 0x00 "TIMER4CAPTSEL[3],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1CC++0x03
line.long 0x00 "TIMER4CAPTSEL[3],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: val17,18: val18,19: val19,20: val20,21: val21,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25_25,26: val25_26,27: val25_27,28: val25_28,29: val25_29,30: val25_30,31: val25_31"
group.long 0x1CC++0x03
line.long 0x00 "TIMER4CAPTSEL[3],Capture select registers for TIMER4 inputs"
bitfld.long 0x00 0.--4. "CAPTSEL,Input number to TIMER4 capture inputs 0 to 4" "0: CT_INP0 function selected from IOCON register,1: CT_INP1 function selected from IOCON register,2: CT_INP2 function selected from IOCON register,3: CT_INP3 function selected from IOCON register,4: CT_INP4 function selected from IOCON register,5: CT_INP5 function selected from IOCON register,6: CT_INP6 function selected from IOCON register,7: CT_INP7 function selected from IOCON register,8: CT_INP8 function selected from IOCON register,9: CT_INP9 function selected from IOCON register,10: CT_INP10 function selected from IOCON register,11: CT_INP11 function selected from IOCON register,12: CT_INP12 function selected from IOCON register,13: CT_INP13 function selected from IOCON register,14: CT_INP14 function selected from IOCON register,15: CT_INP15 function selected from IOCON register,16: CT_INP16 function selected from IOCON register,17: CT_INP17 function selected from IOCON register,18: CT_INP18 function selected from IOCON register,19: CT_INP19 function selected from IOCON register,20: USB0_FRAME_TOGGLE,21: USB1_FRAME_TOGGLE,22: COMP_OUTPUT output from analog comparator,23: I2S_SHARED_WS[0] output from I2S pin sharing,24: I2S_SHARED_WS[1] output from I2S pin sharing,25: val25,26: val25,27: val25,28: val25,29: val25,30: val25,31: val25"
repeat 2. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1E0)++0x03
line.long 0x00 "PINTSECSEL[$1],Pin interrupt secure select register $1"
bitfld.long 0x00 0.--5. "INTPIN,Pin number select for pin interrupt secure or pattern match engine input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 10. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "DMA1_ITRIG_INMUX[$1],Trigger select register for DMA1 channel $1"
bitfld.long 0x00 0.--3. "INP,Trigger input number (decimal value) for DMA channel n (n = 0 to 9)" "0: Pin interrupt 0,1: Pin interrupt 1,2: Pin interrupt 2,3: Pin interrupt 3,4: Timer CTIMER0 Match 0,5: Timer CTIMER0 Match 1,6: Timer CTIMER2 Match 0,7: Timer CTIMER4 Match 0,8: DMA1 output trigger mux 0,9: DMA1 output trigger mux 1,10: DMA1 output trigger mux 2,11: DMA1 output trigger mux 3,12: SCT0 DMA request 0,13: SCT0 DMA request 1,14: HASH DMA RX trigger,15: val15"
repeat.end
repeat 4. (increment 0 1) (increment 0 0x04)
group.long ($2+0x240)++0x03
line.long 0x00 "DMA1_OTRIG_INMUX[$1],DMA1 output trigger selection to become DMA1 trigger $1"
bitfld.long 0x00 0.--3. "INP,DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0x740++0x03
line.long 0x00 "DMA0_REQ_ENA,Enable DMA0 requests"
hexmask.long.tbyte 0x00 0.--22. 1. "REQ_ENA,Controls the 23 request inputs of DMA0"
wgroup.long 0x748++0x03
line.long 0x00 "DMA0_REQ_ENA_SET,Set one or several bits in DMA0_REQ_ENA register"
hexmask.long.tbyte 0x00 0.--22. 1. "SET,Write : If bit #i = 1 bit #i in DMA0_REQ_ENA register is set to 1 if bit #i = 0 no change in DMA0_REQ_ENA register"
wgroup.long 0x750++0x03
line.long 0x00 "DMA0_REQ_ENA_CLR,Clear one or several bits in DMA0_REQ_ENA register"
hexmask.long.tbyte 0x00 0.--22. 1. "CLR,Write : If bit #i = 1 bit #i in DMA0_REQ_ENA register is reset to 0 if bit #i = 0 no change in DMA0_REQ_ENA register"
group.long 0x760++0x03
line.long 0x00 "DMA1_REQ_ENA,Enable DMA1 requests"
hexmask.long.word 0x00 0.--9. 1. "REQ_ENA,Controls the 10 request inputs of DMA1"
wgroup.long 0x768++0x03
line.long 0x00 "DMA1_REQ_ENA_SET,Set one or several bits in DMA1_REQ_ENA register"
hexmask.long.word 0x00 0.--9. 1. "SET,Write : If bit #i = 1 bit #i in DMA1_REQ_ENA register is set to 1 if bit #i = 0 no change in DMA1_REQ_ENA register"
wgroup.long 0x770++0x03
line.long 0x00 "DMA1_REQ_ENA_CLR,Clear one or several bits in DMA1_REQ_ENA register"
hexmask.long.word 0x00 0.--9. 1. "CLR,Write : If bit #i = 1 bit #i in DMA1_REQ_ENA register is reset to 0 if bit #i = 0 no change in DMA1_REQ_ENA register"
group.long 0x780++0x03
line.long 0x00 "DMA0_ITRIG_ENA,Enable DMA0 triggers"
hexmask.long.tbyte 0x00 0.--21. 1. "ITRIG_ENA,Controls the 22 trigger inputs of DMA0"
wgroup.long 0x788++0x03
line.long 0x00 "DMA0_ITRIG_ENA_SET,Set one or several bits in DMA0_ITRIG_ENA register"
hexmask.long.tbyte 0x00 0.--21. 1. "SET,Write : If bit #i = 1 bit #i in DMA0_ITRIG_ENA register is set to 1 if bit #i = 0 no change in DMA0_ITRIG_ENA register"
wgroup.long 0x790++0x03
line.long 0x00 "DMA0_ITRIG_ENA_CLR,Clear one or several bits in DMA0_ITRIG_ENA register"
hexmask.long.tbyte 0x00 0.--21. 1. "CLR,Write : If bit #i = 1 bit #i in DMA0_ITRIG_ENA register is reset to 0 if bit #i = 0 no change in DMA0_ITRIG_ENA register"
group.long 0x7A0++0x03
line.long 0x00 "DMA1_ITRIG_ENA,Enable DMA1 triggers"
hexmask.long.word 0x00 0.--14. 1. "ITRIG_ENA,Controls the 15 trigger inputs of DMA1"
wgroup.long 0x7A8++0x03
line.long 0x00 "DMA1_ITRIG_ENA_SET,Set one or several bits in DMA1_ITRIG_ENA register"
hexmask.long.word 0x00 0.--14. 1. "SET,Write : If bit #i = 1 bit #i in DMA1_ITRIG_ENA register is set to 1 if bit #i = 0 no change in DMA1_ITRIG_ENA register"
wgroup.long 0x7B0++0x03
line.long 0x00 "DMA1_ITRIG_ENA_CLR,Clear one or several bits in DMA1_ITRIG_ENA register"
hexmask.long.word 0x00 0.--14. 1. "CLR,Write : If bit #i = 1 bit #i in DMA1_ITRIG_ENA register is reset to 0 if bit #i = 0 no change in DMA1_ITRIG_ENA register"
tree.end
tree "IOCON (I/O pin configuration)"
base ad:0x40001000
group.long 0x00++0x03
line.long 0x00 "PIO0_0,Digital I/O control for port 0 pins PIO0_0"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x00++0x03
line.long 0x00 "PIO0_0,Digital I/O control for port 0 pins PIO0_0"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x04)++0x03
line.long 0x00 "PIO0_$1,Digital I/O control for port 0 pins PIO0_ $1"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0x24++0x03
line.long 0x00 "PIO0_9,Digital I/O control for port 0 pins PIO0_9"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x24++0x03
line.long 0x00 "PIO0_9,Digital I/O control for port 0 pins PIO0_9"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x28++0x03
line.long 0x00 "PIO0_10,Digital I/O control for port 0 pins PIO0_10"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x28++0x03
line.long 0x00 "PIO0_10,Digital I/O control for port 0 pins PIO0_10"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x2C++0x03
line.long 0x00 "PIO0_11,Digital I/O control for port 0 pins PIO0_11"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x2C++0x03
line.long 0x00 "PIO0_11,Digital I/O control for port 0 pins PIO0_11"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x30++0x03
line.long 0x00 "PIO0_12,Digital I/O control for port 0 pins PIO0_12"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x30++0x03
line.long 0x00 "PIO0_12,Digital I/O control for port 0 pins PIO0_12"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 2. (strings "13" "14" )(list 0x0 0x4 )
group.long ($2+0x34)++0x03
line.long 0x00 "PIO0_$1,Digital I/O control for port 0 pins PIO0_ $1"
bitfld.long 0x00 15. "I2CFILTER,Configures I2C features for standard mode fast mode and Fast Mode Plus operation and High-Speed mode operation" "0: I2C 50 ns glitch filter enabled,1: I2C 10 ns glitch filter enabled"
bitfld.long 0x00 14. "EGP,Switch between GPIO mode and I2C mode" "0: I2C mode,1: GPIO mode"
newline
bitfld.long 0x00 13. "ECS,Pull-up current source enable in I2C mode" "0: Disabled,1: Enabled"
bitfld.long 0x00 12. "FILTEROFF,Controls input glitch filter" "0: Filter enabled,1: Filter disabled"
newline
bitfld.long 0x00 11. "SSEL,Supply Selection bit" "0: 3V3 Signaling in I2C Mode,1: 1V8 Signaling in I2C Mode"
bitfld.long 0x00 9. "OD,Controls open-drain mode in standard GPIO mode (EGP = 1)" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0x3C++0x03
line.long 0x00 "PIO0_15,Digital I/O control for port 0 pins PIO0_15"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x3C++0x03
line.long 0x00 "PIO0_15,Digital I/O control for port 0 pins PIO0_15"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x40++0x03
line.long 0x00 "PIO0_16,Digital I/O control for port 0 pins PIO0_16"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x40++0x03
line.long 0x00 "PIO0_16,Digital I/O control for port 0 pins PIO0_16"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x44++0x03
line.long 0x00 "PIO0_17,Digital I/O control for port 0 pins PIO0_17"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x48++0x03
line.long 0x00 "PIO0_18,Digital I/O control for port 0 pins PIO0_18"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x48++0x03
line.long 0x00 "PIO0_18,Digital I/O control for port 0 pins PIO0_18"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 4. (strings "19" "20" "21" "22" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x4C)++0x03
line.long 0x00 "PIO0_$1,Digital I/O control for port 0 pins PIO0_ $1"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0x5C++0x03
line.long 0x00 "PIO0_23,Digital I/O control for port 0 pins PIO0_23"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x5C++0x03
line.long 0x00 "PIO0_23,Digital I/O control for port 0 pins PIO0_23"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 7. (strings "24" "25" "26" "27" "28" "29" "30" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
group.long ($2+0x60)++0x03
line.long 0x00 "PIO0_$1,Digital I/O control for port 0 pins PIO0_ $1"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0x7C++0x03
line.long 0x00 "PIO0_31,Digital I/O control for port 0 pins PIO0_31"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x7C++0x03
line.long 0x00 "PIO0_31,Digital I/O control for port 0 pins PIO0_31"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x80++0x03
line.long 0x00 "PIO1_0,Digital I/O control for port 1 pins PIO1_0"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0x80++0x03
line.long 0x00 "PIO1_0,Digital I/O control for port 1 pins PIO1_0"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
group.long ($2+0x84)++0x03
line.long 0x00 "PIO1_$1,Digital I/O control for port 1 pins PIO1_ $1"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0xA0++0x03
line.long 0x00 "PIO1_8,Digital I/O control for port 1 pins PIO1_8"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
group.long ($2+0xA0)++0x03
line.long 0x00 "PIO1_$1,Digital I/O control for port 1 pins PIO1_ $1"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0xA4++0x03
line.long 0x00 "PIO1_9,Digital I/O control for port 1 pins PIO1_9"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 4. (strings "10" "11" "12" "13" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0xA8)++0x03
line.long 0x00 "PIO1_$1,Digital I/O control for port 1 pins PIO1_ $1"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0xB8++0x03
line.long 0x00 "PIO1_14,Digital I/O control for port 1 pins PIO1_14"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0xB8++0x03
line.long 0x00 "PIO1_14,Digital I/O control for port 1 pins PIO1_14"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 4. (strings "15" "16" "17" "18" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0xBC)++0x03
line.long 0x00 "PIO1_$1,Digital I/O control for port 1 pins PIO1_ $1"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
group.long 0xCC++0x03
line.long 0x00 "PIO1_19,Digital I/O control for port 1 pins PIO1_19"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: Analog switch is open,1: Analog switch is closed"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
group.long 0xCC++0x03
line.long 0x00 "PIO1_19,Digital I/O control for port 1 pins PIO1_19"
bitfld.long 0x00 10. "ASW,Analog switch input control" "0: For pins PIO0_9 PIO0_11 PIO0_12 PIO0_15..,1: For all pins except PIO0_9 PIO0_11 PIO0_12.."
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
newline
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat 12. (strings "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0xD0)++0x03
line.long 0x00 "PIO1_$1,Digital I/O control for port 1 pins PIO1_ $1"
bitfld.long 0x00 9. "OD,Controls open-drain mode" "0: Normal,1: Open-drain"
bitfld.long 0x00 8. "DIGIMODE,Select Digital mode" "0: Disable digital mode,1: Enable Digital mode"
newline
bitfld.long 0x00 7. "INVERT,Input polarity" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "SLEW,Driver slew rate" "0: Standard-mode output slew rate is slower,1: Fast-mode output slew rate is faster"
newline
bitfld.long 0x00 4.--5. "MODE,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
bitfld.long 0x00 0.--3. "FUNC,Selects pin function" "0: Alternative connection 0,1: Alternative connection 1,2: Alternative connection 2,3: Alternative connection 3,4: Alternative connection 4,5: Alternative connection 5,6: Alternative connection 6,7: Alternative connection 7,?..."
repeat.end
tree.end
sif cpuis("LPC55S66*")||cpuis("LPC55S69*")
tree "MAILBOX (Mailbox)"
base ad:0x4008B000
group.long 0xF8++0x03
line.long 0x00 "MUTEX,Mutual exclusion register[1]"
bitfld.long 0x00 0. "EX,Cleared when read set when written" "0,1"
repeat 2. (increment 0 1)(increment  0 0x10)
tree "MBOXIRQ[$1]"
group.long ($2+0x00)++0x03
line.long 0x00 "IRQ,Interrupt request register for the Cortex-M0+ CPU"
hexmask.long 0x00 0.--31. 1. "INTREQ,If any bit is set an interrupt request is sent to the Cortex-M0+ interrupt controller"
wgroup.long ($2+0x04)++0x03
line.long 0x00 "IRQSET,Set bits in IRQ0"
hexmask.long 0x00 0.--31. 1. "INTREQSET,Writing 1 sets the corresponding bit in the IRQ0 register"
wgroup.long ($2+0x08)++0x03
line.long 0x00 "IRQCLR,Clear bits in IRQ0"
hexmask.long 0x00 0.--31. 1. "INTREQCLR,Writing 1 clears the corresponding bit in the IRQ0 register"
tree.end
repeat.end
tree.end
endif
sif cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")
tree "MPU (Memory Protection Unit)"
base ad:0xE000ED90
rgroup.long 0x00++0x03
line.long 0x00 "TYPE,The MPU Type Register indicates how many regions the MPU support"
hexmask.long.byte 0x00 8.--15. 1. "DREGION,Number of regions supported by the MPU"
bitfld.long 0x00 0. "SEPARATE,Indicates support for separate instruction and data address maps" "0,1"
group.long 0x04++0x03
line.long 0x00 "CTRL,MPU Control Register"
bitfld.long 0x00 2. "PRIVDEFENA,no description available" "0: Disables the default memory map,1: Enables the default memory map as a.."
bitfld.long 0x00 1. "HFNMIENA,Enables the operation of MPU during HardFault and NMI handlers" "0: MPU is disabled during HardFault and NMI..,1: The MPU is enabled during HardFault and NMI.."
newline
bitfld.long 0x00 0. "ENABLE,Enables the MPU" "0: The MPU is disabled,1: The MPU is enabled"
group.long 0x08++0x03
line.long 0x00 "RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. "REGION,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
group.long 0x0C++0x03
line.long 0x00 "RBAR,MPU Region Base Address Register"
hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region"
bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable"
newline
bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted"
group.long 0x10++0x03
line.long 0x00 "RLAR,MPU Region Limit Address Register"
hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address"
bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled"
group.long 0x14++0x03
line.long 0x00 "RBAR_A1,MPU Region Base Address Register"
hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region"
bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable"
newline
bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted"
group.long 0x18++0x03
line.long 0x00 "RLAR_A1,MPU Region Limit Address Register"
hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address"
bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled"
group.long 0x1C++0x03
line.long 0x00 "RBAR_A2,MPU Region Base Address Register"
hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region"
bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable"
newline
bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted"
group.long 0x20++0x03
line.long 0x00 "RLAR_A2,MPU Region Limit Address Register"
hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address"
bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled"
group.long 0x24++0x03
line.long 0x00 "RBAR_A3,MPU Region Base Address Register"
hexmask.long 0x00 5.--31. 1. "BASE,Contains bits[31:5] of the lower inclusive limit of the selected MPU memory region"
bitfld.long 0x00 3.--4. "SH,For Normal memory regions the S bit indicates whether the region is shareable" "0: Non-shareable memory,1: Unpredictable,2: OUTER_SHAREABLE,3: Inner Shareable"
newline
bitfld.long 0x00 1.--2. "AP,The AP[2:0] bits indicate the access and privilege properties of the region" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
bitfld.long 0x00 0. "XN,The XN bit is an Execute Never bit that indicates whether the processor can execute instructions from the region" "0: Execution is only permitted if read permitted,1: Execution is not permitted"
group.long 0x28++0x03
line.long 0x00 "RLAR_A3,MPU Region Limit Address Register"
hexmask.long 0x00 5.--31. 1. "LIMIT,Limit address"
bitfld.long 0x00 1.--3. "ATTRINDX,Attribute index" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "EN,Enables this region" "0: Region is disabled,1: Region is enabled"
group.long 0x30++0x03
line.long 0x00 "MAIR0,MPU Memory Attribute Indirection Registers 0"
hexmask.long.byte 0x00 24.--31. 1. "ATTR3,Memory attribute encoding for MPU regions with an AttrIndex of 3"
hexmask.long.byte 0x00 16.--23. 1. "ATTR2,Memory attribute encoding for MPU regions with an AttrIndex of 2"
newline
hexmask.long.byte 0x00 8.--15. 1. "ATTR1,Memory attribute encoding for MPU regions with an AttrIndex of 1"
hexmask.long.byte 0x00 0.--7. 1. "ATTR0,Memory attribute encoding for MPU regions with an AttrIndex of 0"
group.long 0x3C++0x03
line.long 0x00 "MAIR1,MPU Memory Attribute Indirection Registers 1"
hexmask.long.byte 0x00 24.--31. 1. "ATTR7,Memory attribute encoding for MPU regions with an AttrIndex of 7"
hexmask.long.byte 0x00 16.--23. 1. "ATTR6,Memory attribute encoding for MPU regions with an AttrIndex of 6"
newline
hexmask.long.byte 0x00 8.--15. 1. "ATTR5,Memory attribute encoding for MPU regions with an AttrIndex of 5"
hexmask.long.byte 0x00 0.--7. 1. "ATTR4,Memory attribute encoding for MPU regions with an AttrIndex of 4"
tree.end
endif
tree "MRT (Multi-Rate Timer)"
base ad:0x4000D000
group.long 0xF0++0x03
line.long 0x00 "MODCFG,Module Configuration register"
bitfld.long 0x00 31. "MULTITASK,Selects the operating mode for the INUSE flags and the IDLE_CH register" "0: Hardware status mode,1: Multi-task mode"
bitfld.long 0x00 4.--8. "NOB,Identifies the number of timer bits in this MRT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--3. "NOC,Identifies the number of channels in this MRT.(4 channels on this device.)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xF4++0x03
line.long 0x00 "IDLE_CH,Idle channel register"
bitfld.long 0x00 4.--7. "CHAN,Idle channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF8++0x03
line.long 0x00 "IRQ_FLAG,Global interrupt flag register"
bitfld.long 0x00 3. "GFLAG3,Monitors the interrupt flag of TIMER3" "0,1"
bitfld.long 0x00 2. "GFLAG2,Monitors the interrupt flag of TIMER2" "0,1"
bitfld.long 0x00 1. "GFLAG1,Monitors the interrupt flag of TIMER1" "0,1"
bitfld.long 0x00 0. "GFLAG0,Monitors the interrupt flag of TIMER0" "0: No pending interrupt,1: Pending interrupt"
repeat 4. (increment 0 1)(increment  0 0x10)
tree "CHANNEL[$1]"
group.long ($2+0x00)++0x03
line.long 0x00 "INTVAL,MRT Time interval value register"
bitfld.long 0x00 31. "LOAD,Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register" "0: No force load,1: Force load"
hexmask.long.tbyte 0x00 0.--23. 1. "IVALUE,Time interval load value"
rgroup.long ($2+0x04)++0x03
line.long 0x00 "TIMER,MRT Timer register"
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Holds the current timer value of the down-counter"
group.long ($2+0x08)++0x03
line.long 0x00 "CTRL,MRT Control register"
bitfld.long 0x00 1.--2. "MODE,Selects timer mode" "0: Repeat interrupt mode,1: One-shot interrupt mode,2: One-shot stall mode,?..."
bitfld.long 0x00 0. "INTEN,Enable the TIMERn interrupt" "0: Disabled,1: Enabled"
group.long ($2+0x0C)++0x03
line.long 0x00 "STAT,MRT Status register"
bitfld.long 0x00 2. "INUSE,Channel In Use flag" "0: This channel is not in use,1: This channel is in use"
bitfld.long 0x00 1. "RUN,Indicates the state of TIMERn" "0: Idle state,1: Running"
bitfld.long 0x00 0. "INTFLAG,Monitors the interrupt flag" "0: No pending interrupt,1: Pending interrupt"
tree.end
repeat.end
tree.end
tree "NVIC"
base ad:0xE000E100
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0x00)++0x03
line.long 0x00 "ISER[$1],Interrupt Set Enable Register $1"
bitfld.long 0x00 31. "SETENA31,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 30. "SETENA30,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 29. "SETENA29,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 28. "SETENA28,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 27. "SETENA27,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 26. "SETENA26,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 25. "SETENA25,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 24. "SETENA24,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 23. "SETENA23,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 22. "SETENA22,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 21. "SETENA21,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 20. "SETENA20,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 19. "SETENA19,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 18. "SETENA18,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 17. "SETENA17,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 16. "SETENA16,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 15. "SETENA15,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 14. "SETENA14,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 13. "SETENA13,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 12. "SETENA12,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 11. "SETENA11,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 10. "SETENA10,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 9. "SETENA9,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 8. "SETENA8,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 7. "SETENA7,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 6. "SETENA6,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 5. "SETENA5,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 4. "SETENA4,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 3. "SETENA3,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 2. "SETENA2,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 1. "SETENA1,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 0. "SETENA0,Interrupt set-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "ICER[$1],Interrupt Clear Enable Register $1"
bitfld.long 0x00 31. "CLRENA31,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 30. "CLRENA30,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 29. "CLRENA29,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 28. "CLRENA28,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 27. "CLRENA27,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 26. "CLRENA26,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 25. "CLRENA25,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 24. "CLRENA24,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 23. "CLRENA23,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 22. "CLRENA22,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 21. "CLRENA21,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 20. "CLRENA20,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 19. "CLRENA19,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 18. "CLRENA18,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 17. "CLRENA17,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 16. "CLRENA16,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 15. "CLRENA15,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 14. "CLRENA14,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 13. "CLRENA13,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 12. "CLRENA12,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 11. "CLRENA11,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 10. "CLRENA10,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 9. "CLRENA9,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 8. "CLRENA8,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 7. "CLRENA7,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 6. "CLRENA6,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 5. "CLRENA5,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 4. "CLRENA4,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 3. "CLRENA3,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 2. "CLRENA2,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 1. "CLRENA1,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 0. "CLRENA0,Interrupt clear-enable bits" "0: Write: No effect Read: Interrupt 32n+m disabled,1: Write: Enable interrupt 32n+m Read: Interrupt.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "ISPR[$1],Interrupt Set Pending Register $1"
bitfld.long 0x00 31. "SETPEND31,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 30. "SETPEND30,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 29. "SETPEND29,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 28. "SETPEND28,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 27. "SETPEND27,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 26. "SETPEND26,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 25. "SETPEND25,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 24. "SETPEND24,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 23. "SETPEND23,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 22. "SETPEND22,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 21. "SETPEND21,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 20. "SETPEND20,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 19. "SETPEND19,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 18. "SETPEND18,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 17. "SETPEND17,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 16. "SETPEND16,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 15. "SETPEND15,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 14. "SETPEND14,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 13. "SETPEND13,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 12. "SETPEND12,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 11. "SETPEND11,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 10. "SETPEND10,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 9. "SETPEND9,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 8. "SETPEND8,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 7. "SETPEND7,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 6. "SETPEND6,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 5. "SETPEND5,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 4. "SETPEND4,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 3. "SETPEND3,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 2. "SETPEND2,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
newline
bitfld.long 0x00 1. "SETPEND1,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
bitfld.long 0x00 0. "SETPEND0,Interrupt set-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Pend interrupt 32n+m Read: Interrupt.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x180)++0x03
line.long 0x00 "ICPR[$1],Interrupt Clear Pending Register $1"
bitfld.long 0x00 31. "CLRPEND31,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 30. "CLRPEND30,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 29. "CLRPEND29,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 28. "CLRPEND28,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 27. "CLRPEND27,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 26. "CLRPEND26,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 25. "CLRPEND25,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 24. "CLRPEND24,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 23. "CLRPEND23,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 22. "CLRPEND22,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 21. "CLRPEND21,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 20. "CLRPEND20,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 19. "CLRPEND19,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 18. "CLRPEND18,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 17. "CLRPEND17,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 16. "CLRPEND16,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 15. "CLRPEND15,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 14. "CLRPEND14,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 13. "CLRPEND13,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 12. "CLRPEND12,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 11. "CLRPEND11,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 10. "CLRPEND10,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 9. "CLRPEND9,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 8. "CLRPEND8,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 7. "CLRPEND7,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 6. "CLRPEND6,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 5. "CLRPEND5,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 4. "CLRPEND4,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 3. "CLRPEND3,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 2. "CLRPEND2,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
newline
bitfld.long 0x00 1. "CLRPEND1,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
bitfld.long 0x00 0. "CLRPEND0,Interrupt clear-pending bits" "0: Write: No effect Read: Interrupt 32n+m is not..,1: Write: Clear pending state of interrupt 32n+m.."
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "IABR[$1],Interrupt Active Bit Register $1"
bitfld.long 0x00 31. "ACTIVE31,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 30. "ACTIVE30,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 29. "ACTIVE29,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 28. "ACTIVE28,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 27. "ACTIVE27,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 26. "ACTIVE26,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 25. "ACTIVE25,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 24. "ACTIVE24,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 23. "ACTIVE23,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 22. "ACTIVE22,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 21. "ACTIVE21,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 20. "ACTIVE20,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 19. "ACTIVE19,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 18. "ACTIVE18,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 17. "ACTIVE17,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 16. "ACTIVE16,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 15. "ACTIVE15,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 14. "ACTIVE14,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 13. "ACTIVE13,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 12. "ACTIVE12,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 11. "ACTIVE11,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 10. "ACTIVE10,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 9. "ACTIVE9,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 8. "ACTIVE8,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 7. "ACTIVE7,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 6. "ACTIVE6,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 5. "ACTIVE5,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 4. "ACTIVE4,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 3. "ACTIVE3,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 2. "ACTIVE2,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
newline
bitfld.long 0x00 1. "ACTIVE1,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
bitfld.long 0x00 0. "ACTIVE0,Active state bits" "0: The interrupt is not active,1: The interrupt is active"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x280)++0x03
line.long 0x00 "ITNS[$1],Interrupt Target Non-secure Register $1"
bitfld.long 0x00 31. "INTS31,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 30. "INTS30,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 29. "INTS29,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 28. "INTS28,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 27. "INTS27,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 26. "INTS26,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 25. "INTS25,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 24. "INTS24,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 23. "INTS23,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 22. "INTS22,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 21. "INTS21,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 20. "INTS20,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 19. "INTS19,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 18. "INTS18,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 17. "INTS17,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 16. "INTS16,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 15. "INTS15,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 14. "INTS14,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 13. "INTS13,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 12. "INTS12,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 11. "INTS11,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 10. "INTS10,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 9. "INTS9,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 8. "INTS8,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 7. "INTS7,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 6. "INTS6,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 5. "INTS5,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 4. "INTS4,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 3. "INTS3,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 2. "INTS2,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
newline
bitfld.long 0x00 1. "INTS1,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
bitfld.long 0x00 0. "INTS0,Interrupt Targets Non-secure bits" "0: The interrupt targets Secure state,1: The interrupt targets Non-secure state"
repeat.end
repeat 120. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "IPR[$1],Interrupt Priority Register $1"
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,no description available"
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,no description available"
newline
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,no description available"
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,no description available"
repeat.end
wgroup.long 0xE00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger in the range 0-479"
tree.end
tree "OSTIMER (Synchronous OS/Event timer with Wakeup Timer)"
base ad:0x4002D000
rgroup.long 0x00++0x03
line.long 0x00 "EVTIMERL,EVTIMER Low Register"
hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER"
rgroup.long 0x00++0x03
line.long 0x00 "EVTIMERL,EVTIMER Low Register"
hexmask.long 0x00 0.--31. 1. "EVTIMER_COUNT_VALUE,A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER"
group.long 0x04++0x03
line.long 0x00 "EVTIMERH,EVTIMER High Register"
hexmask.long.word 0x00 0.--9. 1. "EVTIMER_COUNT_VALUE,A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER"
rgroup.long 0x08++0x03
line.long 0x00 "CAPTURE_L,Capture Low Register"
hexmask.long 0x00 0.--31. 1. "CAPTURE_VALUE,A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function __SEV() )"
group.long 0x0C++0x03
line.long 0x00 "CAPTURE_H,Capture High Register"
hexmask.long.word 0x00 0.--9. 1. "CAPTURE_VALUE,A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function __SEV() )"
group.long 0x10++0x03
line.long 0x00 "MATCH_L,Match Low Register"
hexmask.long 0x00 0.--31. 1. "MATCH_VALUE,The value written to the MATCH (L/H) register pair is compared against the central EVTIMER"
group.long 0x14++0x03
line.long 0x00 "MATCH_H,Match High Register"
hexmask.long.word 0x00 0.--9. 1. "MATCH_VALUE,The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER"
group.long 0x1C++0x03
line.long 0x00 "OSEVENT_CTRL,OS_EVENT TIMER Control Register"
rbitfld.long 0x00 2. "MATCH_WR_RDY,This bit will be low when it is safe to write to reload the Match Registers" "0,1"
bitfld.long 0x00 1. "OSTIMER_INTENA,When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set" "0,1"
bitfld.long 0x00 0. "OSTIMER_INTRFLAG,This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair" "0,1"
tree.end
tree "PINT (Pin interrupt and pattern match)"
tree "PINT"
base ad:0x40004000
group.long 0x00++0x03
line.long 0x00 "ISEL,Pin Interrupt Mode register"
abitfld.long 0x00 0.--7. "PMODE,Selects the interrupt mode for each pin interrupt" "0x00=0: Edge sensitive,0x01=1: Level sensitive"
group.long 0x04++0x03
line.long 0x00 "IENR,Pin interrupt level or rising edge interrupt enable register"
abitfld.long 0x00 0.--7. "ENRL,Enables the rising edge or level interrupt for each pin interrupt" "0x00=0: Disable rising edge or level interrupt,0x01=1: Enable rising edge or level interrupt"
wgroup.long 0x08++0x03
line.long 0x00 "SIENR,Pin interrupt level or rising edge interrupt set register"
abitfld.long 0x00 0.--7. "SETENRL,Ones written to this address set bits in the IENR thus enabling interrupts" "0x00=0: No operation,0x01=1: Enable rising edge or level"
wgroup.long 0x0C++0x03
line.long 0x00 "CIENR,Pin interrupt level (rising edge interrupt) clear register"
abitfld.long 0x00 0.--7. "CENRL,Ones written to this address clear bits in the IENR thus disabling the interrupts" "0x00=0: No operation,0x01=1: Disable rising edge or level"
group.long 0x10++0x03
line.long 0x00 "IENF,Pin interrupt active level or falling edge interrupt enable register"
abitfld.long 0x00 0.--7. "ENAF,Enables the falling edge or configures the active level interrupt for each pin interrupt" "0x00=0: Disable falling edge interrupt or set..,0x01=1: Enable falling edge interrupt enabled or.."
wgroup.long 0x14++0x03
line.long 0x00 "SIENF,Pin interrupt active level or falling edge interrupt set register"
abitfld.long 0x00 0.--7. "SETENAF,Ones written to this address set bits in the IENF thus enabling interrupts" "0x00=0: No operation,0x01=1: Select HIGH-active interrupt or"
wgroup.long 0x18++0x03
line.long 0x00 "CIENF,Pin interrupt active level or falling edge interrupt clear register"
abitfld.long 0x00 0.--7. "CENAF,Ones written to this address clears bits in the IENF thus disabling interrupts" "0x00=0: No operation,0x01=1: LOW-active interrupt selected or"
group.long 0x1C++0x03
line.long 0x00 "RISE,Pin interrupt rising edge register"
abitfld.long 0x00 0.--7. "RDET,Rising edge detect" "0x00=0: no operation,0x01=1: clear rising edge detection for this pin"
group.long 0x20++0x03
line.long 0x00 "FALL,Pin interrupt falling edge register"
abitfld.long 0x00 0.--7. "FDET,Falling edge detect" "0x00=0: no operation,0x01=1: clear falling edge detection for this pin"
group.long 0x24++0x03
line.long 0x00 "IST,Pin interrupt status register"
abitfld.long 0x00 0.--7. "PSTAT,Pin interrupt status" "0x00=0: no operation,0x01=1: interrupt is being requested for this.."
group.long 0x28++0x03
line.long 0x00 "PMCTRL,Pattern match interrupt control register"
hexmask.long.byte 0x00 24.--31. 1. "PMAT,This field displays the current state of pattern matches"
bitfld.long 0x00 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "SEL_PMATCH,Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function" "0: Pin interrupt,1: Pattern match"
group.long 0x2C++0x03
line.long 0x00 "PMSRC,Pattern match interrupt bit-slice source register"
bitfld.long 0x00 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
newline
bitfld.long 0x00 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
newline
bitfld.long 0x00 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
group.long 0x30++0x03
line.long 0x00 "PMCFG,Pattern match interrupt bit slice configuration register"
bitfld.long 0x00 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
newline
bitfld.long 0x00 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
newline
bitfld.long 0x00 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint" "0: No effect,1: endpoint"
newline
bitfld.long 0x00 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint" "0: No effect,1: endpoint"
newline
bitfld.long 0x00 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint" "0: No effect,1: endpoint"
tree.end
tree "SECPINT"
base ad:0x40005000
group.long 0x00++0x03
line.long 0x00 "ISEL,Pin Interrupt Mode register"
abitfld.long 0x00 0.--7. "PMODE,Selects the interrupt mode for each pin interrupt" "0x00=0: Edge sensitive,0x01=1: Level sensitive"
group.long 0x04++0x03
line.long 0x00 "IENR,Pin interrupt level or rising edge interrupt enable register"
abitfld.long 0x00 0.--7. "ENRL,Enables the rising edge or level interrupt for each pin interrupt" "0x00=0: Disable rising edge or level interrupt,0x01=1: Enable rising edge or level interrupt"
wgroup.long 0x08++0x03
line.long 0x00 "SIENR,Pin interrupt level or rising edge interrupt set register"
abitfld.long 0x00 0.--7. "SETENRL,Ones written to this address set bits in the IENR thus enabling interrupts" "0x00=0: No operation,0x01=1: Enable rising edge or level"
wgroup.long 0x0C++0x03
line.long 0x00 "CIENR,Pin interrupt level (rising edge interrupt) clear register"
abitfld.long 0x00 0.--7. "CENRL,Ones written to this address clear bits in the IENR thus disabling the interrupts" "0x00=0: No operation,0x01=1: Disable rising edge or level"
group.long 0x10++0x03
line.long 0x00 "IENF,Pin interrupt active level or falling edge interrupt enable register"
abitfld.long 0x00 0.--7. "ENAF,Enables the falling edge or configures the active level interrupt for each pin interrupt" "0x00=0: Disable falling edge interrupt or set..,0x01=1: Enable falling edge interrupt enabled or.."
wgroup.long 0x14++0x03
line.long 0x00 "SIENF,Pin interrupt active level or falling edge interrupt set register"
abitfld.long 0x00 0.--7. "SETENAF,Ones written to this address set bits in the IENF thus enabling interrupts" "0x00=0: No operation,0x01=1: Select HIGH-active interrupt or"
wgroup.long 0x18++0x03
line.long 0x00 "CIENF,Pin interrupt active level or falling edge interrupt clear register"
abitfld.long 0x00 0.--7. "CENAF,Ones written to this address clears bits in the IENF thus disabling interrupts" "0x00=0: No operation,0x01=1: LOW-active interrupt selected or"
group.long 0x1C++0x03
line.long 0x00 "RISE,Pin interrupt rising edge register"
abitfld.long 0x00 0.--7. "RDET,Rising edge detect" "0x00=0: no operation,0x01=1: clear rising edge detection for this pin"
group.long 0x20++0x03
line.long 0x00 "FALL,Pin interrupt falling edge register"
abitfld.long 0x00 0.--7. "FDET,Falling edge detect" "0x00=0: no operation,0x01=1: clear falling edge detection for this pin"
group.long 0x24++0x03
line.long 0x00 "IST,Pin interrupt status register"
abitfld.long 0x00 0.--7. "PSTAT,Pin interrupt status" "0x00=0: no operation,0x01=1: interrupt is being requested for this.."
group.long 0x28++0x03
line.long 0x00 "PMCTRL,Pattern match interrupt control register"
hexmask.long.byte 0x00 24.--31. 1. "PMAT,This field displays the current state of pattern matches"
bitfld.long 0x00 1. "ENA_RXEV,Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "SEL_PMATCH,Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function" "0: Pin interrupt,1: Pattern match"
group.long 0x2C++0x03
line.long 0x00 "PMSRC,Pattern match interrupt bit-slice source register"
bitfld.long 0x00 29.--31. "SRC7,Selects the input source for bit slice 7" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 26.--28. "SRC6,Selects the input source for bit slice 6" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 23.--25. "SRC5,Selects the input source for bit slice 5" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
newline
bitfld.long 0x00 20.--22. "SRC4,Selects the input source for bit slice 4" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 17.--19. "SRC3,Selects the input source for bit slice 3" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 14.--16. "SRC2,Selects the input source for bit slice 2" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
newline
bitfld.long 0x00 11.--13. "SRC1,Selects the input source for bit slice 1" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
bitfld.long 0x00 8.--10. "SRC0,Selects the input source for bit slice 0" "0: Input 0,1: Input 1,2: Input 2,3: Input 3,4: Input 4,5: Input 5,6: Input 6,7: Input 7"
group.long 0x30++0x03
line.long 0x00 "PMCFG,Pattern match interrupt bit slice configuration register"
bitfld.long 0x00 29.--31. "CFG7,Specifies the match contribution condition for bit slice 7" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 26.--28. "CFG6,Specifies the match contribution condition for bit slice 6" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 23.--25. "CFG5,Specifies the match contribution condition for bit slice 5" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
newline
bitfld.long 0x00 20.--22. "CFG4,Specifies the match contribution condition for bit slice 4" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 17.--19. "CFG3,Specifies the match contribution condition for bit slice 3" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 14.--16. "CFG2,Specifies the match contribution condition for bit slice 2" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
newline
bitfld.long 0x00 11.--13. "CFG1,Specifies the match contribution condition for bit slice 1" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 8.--10. "CFG0,Specifies the match contribution condition for bit slice 0" "0: Constant HIGH,1: Sticky rising edge,2: Sticky falling edge,3: Sticky rising or falling edge,4: High level,5: Low level,6: Constant 0,7: Event"
bitfld.long 0x00 6. "PROD_ENDPTS6,Determines whether slice 6 is an endpoint" "0: No effect,1: endpoint"
newline
bitfld.long 0x00 5. "PROD_ENDPTS5,Determines whether slice 5 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 4. "PROD_ENDPTS4,Determines whether slice 4 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 3. "PROD_ENDPTS3,Determines whether slice 3 is an endpoint" "0: No effect,1: endpoint"
newline
bitfld.long 0x00 2. "PROD_ENDPTS2,Determines whether slice 2 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 1. "PROD_ENDPTS1,Determines whether slice 1 is an endpoint" "0: No effect,1: endpoint"
bitfld.long 0x00 0. "PROD_ENDPTS0,Determines whether slice 0 is an endpoint" "0: No effect,1: endpoint"
tree.end
tree.end
tree "PLU (LPC80X Programmable Logic Unit)"
base ad:0x4003D000
repeat 26. (increment 0 1) (increment 0 0x04)
group.long ($2+0x800)++0x03
line.long 0x00 "LUT_TRUTH[$1],Specifies the Truth Table contents for LUTLUTn $1"
hexmask.long 0x00 0.--31. 1. "LUTn_TRUTH,Specifies the Truth Table contents for LUT0"
repeat.end
group.long 0x900++0x03
line.long 0x00 "OUTPUTS,Provides the current state of the 8 designated PLU Outputs"
hexmask.long.byte 0x00 0.--7. 1. "OUTPUT_STATE,Provides the current state of the 8 designated PLU Outputs"
group.long 0x904++0x03
line.long 0x00 "WAKEINT_CTRL,Wakeup interrupt control for PLU"
eventfld.long 0x00 13. "INTR_CLEAR,Write to clear wakeint_latched" "0,1"
bitfld.long 0x00 12. "LATCH_ENABLE,latch the interrupt then can be cleared with next bit INTR_CLEAR" "0,1"
bitfld.long 0x00 10.--11. "FILTER_CLKSEL,hclk is divided by 2**filter_clksel" "0: Selects the 1 MHz low-power oscillator as the..,1: Selects the 12 Mhz FRO as the filter clock,2: Selects a third filter clock source if provided,?..."
newline
bitfld.long 0x00 8.--9. "FILTER_MODE,control input of the PLU add filtering for glitch" "0: Bypass mode,1: Filter 1 clock period,2: Filter 2 clock period,3: Filter 3 clock period"
hexmask.long.byte 0x00 0.--7. 1. "MASK,Interrupt mask (which of the 8 PLU Outputs contribute to interrupt)"
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0xC00)++0x03
line.long 0x00 "OUTPUT_MUX[$1],Selects the source to be connected to PLU Output OUTPUT_n $1"
bitfld.long 0x00 0.--4. "OUTPUTn,Selects the source to be connected to PLU Output 0" "0: The PLU output 0,1: The PLU output 1,2: The PLU output 2,3: The PLU output 3,4: The PLU output 4,5: The PLU output 5,6: The PLU output 6,7: The PLU output 7,8: The PLU output 8,9: The PLU output 9,10: The PLU output 10,11: The PLU output 11,12: The PLU output 12,13: The PLU output 13,14: The PLU output 14,15: The PLU output 15,16: The PLU output 16,17: The PLU output 17,18: The PLU output 18,19: The PLU output 19,20: The PLU output 20,21: The PLU output 21,22: The PLU output 22,23: The PLU output 23,24: The PLU output 24,25: The PLU output 25,26: state(0),27: state(1),28: state(2),29: state(3),?..."
repeat.end
repeat 26. (increment 0 1)(increment  0 0x20)
tree "LUT[$1]"
group.long ($2+0x00)++0x03
line.long 0x00 "LUT_INP_MUX0,LUTn input x MUX"
bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..."
group.long ($2+0x04)++0x03
line.long 0x00 "LUT_INP_MUX1,LUTn input x MUX"
bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..."
group.long ($2+0x08)++0x03
line.long 0x00 "LUT_INP_MUX2,LUTn input x MUX"
bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..."
group.long ($2+0x0C)++0x03
line.long 0x00 "LUT_INP_MUX3,LUTn input x MUX"
bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..."
group.long ($2+0x10)++0x03
line.long 0x00 "LUT_INP_MUX4,LUTn input x MUX"
bitfld.long 0x00 0.--5. "LUTn_INPx,Selects the input source to be connected to LUT0 input0" "0: The PLU primary inputs 0,1: The PLU primary inputs 1,2: The PLU primary inputs 2,3: The PLU primary inputs 3,4: The PLU primary inputs 4,5: The PLU primary inputs 5,6: The output of LUT0,7: The output of LUT1,8: The output of LUT2,9: The output of LUT3,10: The output of LUT4,11: The output of LUT5,12: The output of LUT6,13: The output of LUT7,14: The output of LUT8,15: The output of LUT9,16: The output of LUT10,17: The output of LUT11,18: The output of LUT12,19: The output of LUT13,20: The output of LUT14,21: The output of LUT15,22: The output of LUT16,23: The output of LUT17,24: The output of LUT18,25: The output of LUT19,26: The output of LUT20,27: The output of LUT21,28: The output of LUT22,29: The output of LUT23,30: The output of LUT24,31: The output of LUT25,32: state(0),33: state(1),34: state(2),35: state(3),?..."
tree.end
repeat.end
tree.end
tree "PMC"
base ad:0x40020000
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rgroup.long 0x04++0x03
line.long 0x00 "STATUS,Power Management Controller FSM (Finite State Machines) status"
bitfld.long 0x00 18.--19. "BOOTMODE,Latest IC Boot cause" "0: Latest IC boot was a Full power cycle boot..,1: Latest IC boot was from DEEP SLEEP low power..,2: Latest IC boot was from POWER DOWN low power..,3: Latest IC boot was from DEEP POWER DOWN low.."
endif
group.long 0x04++0x03
line.long 0x00 "STATUS,Power Management Controller FSM (Finite State Machines) status"
rbitfld.long 0x00 28.--31. "WAFERTESTDONEVECT,Indicates cuurent status of wafer test level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 18.--19. "BOOTMODE,Latest IC Boot cause" "0: Latest IC boot was a Full power cycle boot..,1: Latest IC boot was from DEEP SLEEP low power..,2: Latest IC boot was from POWER DOWN low power..,3: Latest IC boot was from DEEP POWER DOWN low.."
newline
rbitfld.long 0x00 15.--17. "FSMDPWD,DEEP POWER DOWN Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11.--14. "FSMPWDN,POWER DOWN Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 7.--10. "FSMDSLP,DEEP SLEEP Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 3.--6. "FSMPWUP,POWER UP Finite State Machine (FSM) status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--2. "FSMMAIN,Power Management Controller Main Finite State Machine (FSM) status" "0: POWER UP,1: ACTIVE,2: POWER DOWN,3: DEEP SLEEP,?,?,6: DEEP POWER DOWN,7: IC Structural TEST Mode"
group.long 0x08++0x03
line.long 0x00 "RESETCTRL,Reset Control [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 30.--31. "BODCORERESETENA_SECURE_DP,BOD Core reset enable" "?,1: Any other value than b10 BOD Core reset is..,2: BOD Core reset is disable,?..."
newline
bitfld.long 0x00 28.--29. "BODVBATRESETENA_SECURE_DP,BOD VBAT reset enable" "?,1: Any other value than b10 BOD VBAT reset is..,2: BOD VBAT reset is disable,?..."
newline
bitfld.long 0x00 6.--7. "BODCORERESETENA_SECURE,BOD Core reset enable" "?,1: Any other value than b10 BOD Core reset is..,2: BOD Core reset is disable,?..."
newline
bitfld.long 0x00 4.--5. "BODVBATRESETENA_SECURE,BOD VBAT reset enable" "?,1: Any other value than b10 BOD VBAT reset is..,2: BOD VBAT reset is disable,?..."
newline
endif
bitfld.long 0x00 3. "SWRRESETENABLE,Software reset enable" "0: Software reset is disable,1: Software reset is enable"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 2. "BODCORERESETENABLE,BOD CORE reset enable" "0: BOD CORE reset is disable,1: BOD CORE reset is enable"
newline
bitfld.long 0x00 1. "BODVBATRESETENABLE,BOD VBAT reset enable" "0: BOD VBAT reset is disable,1: BOD VBAT reset is enable"
newline
endif
bitfld.long 0x00 0. "DPDWAKEUPRESETENABLE,Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer)" "0: Reset event from DEEP POWER DOWN mode is..,1: Reset event from DEEP POWER DOWN mode is enable"
group.long 0x10++0x03
line.long 0x00 "DCDC0,DCDC (first) control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 23.--26. "VOUT_PWD,Set output regulation voltage during Deep Sleep" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 21.--26. "CONFIG1,DCDC configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 22. "INDUCTORCLAMPENABLE,Enable shorting of Inductor during PFM idle time" "0,1"
newline
bitfld.long 0x00 21. "SLICINGENABLE,Enable staggered switching of power switches" "0,1"
newline
endif
bitfld.long 0x00 17.--20. "VOUT,Set output regulation voltage" "0: V_DCDC_0P950,1: V_DCDC_0P975,2: V_DCDC_1P000,3: V_DCDC_1P025,4: V_DCDC_1P050,5: V_DCDC_1P075,6: V_DCDC_1P100,7: V_DCDC_1P125,8: V_DCDC_1P150,9: V_DCDC_1P175,10: V_DCDC_1P200,?..."
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long.tbyte 0x00 0.--16. 1. "CONFIG0,DCDC configuration"
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 16. "DISABLEISENSE,Disable Current sensing" "0,1"
newline
bitfld.long 0x00 11.--15. "TMOS,One-shot generator reference current trimming signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 10. "ICENABLE,Selection of auto scaling of COT period with variations in VDD" "0,1"
newline
bitfld.long 0x00 8.--9. "ISEL,Alter Internal biasing currents" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "ICOMP,Select the type of ZCD comparator" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "RC,Constant On-Time calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.long 0x14++0x03
line.long 0x00 "DCDC1,DCDC (second) control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long 0x00 0.--31. 1. "CONFIG2,DCDC configuration"
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 31. "TOFFENABLE,Enable Constant Off-Time feature" "0,1"
newline
bitfld.long 0x00 26.--30. "TOFF,Constant Off-Time calibration input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 25. "LCENABLE,Change the range of the peak detector of current inside the inductor" "0,1"
newline
bitfld.long 0x00 24. "FORCEFULLCYCLE,Force full PFM PMOS and NMOS cycle" "0,1"
newline
bitfld.long 0x00 20.--23. "TRIMAUTOCOT,Change the scaling ratio of the feedforward compensation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "FORCEBYPASS,Force bypass mode" "0,1"
newline
bitfld.long 0x00 18. "ISCALEENABLE,Modify COT behavior" "0,1"
newline
bitfld.long 0x00 15.--17. "DTESTSEL,Select the output signal for test" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 11.--14. "SETDC,Bandgap calibration parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9.--10. "SETCURVE,Bandgap calibration parameter" "0,1,2,3"
newline
bitfld.long 0x00 8. "DTESTENABLE,Enable Digital test signals" "0,1"
newline
bitfld.long 0x00 4.--7. "RSENSETRIM,Adjust Max inductor peak current limiting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RTRIMOFFET,Adjust the offset voltage of BJT based comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x1C++0x03
line.long 0x00 "LDOPMU,Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 25. "BOOST_ENA_PWD,Control the LDO AO boost mode in the different low power modes (DEEP SLEEP POWERDOWN and DEEP POWER DOWN)" "0: LDO AO Boost Mode is disable,1: LDO AO Boost Mode is enable"
newline
bitfld.long 0x00 24. "BOOST_ENA,Control the LDO AO boost mode in ACTIVE mode" "0: LDO AO Boost Mode is disable,1: LDO AO Boost Mode is enable"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 20. "BLEED,Controls LDOMEM bleed current" "0: Bleed current is disable,1: Bleed current is enable"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 15.--19. "VADJ_BOOST_PWD,Sets the Always-On domain LDO Boost output level in all power down modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
endif
bitfld.long 0x00 10.--14. "VADJ_BOOST,Sets the Always-On domain LDO Boost output level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 5.--9. "VADJ_PWD,Sets the Always-On domain LDO output level in all power down modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
endif
bitfld.long 0x00 0.--4. "VADJ,Sets the Always-On domain LDO output level" "0: V_1P220,1: V_0P700,2: 0.725 V,3: V_0P750,4: 0.775 V,5: V_0P800,6: 0.825 V,7: V_0P850,8: 0.875 V,9: V_0P900,10: V_0P960,11: V_0P970,12: V_0P980,13: V_0P990,14: V_1P000,15: V_1P010,16: V_1P020,17: V_1P030,18: V_1P040,19: V_1P050,20: V_1P060,21: V_1P070,22: V_1P080,23: V_1P090,24: V_1P100,25: V_1P110,26: V_1P120,27: V_1P130,28: V_1P140,29: V_1P150,30: V_1P160,31: V_1P220_1"
group.long 0x30++0x03
line.long 0x00 "BODVBAT,VBAT Brown Out Dectector (BoD) control register [Reset by: PoR Pin Reset Software Reset]"
bitfld.long 0x00 5.--6. "HYST,BoD Hysteresis control" "0: HYST_25MV,1: HYST_50MV,2: HYST_75MV,3: HYST_100MV"
newline
bitfld.long 0x00 0.--4. "TRIGLVL,BoD trigger level" "0: 1.00 V,1: 1.10 V,2: 1.20 V,3: 1.30 V,4: 1.40 V,5: 1.50 V,6: 1.60 V,7: 1.65 V,8: 1.70 V,9: 1.75 V,10: 1.80 V,11: 1.90 V,12: 2.00 V,13: 2.10 V,14: 2.20 V,15: 2.30 V,16: 2.40 V,17: 2.50 V,18: 2.60 V,19: 2.70 V,20: 2.806 V,21: 2.90 V,22: 3.00 V,23: 3.10 V,24: 3.20 V,25: V_3P30_2,26: V_3P30_3,27: V_3P30_4,28: V_3P30_5,29: V_3P30_6,30: V_3P30_7,31: V_3P30_8"
group.long 0x40++0x03
line.long 0x00 "REFFASTWKUP,Analog References fast wake-up Control register [Reset by: PoR]"
bitfld.long 0x00 1. "HWWKUP,Analog References fast wake-up in case of Hardware Pin reset" "0: Analog References fast wake-up feature is..,1: Analog References fast wake-up feature is.."
newline
bitfld.long 0x00 0. "LPWKUP,Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP POWER DOWN and DEEP POWER DOWN)" "0: Analog References fast wake-up feature is..,1: Analog References fast wake-up feature is.."
group.long 0x4C++0x03
line.long 0x00 "XTAL32K,32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR Brown Out Detectors Reset]"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 25. "CAPTESTOSCINSEL,Select the input for test" "0: Oscillator output pin (osc_out),1: Oscillator input pin (osc_in)"
newline
bitfld.long 0x00 24. "CAPTESTENABLE,Enable signal for cap test" "0,1"
newline
bitfld.long 0x00 23. "CAPTESTSTART,Start test" "0,1"
newline
bitfld.long 0x00 22. "CAPTESTSTARTSRCSEL,Source selection for xo32k_captest_start_ao_set" "0: Sourced from CAPTESTSTART,1: Sourced from calibration"
newline
endif
hexmask.long.byte 0x00 15.--21. 1. "CAPBANKOUT,Capa bank setting output"
newline
hexmask.long.byte 0x00 8.--14. 1. "CAPBANKIN,Capa bank setting input"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6.--7. "AMPL,oscillator amplitude selection inputs" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "IBIAS,bias current selection inputs" "0,1,2,3"
newline
bitfld.long 0x00 3. "TEST,Oscillator Test Mode" "0,1"
newline
bitfld.long 0x00 1.--2. "IREF,reference output current selection inputs" "0,1,2,3"
endif
group.long 0x50++0x03
line.long 0x00 "COMP,Analog Comparator control register [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
bitfld.long 0x00 18.--20. "FILTERCGF_CLKDIV,Filter Clock divider" "0: Filter clock period duration equals 1 Analog..,1: Filter clock period duration equals 2 Analog..,2: Filter clock period duration equals 4 Analog..,3: Filter clock period duration equals 8 Analog..,4: Filter clock period duration equals 16 Analog..,5: Filter clock period duration equals 32 Analog..,6: Filter clock period duration equals 64 Analog..,7: Filter clock period duration equals 128.."
newline
bitfld.long 0x00 16.--17. "FILTERCGF_SAMPLEMODE,Control the filtering of the Analog Comparator output" "0: Bypass mode,1: Filter 1 clock period,2: Filter 2 clock period,3: Filter 3 clock period"
newline
bitfld.long 0x00 10.--14. "VREF,Control reference voltage step per steps of (VREFINPUT/31)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7.--9. "NMUX,Control word for N multiplexer" "0: VREF (See field VREFINPUT),1: Pin P0_0,2: Pin P0_9,3: Pin P0_18,4: Pin P1_14,5: Pin P2_23,?..."
newline
bitfld.long 0x00 4.--6. "PMUX,Control word for P multiplexer" "0: VREF (See fiedl VREFINPUT),1: Pin P0_0,2: Pin P0_9,3: Pin P0_18,4: Pin P1_14,5: Pin P2_23,?..."
newline
bitfld.long 0x00 3. "LOWPOWER,Low power mode" "0: High speed mode,1: Low power mode (Low speed)"
newline
bitfld.long 0x00 2. "VREFINPUT,Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder)" "0: Select internal VREF,1: Select VDDA"
newline
bitfld.long 0x00 1. "HYST,Hysteris when hyst = '1'" "0: Hysteresis is disable,1: Hysteresis is enable"
group.long 0x64++0x03
line.long 0x00 "WAKEUPIOCTRL,Deep Power Down wake-up source [Reset by: PoR Pin Reset Software Reset]"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 21. "WAKEUPIO_RSTN,WAKEUP IO event detector reset control" "0: Bloc is reset,1: Bloc is not reset"
newline
bitfld.long 0x00 20. "WAKEUPIO_ENABLE_CTRL,Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 12 to 19)" "0: WAKEUP IO PAD mode control comes from IOCON,1: WAKEUP IO PAD mode control comes from.."
newline
bitfld.long 0x00 18.--19. "MODEWAKEUPIOPAD3,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 16.--17. "MODEWAKEUPIOPAD2,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 14.--15. "MODEWAKEUPIOPAD1,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
bitfld.long 0x00 12.--13. "MODEWAKEUPIOPAD0,Selects function mode (on-chip pull-up/pull-down resistor control)" "0: Inactive,1: Pull-down,2: Pull-up,3: Repeater"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 11. "MODEWAKEUP3,Configure wake up I/O 3 in Deep Power Down mode" "0,1"
newline
bitfld.long 0x00 10. "MODEWAKEUP2,Configure wake up I/O 2 in Deep Power Down mode" "0,1"
newline
bitfld.long 0x00 9. "MODEWAKEUP1,Configure wake up I/O 1 in Deep Power Down mode" "0,1"
newline
bitfld.long 0x00 8. "MODEWAKEUP0,Configure wake up I/O 0 in Deep Power Down mode" "0,1"
newline
endif
bitfld.long 0x00 7. "FALLINGEDGEWAKEUP3,Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable"
newline
bitfld.long 0x00 6. "RISINGEDGEWAKEUP3,Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable"
newline
bitfld.long 0x00 5. "FALLINGEDGEWAKEUP2,Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable"
newline
bitfld.long 0x00 4. "RISINGEDGEWAKEUP2,Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable"
newline
bitfld.long 0x00 3. "FALLINGEDGEWAKEUP1,Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable"
newline
bitfld.long 0x00 2. "RISINGEDGEWAKEUP1,Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable"
newline
bitfld.long 0x00 1. "FALLINGEDGEWAKEUP0,Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes" "0: Falling edge detection is disable,1: Falling edge detection is enable"
newline
bitfld.long 0x00 0. "RISINGEDGEWAKEUP0,Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes" "0: Rising edge detection is disable,1: Rising edge detection is enable"
group.long 0x68++0x03
line.long 0x00 "WAKEIOCAUSE,Allows to identify the Wake-up I/O source from Deep Power Down mode"
bitfld.long 0x00 3. "WAKEUP3,Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.."
newline
bitfld.long 0x00 2. "WAKEUP2,Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.."
newline
bitfld.long 0x00 1. "WAKEUP1,Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.."
newline
rbitfld.long 0x00 0. "WAKEUP0,Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode" "0: Last wake up from Deep Power down mode was..,1: Last wake up from Deep Power down mode was.."
group.long 0x74++0x03
line.long 0x00 "STATUSCLK,FRO and XTAL status register [Reset by: PoR Brown Out Detectors Reset]"
bitfld.long 0x00 2. "XTAL32KOSCFAILURE,XTAL32 KHZ oscillator oscillation failure detection indicator" "0: No oscillation failure has been detetced..,1: At least one oscillation failure has been.."
newline
rbitfld.long 0x00 0. "XTAL32KOK,XTAL oscillator 32 K OK signal" "0,1"
group.long 0x84++0x03
line.long 0x00 "AOREG1,General purpose always on domain data storage [Reset by: PoR Brown Out Detectors Reset]"
bitfld.long 0x00 16.--19. "BOOTERRORCOUNTER,ROM Boot Fatal Error Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 13. "CDOGRESET,The last chip reset was caused by the code Watchdog" "0,1"
newline
endif
bitfld.long 0x00 12. "DPDRESET_OSTIMER,The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode" "0,1"
newline
bitfld.long 0x00 11. "DPDRESET_RTC,The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode" "0,1"
newline
bitfld.long 0x00 10. "DPDRESET_WAKEUPIO,The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode" "0,1"
newline
bitfld.long 0x00 9. "SWRRESET,The last chip reset was caused by a Software event" "0,1"
newline
bitfld.long 0x00 8. "WDTRESET,The last chip reset was caused by the Watchdog Timer" "0,1"
newline
bitfld.long 0x00 7. "SYSTEMRESET,The last chip reset was caused by a System Reset requested by the ARM CPU" "0,1"
newline
bitfld.long 0x00 6. "BODRESET,The last chip reset was caused by a Brown Out Detector (BoD) either VBAT BoD or Core Logic BoD" "0,1"
newline
bitfld.long 0x00 5. "PADRESET,The last chip reset was caused by a Pin Reset" "0,1"
newline
bitfld.long 0x00 4. "POR,The last chip reset was caused by a Power On Reset" "0,1"
group.long 0x90++0x03
line.long 0x00 "MISCCTRL,Dummy Control bus to PMU [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 15. "WAKUPIO_RST,WAKEUP IO event detector reset control" "0: Wakeup IO is not reset,1: Wakeup IO is reset"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 13.--15. "MISCCTRL_13_15,Reserved" "0,1,2,3,4,5,6,7"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 13.--14. "MISCCTRL_13_14,Reserved" "0,1,2,3"
newline
endif
bitfld.long 0x00 12. "DISABLE_BLEED,Controls LDO MEM bleed current" "0: LDO_MEM bleed current is enabled,1: LDO_MEM bleed current is disabled"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 11. "MODEWAKEUP3,Configure wake up I/O 3 in Deep Power Down mode" "0,1"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
hexmask.long.word 0x00 3.--11. 1. "MISCCTRL_3_11,Reserved"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 10. "MODEWAKEUP2,Configure wake up I/O 2 in Deep Power Down mode" "0,1"
newline
bitfld.long 0x00 9. "MODEWAKEUP1,Configure wake up I/O 1 in Deep Power Down mode" "0,1"
newline
bitfld.long 0x00 8. "MODEWAKEUP0,Configure wake up I/O 0 in Deep Power Down mode" "0,1"
newline
bitfld.long 0x00 3.--7. "MISCCTRL_3_8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 2. "LOWPWR_FLASH_BUF,no description available" "0,1"
newline
endif
bitfld.long 0x00 1. "LDOMEMHIGHZMODE,Control the activation of LDO MEM High Z mode" "0: LDO MEM High Z mode is disabled,1: LDO MEM High Z mode is enabled"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0. "LDODEEPSLEEPREF,Select LDO Deep Sleep reference source" "0: LDO DEEP Sleep uses Flash buffer biasing as..,1: LDO DEEP Sleep uses Band Gap 0.8V as reference"
endif
group.long 0x98++0x03
line.long 0x00 "RTCOSC32K,RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR Brown Out Detectors Reset]"
bitfld.long 0x00 31. "CLK1HZDIVUPDATEREQ,RTC 1Hz Divider status flag" "0,1"
newline
bitfld.long 0x00 30. "CLK1HZDIVHALT,Halts the divider counter" "0,1"
newline
hexmask.long.word 0x00 16.--26. 1. "CLK1HZDIV,Actual division ratio is : 31744 + CLK1HZDIV"
newline
bitfld.long 0x00 15. "CLK1KHZDIVUPDATEREQ,RTC 1KHz clock Divider status flag" "0,1"
newline
bitfld.long 0x00 1.--3. "CLK1KHZDIV,Actual division ratio is : 28 + CLK1KHZDIV" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "SEL,Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz)" "0: FRO 32 KHz,1: XTAL 32KHz"
group.long 0x9C++0x03
line.long 0x00 "OSTIMER,OS Timer control register [Reset by: PoR Brown Out Detectors Reset]"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 4.--5. "OSTIMERCLKSEL,OS event timer clock select" "0: Oscillator 32 kHz clock,1: FRO 1MHz clock,2: Main clock for OS timer,3: No clock"
newline
endif
bitfld.long 0x00 3. "OSC32KPD,Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K" "0,1"
newline
bitfld.long 0x00 2. "DPDWAKEUPENABLE,Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode)" "0,1"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 1. "CLOCKENABLE,Enable OSTIMER 32 KHz clock" "0,1"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 1. "CLOCKENABLE,Enable OS event timer clock" "0,1"
newline
endif
bitfld.long 0x00 0. "SOFTRESET,Active high reset" "0,1"
group.long 0xB8++0x03
line.long 0x00 "PDRUNCFG0,Controls the power to various analog blocks [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
bitfld.long 0x00 23. "PDEN_PLL0_SSCG,Controls power to System PLL (PLL0) Spread Spectrum module" "0: PLL0 Sread spectrum module is powered,1: PLL0 Sread spectrum module is powered down"
newline
bitfld.long 0x00 22. "PDEN_RNG,Controls power to all True Random Number Genetaor (TRNG) clock sources" "0: TRNG clocks are powered,1: TRNG clocks are powered down"
newline
bitfld.long 0x00 20. "PDEN_LDOXO32M,Controls power to high speed crystal LDO" "0: High speed crystal LDO is powered,1: High speed crystal LDO is powered down"
newline
bitfld.long 0x00 19. "PDEN_AUXBIAS,Controls power to auxiliary biasing (AUXBIAS)" "0: auxiliary biasing is powered,1: auxiliary biasing is powered down"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 18. "PDEN_LDOUSBHS,Controls power to USB high speed LDO" "0: USB high speed LDO is powered,1: USB high speed LDO is powered down"
newline
endif
bitfld.long 0x00 13. "PDEN_COMP,Controls power to Analog Comparator" "0: Analog Comparator is powered,1: Analog Comparator is powered down"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 12. "PDEN_USBHSPHY,Controls power to USB High Speed Phy" "0: USB HS phy is powered,1: USB HS phy is powered down"
newline
bitfld.long 0x00 11. "PDEN_USBFSPHY,Controls power to USB Full Speed phy" "0: USB Full Speed phy is powered,1: USB Full Speed phy is powered down"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 10. "PDEN_PLL1,Controls power to PLL1" "0: PLL1 is powered,1: PLL1 is powered down"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 10. "PDEN_PLL1,Controls power to USB PLL (also refered as PLL1)" "0: PLL1 is powered,1: PLL1 is powered down"
newline
endif
bitfld.long 0x00 9. "PDEN_PLL0,Controls power to System PLL (also refered as PLL0)" "0: PLL0 is powered,1: PLL0 is powered down"
newline
bitfld.long 0x00 8. "PDEN_XTAL32M,Controls power to high speed crystal" "0: High speed crystal is powered,1: High speed crystal is powered down"
newline
bitfld.long 0x00 7. "PDEN_XTAL32K,Controls power to crystal 32 KHz" "0: Crystal 32KHz is powered,1: Crystal 32KHz is powered down"
newline
bitfld.long 0x00 6. "PDEN_FRO32K,Controls power to the Free Running Oscillator (FRO) 32 KHz" "0: FRO32KHz is powered,1: FRO32KHz is powered down"
newline
bitfld.long 0x00 3. "PDEN_BODVBAT,Controls power to VBAT Brown Out Detector (BOD)" "0: BOD VBAT is powered,1: BOD VBAT is powered down"
wgroup.long 0xC0++0x03
line.long 0x00 "PDRUNCFGSET0,Controls the power to various analog blocks [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
hexmask.long 0x00 0.--31. 1. "PDRUNCFGSET0,Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register if they are implemented"
wgroup.long 0xC8++0x03
line.long 0x00 "PDRUNCFGCLR0,Controls the power to various analog blocks [Reset by: PoR Pin Reset Brown Out Detectors Reset Deep Power Down Reset Software Reset]"
hexmask.long 0x00 0.--31. 1. "PDRUNCFGCLR0,Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register if they are implemented"
group.long 0xD4++0x03
line.long 0x00 "SRAMCTRL,All SRAMs common control signals [Reset by: PoR Pin Reset Brown Out Detectors Reset Software Reset]"
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 8. "WRME,Write read margin enable" "0,1"
newline
bitfld.long 0x00 5.--7. "WM,Write Margin control settings" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--4. "RM,Read Margin control settings" "0,1,2,3,4,5,6,7"
newline
endif
bitfld.long 0x00 0.--1. "SMB,Source Biasing voltage" "0: Low leakage,1: Medium leakage,2: Highest leakage,3: Disable"
tree.end
sif cpuis("LPC55S66*")||cpuis("LPC55S69*")
tree "POWERQUAD (Digital Signal Co-Processing companion to a Cortex-M v8M CPU core)"
base ad:0x400A6000
group.long 0x00++0x03
line.long 0x00 "OUTBASE,Base address register for output region"
hexmask.long 0x00 0.--31. 1. "outbase,Base address register for the output region"
group.long 0x04++0x03
line.long 0x00 "OUTFORMAT,Output format"
hexmask.long.byte 0x00 8.--15. 1. "out_scaler,Output Scaler value (for scaled 'q31' formats)"
bitfld.long 0x00 4.--5. "out_formatext,Output External format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
bitfld.long 0x00 0.--1. "out_formatint,Output Internal format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
group.long 0x08++0x03
line.long 0x00 "TMPBASE,Base address register for temp region"
hexmask.long 0x00 0.--31. 1. "tmpbase,Base address register for the temporary region"
group.long 0x0C++0x03
line.long 0x00 "TMPFORMAT,Temp format"
hexmask.long.byte 0x00 8.--15. 1. "tmp_scaler,Temp Scaler value (for scaled 'q31' formats)"
bitfld.long 0x00 4.--5. "tmp_formatext,Temp External format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
bitfld.long 0x00 0.--1. "tmp_formatint,Temp Internal format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
group.long 0x10++0x03
line.long 0x00 "INABASE,Base address register for input A region"
hexmask.long 0x00 0.--31. 1. "inabase,Base address register for the input A region"
group.long 0x14++0x03
line.long 0x00 "INAFORMAT,Input A format"
hexmask.long.byte 0x00 8.--15. 1. "ina_scaler,Input A Scaler value (for scaled 'q31' formats)"
bitfld.long 0x00 4.--5. "ina_formatext,Input A External format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
bitfld.long 0x00 0.--1. "ina_formatint,Input A Internal format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
group.long 0x18++0x03
line.long 0x00 "INBBASE,Base address register for input B region"
hexmask.long 0x00 0.--31. 1. "inbbase,Base address register for the input B region"
group.long 0x1C++0x03
line.long 0x00 "INBFORMAT,Input B format"
hexmask.long.byte 0x00 8.--15. 1. "inb_scaler,Input B Scaler value (for scaled 'q31' formats)"
bitfld.long 0x00 4.--5. "inb_formatext,Input B External format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
bitfld.long 0x00 0.--1. "inb_formatint,Input B Internal format (00: q15 01:q31 10:float)" "?,1: q31,2: float),?..."
group.long 0x100++0x03
line.long 0x00 "CONTROL,PowerQuad Control register"
rbitfld.long 0x00 31. "inst_busy,Instruction busy signal when high indicates processing is on" "0,1"
bitfld.long 0x00 4.--7. "decode_machine," "?,1: matrix,2: fft,3: fir,4: stat,5: cordic 6 -15,?..."
bitfld.long 0x00 0.--3. "decode_opcode,opcode specific to decode_machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x104++0x03
line.long 0x00 "LENGTH,Length register"
hexmask.long 0x00 0.--31. 1. "inst_length,Length register"
group.long 0x108++0x03
line.long 0x00 "CPPRE,Pre-scale register"
bitfld.long 0x00 17. "cppre_sat8," "0,1"
bitfld.long 0x00 16. "cppre_sat," "0,1"
hexmask.long.byte 0x00 8.--15. 1. "cppre_out,co-processor fixed point output"
hexmask.long.byte 0x00 0.--7. 1. "cppre_in,co-processor scaling of input"
group.long 0x10C++0x03
line.long 0x00 "MISC,Misc register"
hexmask.long 0x00 0.--31. 1. "inst_misc,Misc register"
group.long 0x110++0x03
line.long 0x00 "CURSORY,Cursory register"
bitfld.long 0x00 0. "cursory," "0,1"
group.long 0x180++0x03
line.long 0x00 "CORDIC_X,Cordic input X register"
hexmask.long 0x00 0.--31. 1. "cordic_x,Cordic input x"
group.long 0x184++0x03
line.long 0x00 "CORDIC_Y,Cordic input Y register"
hexmask.long 0x00 0.--31. 1. "cordic_y,Cordic input y"
group.long 0x188++0x03
line.long 0x00 "CORDIC_Z,Cordic input Z register"
hexmask.long 0x00 0.--31. 1. "cordic_z,Cordic input z"
group.long 0x18C++0x03
line.long 0x00 "ERRSTAT,Read/Write register where error statuses are captured (sticky)"
bitfld.long 0x00 4. "BUSERROR,bus_error" "0,1"
bitfld.long 0x00 3. "UNDERFLOW,underflow" "0,1"
bitfld.long 0x00 2. "FIXEDOVERFLOW,fixed_pt_overflow" "0,1"
bitfld.long 0x00 1. "NAN,nan" "0,1"
bitfld.long 0x00 0. "OVERFLOW,overflow" "0,1"
group.long 0x190++0x03
line.long 0x00 "INTREN,INTERRUPT enable register"
bitfld.long 0x00 7. "intr_comp," "0,1"
bitfld.long 0x00 4. "intr_berr," "0,1"
bitfld.long 0x00 3. "intr_uflow," "0,1"
bitfld.long 0x00 2. "intr_fixed," "0,1"
bitfld.long 0x00 1. "intr_nan," "0,1"
bitfld.long 0x00 0. "intr_oflow," "0,1"
group.long 0x194++0x03
line.long 0x00 "EVENTEN,Event Enable register"
bitfld.long 0x00 7. "event_comp," "0,1"
bitfld.long 0x00 4. "event_berr," "0,1"
bitfld.long 0x00 3. "event_uflow," "0,1"
bitfld.long 0x00 2. "event_fixed," "0,1"
bitfld.long 0x00 1. "event_nan," "0,1"
bitfld.long 0x00 0. "event_oflow," "0,1"
group.long 0x198++0x03
line.long 0x00 "INTRSTAT,INTERRUPT STATUS register"
bitfld.long 0x00 0. "intr_stat,Intr status ( 1 bit to indicate interrupt captured 0 means no new interrupt) write any value will clear this bit" "0,1"
repeat 16. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "gpreg[$1],General purpose register bank N $1"
hexmask.long 0x00 0.--31. 1. "gpreg,General purpose register bank"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x240)++0x03
line.long 0x00 "compreg[$1],Compute register bank $1"
hexmask.long 0x00 0.--31. 1. "compreg,Compute register bank"
repeat.end
tree.end
endif
tree "PRINCE"
base ad:0x40035000
group.long 0x00++0x03
line.long 0x00 "ENC_ENABLE,Encryption Enable register"
bitfld.long 0x00 0. "EN,Encryption Enable" "0: Encryption of writes to the flash controller..,1: Encryption of writes to the flash controller.."
group.long 0x00++0x03
line.long 0x00 "ENC_ENABLE,Encryption Enable register"
bitfld.long 0x00 0. "EN,Enables PRINCE encryption for flash programming" "0: Encryption of writes to the flash controller..,1: Encryption of writes to the flash controller.."
wgroup.long 0x04++0x03
line.long 0x00 "MASK_LSB,Data Mask register 32 Least Significant Bits"
hexmask.long 0x00 0.--31. 1. "MASKVAL,Value of the 32 Least Significant Bits of the 64-bit data mask"
wgroup.long 0x08++0x03
line.long 0x00 "MASK_MSB,Data Mask register 32 Most Significant Bits"
hexmask.long 0x00 0.--31. 1. "MASKVAL,Value of the 32 Most Significant Bits of the 64-bit data mask"
group.long 0x0C++0x03
line.long 0x00 "LOCK,Lock register"
bitfld.long 0x00 8. "LOCKMASK,Lock the Mask registers" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "LOCKREG2,Lock Region 2 registers" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "LOCKREG1,Lock Region 1 registers" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "LOCKREG0,Lock Region 0 registers" "0: Disabled,1: Enabled"
wgroup.long 0x10++0x03
line.long 0x00 "IV_LSB0,Initial Vector register for region 0 Least Significant Bits"
hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector"
wgroup.long 0x14++0x03
line.long 0x00 "IV_MSB0,Initial Vector register for region 0 Most Significant Bits"
hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector"
group.long 0x18++0x03
line.long 0x00 "BASE_ADDR0,Base Address for region 0 register"
bitfld.long 0x00 18.--19. "ADDR_PRG,Programmable portion of the base address of region 0" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "ADDR_FIXED,Fixed portion of the base address of region 0"
group.long 0x1C++0x03
line.long 0x00 "SR_ENABLE0,Sub-Region Enable register for region 0"
hexmask.long 0x00 0.--31. 1. "EN,Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0"
wgroup.long 0x20++0x03
line.long 0x00 "IV_LSB1,Initial Vector register for region 1 Least Significant Bits"
hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector"
wgroup.long 0x24++0x03
line.long 0x00 "IV_MSB1,Initial Vector register for region 1 Most Significant Bits"
hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector"
group.long 0x28++0x03
line.long 0x00 "BASE_ADDR1,Base Address for region 1 register"
bitfld.long 0x00 18.--19. "ADDR_PRG,Programmable portion of the base address of region 1" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "ADDR_FIXED,Fixed portion of the base address of region 1"
group.long 0x2C++0x03
line.long 0x00 "SR_ENABLE1,Sub-Region Enable register for region 1"
hexmask.long 0x00 0.--31. 1. "EN,Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1"
wgroup.long 0x30++0x03
line.long 0x00 "IV_LSB2,Initial Vector register for region 2 Least Significant Bits"
hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector"
wgroup.long 0x34++0x03
line.long 0x00 "IV_MSB2,Initial Vector register for region 2 Most Significant Bits"
hexmask.long 0x00 0.--31. 1. "IVVAL,Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector"
group.long 0x38++0x03
line.long 0x00 "BASE_ADDR2,Base Address for region 2 register"
bitfld.long 0x00 18.--19. "ADDR_PRG,Programmable portion of the base address of region 2" "0,1,2,3"
hexmask.long.tbyte 0x00 0.--17. 1. "ADDR_FIXED,Fixed portion of the base address of region 2"
group.long 0x3C++0x03
line.long 0x00 "SR_ENABLE2,Sub-Region Enable register for region 2"
hexmask.long 0x00 0.--31. 1. "EN,Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2"
group.long 0x90++0x03
line.long 0x00 "ERR,Error status register"
bitfld.long 0x00 0. "ERRSTAT,PRINCE Error Status" "0: No PRINCE error,1: Error"
tree.end
tree "PUF (PUFCTRL)"
base ad:0x4003B000
group.long 0x00++0x03
line.long 0x00 "CTRL,PUF Control register"
bitfld.long 0x00 6. "GETKEY,Begin Get Key operation" "0,1"
bitfld.long 0x00 4. "SETKEY,Begin Set User Key operation" "0,1"
newline
bitfld.long 0x00 3. "GENERATEKEY,Begin Set Intrinsic Key operation" "0,1"
bitfld.long 0x00 2. "start,Begin Start operation" "0,1"
newline
bitfld.long 0x00 1. "enroll,Begin Enroll operation" "0,1"
bitfld.long 0x00 0. "zeroize,Begin Zeroize operation for PUF and go to Error state" "0,1"
group.long 0x04++0x03
line.long 0x00 "KEYINDEX,PUF Key Index register"
bitfld.long 0x00 0.--3. "KEYIDX,Key index for Set Key operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "KEYSIZE,PUF Key Size register"
bitfld.long 0x00 0.--5. "KEYSIZE,Key size for Set Key operations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x20++0x03
line.long 0x00 "STAT,PUF Status register"
rbitfld.long 0x00 7. "CODEOUTAVAIL,Next part of AC/KC is available" "0,1"
rbitfld.long 0x00 6. "CODEINREQ,Request for next part of AC/KC" "0,1"
newline
rbitfld.long 0x00 5. "KEYOUTAVAIL,Next part of key is available" "0,1"
rbitfld.long 0x00 4. "KEYINREQ,Request for next part of key" "0,1"
newline
rbitfld.long 0x00 2. "error,PUF is in the Error state and no operations can be performed" "0,1"
rbitfld.long 0x00 1. "SUCCESS,Last operation was successful" "0,1"
newline
rbitfld.long 0x00 0. "busy,Indicates that operation is in progress" "0,1"
rgroup.long 0x20++0x03
line.long 0x00 "STAT,PUF Status register"
bitfld.long 0x00 7. "CODEOUTAVAIL,Next part of AC/KC is available" "0,1"
bitfld.long 0x00 6. "CODEINREQ,Request for next part of AC/KC" "0,1"
newline
bitfld.long 0x00 5. "KEYOUTAVAIL,Next part of key is available" "0,1"
bitfld.long 0x00 4. "KEYINREQ,Request for next part of key" "0,1"
newline
bitfld.long 0x00 2. "error,PUF is in the Error state and no operations can be performed" "0,1"
bitfld.long 0x00 1. "SUCCESS,Last operation was successful" "0,1"
newline
bitfld.long 0x00 0. "busy,Indicates that operation is in progress" "0,1"
group.long 0x28++0x03
line.long 0x00 "ALLOW,PUF Allow register"
rbitfld.long 0x00 3. "ALLOWGETKEY,Get Key operation is allowed" "0,1"
rbitfld.long 0x00 2. "ALLOWSETKEY,Set Key operations are allowed" "0,1"
newline
rbitfld.long 0x00 1. "ALLOWSTART,Start operation is allowed" "0,1"
rbitfld.long 0x00 0. "ALLOWENROLL,Enroll operation is allowed" "0,1"
wgroup.long 0x40++0x03
line.long 0x00 "KEYINPUT,PUF Key Input register"
hexmask.long 0x00 0.--31. 1. "KEYIN,Key input data"
wgroup.long 0x44++0x03
line.long 0x00 "CODEINPUT,PUF Code Input register"
hexmask.long 0x00 0.--31. 1. "CODEIN,AC/KC input data"
rgroup.long 0x48++0x03
line.long 0x00 "CODEOUTPUT,PUF Code Output register"
hexmask.long 0x00 0.--31. 1. "CODEOUT,AC/KC output data"
rgroup.long 0x60++0x03
line.long 0x00 "KEYOUTINDEX,PUF Key Output Index register"
bitfld.long 0x00 0.--3. "KEYOUTIDX,Key index for the key that is currently output via the Key Output register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60++0x03
line.long 0x00 "KEYOUTINDEX,PUF Key Output Index register"
rbitfld.long 0x00 0.--3. "KEYOUTIDX,Key index for the key that is currently output via the Key Output register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x64++0x03
line.long 0x00 "KEYOUTPUT,PUF Key Output register"
hexmask.long 0x00 0.--31. 1. "KEYOUT,Key output data"
group.long 0xDC++0x03
line.long 0x00 "IFSTAT,PUF Interface Status and clear register"
bitfld.long 0x00 0. "ERROR,Indicates that an APB error has occurred Writing logic1 clears the if_error bit" "0,1"
rgroup.long 0xFC++0x03
line.long 0x00 "VERSION,PUF version register"
hexmask.long 0x00 0.--31. 1. "VERSION,Version of the PUF module"
group.long 0x100++0x03
line.long 0x00 "INTEN,PUF Interrupt Enable"
bitfld.long 0x00 7. "CODEOUTAVAILEN,Enable corresponding interrupt" "0,1"
bitfld.long 0x00 6. "CODEINREQEN,Enable corresponding interrupt" "0,1"
newline
bitfld.long 0x00 5. "KEYOUTAVAILEN,Enable corresponding interrupt" "0,1"
bitfld.long 0x00 4. "KEYINREQEN,Enable corresponding interrupt" "0,1"
newline
bitfld.long 0x00 2. "ERROREN,Enable corresponding interrupt" "0,1"
bitfld.long 0x00 1. "SUCCESEN,Enable corresponding interrupt" "0,1"
newline
bitfld.long 0x00 0. "READYEN,Enable corresponding interrupt" "0,1"
group.long 0x104++0x03
line.long 0x00 "INTSTAT,PUF interrupt status"
bitfld.long 0x00 7. "CODEOUTAVAIL,Level sensitive interrupt cleared when interrupt source clears" "0,1"
bitfld.long 0x00 6. "CODEINREQ,Level sensitive interrupt cleared when interrupt source clears" "0,1"
newline
bitfld.long 0x00 5. "KEYOUTAVAIL,Level sensitive interrupt cleared when interrupt source clears" "0,1"
bitfld.long 0x00 4. "KEYINREQ,Level sensitive interrupt cleared when interrupt source clears" "0,1"
newline
bitfld.long 0x00 2. "ERROR,Level sensitive interrupt cleared when interrupt source clears" "0,1"
bitfld.long 0x00 1. "SUCCESS,Level sensitive interrupt cleared when interrupt source clears" "0,1"
newline
bitfld.long 0x00 0. "READY,Triggers on falling edge of busy write 1 to clear" "0,1"
group.long 0x108++0x03
line.long 0x00 "PWRCTRL,PUF RAM Power Control"
bitfld.long 0x00 1. "RAMSTAT,PUF RAM status" "0,1"
bitfld.long 0x00 0. "RAMON,Power on the PUF RAM" "0,1"
group.long 0x10C++0x03
line.long 0x00 "CFG,PUF config register for block bits"
bitfld.long 0x00 1. "BLOCKKEYOUTPUT,Block set key operation" "0,1"
bitfld.long 0x00 0. "BLOCKENROLL_SETKEY,Block enroll operation" "0,1"
group.long 0x200++0x03
line.long 0x00 "KEYLOCK,Only reset in case of full IC reset"
bitfld.long 0x00 6.--7. "KEY3," "?,?,2: Write access to KEY3MASK KEYENABLE.KEY3 and,3: Write access to KEY3MASK KEYENABLE.KEY3 and"
bitfld.long 0x00 4.--5. "KEY2," "?,?,2: Write access to KEY2MASK KEYENABLE.KEY2 and,3: Write access to KEY2MASK KEYENABLE.KEY2 and"
newline
bitfld.long 0x00 2.--3. "KEY1," "?,?,2: Write access to KEY1MASK KEYENABLE.KEY1 and,3: Write access to KEY1MASK KEYENABLE.KEY1 and"
bitfld.long 0x00 0.--1. "KEY0," "?,?,2: Write access to KEY0MASK KEYENABLE.KEY0 and,3: Write access to KEY0MASK KEYENABLE.KEY0 and"
group.long 0x204++0x03
line.long 0x00 "KEYENABLE,no description available"
bitfld.long 0x00 6.--7. "KEY3," "?,?,2: Data coming out from PUF Index 0 interface are,3: Data coming out from PUF Index 0 interface are"
bitfld.long 0x00 4.--5. "KEY2," "?,?,2: Data coming out from PUF Index 0 interface are,3: Data coming out from PUF Index 0 interface are"
newline
bitfld.long 0x00 2.--3. "KEY1," "?,?,2: Data coming out from PUF Index 0 interface are,3: Data coming out from PUF Index 0 interface are"
bitfld.long 0x00 0.--1. "KEY0," "?,?,2: Data coming out from PUF Index 0 interface are,3: Data coming out from PUF Index 0 interface are"
wgroup.long 0x208++0x03
line.long 0x00 "KEYRESET,Reinitialize Keys shift registers counters"
bitfld.long 0x00 6.--7. "KEY3," "0,1,2,3"
bitfld.long 0x00 4.--5. "KEY2," "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "KEY1," "0,1,2,3"
bitfld.long 0x00 0.--1. "KEY0," "0,1,2,3"
group.long 0x20C++0x03
line.long 0x00 "IDXBLK_L,no description available"
bitfld.long 0x00 30.--31. "LOCK_IDX,Lock 0 to 7 PUF key indexes" "0,1,2,3"
bitfld.long 0x00 14.--15. "IDX7,Use to block PUF index 7" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "IDX6,Use to block PUF index 6" "0,1,2,3"
bitfld.long 0x00 10.--11. "IDX5,Use to block PUF index 5" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IDX4,Use to block PUF index 4" "0,1,2,3"
bitfld.long 0x00 6.--7. "IDX3,Use to block PUF index 3" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "IDX2,Use to block PUF index 2" "0,1,2,3"
bitfld.long 0x00 2.--3. "IDX1,Use to block PUF index 1" "0,1,2,3"
wgroup.long 0x20C++0x03
line.long 0x00 "IDXBLK,no description available"
bitfld.long 0x00 30.--31. "IDX15,Use to block PUF index 15" "0,1,2,3"
bitfld.long 0x00 28.--29. "IDX14,Use to block PUF index 14" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "IDX13,Use to block PUF index 13" "0,1,2,3"
bitfld.long 0x00 24.--25. "IDX12,Use to block PUF index 12" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "IDX11,Use to block PUF index 11" "0,1,2,3"
bitfld.long 0x00 20.--21. "IDX10,Use to block PUF index 10" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "IDX9,Use to block PUF index 9" "0,1,2,3"
bitfld.long 0x00 16.--17. "IDX8,Use to block PUF index 8" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "IDX7,Use to block PUF index 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "IDX6,Use to block PUF index 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "IDX5,Use to block PUF index 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "IDX4,Use to block PUF index 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "IDX3,Use to block PUF index 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "IDX2,Use to block PUF index 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "IDX1,Use to block PUF index 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "IDX0,Use to block PUF index 0" "0,1,2,3"
group.long 0x210++0x03
line.long 0x00 "IDXBLK_H_DP,no description available"
bitfld.long 0x00 14.--15. "IDX15,Use to block PUF index 15" "0,1,2,3"
bitfld.long 0x00 12.--13. "IDX14,Use to block PUF index 14" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "IDX13,Use to block PUF index 13" "0,1,2,3"
bitfld.long 0x00 8.--9. "IDX12,Use to block PUF index 12" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "IDX11,Use to block PUF index 11" "0,1,2,3"
bitfld.long 0x00 4.--5. "IDX10,Use to block PUF index 10" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "IDX9,Use to block PUF index 9" "0,1,2,3"
bitfld.long 0x00 0.--1. "IDX8,Use to block PUF index 8" "0,1,2,3"
wgroup.long 0x210++0x03
line.long 0x00 "IDXBLK_DP,no description available"
bitfld.long 0x00 30.--31. "IDX15,Use to block PUF index 15" "0,1,2,3"
bitfld.long 0x00 28.--29. "IDX14,Use to block PUF index 14" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "IDX13,Use to block PUF index 13" "0,1,2,3"
bitfld.long 0x00 24.--25. "IDX12,Use to block PUF index 12" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "IDX11,Use to block PUF index 11" "0,1,2,3"
bitfld.long 0x00 20.--21. "IDX10,Use to block PUF index 10" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "IDX9,Use to block PUF index 9" "0,1,2,3"
bitfld.long 0x00 16.--17. "IDX8,Use to block PUF index 8" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "IDX7,Use to block PUF index 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "IDX6,Use to block PUF index 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "IDX5,Use to block PUF index 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "IDX4,Use to block PUF index 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "IDX3,Use to block PUF index 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "IDX2,Use to block PUF index 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "IDX1,Use to block PUF index 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "IDX0,Use to block PUF index 0" "0,1,2,3"
repeat 4. (increment 0 1) (increment 0 0x04)
wgroup.long ($2+0x214)++0x03
line.long 0x00 "KEYMASK[$1],Only reset in case of full IC reset $1"
hexmask.long 0x00 0.--31. 1. "KEYMASK,no description available"
repeat.end
rgroup.long 0x254++0x03
line.long 0x00 "IDXBLK_STATUS,Index block status"
bitfld.long 0x00 30.--31. "IDX15,Status block index 15" "0,1,2,3"
bitfld.long 0x00 28.--29. "IDX14,Status block index 14" "0,1,2,3"
newline
bitfld.long 0x00 26.--27. "IDX13,Status block index 13" "0,1,2,3"
bitfld.long 0x00 24.--25. "IDX12,Status block index 12" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "IDX11,Status block index 11" "0,1,2,3"
bitfld.long 0x00 20.--21. "IDX10,Status block index 10" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "IDX9,Status block index 9" "0,1,2,3"
bitfld.long 0x00 16.--17. "IDX8,Status block index 8" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "IDX7,Status block index 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "IDX6,Status block index 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "IDX5,Status block index 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "IDX4,Status block index 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "IDX3,Status block index 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "IDX2,Status block index 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "IDX1,Status block index 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "IDX0,Status block index 0" "0,1,2,3"
group.long 0x254++0x03
line.long 0x00 "IDXBLK_H,no description available"
bitfld.long 0x00 30.--31. "LOCK_IDX,Lock 8 to 15 PUF key indexes" "0,1,2,3"
bitfld.long 0x00 14.--15. "IDX15,Use to block PUF index 15" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "IDX14,Use to block PUF index 14" "0,1,2,3"
bitfld.long 0x00 10.--11. "IDX13,Use to block PUF index 13" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IDX12,Use to block PUF index 12" "0,1,2,3"
bitfld.long 0x00 6.--7. "IDX11,Use to block PUF index 11" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "IDX10,Use to block PUF index 10" "0,1,2,3"
bitfld.long 0x00 2.--3. "IDX9,Use to block PUF index 9" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "IDX8,Use to block PUF index 8" "0,1,2,3"
group.long 0x258++0x03
line.long 0x00 "IDXBLK_L_DP,no description available"
bitfld.long 0x00 14.--15. "IDX7,Use to block PUF index 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "IDX6,Use to block PUF index 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "IDX5,Use to block PUF index 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "IDX4,Use to block PUF index 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "IDX3,Use to block PUF index 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "IDX2,Use to block PUF index 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "IDX1,Use to block PUF index 1" "0,1,2,3"
rgroup.long 0x258++0x03
line.long 0x00 "SHIFT_STATUS,no description available"
bitfld.long 0x00 12.--15. "KEY3,Index counter from key 3 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "KEY2,Index counter from key 2 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "KEY1,Index counter from key 1 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "KEY0,Index counter from key 0 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x25C++0x03
line.long 0x00 "SHIFT_STATUS,no description available"
rbitfld.long 0x00 12.--15. "KEY3,Index counter from key 3 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 8.--11. "KEY2,Index counter from key 2 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 4.--7. "KEY1,Index counter from key 1 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "KEY0,Index counter from key 0 shift register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
sif cpuis("LPC55S16*")||cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")
tree "PUF_SRAM_CTRL (PUF SRAM Control)"
base ad:0x4003B000
group.long 0x300++0x03
line.long 0x00 "CFG,Configuration Register"
bitfld.long 0x00 2. "ckgating,PUF SRAM Clock Gating control" "0,1"
bitfld.long 0x00 0. "enable,PUF SRAM Controller activation" "0,1"
group.long 0x304++0x03
line.long 0x00 "STATUS,Status Register"
rbitfld.long 0x00 0. "READY,PUF SRAM Controller State" "0,1"
wgroup.long 0x3D8++0x03
line.long 0x00 "INT_CLR_ENABLE,Interrupt Enable Clear Register"
bitfld.long 0x00 1. "APB_ERR,APB_ERR Interrupt Enable clear" "0,1"
bitfld.long 0x00 0. "READY,READY Interrupt Enable clear" "0,1"
wgroup.long 0x3DC++0x03
line.long 0x00 "INT_SET_ENABLE,Interrupt Enable Set Register"
bitfld.long 0x00 1. "APB_ERR,APB_ERR Interrupt Enable set" "0,1"
bitfld.long 0x00 0. "READY,READY Interrupt Enable set" "0,1"
group.long 0x3E0++0x03
line.long 0x00 "INT_STATUS,Interrupt Status Register"
rbitfld.long 0x00 1. "APB_ERR,APB_ERR Interrupt Status" "0,1"
rbitfld.long 0x00 0. "READY,READY Interrupt Status" "0,1"
group.long 0x3E4++0x03
line.long 0x00 "INT_ENABLE,Interrupt Enable Register"
rbitfld.long 0x00 1. "APB_ERR,APB_ERR Interrupt Enable" "0,1"
rbitfld.long 0x00 0. "READY,READY Interrupt Enable" "0,1"
wgroup.long 0x3E8++0x03
line.long 0x00 "INT_CLR_STATUS,Interrupt Status Clear Register"
bitfld.long 0x00 1. "APB_ERR,APB_ERR Interrupt Status Clear" "0,1"
bitfld.long 0x00 0. "READY,READY Interrupt Status clear" "0,1"
wgroup.long 0x3EC++0x03
line.long 0x00 "INT_SET_STATUS,Interrupt Status set"
bitfld.long 0x00 1. "APB_ERR,APB_ERR Interrupt Status Set" "0,1"
bitfld.long 0x00 0. "READY,READY Interrupt Status set" "0,1"
tree.end
endif
tree "RNG (Random Number Generator)"
base ad:0x4003A000
rgroup.long 0x00++0x03
line.long 0x00 "RANDOM_NUMBER,This register contains a random 32 bit number which is computed on demand at each time it is"
hexmask.long 0x00 0.--31. 1. "RANDOM_NUMBER,This register contains a random 32 bit number which is computed on demand at each time it is"
group.long 0x04++0x03
line.long 0x00 "ENCRYPTED_NUMBER,This register contains a random 32 bit number which is pre-computed"
hexmask.long 0x00 0.--31. 1. "ENCRYPTED_NUMBER,This register contains a random 32 bit number which is pre-computed"
group.long 0x08++0x03
line.long 0x00 "COUNTER_VAL,no description available"
rbitfld.long 0x00 8.--12. "REFRESH_CNT,Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "CLK_RATIO,Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes"
group.long 0x08++0x03
line.long 0x00 "COUNTER_VAL,no description available"
hexmask.long.word 0x00 8.--21. 1. "REFRESH_CNT,Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER"
hexmask.long.byte 0x00 0.--7. 1. "CLK_RATIO,Gives the ratio between the internal clocks frequencies and the register clock frequency for evaluation and certification purposes"
group.long 0x0C++0x03
line.long 0x00 "COUNTER_CFG,no description available"
bitfld.long 0x00 5.--7. "SHIFT4X,To be used to add precision to clock_ratio and determine 'entropy refill'" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2.--4. "CLOCK_SEL,Selects the internal clock on which to compute statistics" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--1. "MODE," "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "ONLINE_TEST_CFG,no description available"
bitfld.long 0x00 1.--2. "DATA_SEL,Selects source on which to apply online test" "0: LSB of COUNTER,1: MSB of COUNTER,2: RANDOM_NUMBER,3: ENCRYPTED_NUMBER 'activate' should be set to"
bitfld.long 0x00 0. "ACTIVATE," "0,1"
group.long 0x14++0x03
line.long 0x00 "ONLINE_TEST_VAL,no description available"
rbitfld.long 0x00 8.--11. "MAX_CHI_SQUARED,This field is reset when 'activate'==0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 4.--7. "MIN_CHI_SQUARED,This field is reset when 'activate'==0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "LIVE_CHI_SQUARED,This value is updated as described in field 'activate'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "ENTROPY_INJECT,no description available"
hexmask.long 0x00 0.--31. 1. "ENTROPY,Use this register to inject or restore entropy 32 bits at a time"
group.long 0x1C++0x03
line.long 0x00 "MISC_CFG,no description available"
bitfld.long 0x00 1. "AES_DT_CFG,Set this bit to re-seed AES" "0,1"
bitfld.long 0x00 0. "AES_RESEED,If set ENCRYPTED_NUMBER generation becomes predictable provided all secrets and current internal state are known: independant from entropy source" "0,1"
group.long 0xFF4++0x03
line.long 0x00 "POWERDOWN,Powerdown mode (standard but certainly useless here)"
bitfld.long 0x00 31. "POWERDOWN,When set all accesses to standard registers are blocked" "0,1"
bitfld.long 0x00 1. "FORCE_SOFT_RESET,When used with softreset it forces CORE_RESETN to low on acknowledge from CORE" "0,1"
bitfld.long 0x00 0. "SOFT_RESET,Request softreset that will go low automaticaly after acknowledge from CORE" "0,1"
rgroup.long 0xFFC++0x03
line.long 0x00 "MODULEID,IP identifier"
hexmask.long.word 0x00 16.--31. 1. "ID,Identifier"
bitfld.long 0x00 12.--15. "MAJ_REV,Major revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "MIN_REV,Minor revision i" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture i"
tree.end
tree "RTC (Real-time Counter)"
base ad:0x4002C000
group.long 0x00++0x03
line.long 0x00 "CTRL,RTC control register"
bitfld.long 0x00 10. "RTC_SUBSEC_ENA,RTC Sub-second counter control" "0: The sub-second counter (if implemented) is..,1: The 32 KHz sub-second counter is enabled (if.."
bitfld.long 0x00 9. "RTC_OSC_BYPASS,RTC oscillator bypass control" "0: The RTC Oscillator operates normally as a..,1: The RTC Oscillator is in bypass mode"
newline
bitfld.long 0x00 8. "RTC_OSC_PD,RTC oscillator power-down control" "0: See RTC_OSC_BYPASS,1: RTC oscillator is powered-down"
bitfld.long 0x00 7. "RTC_EN,RTC enable" "0: Disable,1: Enable"
newline
bitfld.long 0x00 6. "RTC1KHZ_EN,RTC 1 kHz clock enable" "0: Disable,1: Enable"
bitfld.long 0x00 5. "WAKEDPD_EN,RTC 1 kHz timer wake-up enable for Deep power-down" "0: Disable,1: Enable"
newline
bitfld.long 0x00 4. "ALARMDPD_EN,RTC 1 Hz timer alarm enable for Deep power-down" "0: Disable,1: Enable"
bitfld.long 0x00 3. "WAKE1KHZ,RTC 1 kHz timer wake-up flag status" "0: Run,1: Time-out"
newline
bitfld.long 0x00 2. "ALARM1HZ,RTC 1 Hz timer alarm flag status" "0: No match,1: Match"
bitfld.long 0x00 0. "SWRESET,Software reset control" "0: Not in reset,1: In reset"
group.long 0x04++0x03
line.long 0x00 "MATCH,RTC match register"
hexmask.long 0x00 0.--31. 1. "MATVAL,Contains the match value against which the 1 Hz RTC timer will be compared to set the alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled"
group.long 0x08++0x03
line.long 0x00 "COUNT,RTC counter register"
hexmask.long 0x00 0.--31. 1. "VAL,A read reflects the current value of the main 1 Hz RTC timer"
group.long 0x0C++0x03
line.long 0x00 "WAKE,High-resolution/wake-up timer control register"
hexmask.long.word 0x00 0.--15. 1. "VAL,A read reflects the current value of the high-resolution/wake-up timer"
group.long 0x10++0x03
line.long 0x00 "SUBSEC,Sub-second counter register"
hexmask.long.word 0x00 0.--14. 1. "SUBSEC,A read reflects the current value of the 32KHz sub-second counter"
repeat 8. (increment 0 1) (increment 0 0x4)
group.long ($2+0x40)++0x03
line.long 0x00 "GPREG[$1],General Purpose register $1"
hexmask.long 0x00 0.--31. 1. "GPDATA,Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied"
repeat.end
tree.end
tree "SAU"
base ad:0xE000EDD0
group.long 0xD0++0x03
line.long 0x00 "CTRL,Security Attribution Unit Control Register"
bitfld.long 0x00 1. "ALLNS,All Non-secure" "0: Memory is marked as Secure and is not..,1: Memory is marked as Non-secure"
bitfld.long 0x00 0. "ENABLE,Enable" "0: The SAU is disabled,1: The SAU is enabled"
group.long 0xD4++0x03
line.long 0x00 "TYPE,Security Attribution Unit Type Register"
hexmask.long.byte 0x00 0.--7. 1. "SREGION,SAU regions"
group.long 0xD8++0x03
line.long 0x00 "RNR,Security Attribution Unit Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. "REGION,Region number"
group.long 0xDC++0x03
line.long 0x00 "RBAR,Security Attribution Unit Region Base Address Register"
hexmask.long 0x00 5.--31. 1. "BADDR,Base address"
group.long 0xE0++0x03
line.long 0x00 "RLAR,Security Attribution Unit Region Limit Address Register"
hexmask.long 0x00 5.--31. 1. "LADDR,Limit address"
bitfld.long 0x00 1. "NSC,Non-secure callable" "0: Region is not Non-secure callable,1: Region is Non-secure callable"
bitfld.long 0x00 0. "ENABLE,Enable" "0: SAU region is enabled,1: SAU region is disabled"
group.long 0xE4++0x03
line.long 0x00 "SFSR,Secure Fault Status Register"
bitfld.long 0x00 7. "LSERR,Lazy state error flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 6. "SFARVALID,Secure fault address valid" "0: SFAR content not valid,1: SFAR content valid"
bitfld.long 0x00 5. "LSPERR,Lazy state preservation error flag" "0: Error has not occurred,1: Error has occurred"
newline
bitfld.long 0x00 4. "INVTRAN,Invalid transition flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 3. "AUVIOL,Attribution unit violation flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 2. "INVER,Invalid exception return flag" "0: Error has not occurred,1: Error has occurred"
newline
bitfld.long 0x00 1. "INVIS,Invalid integrity signature flag" "0: Error has not occurred,1: Error has occurred"
bitfld.long 0x00 0. "INVEP,Invalid entry point" "0: Error has not occurred,1: Error has occurred"
group.long 0xE8++0x03
line.long 0x00 "SFAR,Secure Fault Address Register"
hexmask.long 0x00 0.--31. 1. "ADDRESS,When the SFARVALID bit of the SFSR is set to 1 this field holds the address of an access that caused an SAU violation"
tree.end
tree "SCB"
base ad:0xE000ED00
group.long 0x0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key: Reads as 0xFA05"
rbitfld.long 0x00 15. "ENDIANNESS,Data endianness bit" "0: Little-endian,1: BIG_ENDIAN"
newline
bitfld.long 0x00 14. "PRIS,Prioritize Secure exceptions" "0: Priority ranges of Secure and Non-secure..,1: Non-secure exceptions are de-prioritized"
bitfld.long 0x00 13. "BFHFNMINS,BusFault HardFault and NMI Non-secure enable" "0: BusFault HardFault and NMI are Secure,1: BusFault and NMI are Non-secure and.."
newline
bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "SYSRESETREQS,System reset request Secure state only" "0: SYSRESETREQ functionality is available to..,1: SYSRESETREQ functionality is only available.."
newline
bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0: Do not request a system reset,1: Request a system reset"
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1"
group.long 0x10++0x03
line.long 0x00 "SCR,The SCR controls features of entry to and exit from low-power state"
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup..,1: Enabled events and all interrupts including.."
bitfld.long 0x00 3. "SLEEPDEEPS,Controls whether the SLEEPDEEP bit is only accessible from the Secure state" "0: The SLEEPDEEP bit is accessible from both..,1: The SLEEPDEEP bit behaves as RAZ/WI when.."
newline
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low-power mode" "0: Sleep,1: Deep sleep"
bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR"
group.long 0x24++0x03
line.long 0x00 "SHCSR,System Handler Control and State Register"
bitfld.long 0x00 21. "HARDFAULTPENDED,HardFault exception pended state" "0: HardFault exception modification is disabled,1: HardFault exception modification is enabled"
bitfld.long 0x00 20. "SECUREFAULTPENDED,SecureFault exception pended state bit" "0: SecureFault exception modification is disabled,1: SecureFault exception modification is enabled"
newline
bitfld.long 0x00 19. "SECUREFAULTENA,SecureFault exception enable" "0: SecureFault exception is disabled,1: SecureFault exception is enabled"
bitfld.long 0x00 18. "USGFAULTENA,UsageFault enable" "0: UsageFault is disabled,1: UsageFault is enabled"
newline
bitfld.long 0x00 17. "BUSFAULTENA,BusFault enable" "0: BusFault is disabled,1: BusFault is enabled"
bitfld.long 0x00 16. "MEMFAULTENA,MemManage enable" "0: MemManage exception is disabled,1: MemManage exception is enabled"
newline
bitfld.long 0x00 15. "SVCALLPENDED,SVCall pending" "0: SVCall exception is not pending,1: SVCall exception is pending"
bitfld.long 0x00 14. "BUSFAULTPENDED,BusFault exception pending" "0: BusFault exception is pending,1: BusFault exception is not pending"
newline
bitfld.long 0x00 13. "MEMFAULTPENDED,MemManage exception pending" "0: MemManage exception is not pending,1: MemManage exception is pending"
bitfld.long 0x00 12. "USGFAULTPENDED,UsageFault exception pending" "0: UsageFault exception is not pending,1: UsageFault exception is pending"
newline
bitfld.long 0x00 11. "SYSTICKACT,SysTick exception active" "0: SysTick exception is not active,1: SysTick exception is active"
bitfld.long 0x00 10. "PENDSVACT,PendSV exception active" "0: PendSV exception is not active,1: PendSV exception is active"
newline
bitfld.long 0x00 8. "MONITORACT,Debug monitor active" "0: Debug monitor exception is not active,1: Debug monitor exception is active"
bitfld.long 0x00 7. "SVCALLACT,SVCall active" "0: SVCall exception is not active,1: SVCall exception is active"
newline
bitfld.long 0x00 5. "NMIACT,NMI exception active" "0: NMI exception is not active,1: NMI exception is active"
bitfld.long 0x00 4. "SECUREFAULTACT,SecureFault exception active" "0: SecureFault exception is not active,1: SecureFault exception is active"
newline
bitfld.long 0x00 3. "USGFAULTACT,UsageFault exception active" "0: UsageFault exception is not active,1: UsageFault exception is active"
bitfld.long 0x00 2. "HARDFAULTACT,HardFault exception active" "0: HardFault exception is not active,1: HardFault exception is active"
newline
bitfld.long 0x00 1. "BUSFAULTACT,BusFault exception active" "0: BusFault exception is not active,1: BusFault exception is active"
bitfld.long 0x00 0. "MEMFAULTACT,MemManage exception active" "0: MemManage exception is not active,1: MemManage exception is active"
group.long 0x8C++0x03
line.long 0x00 "NSACR,Non-secure Access Control Register"
bitfld.long 0x00 11. "CP11,CP11 access" "0,1"
bitfld.long 0x00 10. "CP10,CP10 access" "0: Non-secure accesses to the Floating-point..,1: Non-secure access to the Floatingpoint.."
newline
bitfld.long 0x00 7. "CP7,CP7 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 6. "CP6,CP6 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
newline
bitfld.long 0x00 5. "CP5,CP5 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 4. "CP4,CP4 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
newline
bitfld.long 0x00 3. "CP3,CP3 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 2. "CP2,CP2 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
newline
bitfld.long 0x00 1. "CP1,CP1 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
bitfld.long 0x00 0. "CP0,CP0 access" "0: Non-secure accesses to this coprocessor..,1: Non-secure access to this coprocessor permitted"
tree.end
tree "SCNSCB"
base ad:0xE000E000
group.long 0x0C++0x03
line.long 0x00 "CPPWR,Coprocessor Power Control Register"
bitfld.long 0x00 23. "SUS11,State UNKNOWN Secure only 11" "0,1"
bitfld.long 0x00 22. "SU11,State UNKNOWN 11" "0,1"
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bitfld.long 0x00 21. "SUS10,State UNKNOWN Secure only 10" "0: The SU10 field is accessible from both..,1: The SU10 field is only accessible from the.."
bitfld.long 0x00 20. "SU10,State UNKNOWN 10" "0: The floating-point state is not permitted to..,1: The floating-point state is permitted to.."
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bitfld.long 0x00 15. "SUS7,State UNKNOWN Secure only 7" "0: The SU7 field is accessible from both..,1: The SU7 field is only accessible from the.."
bitfld.long 0x00 14. "SU7,State UNKNOWN 7" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
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bitfld.long 0x00 13. "SUS6,State UNKNOWN Secure only 6" "0: The SU6 field is accessible from both..,1: The SU6 field is only accessible from the.."
bitfld.long 0x00 12. "SU6,State UNKNOWN 6" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
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bitfld.long 0x00 11. "SUS5,State UNKNOWN Secure only 5" "0: The SU5 field is accessible from both..,1: The SU5 field is only accessible from the.."
bitfld.long 0x00 10. "SU5,State UNKNOWN 5" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
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bitfld.long 0x00 9. "SUS4,State UNKNOWN Secure only 4" "0: The SU4 field is accessible from both..,1: The SU4 field is only accessible from the.."
bitfld.long 0x00 8. "SU4,State UNKNOWN 4" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
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bitfld.long 0x00 7. "SUS3,State UNKNOWN Secure only 3" "0: The SU3 field is accessible from both..,1: The SU3 field is only accessible from the.."
bitfld.long 0x00 6. "SU3,State UNKNOWN 3" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
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bitfld.long 0x00 5. "SUS2,State UNKNOWN Secure only 2" "0: The SU2 field is accessible from both..,1: The SU2 field is only accessible from the.."
bitfld.long 0x00 4. "SU2,State UNKNOWN 2" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
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bitfld.long 0x00 3. "SUS1,State UNKNOWN Secure only 1" "0: The SU7 field is accessible from both..,1: The SU7 field is only accessible from the.."
bitfld.long 0x00 2. "SU1,State UNKNOWN 1" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
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bitfld.long 0x00 1. "SUS0,State UNKNOWN Secure only 0" "0: The SU0 field is accessible from both..,1: The SU0 field is only accessible from the.."
bitfld.long 0x00 0. "SU0,State UNKNOWN 0" "0: The coprocessor state is not permitted to..,1: The coprocessor state is permitted to become.."
tree.end
tree "SCT (SCTimer/PWM)"
base ad:0x40085000
group.long 0x00++0x03
line.long 0x00 "CONFIG,SCT configuration register"
bitfld.long 0x00 18. "AUTOLIMIT_H,A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event" "0,1"
bitfld.long 0x00 17. "AUTOLIMIT_L,A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event" "0,1"
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bitfld.long 0x00 9.--12. "INSYNC,Synchronization for input N (bit 9 = input 0 bit 10 = input 1 bit 12 = input 3) all other bits are reserved" "?,?,?,?,?,?,?,?,?,9: input 0 bit,10: input 1 bit,?,12: input 3) all other bits are,?..."
bitfld.long 0x00 8. "NORELOAD_H,A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers" "0,1"
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bitfld.long 0x00 7. "NORELOAD_L,A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers" "0,1"
bitfld.long 0x00 3.--6. "CKSEL,SCT clock select" "0: Rising edges on input 0,1: Falling edges on input 0,2: Rising edges on input 1,3: Falling edges on input 1,4: Rising edges on input 2,5: Falling edges on input 2,6: Rising edges on input 3,7: Falling edges on input 3,8: Rising edges on input 4,9: Falling edges on input 4,10: Rising edges on input 5,11: Falling edges on input 5,12: Rising edges on input 6,13: Falling edges on input 6,14: Rising edges on input 7,15: Falling edges on input 7"
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bitfld.long 0x00 1.--2. "CLKMODE,SCT clock mode" "0: System Clock Mode,1: Sampled System Clock Mode,2: SCT Input Clock Mode,3: Asynchronous Mode"
bitfld.long 0x00 0. "UNIFY,SCT operation" "0: The SCT operates as two 16-bit counters named..,1: The SCT operates as a unified 32-bit counter"
group.long 0x04++0x03
line.long 0x00 "CTRL,SCT control register"
hexmask.long.byte 0x00 21.--28. 1. "PRE_H,Specifies the factor by which the SCT clock is prescaled to produce the H counter clock"
bitfld.long 0x00 20. "BIDIR_H,Direction select" "0: The H counter counts up to its limit..,1: The H counter counts up to its limit then.."
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bitfld.long 0x00 19. "CLRCTR_H,Writing a 1 to this bit clears the H counter" "0,1"
bitfld.long 0x00 18. "HALT_H,When this bit is 1 the H counter does not run and no events can occur" "0,1"
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bitfld.long 0x00 17. "STOP_H,When this bit is 1 and HALT is 0 the H counter does not run but I/O events related to the counter can occur" "0,1"
bitfld.long 0x00 16. "DOWN_H,This bit is 1 when the H counter is counting down" "0,1"
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hexmask.long.byte 0x00 5.--12. 1. "PRE_L,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
bitfld.long 0x00 4. "BIDIR_L,L or unified counter direction select" "0: Up,1: Up-down"
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bitfld.long 0x00 3. "CLRCTR_L,Writing a 1 to this bit clears the L or unified counter" "0,1"
bitfld.long 0x00 2. "HALT_L,When this bit is 1 the L or unified counter does not run and no events can occur" "0,1"
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bitfld.long 0x00 1. "STOP_L,When this bit is 1 and HALT is 0 the L or unified counter does not run but I/O events related to the counter can occur" "0,1"
bitfld.long 0x00 0. "DOWN_L,This bit is 1 when the L or unified counter is counting down" "0,1"
group.long 0x08++0x03
line.long 0x00 "LIMIT,SCT limit event select register"
abitfld.long 0x00 16.--31. "LIMMSK_H,If bit n is one event n is used as a counter limit for the H counter (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "LIMMSK_L,If bit n is one event n is used as a counter limit for the L or unified counter (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x0C++0x03
line.long 0x00 "HALT,SCT halt event select register"
abitfld.long 0x00 16.--31. "HALTMSK_H,If bit n is one event n sets the HALT_H bit in the CTRL register (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "HALTMSK_L,If bit n is one event n sets the HALT_L bit in the CTRL register (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x10++0x03
line.long 0x00 "STOP,SCT stop event select register"
abitfld.long 0x00 16.--31. "STOPMSK_H,If bit n is one event n sets the STOP_H bit in the CTRL register (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "STOPMSK_L,If bit n is one event n sets the STOP_L bit in the CTRL register (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x14++0x03
line.long 0x00 "START,SCT start event select register"
abitfld.long 0x00 16.--31. "STARTMSK_H,If bit n is one event n clears the STOP_H bit in the CTRL register (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "STARTMSK_L,If bit n is one event n clears the STOP_L bit in the CTRL register (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x40++0x03
line.long 0x00 "COUNT,SCT counter register"
hexmask.long.word 0x00 16.--31. 1. "CTR_H,When UNIFY = 0 read or write the 16-bit H counter value"
hexmask.long.word 0x00 0.--15. 1. "CTR_L,When UNIFY = 0 read or write the 16-bit L counter value"
group.long 0x44++0x03
line.long 0x00 "STATE,SCT state register"
bitfld.long 0x00 16.--20. "STATE_H,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "STATE_L,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x48++0x03
line.long 0x00 "INPUT,SCT input register"
bitfld.long 0x00 31. "SIN15,Input 15 state" "0,1"
bitfld.long 0x00 30. "SIN14,Input 14 state" "0,1"
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bitfld.long 0x00 29. "SIN13,Input 13 state" "0,1"
bitfld.long 0x00 28. "SIN12,Input 12 state" "0,1"
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bitfld.long 0x00 27. "SIN11,Input 11 state" "0,1"
bitfld.long 0x00 26. "SIN10,Input 10 state" "0,1"
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bitfld.long 0x00 25. "SIN9,Input 9 state" "0,1"
bitfld.long 0x00 24. "SIN8,Input 8 state" "0,1"
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bitfld.long 0x00 23. "SIN7,Input 7 state" "0,1"
bitfld.long 0x00 22. "SIN6,Input 6 state" "0,1"
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bitfld.long 0x00 21. "SIN5,Input 5 state" "0,1"
bitfld.long 0x00 20. "SIN4,Input 4 state" "0,1"
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bitfld.long 0x00 19. "SIN3,Input 3 state" "0,1"
bitfld.long 0x00 18. "SIN2,Input 2 state" "0,1"
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bitfld.long 0x00 17. "SIN1,Input 1 state" "0,1"
bitfld.long 0x00 16. "SIN0,Input 0 state" "0,1"
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bitfld.long 0x00 15. "AIN15,Input 15 state" "0,1"
bitfld.long 0x00 14. "AIN14,Input 14 state" "0,1"
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bitfld.long 0x00 13. "AIN13,Input 13 state" "0,1"
bitfld.long 0x00 12. "AIN12,Input 12 state" "0,1"
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bitfld.long 0x00 11. "AIN11,Input 11 state" "0,1"
bitfld.long 0x00 10. "AIN10,Input 10 state" "0,1"
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bitfld.long 0x00 9. "AIN9,Input 9 state" "0,1"
bitfld.long 0x00 8. "AIN8,Input 8 state" "0,1"
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bitfld.long 0x00 7. "AIN7,Input 7 state" "0,1"
bitfld.long 0x00 6. "AIN6,Input 6 state" "0,1"
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bitfld.long 0x00 5. "AIN5,Input 5 state" "0,1"
bitfld.long 0x00 4. "AIN4,Input 4 state" "0,1"
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bitfld.long 0x00 3. "AIN3,Input 3 state" "0,1"
bitfld.long 0x00 2. "AIN2,Input 2 state" "0,1"
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bitfld.long 0x00 1. "AIN1,Input 1 state" "0,1"
bitfld.long 0x00 0. "AIN0,Input 0 state" "0,1"
group.long 0x4C++0x03
line.long 0x00 "REGMODE,SCT match/capture mode register"
abitfld.long 0x00 16.--31. "REGMOD_H,Each bit controls one match/capture register (register 0 = bit 16 register 1 = bit 17 etc.)" "0x0000=0: register operates as match registers,0x0001=1: register operates as capture registers"
abitfld.long 0x00 0.--15. "REGMOD_L,Each bit controls one match/capture register (register 0 = bit 0 register 1 = bit 1 etc.)" "0x0000=0: register operates as match register,0x0001=1: register operates as capture register"
group.long 0x50++0x03
line.long 0x00 "OUTPUT,SCT output register"
abitfld.long 0x00 0.--15. "OUT,Writing a 1 to bit n forces the corresponding output HIGH" "0x0000=0: bit 0 output,0x0001=1: bit 1 etc.). The number of bits ="
group.long 0x54++0x03
line.long 0x00 "OUTPUTDIRCTRL,SCT output counter direction control register"
bitfld.long 0x00 30.--31. "SETCLR15,Set/clear operation on output 15" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 28.--29. "SETCLR14,Set/clear operation on output 14" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
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bitfld.long 0x00 26.--27. "SETCLR13,Set/clear operation on output 13" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 24.--25. "SETCLR12,Set/clear operation on output 12" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
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bitfld.long 0x00 22.--23. "SETCLR11,Set/clear operation on output 11" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 20.--21. "SETCLR10,Set/clear operation on output 10" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
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bitfld.long 0x00 18.--19. "SETCLR9,Set/clear operation on output 9" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 16.--17. "SETCLR8,Set/clear operation on output 8" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
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bitfld.long 0x00 14.--15. "SETCLR7,Set/clear operation on output 7" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 12.--13. "SETCLR6,Set/clear operation on output 6" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
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bitfld.long 0x00 10.--11. "SETCLR5,Set/clear operation on output 5" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 8.--9. "SETCLR4,Set/clear operation on output 4" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
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bitfld.long 0x00 6.--7. "SETCLR3,Set/clear operation on output 3" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 4.--5. "SETCLR2,Set/clear operation on output 2" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
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bitfld.long 0x00 2.--3. "SETCLR1,Set/clear operation on output 1" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
bitfld.long 0x00 0.--1. "SETCLR0,Set/clear operation on output 0" "0: Set and clear do not depend on the direction..,1: Set and clear are reversed when counter L or..,2: Set and clear are reversed when counter H is..,?..."
group.long 0x58++0x03
line.long 0x00 "RES,SCT conflict resolution register"
bitfld.long 0x00 30.--31. "O15RES,Effect of simultaneous set and clear on output 15" "0: No change,1: Set output (or clear based on the SETCLR15..,2: Clear output (or set based on the SETCLR15..,3: Toggle output"
bitfld.long 0x00 28.--29. "O14RES,Effect of simultaneous set and clear on output 14" "0: No change,1: Set output (or clear based on the SETCLR14..,2: Clear output (or set based on the SETCLR14..,3: Toggle output"
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bitfld.long 0x00 26.--27. "O13RES,Effect of simultaneous set and clear on output 13" "0: No change,1: Set output (or clear based on the SETCLR13..,2: Clear output (or set based on the SETCLR13..,3: Toggle output"
bitfld.long 0x00 24.--25. "O12RES,Effect of simultaneous set and clear on output 12" "0: No change,1: Set output (or clear based on the SETCLR12..,2: Clear output (or set based on the SETCLR12..,3: Toggle output"
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bitfld.long 0x00 22.--23. "O11RES,Effect of simultaneous set and clear on output 11" "0: No change,1: Set output (or clear based on the SETCLR11..,2: Clear output (or set based on the SETCLR11..,3: Toggle output"
bitfld.long 0x00 20.--21. "O10RES,Effect of simultaneous set and clear on output 10" "0: No change,1: Set output (or clear based on the SETCLR10..,2: Clear output (or set based on the SETCLR10..,3: Toggle output"
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bitfld.long 0x00 18.--19. "O9RES,Effect of simultaneous set and clear on output 9" "0: No change,1: Set output (or clear based on the SETCLR9..,2: Clear output (or set based on the SETCLR9..,3: Toggle output"
bitfld.long 0x00 16.--17. "O8RES,Effect of simultaneous set and clear on output 8" "0: No change,1: Set output (or clear based on the SETCLR8..,2: Clear output (or set based on the SETCLR8..,3: Toggle output"
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bitfld.long 0x00 14.--15. "O7RES,Effect of simultaneous set and clear on output 7" "0: No change,1: Set output (or clear based on the SETCLR7..,2: Clear output n (or set based on the SETCLR7..,3: Toggle output"
bitfld.long 0x00 12.--13. "O6RES,Effect of simultaneous set and clear on output 6" "0: No change,1: Set output (or clear based on the SETCLR6..,2: Clear output (or set based on the SETCLR6..,3: Toggle output"
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bitfld.long 0x00 10.--11. "O5RES,Effect of simultaneous set and clear on output 5" "0: No change,1: Set output (or clear based on the SETCLR5..,2: Clear output (or set based on the SETCLR5..,3: Toggle output"
bitfld.long 0x00 8.--9. "O4RES,Effect of simultaneous set and clear on output 4" "0: No change,1: Set output (or clear based on the SETCLR4..,2: Clear output (or set based on the SETCLR4..,3: Toggle output"
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bitfld.long 0x00 6.--7. "O3RES,Effect of simultaneous set and clear on output 3" "0: No change,1: Set output (or clear based on the SETCLR3..,2: Clear output (or set based on the SETCLR3..,3: Toggle output"
bitfld.long 0x00 4.--5. "O2RES,Effect of simultaneous set and clear on output 2" "0: No change,1: Set output (or clear based on the SETCLR2..,2: Clear output n (or set based on the SETCLR2..,3: Toggle output"
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bitfld.long 0x00 2.--3. "O1RES,Effect of simultaneous set and clear on output 1" "0: No change,1: Set output (or clear based on the SETCLR1..,2: Clear output (or set based on the SETCLR1..,3: Toggle output"
bitfld.long 0x00 0.--1. "O0RES,Effect of simultaneous set and clear on output 0" "0: No change,1: Set output (or clear based on the SETCLR0..,2: Clear output (or set based on the SETCLR0..,3: Toggle output"
group.long 0x5C++0x03
line.long 0x00 "DMAREQ0,SCT DMA request 0 register"
bitfld.long 0x00 31. "DRQ0,This read-only bit indicates the state of DMA Request 0" "0,1"
bitfld.long 0x00 30. "DRL0,A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers" "0,1"
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abitfld.long 0x00 0.--15. "DEV_0,If bit n is one event n triggers DMA request 0 (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x60++0x03
line.long 0x00 "DMAREQ1,SCT DMA request 1 register"
bitfld.long 0x00 31. "DRQ1,This read-only bit indicates the state of DMA Request 1" "0,1"
bitfld.long 0x00 30. "DRL1,A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers" "0,1"
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abitfld.long 0x00 0.--15. "DEV_1,If bit n is one event n triggers DMA request 1 (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0xF0++0x03
line.long 0x00 "EVEN,SCT event interrupt enable register"
abitfld.long 0x00 0.--15. "IEN,The SCT requests an interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0xF4++0x03
line.long 0x00 "EVFLAG,SCT event flag register"
abitfld.long 0x00 0.--15. "FLAG,Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0xF8++0x03
line.long 0x00 "CONEN,SCT conflict interrupt enable register"
abitfld.long 0x00 0.--15. "NCEN,The SCT requests an interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0 output 1 = bit 1 etc.)" "0x0000=0: bit 0 output,0x0001=1: bit 1 etc.). The number of bits ="
group.long 0xFC++0x03
line.long 0x00 "CONFLAG,SCT conflict flag register"
bitfld.long 0x00 31. "BUSERRH,The most recent bus error from this SCT involved writing CTR H STATE H MATCH H or the Output register when the H counter was not halted" "0,1"
bitfld.long 0x00 30. "BUSERRL,The most recent bus error from this SCT involved writing CTR L/Unified STATE L/Unified MATCH L/Unified or the Output register when the L/U counter was not halted" "0,1"
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abitfld.long 0x00 0.--15. "NCFLAG,Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was last written to this bit (output 0 = bit 0 output 1 = bit 1 etc.)" "0x0000=0: bit 0 output,0x0001=1: bit 1 etc.). The number of bits ="
group.long 0x100++0x03
line.long 0x00 "CAP0,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x100++0x03
line.long 0x00 "MATCH0,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x104++0x03
line.long 0x00 "CAP1,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x104++0x03
line.long 0x00 "MATCH1,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x108++0x03
line.long 0x00 "CAP2,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x108++0x03
line.long 0x00 "MATCH2,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x10C++0x03
line.long 0x00 "CAP3,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x10C++0x03
line.long 0x00 "MATCH3,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x110++0x03
line.long 0x00 "CAP4,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x110++0x03
line.long 0x00 "MATCH4,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x114++0x03
line.long 0x00 "CAP5,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x114++0x03
line.long 0x00 "MATCH5,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x118++0x03
line.long 0x00 "CAP6,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x118++0x03
line.long 0x00 "MATCH6,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x11C++0x03
line.long 0x00 "CAP7,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x11C++0x03
line.long 0x00 "MATCH7,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x120++0x03
line.long 0x00 "CAP8,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x120++0x03
line.long 0x00 "MATCH8,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x124++0x03
line.long 0x00 "CAP9,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x124++0x03
line.long 0x00 "MATCH9,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x128++0x03
line.long 0x00 "CAP10,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x128++0x03
line.long 0x00 "MATCH10,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x12C++0x03
line.long 0x00 "CAP11,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x12C++0x03
line.long 0x00 "MATCH11,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x130++0x03
line.long 0x00 "CAP12,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x130++0x03
line.long 0x00 "MATCH12,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x134++0x03
line.long 0x00 "CAP13,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x134++0x03
line.long 0x00 "MATCH13,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x138++0x03
line.long 0x00 "CAP14,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x138++0x03
line.long 0x00 "MATCH14,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x13C++0x03
line.long 0x00 "CAP15,SCT capture register of capture channel"
hexmask.long.word 0x00 16.--31. 1. "CAPn_H,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
hexmask.long.word 0x00 0.--15. 1. "CAPn_L,When UNIFY = 0 read the 16-bit counter value at which this register was last captured"
group.long 0x13C++0x03
line.long 0x00 "MATCH15,SCT match value register of match channels"
hexmask.long.word 0x00 16.--31. 1. "MATCHn_H,When UNIFY = 0 read or write the 16-bit value to be compared to the H counter"
hexmask.long.word 0x00 0.--15. 1. "MATCHn_L,When UNIFY = 0 read or write the 16-bit value to be compared to the L counter"
group.long 0x200++0x03
line.long 0x00 "CAPCTRL0,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x200++0x03
line.long 0x00 "MATCHREL0,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x204++0x03
line.long 0x00 "CAPCTRL1,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x204++0x03
line.long 0x00 "MATCHREL1,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x208++0x03
line.long 0x00 "CAPCTRL2,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x208++0x03
line.long 0x00 "MATCHREL2,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x20C++0x03
line.long 0x00 "CAPCTRL3,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x20C++0x03
line.long 0x00 "MATCHREL3,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x210++0x03
line.long 0x00 "CAPCTRL4,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x210++0x03
line.long 0x00 "MATCHREL4,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x214++0x03
line.long 0x00 "CAPCTRL5,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x214++0x03
line.long 0x00 "MATCHREL5,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x218++0x03
line.long 0x00 "CAPCTRL6,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x218++0x03
line.long 0x00 "MATCHREL6,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x21C++0x03
line.long 0x00 "CAPCTRL7,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x21C++0x03
line.long 0x00 "MATCHREL7,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x220++0x03
line.long 0x00 "CAPCTRL8,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x220++0x03
line.long 0x00 "MATCHREL8,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x224++0x03
line.long 0x00 "CAPCTRL9,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x224++0x03
line.long 0x00 "MATCHREL9,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x228++0x03
line.long 0x00 "CAPCTRL10,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x228++0x03
line.long 0x00 "MATCHREL10,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x22C++0x03
line.long 0x00 "CAPCTRL11,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x22C++0x03
line.long 0x00 "MATCHREL11,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x230++0x03
line.long 0x00 "CAPCTRL12,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x230++0x03
line.long 0x00 "MATCHREL12,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x234++0x03
line.long 0x00 "CAPCTRL13,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x234++0x03
line.long 0x00 "MATCHREL13,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x238++0x03
line.long 0x00 "CAPCTRL14,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x238++0x03
line.long 0x00 "MATCHREL14,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
group.long 0x23C++0x03
line.long 0x00 "CAPCTRL15,SCT capture control register"
abitfld.long 0x00 16.--31. "CAPCONn_H,If bit m is one event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16 event 1 = bit 17 etc.)" "0x0000=0: bit 16 event,0x0001=1: bit 17 etc.). The number of bits ="
abitfld.long 0x00 0.--15. "CAPCONn_L,If bit m is one event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0 event 1 = bit 1 etc.)" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc.). The number of bits"
group.long 0x23C++0x03
line.long 0x00 "MATCHREL15,SCT match reload value register"
hexmask.long.word 0x00 16.--31. 1. "RELOADn_H,When UNIFY = 0 specifies the 16-bit to be loaded into the MATCHn_H register"
hexmask.long.word 0x00 0.--15. 1. "RELOADn_L,When UNIFY = 0 specifies the 16-bit value to be loaded into the MATCHn_L register"
repeat 16. (increment 0 1)(increment  0 0x08)
tree "EV[$1]"
group.long ($2+0x300)++0x03
line.long 0x00 "EV_STATE,SCT event state register 0"
abitfld.long 0x00 0.--15. "STATEMSKn,If bit m is one event n happens in state m of the counter selected by the HEVENT bit (n = event number m = state number state 0 = bit 0 state 1= bit 1 etc.)" "0x0000=0: bit 0 state,0x0001=1: bit 1 etc.). The number of bits"
group.long ($2+0x304)++0x03
line.long 0x00 "EV_CTRL,SCT event control register 0"
bitfld.long 0x00 21.--22. "DIRECTION,Direction qualifier for event generation" "0: Direction independent,1: Counting up,2: Counting down,?..."
bitfld.long 0x00 20. "MATCHMEM,If this bit is one and the COMBMODE field specifies a match component to the triggering of this event then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when.." "0,1"
newline
bitfld.long 0x00 15.--19. "STATEV,This value is loaded into or added to the state selected by HEVENT depending on STATELD when this event is the highest-numbered event occurring for that state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "STATELD,This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state" "0: STATEV value is added into STATE (the..,1: STATEV value is loaded into STATE"
newline
bitfld.long 0x00 12.--13. "COMBMODE,Selects how the specified match and I/O condition are used and combined" "0: OR,1: MATCH,2: IO,3: AND"
bitfld.long 0x00 10.--11. "IOCOND,Selects the I/O condition for event n" "0: LOW,1: RISE,2: FALL,3: HIGH"
newline
bitfld.long 0x00 6.--9. "IOSEL,Selects the input or output signal number associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. "OUTSEL,Input/output select" "0: Selects the inputs selected by IOSEL,1: Selects the outputs selected by IOSEL"
newline
bitfld.long 0x00 4. "HEVENT,Select L/H counter" "0: Selects the L state and the L match register..,1: Selects the H state and the H match register.."
bitfld.long 0x00 0.--3. "MATCHSEL,Selects the Match register associated with this event (if any)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
repeat.end
repeat 10. (increment 0 1)(increment  0 0x208)
tree "OUT[$1]"
group.long ($2+0x500)++0x03
line.long 0x00 "OUT_SET,SCT output 0 set register"
abitfld.long 0x00 0.--15. "SET,A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output" "0x0000=0: bit 0 output,0x0001=1: bit 1 etc"
group.long ($2+0x504)++0x03
line.long 0x00 "OUT_CLR,SCT output 0 clear register"
abitfld.long 0x00 0.--15. "CLR,A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event" "0x0000=0: bit 0 event,0x0001=1: bit 1 etc"
tree.end
repeat.end
tree.end
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
tree "SDIF (SDMMC)"
base ad:0x4009B000
group.long 0x00++0x03
line.long 0x00 "CTRL,Control register"
bitfld.long 0x00 25. "USE_INTERNAL_DMAC,SD/MMC DMA use" "0,1"
bitfld.long 0x00 18. "CARD_VOLTAGE_A2,Controls the state of the SD_VOLT2 pin" "0,1"
newline
bitfld.long 0x00 17. "CARD_VOLTAGE_A1,Controls the state of the SD_VOLT1 pin" "0,1"
bitfld.long 0x00 16. "CARD_VOLTAGE_A0,Controls the state of the SD_VOLT0 pin" "0,1"
newline
bitfld.long 0x00 11. "CEATA_DEVICE_INTERRUPT_STATUS,CEATA device interrupt status" "0,1"
bitfld.long 0x00 10. "SEND_AUTO_STOP_CCSD,Send auto stop ccsd" "0,1"
newline
bitfld.long 0x00 9. "SEND_CCSD,Send ccsd" "0,1"
bitfld.long 0x00 8. "ABORT_READ_DATA,Abort read data" "0,1"
newline
bitfld.long 0x00 7. "SEND_IRQ_RESPONSE,Send irq response" "0,1"
bitfld.long 0x00 6. "READ_WAIT,Read/wait" "0,1"
newline
bitfld.long 0x00 4. "INT_ENABLE,Global interrupt enable/disable bit" "0,1"
bitfld.long 0x00 2. "DMA_RESET,DMA reset" "0,1"
newline
bitfld.long 0x00 1. "FIFO_RESET,Fifo reset" "0,1"
bitfld.long 0x00 0. "CONTROLLER_RESET,Controller reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "PWREN,Power Enable register"
bitfld.long 0x00 1. "POWER_ENABLE1,Power on/off switch for card 1 once power is turned on software should wait for regulator/switch ramp-up time before trying to initialize card 1" "0,1"
bitfld.long 0x00 0. "POWER_ENABLE0,Power on/off switch for card 0 once power is turned on software should wait for regulator/switch ramp-up time before trying to initialize card 0" "0,1"
group.long 0x08++0x03
line.long 0x00 "CLKDIV,Clock Divider register"
hexmask.long.byte 0x00 0.--7. 1. "CLK_DIVIDER0,Clock divider-0 value"
group.long 0x10++0x03
line.long 0x00 "CLKENA,Clock Enable register"
bitfld.long 0x00 17. "CCLK1_LOW_POWER,Low-power control for SD card 1 clock" "0,1"
bitfld.long 0x00 16. "CCLK0_LOW_POWER,Low-power control for SD card 0 clock" "0,1"
newline
bitfld.long 0x00 1. "CCLK1_ENABLE,Clock-enable control for SD card 1 clock" "0,1"
bitfld.long 0x00 0. "CCLK0_ENABLE,Clock-enable control for SD card 0 clock" "0,1"
group.long 0x14++0x03
line.long 0x00 "TMOUT,Time-out register"
hexmask.long.tbyte 0x00 8.--31. 1. "DATA_TIMEOUT,Value for card Data Read time-out same value also used for Data Starvation by Host time-out"
hexmask.long.byte 0x00 0.--7. 1. "RESPONSE_TIMEOUT,Response time-out value"
group.long 0x18++0x03
line.long 0x00 "CTYPE,Card Type register"
bitfld.long 0x00 17. "CARD1_WIDTH1,Indicates if card 1 is 8-bit" "0,1"
bitfld.long 0x00 16. "CARD0_WIDTH1,Indicates if card 0 is 8-bit" "0,1"
newline
bitfld.long 0x00 1. "CARD1_WIDTH0,Indicates if card 1 is 1-bit or 4-bit" "0,1"
bitfld.long 0x00 0. "CARD0_WIDTH0,Indicates if card 0 is 1-bit or 4-bit" "0,1"
group.long 0x1C++0x03
line.long 0x00 "BLKSIZ,Block Size register"
hexmask.long.word 0x00 0.--15. 1. "BLOCK_SIZE,Block size"
group.long 0x20++0x03
line.long 0x00 "BYTCNT,Byte Count register"
hexmask.long 0x00 0.--31. 1. "BYTE_COUNT,Number of bytes to be transferred should be integer multiple of Block Size for block transfers"
group.long 0x24++0x03
line.long 0x00 "INTMASK,Interrupt Mask register"
bitfld.long 0x00 16. "SDIO_INT_MASK,Mask SDIO interrupt" "0,1"
bitfld.long 0x00 15. "EBE,End-bit error (read)/Write no CRC" "0,1"
newline
bitfld.long 0x00 14. "ACD,Auto command done" "0,1"
bitfld.long 0x00 13. "SBE,Start-bit error" "0,1"
newline
bitfld.long 0x00 12. "HLE,Hardware locked write error" "0,1"
bitfld.long 0x00 11. "FRUN,FIFO underrun/overrun error" "0,1"
newline
bitfld.long 0x00 10. "HTO,Data starvation-by-host time-out (HTO)" "0,1"
bitfld.long 0x00 9. "DRTO,Data read time-out" "0,1"
newline
bitfld.long 0x00 8. "RTO,Response time-out" "0,1"
bitfld.long 0x00 7. "DCRC,Data CRC error" "0,1"
newline
bitfld.long 0x00 6. "RCRC,Response CRC error" "0,1"
bitfld.long 0x00 5. "RXDR,Receive FIFO data request" "0,1"
newline
bitfld.long 0x00 4. "TXDR,Transmit FIFO data request" "0,1"
bitfld.long 0x00 3. "DTO,Data transfer over" "0,1"
newline
bitfld.long 0x00 2. "CDONE,Command done" "0,1"
bitfld.long 0x00 1. "RE,Response error" "0,1"
newline
bitfld.long 0x00 0. "CDET,Card detect" "0,1"
group.long 0x28++0x03
line.long 0x00 "CMDARG,Command Argument register"
hexmask.long 0x00 0.--31. 1. "CMD_ARG,Value indicates command argument to be passed to card"
group.long 0x2C++0x03
line.long 0x00 "CMD,Command register"
bitfld.long 0x00 31. "START_CMD,Start command" "0,1"
bitfld.long 0x00 29. "USE_HOLD_REG,Use Hold Register" "0,1"
newline
bitfld.long 0x00 28. "VOLT_SWITCH,Voltage switch bit" "0,1"
bitfld.long 0x00 27. "BOOT_MODE,Boot Mode" "0,1"
newline
bitfld.long 0x00 26. "DISABLE_BOOT,Disable Boot" "0,1"
bitfld.long 0x00 25. "EXPECT_BOOT_ACK,Expect Boot Acknowledge" "0,1"
newline
bitfld.long 0x00 24. "ENABLE_BOOT,Enable Boot - this bit should be set only for mandatory boot mode" "0,1"
bitfld.long 0x00 23. "CCS_EXPECTED,CCS expected" "0,1"
newline
bitfld.long 0x00 22. "READ_CEATA_DEVICE,Read ceata device" "0,1"
bitfld.long 0x00 21. "UPDATE_CLOCK_REGISTERS_ONLY,Update clock registers only" "0,1"
newline
bitfld.long 0x00 16.--20. "CARD_NUMBER,Specifies the card number of SDCARD for which the current Command is being executed" "0: Command will be execute on SDCARD 0,1: Command will be execute on SDCARD 1,?..."
bitfld.long 0x00 15. "SEND_INITIALIZATION,Send initialization" "0,1"
newline
bitfld.long 0x00 14. "STOP_ABORT_CMD,Stop abort command" "0,1"
bitfld.long 0x00 13. "WAIT_PRVDATA_COMPLETE,Wait prvdata complete" "0,1"
newline
bitfld.long 0x00 12. "SEND_AUTO_STOP,Send auto stop" "0,1"
bitfld.long 0x00 11. "TRANSFER_MODE,Transfer mode" "0,1"
newline
bitfld.long 0x00 10. "READ_WRITE,read/" "0,1"
bitfld.long 0x00 9. "DATA_EXPECTED,Data expected" "0,1"
newline
bitfld.long 0x00 8. "CHECK_RESPONSE_CRC,Check response CRC" "0,1"
bitfld.long 0x00 7. "RESPONSE_LENGTH,Response length" "0,1"
newline
bitfld.long 0x00 6. "RESPONSE_EXPECT,Response expect" "0,1"
bitfld.long 0x00 0.--5. "CMD_INDEX,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (increment 0 1) (increment 0 0x4)
group.long ($2+0x30)++0x03
line.long 0x00 "RESP[$1],Response register $1"
hexmask.long 0x00 0.--31. 1. "RESPONSE,Bits of response"
repeat.end
group.long 0x40++0x03
line.long 0x00 "MINTSTS,Masked Interrupt Status register"
bitfld.long 0x00 16. "SDIO_INTERRUPT,Interrupt from SDIO card" "0,1"
bitfld.long 0x00 15. "EBE,End-bit error (read)/write no CRC" "0,1"
newline
bitfld.long 0x00 14. "ACD,Auto command done" "0,1"
bitfld.long 0x00 13. "SBE,Start-bit error" "0,1"
newline
bitfld.long 0x00 12. "HLE,Hardware locked write error" "0,1"
bitfld.long 0x00 11. "FRUN,FIFO underrun/overrun error" "0,1"
newline
bitfld.long 0x00 10. "HTO,Data starvation-by-host time-out (HTO)" "0,1"
bitfld.long 0x00 9. "DRTO,Data read time-out" "0,1"
newline
bitfld.long 0x00 8. "RTO,Response time-out" "0,1"
bitfld.long 0x00 7. "DCRC,Data CRC error" "0,1"
newline
bitfld.long 0x00 6. "RCRC,Response CRC error" "0,1"
bitfld.long 0x00 5. "RXDR,Receive FIFO data request" "0,1"
newline
bitfld.long 0x00 4. "TXDR,Transmit FIFO data request" "0,1"
bitfld.long 0x00 3. "DTO,Data transfer over" "0,1"
newline
bitfld.long 0x00 2. "CDONE,Command done" "0,1"
bitfld.long 0x00 1. "RE,Response error" "0,1"
newline
bitfld.long 0x00 0. "CDET,Card detect" "0,1"
group.long 0x44++0x03
line.long 0x00 "RINTSTS,Raw Interrupt Status register"
bitfld.long 0x00 16. "SDIO_INTERRUPT,Interrupt from SDIO card" "0,1"
bitfld.long 0x00 15. "EBE,End-bit error (read)/write no CRC" "0,1"
newline
bitfld.long 0x00 14. "ACD,Auto command done" "0,1"
bitfld.long 0x00 13. "SBE,Start-bit error" "0,1"
newline
bitfld.long 0x00 12. "HLE,Hardware locked write error" "0,1"
bitfld.long 0x00 11. "FRUN,FIFO underrun/overrun error" "0,1"
newline
bitfld.long 0x00 10. "HTO,Data starvation-by-host time-out (HTO)" "0,1"
bitfld.long 0x00 9. "DRTO_BDS,Data read time-out (DRTO)/Boot Data Start (BDS)" "0,1"
newline
bitfld.long 0x00 8. "RTO_BAR,Response time-out (RTO)/Boot Ack Received (BAR)" "0,1"
bitfld.long 0x00 7. "DCRC,Data CRC error" "0,1"
newline
bitfld.long 0x00 6. "RCRC,Response CRC error" "0,1"
bitfld.long 0x00 5. "RXDR,Receive FIFO data request" "0,1"
newline
bitfld.long 0x00 4. "TXDR,Transmit FIFO data request" "0,1"
bitfld.long 0x00 3. "DTO,Data transfer over" "0,1"
newline
bitfld.long 0x00 2. "CDONE,Command done" "0,1"
bitfld.long 0x00 1. "RE,Response error" "0,1"
newline
bitfld.long 0x00 0. "CDET,Card detect" "0,1"
group.long 0x48++0x03
line.long 0x00 "STATUS,Status register"
bitfld.long 0x00 31. "DMA_REQ,DMA request signal state" "0,1"
bitfld.long 0x00 30. "DMA_ACK,DMA acknowledge signal state" "0,1"
newline
hexmask.long.word 0x00 17.--29. 1. "FIFO_COUNT,FIFO count - Number of filled locations in FIFO"
bitfld.long 0x00 11.--16. "RESPONSE_INDEX,Index of previous response including any auto-stop sent by core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 10. "DATA_STATE_MC_BUSY,Data transmit or receive state-machine is busy" "0,1"
bitfld.long 0x00 9. "DATA_BUSY,Inverted version of raw selected card_data[0]" "0: card data not busy,1: card data busy"
newline
bitfld.long 0x00 8. "DATA_3_STATUS,Raw selected card_data[3] checks whether card is present" "0: card not present,1: card present"
bitfld.long 0x00 4.--7. "CMDFSMSTATES,Command FSM states" "0: Idle,1: Send init sequence,2: Tx cmd start bit,3: Tx cmd tx bit,4: Tx cmd index + arg,5: Tx cmd crc7,6: Tx cmd end bit,7: Rx resp start bit,8: Rx resp IRQ response,9: Rx resp tx bit,10: Rx resp cmd idx,11: Rx resp data,12: Rx resp crc7,13: Rx resp end bit,14: Cmd path wait NCC,15: Wait CMD-to-response turnaround"
newline
bitfld.long 0x00 3. "FIFO_FULL,FIFO is full status" "0,1"
bitfld.long 0x00 2. "FIFO_EMPTY,FIFO is empty status" "0,1"
newline
bitfld.long 0x00 1. "FIFO_TX_WATERMARK,FIFO reached Transmit watermark level not qualified with data transfer" "0,1"
bitfld.long 0x00 0. "FIFO_RX_WATERMARK,FIFO reached Receive watermark level not qualified with data transfer" "0,1"
group.long 0x4C++0x03
line.long 0x00 "FIFOTH,FIFO Threshold Watermark register"
bitfld.long 0x00 28.--30. "DMA_MTS,Burst size of multiple transaction should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--27. 1. "RX_WMARK,FIFO threshold watermark level when receiving data to card"
newline
hexmask.long.word 0x00 0.--11. 1. "TX_WMARK,FIFO threshold watermark level when transmitting data to card"
group.long 0x50++0x03
line.long 0x00 "CDETECT,Card Detect register"
bitfld.long 0x00 1. "CARD1_DETECT,Card 1 detect" "0,1"
bitfld.long 0x00 0. "CARD0_DETECT,Card 0 detect" "0,1"
group.long 0x54++0x03
line.long 0x00 "WRTPRT,Write Protect register"
bitfld.long 0x00 0. "WRITE_PROTECT,Write protect" "0,1"
group.long 0x5C++0x03
line.long 0x00 "TCBCNT,Transferred CIU Card Byte Count register"
hexmask.long 0x00 0.--31. 1. "TRANS_CARD_BYTE_COUNT,Number of bytes transferred by CIU unit to card"
group.long 0x60++0x03
line.long 0x00 "TBBCNT,Transferred Host to BIU-FIFO Byte Count register"
hexmask.long 0x00 0.--31. 1. "TRANS_FIFO_BYTE_COUNT,Number of bytes transferred between Host/DMA memory and BIU FIFO"
group.long 0x64++0x03
line.long 0x00 "DEBNCE,Debounce Count register"
hexmask.long.tbyte 0x00 0.--23. 1. "DEBOUNCE_COUNT,Number of host clocks (SD_CLK) used by debounce filter logic for card detect typical debounce time is 5-25 ms"
group.long 0x78++0x03
line.long 0x00 "RST_N,Hardware Reset"
bitfld.long 0x00 0. "CARD_RESET,Hardware reset" "0,1"
group.long 0x80++0x03
line.long 0x00 "BMOD,Bus Mode register"
bitfld.long 0x00 8.--10. "PBL,Programmable Burst Length" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "DE,SD/MMC DMA Enable" "0,1"
newline
bitfld.long 0x00 2.--6. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1. "FB,Fixed Burst" "0,1"
newline
bitfld.long 0x00 0. "SWR,Software Reset" "0,1"
group.long 0x84++0x03
line.long 0x00 "PLDMND,Poll Demand register"
hexmask.long 0x00 0.--31. 1. "PD,Poll Demand"
group.long 0x88++0x03
line.long 0x00 "DBADDR,Descriptor List Base Address register"
hexmask.long 0x00 0.--31. 1. "SDL,Start of Descriptor List"
group.long 0x8C++0x03
line.long 0x00 "IDSTS,Internal DMAC Status register"
bitfld.long 0x00 13.--16. "FSM,DMAC state machine present state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--12. "EB,Error Bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9. "AIS,Abnormal Interrupt Summary" "0,1"
bitfld.long 0x00 8. "NIS,Normal Interrupt Summary" "0,1"
newline
bitfld.long 0x00 5. "CES,Card Error Summary" "0,1"
bitfld.long 0x00 4. "DU,Descriptor Unavailable Interrupt" "0,1"
newline
bitfld.long 0x00 2. "FBE,Fatal Bus Error Interrupt" "0,1"
bitfld.long 0x00 1. "RI,Receive Interrupt" "0,1"
newline
bitfld.long 0x00 0. "TI,Transmit Interrupt" "0,1"
group.long 0x90++0x03
line.long 0x00 "IDINTEN,Internal DMAC Interrupt Enable register"
bitfld.long 0x00 9. "AIS,Abnormal Interrupt Summary Enable" "0,1"
bitfld.long 0x00 8. "NIS,Normal Interrupt Summary Enable" "0,1"
newline
bitfld.long 0x00 5. "CES,Card Error summary Interrupt Enable" "0,1"
bitfld.long 0x00 4. "DU,Descriptor Unavailable Interrupt" "0,1"
newline
bitfld.long 0x00 2. "FBE,Fatal Bus Error Enable" "0,1"
bitfld.long 0x00 1. "RI,Receive Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "TI,Transmit Interrupt Enable" "0,1"
group.long 0x94++0x03
line.long 0x00 "DSCADDR,Current Host Descriptor Address register"
hexmask.long 0x00 0.--31. 1. "HDA,Host Descriptor Address Pointer"
group.long 0x98++0x03
line.long 0x00 "BUFADDR,Current Buffer Descriptor Address register"
hexmask.long 0x00 0.--31. 1. "HBA,Host Buffer Address Pointer"
group.long 0x100++0x03
line.long 0x00 "CARDTHRCTL,Card Threshold Control"
hexmask.long.byte 0x00 16.--23. 1. "CARDTHRESHOLD,Card Threshold size"
bitfld.long 0x00 1. "BSYCLRINTEN,Busy Clear Interrupt Enable" "0,1"
newline
bitfld.long 0x00 0. "CARDRDTHREN,Card Read Threshold Enable" "0,1"
group.long 0x104++0x03
line.long 0x00 "BACKENDPWR,Power control"
bitfld.long 0x00 0. "BACKENDPWR,Back-end Power control for card application" "0,1"
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "FIFO[$1],SDIF FIFO $1"
hexmask.long 0x00 0.--31. 1. "DATA,SDIF FIFO"
repeat.end
tree.end
endif
tree "SPI (Serial Peripheral Interfaces)"
repeat 2. (list 0. 1.) (list ad:0x40086000 ad:0x40087000)
tree "SPI$1"
base $2
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High"
bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High"
bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture"
bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse"
newline
bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode"
bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16"
bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
newline
bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1"
bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1"
newline
rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled"
wgroup.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
newline
bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.."
bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1"
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1"
newline
rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15"
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
newline
bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
newline
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
newline
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
newline
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
newline
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
newline
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
newline
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
newline
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
tree.end
repeat.end
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
tree "SPI2"
base ad:0x40088000
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High"
bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High"
bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture"
bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse"
newline
bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode"
bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16"
bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
newline
bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1"
bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1"
newline
rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled"
wgroup.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
newline
bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.."
bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1"
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1"
newline
rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15"
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
newline
bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
newline
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
newline
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
newline
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
newline
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
newline
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
newline
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
newline
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
tree.end
endif
repeat 2. (list 3. 4.) (list ad:0x40089000 ad:0x4008A000)
tree "SPI$1"
base $2
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High"
bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High"
bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture"
bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse"
newline
bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode"
bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16"
bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
newline
bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1"
bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1"
newline
rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled"
wgroup.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
newline
bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.."
bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1"
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1"
newline
rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15"
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
newline
bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
newline
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
newline
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
newline
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
newline
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
newline
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
newline
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
newline
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
tree.end
repeat.end
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
tree "SPI5"
base ad:0x40096000
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High"
bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High"
bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture"
bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse"
newline
bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode"
bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16"
bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
newline
bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1"
bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1"
newline
rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled"
wgroup.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
newline
bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.."
bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1"
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1"
newline
rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15"
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
newline
bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
newline
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
newline
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
newline
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
newline
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
newline
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
newline
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
newline
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
tree.end
endif
repeat 3. (list 6. 7. 8.) (list ad:0x40097000 ad:0x40098000 ad:0x4009F000)
tree "SPI$1"
base $2
group.long 0x400++0x03
line.long 0x00 "CFG,SPI Configuration register"
bitfld.long 0x00 11. "SPOL3,SSEL3 Polarity select" "0: Low,1: High"
bitfld.long 0x00 10. "SPOL2,SSEL2 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 9. "SPOL1,SSEL1 Polarity select" "0: Low,1: High"
bitfld.long 0x00 8. "SPOL0,SSEL0 Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 7. "LOOP,Loopback mode enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 5. "CPOL,Clock Polarity select" "0: Low,1: High"
newline
bitfld.long 0x00 4. "CPHA,Clock Phase select" "0: Change,1: Capture"
bitfld.long 0x00 3. "LSBF,LSB First mode enable" "0: Standard,1: Reverse"
newline
bitfld.long 0x00 2. "MASTER,Master mode select" "0: Slave mode,1: Master mode"
bitfld.long 0x00 0. "ENABLE,SPI enable" "0: Disabled,1: Enabled"
group.long 0x404++0x03
line.long 0x00 "DLY,SPI Delay register"
bitfld.long 0x00 12.--15. "TRANSFER_DELAY,Controls the minimum amount of time that the SSEL is deasserted between transfers" "0: The minimum time that SSEL is deasserted is 1,1: The minimum time that SSEL is deasserted is 2,2: The minimum time that SSEL is deasserted is 3,?,?,?,?,?,?,?,?,?,?,?,?,15: The minimum time that SSEL is deasserted is 16"
bitfld.long 0x00 8.--11. "FRAME_DELAY,If the EOF flag is set controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT)" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
newline
bitfld.long 0x00 4.--7. "POST_DELAY,Controls the amount of time between the end of a data transfer and SSEL deassertion" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
bitfld.long 0x00 0.--3. "PRE_DELAY,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "0: No additional time is inserted,1: 1 SPI clock time is inserted,2: 2 SPI clock times are inserted,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 SPI clock times are inserted"
group.long 0x408++0x03
line.long 0x00 "STAT,SPI Status"
rbitfld.long 0x00 8. "MSTIDLE,Master idle status flag" "0,1"
bitfld.long 0x00 7. "ENDTRANSFER,End Transfer control bit" "0,1"
newline
rbitfld.long 0x00 6. "STALLED,Stalled status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0x40C++0x03
line.long 0x00 "INTENSET,SPI Interrupt Enable read and Set"
bitfld.long 0x00 8. "MSTIDLEEN,Master idle interrupt enable" "0: No interrupt will be generated when the SPI..,1: An interrupt will be generated when the SPI.."
bitfld.long 0x00 5. "SSDEN,Slave select deassert interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 4. "SSAEN,Slave select assert interrupt enable" "0: Disabled,1: Enabled"
wgroup.long 0x410++0x03
line.long 0x00 "INTENCLR,SPI Interrupt Enable Clear"
bitfld.long 0x00 8. "MSTIDLE,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 5. "SSDEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 4. "SSAEN,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x424++0x03
line.long 0x00 "DIV,SPI clock Divider"
hexmask.long.word 0x00 0.--15. 1. "DIVVAL,Rate divider value"
rgroup.long 0x428++0x03
line.long 0x00 "INTSTAT,SPI Interrupt Status"
bitfld.long 0x00 8. "MSTIDLE,Master Idle status flag" "0,1"
bitfld.long 0x00 5. "SSD,Slave Select Deassert" "0,1"
newline
bitfld.long 0x00 4. "SSA,Slave Select Assert" "0,1"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
newline
bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.."
bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1"
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1"
newline
rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15"
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
newline
bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 23. "TXIGNORE,Transmit Ignore" "0: Write transmit data,1: Ignore transmit data"
newline
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
newline
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
newline
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
newline
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
bitfld.long 0x00 24.--27. "LEN,Data Length" "?,?,?,3: Data transfer is 4 bits in length,4: Data transfer is 5 bits in length,?,?,?,?,?,?,?,?,?,?,15: Data transfer is 16 bits in length"
bitfld.long 0x00 22. "RXIGNORE,Receive Ignore" "0: Read received data,1: Ignore received data"
newline
bitfld.long 0x00 21. "EOF,End of frame" "0: Data not EOF,1: Data EOF"
bitfld.long 0x00 20. "EOT,End of transfer" "0: SSEL not deasserted,1: SSEL deasserted"
newline
bitfld.long 0x00 19. "TXSSEL3_N,Transmit slave select" "0: SSEL3 asserted,1: SSEL3 not asserted"
bitfld.long 0x00 18. "TXSSEL2_N,Transmit slave select" "0: SSEL2 asserted,1: SSEL2 not asserted"
newline
bitfld.long 0x00 17. "TXSSEL1_N,Transmit slave select" "0: SSEL1 asserted,1: SSEL1 not asserted"
bitfld.long 0x00 16. "TXSSEL0_N,Transmit slave select" "0: SSEL0 asserted,1: SSEL0 not asserted"
newline
hexmask.long.word 0x00 0.--15. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 20. "SOT,Start of Transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 20. "SOT,Start of transfer flag" "0,1"
bitfld.long 0x00 19. "RXSSEL3_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 18. "RXSSEL2_N,Slave Select for receive" "0,1"
bitfld.long 0x00 17. "RXSSEL1_N,Slave Select for receive" "0,1"
newline
bitfld.long 0x00 16. "RXSSEL0_N,Slave Select for receive" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RXDATA,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
tree.end
repeat.end
tree.end
tree "SYSCON"
base ad:0x40000000
group.long 0x00++0x03
line.long 0x00 "MEMORYREMAP,Memory Remap control register"
bitfld.long 0x00 0.--1. "MAP,Select the location of the vector table" "0: Vector Table in ROM,1: Vector Table in RAM,2: Vector Table in Flash,3: Vector Table in Flash"
group.long 0x10++0x03
line.long 0x00 "AHBMATPRIO,AHB Matrix priority control register Priority values are"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 24.--25. "PRI_SDMA1,DMA1 controller priority" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "PRI_USB_HS,USB-HS.(USB1)" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "PRI_HASH_AES,HASH_AES" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "PRI_PQ,PQ (HW Accelerator)" "0,1,2,3"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 18.--19. "PRI_CANFD,CANFD" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "PRI_HASH_AES,HASH_AES" "0,1,2,3"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 16.--17. "PRI_SDIO,SDIO" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "PRI_SDMA0,DMA0 controller priority" "0,1,2,3"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 10.--11. "PRI_USB_FSH,USB0-FS host.(USB0)" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "PRI_USB_FSD,USB0-FS Device.(USB0)" "0,1,2,3"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 8.--9. "PRI_USB_FS,USB-FS.(USB0)" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "PRI_CPU1_SBUS,CPU1 S-AHB bus" "0,1,2,3"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 6.--7. "PRI_SDMA1,DMA1 controller priority" "0,1,2,3"
newline
bitfld.long 0x00 4.--5. "PRI_SDMA0,DMA0 controller priority" "0,1,2,3"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 4.--5. "PRI_CPU1_CBUS,CPU1 C-AHB bus" "0,1,2,3"
newline
endif
bitfld.long 0x00 2.--3. "PRI_CPU0_SBUS,CPU0 S-AHB bus" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "PRI_CPU0_CBUS,CPU0 C-AHB bus" "0,1,2,3"
group.long 0x38++0x03
line.long 0x00 "CPU0STCKCAL,System tick calibration for secure part of CPU0"
bitfld.long 0x00 25. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: reference clock provided,1: no reference clock provided"
newline
bitfld.long 0x00 24. "SKEW,Initial value for the Systick timer" "0,1"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value for 10ms (100Hz) timing subject to system clock skew errors"
group.long 0x3C++0x03
line.long 0x00 "CPU0NSTCKCAL,System tick calibration for non-secure part of CPU0"
bitfld.long 0x00 25. "NOREF,Initial value for the Systick timer" "0,1"
newline
bitfld.long 0x00 24. "SKEW,Indicates whether the TENMS value is exact" "0: TENMS value is exact,1: TENMS value is inexact or not given"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value for 10 ms (100 Hz) timing subject to system clock skew errors"
group.long 0x40++0x03
line.long 0x00 "CPU1STCKCAL,System tick calibration for CPU1"
bitfld.long 0x00 25. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: reference clock provided,1: no reference clock provided"
newline
bitfld.long 0x00 24. "SKEW,Indicates whether the TENMS value is exact" "0: TENMS value is exact,1: TENMS value is inexact or not given"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value for 10ms (100Hz) timing subject to system clock skew errors"
group.long 0x48++0x03
line.long 0x00 "NMISRC,NMI Source Select"
bitfld.long 0x00 31. "NMIENCPU0,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0" "0,1"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 30. "NMIENCPU1,Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1" "0,1"
newline
bitfld.long 0x00 8.--13. "IRQCPU1,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1 if enabled by NMIENCPU1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
endif
bitfld.long 0x00 0.--5. "IRQCPU0,The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0 if enabled by NMIENCPU0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x100++0x03
line.long 0x00 "PRESETCTRL0,Peripheral reset control 0"
bitfld.long 0x00 27. "ADC_RST,ADC reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 26. "MAILBOX_RST,Inter CPU communication Mailbox reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 23. "RTC_RST,Real Time Clock (RTC) reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 22. "WWDT_RST,Watchdog Timer reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 21. "CRCGEN_RST,CRCGEN reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 20. "DMA0_RST,DMA0 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 19. "GINT_RST,Group interrupt (GINT) reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 18. "PINT_RST,Pin interrupt (PINT) reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 17. "GPIO3_RST,GPIO3 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 16. "GPIO2_RST,GPIO2 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 15. "GPIO1_RST,GPIO1 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 14. "GPIO0_RST,GPIO0 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 13. "IOCON_RST,I/O controller reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 11. "MUX_RST,Input Mux reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 8. "FMC_RST,FMC controller reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 7. "FLASH_RST,Flash controller reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6. "SRAM_CTRL4_RST,SRAM Controller 4 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 5. "SRAM_CTRL3_RST,SRAM Controller 3 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 4. "SRAM_CTRL2_RST,SRAM Controller 2 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 3. "SRAM_CTRL1_RST,SRAM Controller 1 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 1. "ROM_RST,ROM reset control" "0: Bloc is not reset,1: Bloc is reset"
group.long 0x100++0x03
line.long 0x00 "PRESETCTRLX0,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x104++0x03
line.long 0x00 "PRESETCTRL1,Peripheral reset control 1"
bitfld.long 0x00 27. "TIMER1_RST,Timer 1 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 26. "TIMER0_RST,Timer 0 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 25. "USB0_DEV_RST,USB0-FS DEV reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 25. "USB0_DEV_RST,USB0 DEV reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 22. "TIMER2_RST,Timer 2 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 18. "FC7_RST,FC7 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 17. "FC6_RST,FC6 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 16. "FC5_RST,FC5 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 15. "FC4_RST,FC4 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 14. "FC3_RST,FC3 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 13. "FC2_RST,FC2 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 12. "FC1_RST,FC1 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 11. "FC0_RST,FC0 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 10. "UTICK_RST,UTICK reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 7. "CAN_RST,CAN reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6. "SCTIPU_RST,SCTIPU reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 2. "SCT_RST,SCT reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 1. "OSTIMER_RST,OS Event Timer reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 0. "MRT_RST,MRT reset control" "0: Bloc is not reset,1: Bloc is reset"
group.long 0x104++0x03
line.long 0x00 "PRESETCTRLX1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x108++0x03
line.long 0x00 "PRESETCTRL2,Peripheral reset control 2"
bitfld.long 0x00 30. "GPIO_SEC_INT_RST,GPIO secure int reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 29. "GPIO_SEC_RST,GPIO secure reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 28. "HS_LSPI_RST,HS LSPI reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 27. "ANALOG_CTRL_RST,analog control reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 24. "CASPER_RST,Casper reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 23. "PUF_RST,PUF reset control reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 22. "TIMER4_RST,Timer 4 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 21. "TIMER3_RST,Timer 3 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 20. "PLULUT_RST,PLU LUT reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 19. "PQ_RST,Power Quad reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 18. "HASH_AES_RST,HASH_AES reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 17. "USB0_HOSTS_RST,USB0 Host Slave reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 17. "USB0_HOSTS_RST,USB0-FS Host Slave reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 16. "USB0_HOSTM_RST,USB0-FS Host Master reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 16. "USB0_HOSTM_RST,USB0 Host Master reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 15. "SYSCTL_RST,SYSCTL Block reset" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 13. "RNG_RST,RNG reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 11. "CDOG_RST,Code Watchdog reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 8. "FREQME_RST,Frequency meter reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 7. "USB1_PHY_RST,USB1 PHY reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 7. "USB1_PHY_RST,USB1-HS PHY reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6. "USB1_RAM_RST,USB1 RAM reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 6. "SRAM_CTRL3_RST,SRAM Controller 3 reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 6. "USB1_RAM_RST,USB1-HS RAM reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 5. "USB1_DEV_RST,USB1 dev reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 5. "USB1_DEV_RST,USB1-HS dev reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 4. "USB1_HOST_RST,USB1-HS Host reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 4. "USB1_HOST_RST,USB1 Host reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 3. "SDIO_RST,SDIO reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
endif
bitfld.long 0x00 2. "COMP_RST,Comparator reset control" "0: Bloc is not reset,1: Bloc is reset"
newline
bitfld.long 0x00 1. "DMA1_RST,DMA1 reset control" "0: Bloc is not reset,1: Bloc is reset"
group.long 0x108++0x03
line.long 0x00 "PRESETCTRLX2,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat 3. (increment 0 1) (increment 0 0x04)
group.long ($2+0x120)++0x03
line.long 0x00 "PRESETCTRLSET[$1],Peripheral reset control set register $1"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
repeat 3. (increment 0 1) (increment 0 0x04)
group.long ($2+0x140)++0x03
line.long 0x00 "PRESETCTRLCLR[$1],Peripheral reset control clear register $1"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
wgroup.long 0x160++0x03
line.long 0x00 "SWR_RESET,generate a software_reset"
hexmask.long 0x00 0.--31. 1. "SWR_RESET,Write 0x5A00_0001 to generate a software_reset"
group.long 0x200++0x03
line.long 0x00 "AHBCLKCTRL0,AHB Clock control 0"
bitfld.long 0x00 27. "ADC,Enables the clock for the ADC" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 26. "MAILBOX,Enables the clock for the Inter CPU communication Mailbox" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 23. "RTC,Enables the clock for the Real Time Clock (RTC)" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 22. "WWDT,Enables the clock for the Watchdog Timer" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 21. "CRCGEN,Enables the clock for the CRCGEN" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 20. "DMA0,Enables the clock for the DMA0" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 19. "GINT,Enables the clock for the Group interrupt (GINT)" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 18. "PINT,Enables the clock for the Pin interrupt (PINT)" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 17. "GPIO3,Enables the clock for the GPIO3" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 16. "GPIO2,Enables the clock for the GPIO2" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 15. "GPIO1,Enables the clock for the GPIO1" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 14. "GPIO0,Enables the clock for the GPIO0" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 13. "IOCON,Enables the clock for the I/O controller" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 11. "MUX,Enables the clock for the Input Mux" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 8. "FMC,Enables the clock for the FMC controller" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 7. "FLASH,Enables the clock for the Flash controller" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6. "SRAM_CTRL4,Enables the clock for the SRAM Controller 4" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 5. "SRAM_CTRL3,Enables the clock for the SRAM Controller 3" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 4. "SRAM_CTRL2,Enables the clock for the SRAM Controller 2" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 3. "SRAM_CTRL1,Enables the clock for the SRAM Controller 1" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 1. "ROM,Enables the clock for the ROM" "0: Disable Clock,1: Enable Clock"
group.long 0x200++0x03
line.long 0x00 "AHBCLKCTRLX0,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x204++0x03
line.long 0x00 "AHBCLKCTRL1,AHB Clock control 1"
bitfld.long 0x00 27. "TIMER1,Enables the clock for the Timer 1" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 26. "TIMER0,Enables the clock for the Timer 0" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 25. "USB0_DEV,Enables the clock for the USB0 DEV" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 25. "USB0_DEV,Enables the clock for the USB0-FS device" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 22. "TIMER2,Enables the clock for the Timer 2" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 18. "FC7,Enables the clock for the FC7" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 17. "FC6,Enables the clock for the FC6" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 16. "FC5,Enables the clock for the FC5" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 15. "FC4,Enables the clock for the FC4" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 14. "FC3,Enables the clock for the FC3" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 13. "FC2,Enables the clock for the FC2" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 12. "FC1,Enables the clock for the FC1" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 11. "FC0,Enables the clock for the FC0" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 10. "UTICK,Enables the clock for the UTICK" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 7. "CAN,Enables the clock for the CAN" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 2. "SCT,Enables the clock for the SCT" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 1. "OSTIMER,Enables the clock for the OS Event Timer" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 0. "MRT,Enables the clock for the MRT" "0: Disable Clock,1: Enable Clock"
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
group.long ($2+0x204)++0x03
line.long 0x00 "AHBCLKCTRLX$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x208++0x03
line.long 0x00 "AHBCLKCTRL2,AHB Clock control 2"
bitfld.long 0x00 30. "GPIO_SEC_INT,Enables the clock for the GPIO secure int" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 29. "GPIO_SEC,Enables the clock for the GPIO secure" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 28. "HS_LSPI,Enables the clock for the HS LSPI" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 27. "ANALOG_CTRL,Enables the clock for the analog control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 24. "CASPER,Enables the clock for the Casper" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 23. "PUF,Enables the clock for the PUF reset control" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 22. "TIMER4,Enables the clock for the Timer 4" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 21. "TIMER3,Enables the clock for the Timer 3" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 20. "PLULUT,Enables the clock for the PLU LUT" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 19. "PQ,Enables the clock for the Power Quad" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 18. "HASH_AES,Enables the clock for the HASH_AES" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 17. "USB0_HOSTS,Enables the clock for the USB0 Host Slave" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 17. "USB0_HOSTS,Enables the clock for the USB0-FS Host Slave" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 16. "USB0_HOSTM,Enables the clock for the USB0-FS Host Master" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 16. "USB0_HOSTM,Enables the clock for the USB0 Host Master" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 15. "SYSCTL,SYSCTL block clock" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 13. "RNG,Enables the clock for the RNG" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 11. "CDOG,Enables the clock for the code watchdog" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 8. "FREQME,Enables the clock for the Frequency meter" "0: Disable Clock,1: Enable Clock"
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 7. "USB1_PHY,Enables the clock for the USB1-HS PHY" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 7. "USB1_PHY,Enables the clock for the USB1 PHY" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
bitfld.long 0x00 6. "SRAM_CTRL3,Enables the clock for the SRAM Controller 3" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 6. "USB1_RAM,Enables the clock for the USB1-HS RAM" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6. "USB1_RAM,Enables the clock for the USB1 RAM" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 5. "USB1_DEV,Enables the clock for the USB1 dev" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 5. "USB1_DEV,Enables the clock for the USB1-HS device" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 4. "USB1_HOST,Enables the clock for the USB1-HS Host" "0: Disable Clock,1: Enable Clock"
newline
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 4. "USB1_HOST,Enables the clock for the USB1 Host" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 3. "SDIO,Enables the clock for the SDIO" "0: Disable Clock,1: Enable Clock"
newline
endif
bitfld.long 0x00 2. "COMP,Enables the clock for the Comparator" "0: Disable Clock,1: Enable Clock"
newline
bitfld.long 0x00 1. "DMA1,Enables the clock for the DMA1" "0: Disable Clock,1: Enable Clock"
repeat 3. (increment 0 1) (increment 0 0x04)
group.long ($2+0x220)++0x03
line.long 0x00 "AHBCLKCTRLSET[$1],Peripheral reset control register $1"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
repeat 3. (increment 0 1) (increment 0 0x04)
group.long ($2+0x240)++0x03
line.long 0x00 "AHBCLKCTRLCLR[$1],Peripheral reset control register $1"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x260++0x03
line.long 0x00 "SYSTICKCLKSELX0,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x260++0x03
line.long 0x00 "SYSTICKCLKSEL0,System Tick Timer for CPU0 source select"
bitfld.long 0x00 0.--2. "SEL,System Tick Timer for CPU0 source select" "0: System Tick 0 divided clock,1: FRO 1MHz clock,2: Oscillator 32 kHz clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock"
group.long 0x264++0x03
line.long 0x00 "SYSTICKCLKSEL1,System Tick Timer for CPU1 source select"
bitfld.long 0x00 0.--2. "SEL,System Tick Timer for CPU1 source select" "0: System Tick 1 divided clock,1: FRO 1MHz clock,2: Oscillator 32 kHz clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock"
group.long 0x264++0x03
line.long 0x00 "SYSTICKCLKSELX1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x268++0x03
line.long 0x00 "TRACECLKSEL,Trace clock source select"
bitfld.long 0x00 0.--2. "SEL,Trace clock source select" "0: Trace divided clock,1: FRO 1MHz clock,2: Oscillator 32 kHz clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock"
group.long 0x26C++0x03
line.long 0x00 "CTIMERCLKSEL0,CTimer 0 clock source select"
bitfld.long 0x00 0.--2. "SEL,CTimer 0 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock"
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
group.long ($2+0x26C)++0x03
line.long 0x00 "CTIMERCLKSELX$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x270++0x03
line.long 0x00 "CTIMERCLKSEL1,CTimer 1 clock source select"
bitfld.long 0x00 0.--2. "SEL,CTimer 1 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock"
group.long 0x274++0x03
line.long 0x00 "CTIMERCLKSEL2,CTimer 2 clock source select"
bitfld.long 0x00 0.--2. "SEL,CTimer 2 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock"
group.long 0x274++0x03
line.long 0x00 "CTIMERCLKSELX2,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x278++0x03
line.long 0x00 "CTIMERCLKSEL3,CTimer 3 clock source select"
bitfld.long 0x00 0.--2. "SEL,CTimer 3 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock"
repeat 2. (strings "3" "4" )(list 0x00 0x04 )
group.long ($2+0x278)++0x03
line.long 0x00 "CTIMERCLKSELX$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x27C++0x03
line.long 0x00 "CTIMERCLKSEL4,CTimer 4 clock source select"
bitfld.long 0x00 0.--2. "SEL,CTimer 4 clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32kHz clock,7: No clock"
group.long 0x280++0x03
line.long 0x00 "MAINCLKSELA,Main clock A source select"
bitfld.long 0x00 0.--2. "SEL,Main clock A source select" "0: FRO 12 MHz clock,1: CLKIN clock,2: FRO 1MHz clock,3: FRO 96 MHz clock,?..."
group.long 0x284++0x03
line.long 0x00 "MAINCLKSELB,Main clock source select"
bitfld.long 0x00 0.--2. "SEL,Main clock source select" "0: Main Clock A,1: PLL0 clock,2: PLL1 clock,3: Oscillator 32 kHz clock,?..."
group.long 0x288++0x03
line.long 0x00 "CLKOUTSEL,CLKOUT clock source select"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 0.--3. "SEL,CLKOUT clock source select" "0: Main clock,1: PLL0 clock,2: CLKIN clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: PLL1 clock,6: Oscillator 32kHz clock,7: No clock,?,?,?,?,12: No clock,13: No clock,14: No clock,15: No clock"
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--2. "SEL,CLKOUT clock source select" "0: Main clock,1: PLL0 clock,2: CLKIN clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: PLL1 clock,6: Oscillator 32kHz clock,7: No clock"
endif
group.long 0x290++0x03
line.long 0x00 "PLL0CLKSEL,PLL0 clock source select"
bitfld.long 0x00 0.--2. "SEL,PLL0 clock source select" "0: FRO 12 MHz clock,1: CLKIN clock,2: FRO 1MHz clock,3: Oscillator 32kHz clock,4: No clock,5: No clock,6: No clock,7: No clock"
group.long 0x294++0x03
line.long 0x00 "PLL1CLKSEL,PLL1 clock source select"
bitfld.long 0x00 0.--2. "SEL,PLL1 clock source select" "0: FRO 12 MHz clock,1: CLKIN clock,2: FRO 1MHz clock,3: Oscillator 32kHz clock,4: No clock,5: No clock,6: No clock,7: No clock"
group.long 0x2A0++0x03
line.long 0x00 "CANCLKSEL,CAN clock source select"
bitfld.long 0x00 0.--2. "SEL,CAN clock source select" "0: CAN divided clock,1: FRO 1MHz clock,2: Oscillator 32 kHz clock,3: No clock,4: No clock,5: No clock,6: No clock,7: No clock"
group.long 0x2A4++0x03
line.long 0x00 "ADCCLKSEL,ADC clock source select"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--2. "SEL,ADC clock source select" "0: Main clock,1: PLL0 clock,2: FRO 96 MHz clock,?,4: No clock,5: No clock,6: No clock,7: No clock"
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 0.--2. "SEL,ADC clock source select" "0: Main clock,1: PLL0 clock,2: FRO 96 MHz clock,?,4: Xtal clock coming directly,5: No clock,6: No clock,7: No clock"
endif
group.long 0x2A8++0x03
line.long 0x00 "USB0CLKSEL,FS USB clock source select"
bitfld.long 0x00 0.--2. "SEL,FS USB clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: No clock,5: PLL1 clock,6: No clock,7: No clock"
group.long 0x2AC++0x03
line.long 0x00 "CLK32KCLKSEL,clock low speed source select for HS USB"
bitfld.long 0x00 3. "SEL,clock low speed source select for HS USB" "0: Oscillator 32 kHz clock,1: FRO1MHz_divided clock"
group.long 0x2B0++0x03
line.long 0x00 "FCCLKSELX0,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x2B0++0x03
line.long 0x00 "FCCLKSEL0,Flexcomm Interface 0 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 0 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
group.long 0x2B4++0x03
line.long 0x00 "FCCLKSEL1,Flexcomm Interface 1 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 1 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
group.long 0x2B4++0x03
line.long 0x00 "FCCLKSELX1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x2B8++0x03
line.long 0x00 "FCCLKSEL2,Flexcomm Interface 2 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 2 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
group.long 0x2B8++0x03
line.long 0x00 "FCCLKSELX2,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x2BC++0x03
line.long 0x00 "FCCLKSEL3,Flexcomm Interface 3 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 3 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
repeat 2. (strings "3" "4" )(list 0x00 0x04 )
group.long ($2+0x2BC)++0x03
line.long 0x00 "FCCLKSELX$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x2C0++0x03
line.long 0x00 "FCCLKSEL4,Flexcomm Interface 4 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 4 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
group.long 0x2C4++0x03
line.long 0x00 "FCCLKSEL5,Flexcomm Interface 5 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 5 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
repeat 2. (strings "5" "6" )(list 0x00 0x04 )
group.long ($2+0x2C4)++0x03
line.long 0x00 "FCCLKSELX$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x2C8++0x03
line.long 0x00 "FCCLKSEL6,Flexcomm Interface 6 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 6 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
group.long 0x2CC++0x03
line.long 0x00 "FCCLKSEL7,Flexcomm Interface 7 clock source select for Fractional Rate Divider"
bitfld.long 0x00 0.--2. "SEL,Flexcomm Interface 7 clock source select for Fractional Rate Divider" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: MCLK clock,6: Oscillator 32 kHz clock,7: No clock"
group.long 0x2CC++0x03
line.long 0x00 "FCCLKSELX7,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x2D0++0x03
line.long 0x00 "HSLSPICLKSEL,HS LSPI clock source select"
bitfld.long 0x00 0.--2. "SEL,HS LSPI clock source select" "0: Main clock,1: system PLL divided clock,2: FRO 12 MHz clock,3: FRO 96 MHz clock,4: FRO 1MHz clock,5: No clock,6: Oscillator 32 kHz clock,7: No clock"
group.long 0x2E0++0x03
line.long 0x00 "MCLKCLKSEL,MCLK clock source select"
bitfld.long 0x00 0.--2. "SEL,MCLK clock source select" "0: FRO 96 MHz clock,1: PLL0 clock,?,?,4: No clock,5: No clock,6: No clock,7: No clock"
group.long 0x2F0++0x03
line.long 0x00 "SCTCLKSEL,SCTimer/PWM clock source select"
bitfld.long 0x00 0.--2. "SEL,SCTimer/PWM clock source select" "0: Main clock,1: PLL0 clock,2: CLKIN clock,3: FRO 96 MHz clock,4: No clock,5: MCLK clock,6: No clock,7: No clock"
group.long 0x2F8++0x03
line.long 0x00 "SDIOCLKSEL,SDIO clock source select"
bitfld.long 0x00 0.--2. "SEL,SDIO clock source select" "0: Main clock,1: PLL0 clock,2: No clock,3: FRO 96 MHz clock,4: No clock,5: PLL1 clock,6: No clock,7: No clock"
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
group.long ($2+0x300)++0x03
line.long 0x00 "SYSTICKCLKDIV$1,System Tick Timer divider for CPU $1"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
endif
repeat.end
group.long 0x308++0x03
line.long 0x00 "TRACECLKDIV,TRACE clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x30C++0x03
line.long 0x00 "CANCLKDIV,CAN clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x320++0x03
line.long 0x00 "FLEXFRGXCTRL0,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x320++0x03
line.long 0x00 "FLEXFRG0CTRL,Fractional rate divider for flexcomm 0"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
group.long 0x324++0x03
line.long 0x00 "FLEXFRG1CTRL,Fractional rate divider for flexcomm 1"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
group.long ($2+0x324)++0x03
line.long 0x00 "FLEXFRGXCTRL$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x328++0x03
line.long 0x00 "FLEXFRG2CTRL,Fractional rate divider for flexcomm 2"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
group.long 0x32C++0x03
line.long 0x00 "FLEXFRG3CTRL,Fractional rate divider for flexcomm 3"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
repeat 2. (strings "3" "4" )(list 0x00 0x04 )
group.long ($2+0x32C)++0x03
line.long 0x00 "FLEXFRGXCTRL$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x330++0x03
line.long 0x00 "FLEXFRG4CTRL,Fractional rate divider for flexcomm 4"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
group.long 0x334++0x03
line.long 0x00 "FLEXFRG5CTRL,Fractional rate divider for flexcomm 5"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
repeat 2. (strings "5" "6" )(list 0x00 0x04 )
group.long ($2+0x334)++0x03
line.long 0x00 "FLEXFRGXCTRL$1,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
repeat.end
group.long 0x338++0x03
line.long 0x00 "FLEXFRG6CTRL,Fractional rate divider for flexcomm 6"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
group.long 0x33C++0x03
line.long 0x00 "FLEXFRGXCTRL7,Peripheral reset control register"
hexmask.long 0x00 0.--31. 1. "DATA,Data array value"
group.long 0x33C++0x03
line.long 0x00 "FLEXFRG7CTRL,Fractional rate divider for flexcomm 7"
hexmask.long.byte 0x00 8.--15. 1. "MULT,Numerator of the fractional rate divider"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Denominator of the fractional rate divider"
group.long 0x380++0x03
line.long 0x00 "AHBCLKDIV,System clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x384++0x03
line.long 0x00 "CLKOUTDIV,CLKOUT clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x388++0x03
line.long 0x00 "FROHFDIV,FRO_HF (96MHz) clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x38C++0x03
line.long 0x00 "WDTCLKDIV,WDT clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
bitfld.long 0x00 0.--5. "DIV,Clock divider value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x394++0x03
line.long 0x00 "ADCCLKDIV,ADC clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
bitfld.long 0x00 0.--2. "DIV,Clock divider value" "0,1,2,3,4,5,6,7"
group.long 0x398++0x03
line.long 0x00 "USB0CLKDIV,USB0 Clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x398++0x03
line.long 0x00 "USB0CLKDIV,USB0-FS Clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x3A0++0x03
line.long 0x00 "FRO1MCLKDIV,FRO1MHz Clock divider (FRO1M_divided)"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x3AC++0x03
line.long 0x00 "MCLKDIV,I2S MCLK clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x3B4++0x03
line.long 0x00 "SCTCLKDIV,SCT/PWM clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x3BC++0x03
line.long 0x00 "SDIOCLKDIV,SDIO clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x3C4++0x03
line.long 0x00 "PLL0CLKDIV,PLL0 clock divider"
rbitfld.long 0x00 31. "REQFLAG,Divider status flag" "0: Divider clock is stable,1: Clock frequency is not stable"
newline
bitfld.long 0x00 30. "HALT,Halts the divider counter" "0: Divider clock is running,1: Divider clock is stoped"
newline
bitfld.long 0x00 29. "RESET,Resets the divider counter" "0: Divider is not reset,1: Divider is reset"
newline
hexmask.long.byte 0x00 0.--7. 1. "DIV,Clock divider value"
group.long 0x3FC++0x03
line.long 0x00 "CLOCKGENUPDATELOCKOUT,Control clock configuration registers access (like xxxDIV xxxSEL)"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
hexmask.long 0x00 0.--31. 1. "CLOCKGENUPDATELOCKOUT,Control clock configuration registers access (for example xxxDIV xxxSEL)"
endif
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
hexmask.long 0x00 0.--31. 1. "CLOCKGENUPDATELOCKOUT,Control clock configuration registers access (like xxxDIV xxxSEL)"
endif
group.long 0x400++0x03
line.long 0x00 "FMCCR,FMC configuration register"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 12.--15. "FLASHTIM,Flash memory access time" "0: 1 system clock flash access time (for system..,1: 2 system clocks flash access time (for system..,2: 3 system clocks flash access time (for system..,3: 4 system clocks flash access time (for system..,4: 5 system clocks flash access time (for system..,5: 6 system clocks flash access time (for system..,6: 7 system clocks flash access time (for system..,7: 8 system clocks flash access time (for system..,8: 9 system clocks flash access time (for system..,9: 10 system clocks flash access time (for..,10: 11 system clocks flash access time (for..,11: 12 system clocks flash access time (for..,?..."
newline
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 12.--15. "FLASHTIM,Flash memory access time" "0: 1 system clock flash access time (for system..,1: 2 system clocks flash access time (for system..,2: 3 system clocks flash access time (for system..,3: 4 system clocks flash access time (for system..,4: 5 system clocks flash access time (for system..,5: 6 system clocks flash access time (for system..,6: 7 system clocks flash access time (for system..,7: 8 system clocks flash access time (for system..,8: 9 system clocks flash access time (for system..,9: 10 system clocks flash access time (for..,10: 11 system clocks flash access time (for..,11: 12 system clocks flash access time (for..,?..."
newline
endif
bitfld.long 0x00 6. "PREFOVR,Prefetch override" "0: Any previously initiated prefetch will be..,1: Any previously initiated prefetch will be.."
newline
bitfld.long 0x00 5. "PREFEN,Prefetch enable" "0: No instruction prefetch is performed,1: Instruction prefetch is enabled"
newline
bitfld.long 0x00 4. "ACCEL,Acceleration enable" "0: Flash acceleration is disabled,1: Flash acceleration is enabled"
newline
bitfld.long 0x00 2.--3. "DATACFG,Data read configuration" "0: Data accesses from flash are not buffered,1: One buffer is used for all data accesses,2: All buffers can be used for data accesses,?..."
newline
bitfld.long 0x00 0.--1. "FETCHCFG,Instruction fetch configuration" "0: Instruction fetches from flash are not buffered,1: One buffer is used for all instruction fetches,2: All buffers may be used for instruction fetches,?..."
group.long 0x40C++0x03
line.long 0x00 "USB0NEEDCLKCTRL,USB0-FS need clock control"
bitfld.long 0x00 3. "POL_FS_HOST_NEEDCLK,USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.."
newline
bitfld.long 0x00 2. "AP_FS_HOST_NEEDCLK,USB0-FS Host USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high"
newline
bitfld.long 0x00 1. "POL_FS_DEV_NEEDCLK,USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.."
newline
bitfld.long 0x00 0. "AP_FS_DEV_NEEDCLK,USB0-FS Device USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high"
group.long 0x40C++0x03
line.long 0x00 "USB0NEEDCLKCTRL,USB0 need clock control"
bitfld.long 0x00 3. "POL_FS_HOST_NEEDCLK,USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.."
newline
bitfld.long 0x00 2. "AP_FS_HOST_NEEDCLK,USB0 Host USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high"
newline
bitfld.long 0x00 1. "POL_FS_DEV_NEEDCLK,USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt" "0: Falling edge of device USB0_NEEDCLK triggers..,1: Rising edge of device USB0_NEEDCLK triggers.."
newline
bitfld.long 0x00 0. "AP_FS_DEV_NEEDCLK,USB0 Device USB0_NEEDCLK signal control" "0: Under hardware control,1: Forced high"
group.long 0x410++0x03
line.long 0x00 "USB0NEEDCLKSTAT,USB0 need clock status"
rbitfld.long 0x00 1. "HOST_NEEDCLK,USB0 Host USB0_NEEDCLK signal status" "0: USB0 Host clock is low,1: USB0 Host clock is high"
newline
rbitfld.long 0x00 0. "DEV_NEEDCLK,USB0 Device USB0_NEEDCLK signal status" "0: USB0 Device clock is low,1: USB0 Device clock is high"
group.long 0x410++0x03
line.long 0x00 "USB0NEEDCLKSTAT,USB0-FS need clock status"
rbitfld.long 0x00 1. "HOST_NEEDCLK,USB0-FS Host USB0_NEEDCLK signal status" "0: USB0-FS Host clock is low,1: USB0-FS Host clock is high"
newline
rbitfld.long 0x00 0. "DEV_NEEDCLK,USB0-FS Device USB0_NEEDCLK signal status" "0: USB0-FS Device clock is low,1: USB0-FS Device clock is high"
wgroup.long 0x41C++0x03
line.long 0x00 "FMCFLUSH,FMCflush control"
bitfld.long 0x00 0. "FLUSH,Flush control" "0: No action is performed,1: Flush the FMC buffer contents"
group.long 0x420++0x03
line.long 0x00 "MCLKIO,MCLK control"
bitfld.long 0x00 0. "MCLKIO,MCLK control" "0: input mode,1: output mode"
group.long 0x424++0x03
line.long 0x00 "USB1NEEDCLKCTRL,USB1 need clock control"
bitfld.long 0x00 4. "HS_DEV_WAKEUP_N,Software override of device controller PHY wake up logic" "0: Forces USB1_PHY to wake-up,1: Normal USB1_PHY behavior"
newline
bitfld.long 0x00 3. "POL_HS_HOST_NEEDCLK,USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of HOST_NEEDCLK triggers wake-up,1: Rising edge of HOST_NEEDCLK triggers wake-up"
newline
bitfld.long 0x00 2. "AP_HS_HOST_NEEDCLK,USB1 Host need clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high"
newline
bitfld.long 0x00 1. "POL_HS_DEV_NEEDCLK,USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of DEV_NEEDCLK triggers wake-up,1: Rising edge of DEV_NEEDCLK triggers wake-up"
newline
bitfld.long 0x00 0. "AP_HS_DEV_NEEDCLK,USB1 Device need_clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high"
group.long 0x424++0x03
line.long 0x00 "USB1NEEDCLKCTRL,USB1-HS need clock control"
bitfld.long 0x00 4. "HS_DEV_WAKEUP_N,Software override of device controller PHY wake up logic" "0: Forces USB1_PHY to wake-up,1: Normal USB1_PHY behavior"
newline
bitfld.long 0x00 3. "POL_HS_HOST_NEEDCLK,USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of HOST_NEEDCLK triggers wake-up,1: Rising edge of HOST_NEEDCLK triggers wake-up"
newline
bitfld.long 0x00 2. "AP_HS_HOST_NEEDCLK,USB1-HS Host need clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high"
newline
bitfld.long 0x00 1. "POL_HS_DEV_NEEDCLK,USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt" "0: Falling edge of DEV_NEEDCLK triggers wake-up,1: Rising edge of DEV_NEEDCLK triggers wake-up"
newline
bitfld.long 0x00 0. "AP_HS_DEV_NEEDCLK,USB1-HS Device need_clock signal control" "0: HOST_NEEDCLK is under hardware control,1: HOST_NEEDCLK is forced high"
group.long 0x428++0x03
line.long 0x00 "USB1NEEDCLKSTAT,USB1 need clock status"
rbitfld.long 0x00 1. "HOST_NEEDCLK,USB1 Host need_clock signal status" "0: HOST_NEEDCLK is low,1: HOST_NEEDCLK is high"
newline
rbitfld.long 0x00 0. "DEV_NEEDCLK,USB1 Device need_clock signal status" "0: DEV_NEEDCLK is low,1: DEV_NEEDCLK is high"
group.long 0x428++0x03
line.long 0x00 "USB1NEEDCLKSTAT,USB1-HS need clock status"
rbitfld.long 0x00 1. "HOST_NEEDCLK,USB1-HS Host need_clock signal status" "0: HOST_NEEDCLK is low,1: HOST_NEEDCLK is high"
newline
rbitfld.long 0x00 0. "DEV_NEEDCLK,USB1-HS Device need_clock signal status" "0: DEV_NEEDCLK is low,1: DEV_NEEDCLK is high"
group.long 0x440++0x03
line.long 0x00 "FLASHREMAP_SIZE,This 32-bit register contains the size of the image to remap in bytes"
hexmask.long 0x00 0.--31. 1. "FLASHREMAP_SIZE,no description available"
group.long 0x444++0x03
line.long 0x00 "FLASHREMAP_SIZE_DP,This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security"
hexmask.long 0x00 0.--31. 1. "FLASHREMAP_SIZE,no description available"
group.long 0x448++0x03
line.long 0x00 "FLASHREMAP_OFFSET,This 32-bit register contains the offset by which the image is to be remapped"
hexmask.long 0x00 0.--31. 1. "FLASHREMAP_OFFSET,no description available"
group.long 0x44C++0x03
line.long 0x00 "FLASHREMAP_OFFSET_DP,This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security"
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")
hexmask.long 0x00 0.--31. 1. "FLASHREMAP_OFFSET_DP,no description available"
endif
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")
hexmask.long 0x00 0.--31. 1. "FLASHREMAP_OFFSET,no description available"
endif
group.long 0x45C++0x03
line.long 0x00 "FLASHREMAP_LOCK,Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers"
hexmask.long 0x00 0.--31. 1. "LOCK,Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers"
group.long 0x460++0x03
line.long 0x00 "SDIOCLKCTRL,SDIO CCLKIN phase and delay control"
bitfld.long 0x00 31. "CCLK_SAMPLE_DELAY_ACTIVE,Enables sample delay as controlled by the CCLK_SAMPLE_DELAY field" "0: Disables sample delay,1: Enables sample delay"
newline
bitfld.long 0x00 24.--28. "CCLK_SAMPLE_DELAY,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 23. "CCLK_DRV_DELAY_ACTIVE,Enables drive delay as controlled by the CCLK_DRV_DELAY field" "0: Disable drive delay,1: Enable drive delay"
newline
bitfld.long 0x00 16.--20. "CCLK_DRV_DELAY,Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 7. "PHASE_ACTIVE,Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE" "0: Bypassed,1: Activates phase shift logic"
newline
bitfld.long 0x00 2.--3. "CCLK_SAMPLE_PHASE,Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in" "0: 0 degree shift,1: 90 degree shift,2: 180 degree shift,3: 270 degree shift"
newline
bitfld.long 0x00 0.--1. "CCLK_DRV_PHASE,Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in" "0: 0 degree shift,1: 90 degree shift,2: 180 degree shift,3: 270 degree shift"
group.long 0x470++0x03
line.long 0x00 "CASPER_CTRL,Control CASPER integration"
bitfld.long 0x00 0. "INTERLEAVE,Control RAM access for RAMX0 and RAMX1" "0: RAM access to RAMX0 and RAMX1 is consecutive,1: RAM access to RAMX0 and RAMX1 is interleaved"
group.long 0x560++0x03
line.long 0x00 "PLL1CTRL,PLL1 550m control"
bitfld.long 0x00 24. "SKEWEN,Skew mode" "0: skewmode is disable,1: skewmode is enable"
newline
bitfld.long 0x00 23. "FRMCLKSTABLE,free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable" "0,1"
newline
bitfld.long 0x00 22. "FRMEN," "0,1"
newline
bitfld.long 0x00 21. "CLKEN,enable the output clock" "0: Disable the output clock,1: Enable the output clock"
newline
bitfld.long 0x00 20. "BYPASSPOSTDIV,bypass of the post-divider" "0: use the post-divider,1: bypass of the post-divider"
newline
bitfld.long 0x00 19. "BYPASSPREDIV,bypass of the pre-divider" "0: use the pre-divider,1: bypass of the pre-divider"
newline
bitfld.long 0x00 18. "BWDIRECT,control of the bandwidth of the PLL" "0: the bandwidth is changed synchronously with..,1: modify the bandwidth of the PLL directly"
newline
bitfld.long 0x00 17. "LIMUPOFF,limup_off = 1 in spread spectrum and fractional PLL applications" "0,1"
newline
bitfld.long 0x00 16. "BYPASSPOSTDIV2,bypass of the divide-by-2 divider in the post-divider" "0: use the divide-by-2 divider in the post-divider,1: bypass of the divide-by-2 divider in the.."
newline
bitfld.long 0x00 15. "BYPASSPLL,Bypass PLL input clock is sent directly to the PLL output (default)" "0: use PLL,1: PLL input clock is sent directly to the PLL.."
newline
bitfld.long 0x00 10.--14. "SELP,Bandwidth select P value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--9. "SELI,Bandwidth select I value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--3. "SELR,Bandwidth select R value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x564++0x03
line.long 0x00 "PLL1STAT,PLL1 550m status"
rbitfld.long 0x00 4. "FRMDET,free running detector output (active high)" "0,1"
newline
rbitfld.long 0x00 3. "POSTDIVACK,post-divider ratio change acknowledge" "0,1"
newline
rbitfld.long 0x00 2. "FEEDDIVACK,feedback divider ratio change acknowledge" "0,1"
newline
rbitfld.long 0x00 1. "PREDIVACK,pre-divider ratio change acknowledge" "0,1"
newline
rbitfld.long 0x00 0. "LOCK,lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz" "0,1"
group.long 0x568++0x03
line.long 0x00 "PLL1NDEC,PLL1 550m N divider"
bitfld.long 0x00 8. "NREQ,pre-divider ratio change request" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "NDIV,pre-divider divider ratio (N-divider)"
group.long 0x56C++0x03
line.long 0x00 "PLL1MDEC,PLL1 550m M divider"
bitfld.long 0x00 16. "MREQ,feedback ratio change request" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "MDIV,feedback divider divider ratio (M-divider)"
group.long 0x570++0x03
line.long 0x00 "PLL1PDEC,PLL1 550m P divider"
bitfld.long 0x00 5. "PREQ,feedback ratio change request" "0,1"
newline
bitfld.long 0x00 0.--4. "PDIV,post-divider divider ratio (P-divider)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x580++0x03
line.long 0x00 "PLL0CTRL,PLL0 550m control"
bitfld.long 0x00 24. "SKEWEN,skew mode" "0: skew mode is disable,1: skew mode is enable"
newline
bitfld.long 0x00 23. "FRMCLKSTABLE,free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable" "0,1"
newline
bitfld.long 0x00 22. "FRMEN,free running mode" "0: free running mode is disable,1: free running mode is enable"
newline
bitfld.long 0x00 21. "CLKEN,enable the output clock" "0: disable the output clock,1: enable the output clock"
newline
bitfld.long 0x00 20. "BYPASSPOSTDIV,bypass of the post-divider" "0: use the post-divider,1: bypass of the post-divider"
newline
bitfld.long 0x00 19. "BYPASSPREDIV,bypass of the pre-divider" "0: use the pre-divider,1: bypass of the pre-divider"
newline
bitfld.long 0x00 18. "BWDIRECT,Control of the bandwidth of the PLL" "0: the bandwidth is changed synchronously with..,1: modify the bandwidth of the PLL directly"
newline
bitfld.long 0x00 17. "LIMUPOFF,limup_off = 1 in spread spectrum and fractional PLL applications" "0,1"
newline
bitfld.long 0x00 16. "BYPASSPOSTDIV2,bypass of the divide-by-2 divider in the post-divider" "0: use the divide-by-2 divider in the post-divider,1: bypass of the divide-by-2 divider in the.."
newline
bitfld.long 0x00 15. "BYPASSPLL,Bypass PLL input clock is sent directly to the PLL output (default)" "0: use PLL,1: Bypass PLL input clock is sent directly to.."
newline
bitfld.long 0x00 10.--14. "SELP,Bandwidth select P value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--9. "SELI,Bandwidth select I value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--3. "SELR,Bandwidth select R value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x584++0x03
line.long 0x00 "PLL0STAT,PLL0 550m status"
rbitfld.long 0x00 4. "FRMDET,free running detector output (active high)" "0,1"
newline
rbitfld.long 0x00 3. "POSTDIVACK,post-divider ratio change acknowledge" "0,1"
newline
rbitfld.long 0x00 2. "FEEDDIVACK,feedback divider ratio change acknowledge" "0,1"
newline
rbitfld.long 0x00 1. "PREDIVACK,pre-divider ratio change acknowledge" "0,1"
newline
rbitfld.long 0x00 0. "LOCK,lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz" "0,1"
group.long 0x588++0x03
line.long 0x00 "PLL0NDEC,PLL0 550m N divider"
bitfld.long 0x00 8. "NREQ,pre-divider ratio change request" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "NDIV,pre-divider divider ratio (N-divider)"
group.long 0x58C++0x03
line.long 0x00 "PLL0PDEC,PLL0 550m P divider"
bitfld.long 0x00 5. "PREQ,feedback ratio change request" "0,1"
newline
bitfld.long 0x00 0.--4. "PDIV,post-divider divider ratio (P-divider)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x590++0x03
line.long 0x00 "PLL0SSCG0,PLL0 Spread Spectrum Wrapper control register 0"
hexmask.long 0x00 0.--31. 1. "MD_LBS,input word of the wrapper bit 31 to 0"
group.long 0x594++0x03
line.long 0x00 "PLL0SSCG1,PLL0 Spread Spectrum Wrapper control register 1"
bitfld.long 0x00 28. "SEL_EXT,to select mdiv_ext and mreq_ext sel_ext =" "0: mdiv ~ md[32:0] mreq = 1 sel_ext =,1: mdiv = mdiv_ext mreq = mreq_ext"
newline
bitfld.long 0x00 27. "DITHER,dithering between two modulation frequencies in a random way or in a pseudo random way (white noise) in order to decrease the probability that the modulated waveform will occur with the same phase on a particular point on the screen" "0,1"
newline
bitfld.long 0x00 26. "MREQ,to select an external mreq value" "0,1"
newline
hexmask.long.word 0x00 10.--25. 1. "MDIV_EXT,to select an external mdiv value"
newline
bitfld.long 0x00 8.--9. "MC,modulation waveform control Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL giving a flat frequency spectrum" "0,1,2,3"
newline
bitfld.long 0x00 5.--7. "MR,programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) mr[2:0] =" "0: kss = 0 (no spread spectrum),1: kss ~ 1 mr[2:0] =,2: kss ~ 1,?..."
newline
bitfld.long 0x00 2.--4. "MF,programmable modulation frequency fm = Fref/Nss mf[2:0] =" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 1. "MD_REQ,md change request" "0,1"
newline
bitfld.long 0x00 0. "MD_MBS,input word of the wrapper bit 32" "0,1"
group.long 0x704++0x03
line.long 0x00 "FUNCRETENTIONCTRL,Functional retention control register"
hexmask.long.word 0x00 14.--23. 1. "RET_LENTH,lenth of Scan chains to save"
newline
hexmask.long.word 0x00 1.--13. 1. "RET_START,Start address divided by 4 inside SRAMX bank"
newline
bitfld.long 0x00 0. "FUNCRETENA,functional retention in power down only" "0: disable functional retention,1: enable functional retention"
group.long 0x800++0x03
line.long 0x00 "CPUCTRL,CPU Control for multiple processors"
bitfld.long 0x00 5. "CPU1RSTEN,CPU1 reset" "0: The CPU1 is not being reset,1: The CPU1 is being reset"
newline
bitfld.long 0x00 3. "CPU1CLKEN,CPU1 clock enable" "0: The CPU1 clock is not enabled,1: The CPU1 clock is enabled"
group.long 0x804++0x03
line.long 0x00 "CPBOOT,Coprocessor Boot Address"
hexmask.long 0x00 0.--31. 1. "CPBOOT,Coprocessor Boot Address for CPU1"
group.long 0x80C++0x03
line.long 0x00 "CPSTAT,CPU Status"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rbitfld.long 0x00 3. "CPU1LOCKUP,The CPU1 lockup state" "0: the CPU is not in lockup,1: the CPU is in lockup"
newline
endif
rbitfld.long 0x00 2. "CPU0LOCKUP,The CPU0 lockup state" "0: the CPU is not in lockup,1: the CPU is in lockup"
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
rbitfld.long 0x00 1. "CPU1SLEEPING,The CPU1 sleeping state" "0: the CPU is not sleeping,1: the CPU is sleeping"
newline
endif
rbitfld.long 0x00 0. "CPU0SLEEPING,The CPU0 sleeping state" "0: the CPU is not sleeping,1: the CPU is sleeping"
group.long 0x920++0x03
line.long 0x00 "BOOT_SEED_REG0,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG0,no description available"
group.long 0x924++0x03
line.long 0x00 "BOOT_SEED_REG1,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG1,no description available"
group.long 0x928++0x03
line.long 0x00 "BOOT_SEED_REG2,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG2,no description available"
group.long 0x92C++0x03
line.long 0x00 "BOOT_SEED_REG3,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG3,no description available"
group.long 0x930++0x03
line.long 0x00 "BOOT_SEED_REG4,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG4,no description available"
group.long 0x934++0x03
line.long 0x00 "BOOT_SEED_REG5,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG5,no description available"
group.long 0x938++0x03
line.long 0x00 "BOOT_SEED_REG6,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG6,no description available"
group.long 0x93C++0x03
line.long 0x00 "BOOT_SEED_REG7,boot seed (256-bit random value)"
hexmask.long 0x00 0.--31. 1. "BOOT_SEED_REG7,no description available"
group.long 0x940++0x03
line.long 0x00 "HMAC_REG0,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG0,no description available"
group.long 0x944++0x03
line.long 0x00 "HMAC_REG1,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG1,no description available"
group.long 0x948++0x03
line.long 0x00 "HMAC_REG2,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG2,no description available"
group.long 0x94C++0x03
line.long 0x00 "HMAC_REG3,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG3,no description available"
group.long 0x950++0x03
line.long 0x00 "HMAC_REG4,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG4,no description available"
group.long 0x954++0x03
line.long 0x00 "HMAC_REG5,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG5,no description available"
group.long 0x958++0x03
line.long 0x00 "HMAC_REG6,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG6,no description available"
group.long 0x95C++0x03
line.long 0x00 "HMAC_REG7,HMAC"
hexmask.long 0x00 0.--31. 1. "HMAC_REG7,no description available"
group.long 0x960++0x03
line.long 0x00 "BOOT_LOCK,Control write access to boot seed security registers"
bitfld.long 0x00 1. "LOCK_HMAC,Control write access to HMAC_REG registers" "?,1: write access to all 8 registers HMAC_REG is.."
newline
bitfld.long 0x00 0. "LOCK_BOOT_SEED,Control write access to BOOT_SEED_REG registers" "?,1: write access to all 8 registers BOOT_SEED_REG.."
group.long 0xA18++0x03
line.long 0x00 "CLOCK_CTRL,Various system clock controls : Flash clock (48 MHz) control clocks to Frequency Measures"
bitfld.long 0x00 9. "PLU_DEGLITCH_CLK_ENA,Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 8. "XO_CAL_CLK_ENA,Enable clock for cristal oscilator calibration" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 7. "ANA_FRO12M_CLK_ENA,Enable FRO 12MHz clock for analog control of the FRO 192MHz" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 6. "FRO1MHZ_CLK_ENA,Enable FRO 1MHz clock for clock muxing in clock gen" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 5. "CLKIN_ENA,Enable clock_in clock for clock module" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 4. "FRO_HF_FREQM_ENA,Enable FRO 96MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 3. "FRO12MHZ_FREQM_ENA,Enable FRO 12MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 2. "FRO1MHZ_UTICK_ENA,Enable FRO 1MHz clock for Frequency Measure module and for UTICK" "0: The clock is not enabled,1: The clock is enabled"
newline
bitfld.long 0x00 1. "XTAL32MHZ_FREQM_ENA,Enable XTAL32MHz clock for Frequency Measure module" "0: The clock is not enabled,1: The clock is enabled"
group.long 0xB10++0x03
line.long 0x00 "COMP_INT_CTRL,Comparator Interrupt control"
bitfld.long 0x00 5. "INT_SOURCE,Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection" "0: Select Analog Comparator filtered output as..,1: Select Analog Comparator raw output.."
newline
bitfld.long 0x00 2.--4. "INT_CTRL,Comparator interrupt type selector" "0: The analog comparator interrupt edge..,1: The analog comparator interrupt level..,2: analog comparator interrupt is rising edge..,3: Analog Comparator interrupt is high level..,4: analog comparator interrupt is falling edge..,5: Analog Comparator interrupt is low level..,6: analog comparator interrupt is rising and..,7: The analog comparator interrupt level.."
newline
bitfld.long 0x00 1. "INT_CLEAR,Analog Comparator interrupt clear" "0: No effect,1: Clear the interrupt"
newline
bitfld.long 0x00 0. "INT_ENABLE,Analog Comparator interrupt enable control" "0: interrupt disable,1: interrupt enable"
group.long 0xB14++0x03
line.long 0x00 "COMP_INT_STATUS,Comparator Interrupt status"
rbitfld.long 0x00 2. "VAL,comparator analog output" "0: P+ is smaller than P,1: P+ is greater than P"
newline
rbitfld.long 0x00 1. "INT_STATUS,Interrupt status AFTER Interrupt Enable" "0: no interrupt pending,1: interrupt pending"
newline
rbitfld.long 0x00 0. "STATUS,Interrupt status BEFORE Interrupt Enable" "0: no interrupt pending,1: interrupt pending"
group.long 0xE04++0x03
line.long 0x00 "AUTOCLKGATEOVERRIDE,Control automatic clock gating"
hexmask.long.word 0x00 16.--31. 1. "ENABLEUPDATE,The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect"
newline
bitfld.long 0x00 15. "SYSCON,Control automatic clock gating of synchronous system controller registers bank" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
sif cpuis("LPC55S14*")||cpuis("LPC55S16*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 14. "USB0,Control automatic clock gating of USB controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
endif
bitfld.long 0x00 13. "SDMA1,Control automatic clock gating of DMA1 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 12. "SDMA0,Control automatic clock gating of DMA0 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 11. "CRCGEN,Control automatic clock gating of CRCGEN controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 8. "SYNC1_APB,Control automatic clock gating of synchronous bridge controller 1" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 7. "SYNC0_APB,Control automatic clock gating of synchronous bridge controller 0" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 6. "RAM4_CTRL,Control automatic clock gating of RAM4 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 5. "RAM3_CTRL,Control automatic clock gating of RAM3 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
endif
bitfld.long 0x00 4. "RAM2_CTRL,Control automatic clock gating of RAM2 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 3. "RAM1_CTRL,Control automatic clock gating of RAM1 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 2. "RAM0_CTRL,Control automatic clock gating of RAM0 controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 1. "RAMX_CTRL,Control automatic clock gating of RAMX controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
newline
bitfld.long 0x00 0. "ROM,Control automatic clock gating of ROM controller" "0: Automatic clock gating is not overridden,1: Automatic clock gating is overridden (Clock.."
group.long 0xE08++0x03
line.long 0x00 "GPIOPSYNC,Enable bypass of the first stage of synchonization inside GPIO_INT module"
bitfld.long 0x00 0. "PSYNC,Enable bypass of the first stage of synchonization inside GPIO_INT module" "0: use the first stage of synchonization inside..,1: bypass of the first stage of synchonization.."
group.long 0xF88++0x03
line.long 0x00 "HASHRESTHWKEY,Controls whether the HASH AES hardware secret key is restricted to use by secure code"
hexmask.long 0x00 0.--31. 1. "UNLOCKCODE,Code value that controls whether HASH AES hardware secret key is unlocked"
group.long 0xFA0++0x03
line.long 0x00 "DEBUG_LOCK_EN,Control write access to security registers"
sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 0.--3. "LOCK_ALL,Control write access to CODESECURITYPROTTEST CODESECURITYPROTCPU0 CODESECURITYPROTCPU1 CPU0_DEBUG_FEATURES CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers" "0: Any other value than b1010,?,?,?,?,?,?,?,?,?,10: 1010,?..."
endif
sif cpuis("LPC55S04*")||cpuis("LPC55S06*")||cpuis("LPC55S14*")||cpuis("LPC55S16*")
bitfld.long 0x00 0.--3. "LOCK_ALL,Control write access to security registers" "0: Any other value than b1010,?,?,?,?,?,?,?,?,?,10: 1010,?..."
endif
group.long 0xFA4++0x03
line.long 0x00 "DEBUG_FEATURES,Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control"
bitfld.long 0x00 10.--11. "CPU1_NIDEN,CPU1 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 8.--9. "CPU1_DBGEN,CPU1 Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
group.long 0xFA4++0x03
line.long 0x00 "DEBUG_FEATURES,Cortex debug features control"
bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
group.long 0xFA8++0x03
line.long 0x00 "DEBUG_FEATURES_DP,Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register"
bitfld.long 0x00 10.--11. "CPU1_NIDEN,CPU1 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 8.--9. "CPU1_DBGEN,CPU1 Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 (CPU0) Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
group.long 0xFA8++0x03
line.long 0x00 "DEBUG_FEATURES_DP,Cortex debug features control"
bitfld.long 0x00 6.--7. "CPU0_SPNIDEN,CPU0 Secure Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 4.--5. "CPU0_SPIDEN,CPU0 Secure Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 2.--3. "CPU0_NIDEN,CPU0 Non Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
newline
bitfld.long 0x00 0.--1. "CPU0_DBGEN,CPU0 (CPU0) Invasive debug control" "?,1: Any other value than b10,2: 10,?..."
group.long 0xFB4++0x03
line.long 0x00 "SWD_ACCESS_CPU0,This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0"
hexmask.long 0x00 0.--31. 1. "SEC_CODE,CPU0 SWD-AP: 0x12345678"
wgroup.long 0xFBC++0x03
line.long 0x00 "KEY_BLOCK,block quiddikey/PUF all index"
hexmask.long 0x00 0.--31. 1. "KEY_BLOCK,Write a value to block quiddikey/PUF all index"
group.long 0xFC0++0x03
line.long 0x00 "DEBUG_AUTH_BEACON,Debug authentication BEACON register"
hexmask.long 0x00 0.--31. 1. "BEACON,Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code"
group.long 0xFD4++0x03
line.long 0x00 "CPUCFG,CPUs configuration register"
bitfld.long 0x00 2. "CPU1ENABLE,Enable CPU1" "0: CPU1 is disable (Processor in reset),1: CPU1 is enable"
rgroup.long 0xFF8++0x03
line.long 0x00 "DEVICE_ID0,Device ID"
bitfld.long 0x00 20.--23. "ROM_REV_MINOR,ROM revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFC++0x03
line.long 0x00 "DIEID,Chip revision ID and Number"
hexmask.long.tbyte 0x00 4.--23. 1. "MCO_NUM_IN_DIE_ID,Chip Number 0x426B"
newline
bitfld.long 0x00 0.--3. "REV_ID,Chip Metal Revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "SYSCTL (System Controller)"
base ad:0x40023000
group.long 0x00++0x03
line.long 0x00 "UPDATELCKOUT,update lock out control"
bitfld.long 0x00 0. "UPDATELCKOUT,All Registers" "0: Normal Mode,1: Protected Mode"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x40)++0x03
line.long 0x00 "FCCTRLSEL$1,Selects the source for SCK going into Flexcomm index"
bitfld.long 0x00 24.--25. "DATAOUTSEL,Selects the source for DATA output from this Flexcomm" "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA..,1: Output data is taken from shared signal set 0..,2: Output data is taken from shared signal set 1..,?..."
bitfld.long 0x00 16.--17. "DATAINSEL,Selects the source for DATA input to this Flexcomm" "0: Selects the dedicated FCn_RXD_SDA_MOSI_DATA..,1: Input data is taken from shared signal set 0..,2: Input data is taken from shared signal set 1..,?..."
newline
bitfld.long 0x00 8.--9. "WSINSEL,Selects the source for WS going into this Flexcomm" "0: Selects the dedicated (FCn_TXD_SCL_MISO_WS)..,1: WS is taken from shared signal set 0 (defined..,2: WS is taken from shared signal set 1 (defined..,?..."
bitfld.long 0x00 0.--1. "SCKINSEL,Selects the source for SCK going into this Flexcomm" "0: Selects the dedicated FCn_SCK function for..,1: SCK is taken from shared signal set 0..,2: SCK is taken from shared signal set 1..,?..."
repeat.end
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0x80)++0x03
line.long 0x00 "SHAREDCTRLSET$1,Selects sources and data combinations for shared signal set index"
bitfld.long 0x00 23. "FC7DATAOUTEN,Controls FC7 contribution to SHAREDDATAOUT for this shared set" "0: Data output from FC7 does not contribute to..,1: Data output from FC7 does contribute to this.."
bitfld.long 0x00 22. "FC6DATAOUTEN,Controls FC6 contribution to SHAREDDATAOUT for this shared set" "0: Data output from FC6 does not contribute to..,1: Data output from FC6 does contribute to this.."
newline
bitfld.long 0x00 21. "FC5DATAOUTEN,Controls FC5 contribution to SHAREDDATAOUT for this shared set" "0: Data output from FC5 does not contribute to..,1: Data output from FC5 does contribute to this.."
bitfld.long 0x00 20. "FC4DATAOUTEN,Controls FC4 contribution to SHAREDDATAOUT for this shared set" "0: Data output from FC4 does not contribute to..,1: Data output from FC4 does contribute to this.."
newline
bitfld.long 0x00 18. "FC2DATAOUTEN,Controls FC2 contribution to SHAREDDATAOUT for this shared set" "0: Data output from FC2 does not contribute to..,1: Data output from FC2 does contribute to this.."
bitfld.long 0x00 17. "FC1DATAOUTEN,Controls FC1 contribution to SHAREDDATAOUT for this shared set" "0: Data output from FC1 does not contribute to..,1: Data output from FC1 does contribute to this.."
newline
bitfld.long 0x00 16. "FC0DATAOUTEN,Controls FC0 contribution to SHAREDDATAOUT for this shared set" "0: Data output from FC0 does not contribute to..,1: Data output from FC0 does contribute to this.."
bitfld.long 0x00 8.--10. "SHAREDDATASEL,Selects the source for DATA input for this shared signal set" "0: DATA input for this shared signal set comes..,1: DATA input for this shared signal set comes..,2: DATA input for this shared signal set comes..,3: DATA input for this shared signal set comes..,4: DATA input for this shared signal set comes..,5: DATA input for this shared signal set comes..,6: DATA input for this shared signal set comes..,7: DATA input for this shared signal set comes.."
newline
bitfld.long 0x00 4.--6. "SHAREDWSSEL,Selects the source for WS of this shared signal set" "0: WS for this shared signal set comes from..,1: WS for this shared signal set comes from..,2: WS for this shared signal set comes from..,3: WS for this shared signal set comes from..,4: WS for this shared signal set comes from..,5: WS for this shared signal set comes from..,6: WS for this shared signal set comes from..,7: WS for this shared signal set comes from.."
bitfld.long 0x00 0.--2. "SHAREDSCKSEL,Selects the source for SCK of this shared signal set" "0: SCK for this shared signal set comes from..,1: SCK for this shared signal set comes from..,2: SCK for this shared signal set comes from..,3: SCK for this shared signal set comes from..,4: SCK for this shared signal set comes from..,5: SCK for this shared signal set comes from..,6: SCK for this shared signal set comes from..,7: SCK for this shared signal set comes from.."
repeat.end
rgroup.long 0x100++0x03
line.long 0x00 "USB_HS_STATUS,Status register for USB HS"
bitfld.long 0x00 0. "USBHS_3V_NOK,USB_HS: Low voltage detection on 3.3V supply" "0: 3v3 supply is good,1: 3v3 supply is too low"
group.long 0x180++0x03
line.long 0x00 "CODE_GRAY_LSB,CODE_GRAY LSB input Register"
hexmask.long 0x00 0.--31. 1. "CODE_GRAY_LSB,Gray code (42bits) to be converted back to binary"
group.long 0x184++0x03
line.long 0x00 "CODE_GRAY_MSB,CODE_GRAY MSB input Register"
hexmask.long.word 0x00 0.--9. 1. "CODE_GRAY_MSB,Gray code (42bits) to be converted back to binary"
rgroup.long 0x188++0x03
line.long 0x00 "CODE_BIN_LSB,CODE_BIN LSB output Register"
hexmask.long 0x00 0.--31. 1. "CODE_BIN_LSB,Binary converted code (42bits)"
rgroup.long 0x18C++0x03
line.long 0x00 "CODE_BIN_MSB,CODE_BIN MSB output Register"
hexmask.long.word 0x00 0.--9. 1. "CODE_BIN_MSB,Binary converted code (42bits)"
tree.end
tree "USART (USARTs)"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0x40086000 ad:0x40087000 ad:0x40088000 ad:0x40089000 ad:0x4008A000 ad:0x40096000 ad:0x40097000 ad:0x40098000)
tree "USART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CFG,USART Configuration register"
bitfld.long 0x00 23. "TXPOL,Transmit data polarity" "0: Standard,1: Inverted"
bitfld.long 0x00 22. "RXPOL,Receive data polarity" "0: Standard,1: Inverted"
newline
bitfld.long 0x00 21. "OEPOL,Output Enable Polarity" "0: Low,1: High"
bitfld.long 0x00 20. "OESEL,Output Enable Select" "0: Standard,1: RS-485"
newline
bitfld.long 0x00 19. "AUTOADDR,Automatic Address matching enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 18. "OETA,Output Enable Turnaround time enable for RS-485 operation" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 15. "LOOP,Selects data loopback mode" "0: Normal operation,1: Loopback mode"
bitfld.long 0x00 14. "SYNCMST,Synchronous mode Master select" "0: Slave,1: Master"
newline
bitfld.long 0x00 12. "CLKPOL,Selects the clock polarity and sampling edge of received data in synchronous mode" "0: Falling edge,1: Rising edge"
bitfld.long 0x00 11. "SYNCEN,Selects synchronous or asynchronous operation" "0: Asynchronous mode,1: Synchronous mode"
newline
bitfld.long 0x00 9. "CTSEN,CTS Enable" "0: No flow control,1: Flow control enabled"
bitfld.long 0x00 8. "LINMODE,LIN break mode enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 7. "MODE32K,Selects standard or 32 kHz clocking mode" "0: Disabled,1: Enabled"
bitfld.long 0x00 6. "STOPLEN,Number of stop bits appended to transmitted data" "0: 1 stop bit,1: 2 stop bits"
newline
bitfld.long 0x00 4.--5. "PARITYSEL,Selects what type of parity is used by the USART" "0: No parity,?,2: Even parity,3: Odd parity"
bitfld.long 0x00 2.--3. "DATALEN,Selects the data size for the USART" "0: 7 bit Data length,1: 8 bit Data length,2: 9 bit data length,?..."
newline
bitfld.long 0x00 0. "ENABLE,USART Enable" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "CTL,USART Control register"
bitfld.long 0x00 16. "AUTOBAUD,Autobaud enable" "0: Disabled,1: Enabled"
bitfld.long 0x00 9. "CLRCCONRX,Clear Continuous Clock" "0: No effect,1: Auto-clear"
newline
bitfld.long 0x00 8. "CC,Continuous Clock generation" "0: Clock on character,1: Continuous clock"
bitfld.long 0x00 6. "TXDIS,Transmit Disable" "0: Not disabled,1: Disabled"
newline
bitfld.long 0x00 2. "ADDRDET,Enable address detect mode" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "TXBRKEN,Break Enable" "0: Normal operation,1: Continuous break"
group.long 0x08++0x03
line.long 0x00 "STAT,USART Status register"
bitfld.long 0x00 16. "ABERR,Auto baud Error" "0,1"
bitfld.long 0x00 15. "RXNOISEINT,Received Noise interrupt flag" "0,1"
newline
bitfld.long 0x00 14. "PARITYERRINT,Parity Error interrupt flag" "0,1"
bitfld.long 0x00 13. "FRAMERRINT,Framing Error interrupt flag" "0,1"
newline
bitfld.long 0x00 12. "START,This bit is set when a start is detected on the receiver input" "0,1"
bitfld.long 0x00 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs" "0,1"
newline
rbitfld.long 0x00 10. "RXBRK,Received Break" "0,1"
rbitfld.long 0x00 6. "TXDISSTAT,Transmitter Disabled Status flag" "0,1"
newline
bitfld.long 0x00 5. "DELTACTS,This bit is set when a change in the state is detected for the CTS flag above" "0,1"
rbitfld.long 0x00 4. "CTS,This bit reflects the current state of the CTS signal regardless of the setting of the CTSEN bit in the CFG register" "0,1"
newline
rbitfld.long 0x00 3. "TXIDLE,Transmitter Idle" "0,1"
rbitfld.long 0x00 1. "RXIDLE,Receiver Idle" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTENSET,Interrupt Enable read and Set register for USART (not FIFO) status"
bitfld.long 0x00 16. "ABERREN,When 1 enables an interrupt when an auto baud error occurs" "0,1"
bitfld.long 0x00 15. "RXNOISEEN,When 1 enables an interrupt when noise is detected" "0,1"
newline
bitfld.long 0x00 14. "PARITYERREN,When 1 enables an interrupt when a parity error has been detected" "0,1"
bitfld.long 0x00 13. "FRAMERREN,When 1 enables an interrupt when a framing error has been detected" "0,1"
newline
bitfld.long 0x00 12. "STARTEN,When 1 enables an interrupt when a received start bit has been detected" "0,1"
bitfld.long 0x00 11. "DELTARXBRKEN,When 1 enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted)" "0,1"
newline
bitfld.long 0x00 6. "TXDISEN,When 1 enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT" "0,1"
bitfld.long 0x00 5. "DELTACTSEN,When 1 enables an interrupt when there is a change in the state of the CTS input" "0,1"
newline
bitfld.long 0x00 3. "TXIDLEEN,When 1 enables an interrupt when the transmitter becomes idle (TXIDLE = 1)" "0,1"
wgroup.long 0x10++0x03
line.long 0x00 "INTENCLR,Interrupt Enable Clear register"
bitfld.long 0x00 16. "ABERRCLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 15. "RXNOISECLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 14. "PARITYERRCLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 13. "FRAMERRCLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 12. "STARTCLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 11. "DELTARXBRKCLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 6. "TXDISCLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
bitfld.long 0x00 5. "DELTACTSCLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
newline
bitfld.long 0x00 3. "TXIDLECLR,Writing 1 clears the corresponding bit in the INTENSET register" "0,1"
group.long 0x20++0x03
line.long 0x00 "BRG,Baud Rate Generator register"
abitfld.long 0x00 0.--15. "BRGVAL,This value is used to divide the USART input clock to determine the baud rate based on the input clock from the FRG" "0x0000=0: FCLK is used directly by the USART..,0x0001=1: FCLK is divided by 2 before use by the..,0x0002=2: FCLK is divided by 3 before use by the..,0xFFFF=65535: FCLK is divided by 65 536 before.."
rgroup.long 0x24++0x03
line.long 0x00 "INTSTAT,Interrupt status register"
bitfld.long 0x00 16. "ABERRINT,Auto baud Error Interrupt flag" "0,1"
bitfld.long 0x00 15. "RXNOISEINT,Received Noise interrupt flag" "0,1"
newline
bitfld.long 0x00 14. "PARITYERRINT,Parity Error interrupt flag" "0,1"
bitfld.long 0x00 13. "FRAMERRINT,Framing Error interrupt flag" "0,1"
newline
bitfld.long 0x00 12. "START,This bit is set when a start is detected on the receiver input" "0,1"
bitfld.long 0x00 11. "DELTARXBRK,This bit is set when a change in the state of receiver break detection occurs" "0,1"
newline
bitfld.long 0x00 6. "TXDISINT,Transmitter Disabled Interrupt flag" "0,1"
bitfld.long 0x00 5. "DELTACTS,This bit is set when a change in the state of the CTS input is detected" "0,1"
newline
bitfld.long 0x00 3. "TXIDLE,Transmitter Idle status" "0,1"
group.long 0x28++0x03
line.long 0x00 "OSR,Oversample selection register for asynchronous communication"
bitfld.long 0x00 0.--3. "OSRVAL,Oversample Selection Value" "?,?,?,3: not supported,4: 5 function clocks are used to transmit and,5: 6 function clocks are used to transmit and,?,?,?,?,?,?,?,?,?,15: 16 function clocks are used to transmit and"
group.long 0x2C++0x03
line.long 0x00 "ADDR,Address register for automatic address matching"
hexmask.long.byte 0x00 0.--7. 1. "ADDRESS,8-bit address used with automatic address matching"
group.long 0xE00++0x03
line.long 0x00 "FIFOCFG,FIFO configuration and enable register"
bitfld.long 0x00 17. "EMPTYRX,Empty command for the receive FIFO" "0,1"
bitfld.long 0x00 16. "EMPTYTX,Empty command for the transmit FIFO" "0,1"
newline
bitfld.long 0x00 15. "WAKERX,Wake-up for receive FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
bitfld.long 0x00 14. "WAKETX,Wake-up for transmit FIFO level" "0: Only enabled interrupts will wake up the..,1: A device wake-up for DMA will occur if the.."
newline
bitfld.long 0x00 13. "DMARX,DMA configuration for receive" "0: DMA is not used for the receive function,1: Trigger DMA for the receive function if the.."
bitfld.long 0x00 12. "DMATX,DMA configuration for transmit" "0: DMA is not used for the transmit function,1: Trigger DMA for the transmit function if the.."
newline
rbitfld.long 0x00 4.--5. "SIZE,FIFO size configuration" "0: FIFO is configured as 16 entries of 8 bits,?,?,3: not applicable to USART"
bitfld.long 0x00 1. "ENABLERX,Enable the receive FIFO" "0: The receive FIFO is not enabled,1: The receive FIFO is enabled"
newline
bitfld.long 0x00 0. "ENABLETX,Enable the transmit FIFO" "0: The transmit FIFO is not enabled,1: The transmit FIFO is enabled"
group.long 0xE04++0x03
line.long 0x00 "FIFOSTAT,FIFO status register"
rbitfld.long 0x00 16.--20. "RXLVL,Receive FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 8.--12. "TXLVL,Transmit FIFO current level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 7. "RXFULL,Receive FIFO full" "0,1"
rbitfld.long 0x00 6. "RXNOTEMPTY,Receive FIFO not empty" "0,1"
newline
rbitfld.long 0x00 5. "TXNOTFULL,Transmit FIFO not full" "0,1"
rbitfld.long 0x00 4. "TXEMPTY,Transmit FIFO empty" "0,1"
newline
rbitfld.long 0x00 3. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
group.long 0xE08++0x03
line.long 0x00 "FIFOTRIG,FIFO trigger settings for interrupt and DMA request"
bitfld.long 0x00 16.--19. "RXLVL,Receive FIFO level trigger point" "0: trigger when the RX FIFO has received one entry,1: trigger when the RX FIFO has received two..,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the RX FIFO has received 16.."
bitfld.long 0x00 8.--11. "TXLVL,Transmit FIFO level trigger point" "0: trigger when the TX FIFO becomes empty,1: trigger when the TX FIFO level decreases to one,?,?,?,?,?,?,?,?,?,?,?,?,?,15: trigger when the TX FIFO level decreases to 15"
newline
bitfld.long 0x00 1. "RXLVLENA,Receive FIFO level trigger enable" "0: Receive FIFO level does not generate a FIFO..,1: An trigger will be generated if the receive.."
bitfld.long 0x00 0. "TXLVLENA,Transmit FIFO level trigger enable" "0: Transmit FIFO level does not generate a FIFO..,1: An trigger will be generated if the transmit.."
group.long 0xE10++0x03
line.long 0x00 "FIFOINTENSET,FIFO interrupt enable set (enable) and read register"
bitfld.long 0x00 3. "RXLVL,Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If RXLVLENA in the FIFOTRIG register = 1 an.."
bitfld.long 0x00 2. "TXLVL,Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register" "0: No interrupt will be generated based on the..,1: If TXLVLENA in the FIFOTRIG register = 1 an.."
newline
bitfld.long 0x00 1. "RXERR,Determines whether an interrupt occurs when a receive error occurs based on the RXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a receive..,1: An interrupt will be generated when a receive.."
bitfld.long 0x00 0. "TXERR,Determines whether an interrupt occurs when a transmit error occurs based on the TXERR flag in the FIFOSTAT register" "0: No interrupt will be generated for a transmit..,1: An interrupt will be generated when a.."
group.long 0xE14++0x03
line.long 0x00 "FIFOINTENCLR,FIFO interrupt enable clear (disable) and read register"
bitfld.long 0x00 3. "RXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 2. "TXLVL,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
newline
bitfld.long 0x00 1. "RXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
bitfld.long 0x00 0. "TXERR,Writing one clears the corresponding bits in the FIFOINTENSET register" "0,1"
rgroup.long 0xE18++0x03
line.long 0x00 "FIFOINTSTAT,FIFO interrupt status register"
bitfld.long 0x00 4. "PERINT,Peripheral interrupt" "0,1"
bitfld.long 0x00 3. "RXLVL,Receive FIFO level interrupt" "0,1"
newline
bitfld.long 0x00 2. "TXLVL,Transmit FIFO level interrupt" "0,1"
bitfld.long 0x00 1. "RXERR,RX FIFO error" "0,1"
newline
bitfld.long 0x00 0. "TXERR,TX FIFO error" "0,1"
wgroup.long 0xE20++0x03
line.long 0x00 "FIFOWR,FIFO write data"
hexmask.long.word 0x00 0.--8. 1. "TXDATA,Transmit data to the FIFO"
rgroup.long 0xE30++0x03
line.long 0x00 "FIFORD,FIFO read data"
bitfld.long 0x00 15. "RXNOISE,Received Noise flag" "0,1"
bitfld.long 0x00 14. "PARITYERR,Parity Error status flag" "0,1"
newline
bitfld.long 0x00 13. "FRAMERR,Framing Error status flag" "0,1"
hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received data from the FIFO"
rgroup.long 0xE40++0x03
line.long 0x00 "FIFORDNOPOP,FIFO data read with no FIFO pop"
bitfld.long 0x00 15. "RXNOISE,Received Noise flag" "0,1"
bitfld.long 0x00 14. "PARITYERR,Parity Error status flag" "0,1"
newline
bitfld.long 0x00 13. "FRAMERR,Framing Error status flag" "0,1"
hexmask.long.word 0x00 0.--8. 1. "RXDATA,Received data from the FIFO"
group.long 0xE48++0x03
line.long 0x00 "FIFOSIZE,FIFO size register"
rbitfld.long 0x00 0.--4. "FIFOSIZE,Provides the size of the FIFO for software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
rbitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFC++0x03
line.long 0x00 "ID,Peripheral identification register"
hexmask.long.word 0x00 16.--31. 1. "ID,Module identifier for the selected function"
bitfld.long 0x00 12.--15. "MAJOR_REV,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "MINOR_REV,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "APERTURE,Aperture: encoded as (aperture size/4K) -1 so 0x00 means a 4K aperture"
tree.end
repeat.end
tree.end
sif cpuis("LPC55S16*")||cpuis("LPC55S14*")||cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
tree "USB (Universal Serial Bus)"
base ad:0x40084000
group.long 0x00++0x03
line.long 0x00 "DEVCMDSTAT,USB Device Command/Status register"
rbitfld.long 0x00 28. "VBUSDEBOUNCED,This bit indicates if Vbus is detected or not" "0,1"
bitfld.long 0x00 26. "DRES_C,Device status - reset change" "0,1"
newline
bitfld.long 0x00 25. "DSUS_C,Device status - suspend change" "0,1"
bitfld.long 0x00 24. "DCON_C,Device status - connect change" "0,1"
newline
rbitfld.long 0x00 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host" "0,1"
bitfld.long 0x00 19. "LPM_SUS,Device status - LPM Suspend" "0,1"
newline
bitfld.long 0x00 17. "DSUS,Device status - suspend" "0,1"
bitfld.long 0x00 16. "DCON,Device status - connect" "0,1"
newline
bitfld.long 0x00 15. "INTONNAK_CI,Interrupt on NAK for control IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
bitfld.long 0x00 14. "INTONNAK_CO,Interrupt on NAK for control OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
newline
bitfld.long 0x00 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
bitfld.long 0x00 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP" "0: Only acknowledged packets generate an interrupt,1: Both acknowledged and NAKed packets generate.."
newline
bitfld.long 0x00 11. "LPM_SUP,LPM Supported" "0: LPM not supported,1: LPM supported"
bitfld.long 0x00 9. "FORCE_NEEDCLK,Forces the NEEDCLK output to always be on" "0: USB_NEEDCLK has normal function,1: USB_NEEDCLK always 1"
newline
bitfld.long 0x00 8. "SETUP,SETUP token received" "0,1"
bitfld.long 0x00 7. "DEV_EN,USB device enable" "0,1"
newline
hexmask.long.byte 0x00 0.--6. 1. "DEV_ADDR,USB device address"
group.long 0x04++0x03
line.long 0x00 "INFO,USB Info register"
hexmask.long.byte 0x00 24.--31. 1. "MAJREV,Major Revision"
hexmask.long.byte 0x00 16.--23. 1. "MINREV,Minor Revision"
newline
bitfld.long 0x00 11.--14. "ERR_CODE,The error code which last occurred" "0: NO_ERROR,1: PID_ENCODING_ERROR,2: PID_UNKNOWN,3: PACKET_UNEXPECTED,4: TOKEN_CRC_ERROR,5: DATA_CRC_ERROR,6: Time out,7: BABBLE,8: TRUNCATED_EOP,9: SENT_RECEIVED_NAK,10: SENT_STALL,11: OVERRUN,12: SENT_EMPTY_PACKET,13: BITSTUFF_ERROR,14: SYNC_ERROR,15: WRONG_DATA_TOGGLE"
hexmask.long.word 0x00 0.--10. 1. "FRAME_NR,Frame number"
group.long 0x08++0x03
line.long 0x00 "EPLISTSTART,USB EP Command/Status List start address"
hexmask.long.tbyte 0x00 8.--31. 1. "EP_LIST,Start address of the USB EP Command/Status List"
group.long 0x0C++0x03
line.long 0x00 "DATABUFSTART,USB Data buffer start address"
hexmask.long.word 0x00 22.--31. 1. "DA_BUF,Start address of the buffer pointer page where all endpoint data buffers are located"
group.long 0x10++0x03
line.long 0x00 "LPM,USB Link Power Management register"
bitfld.long 0x00 8. "DATA_PENDING,As long as this bit is set to one and LPM supported bit is set to one HW will return a NYET handshake on every LPM token it receives" "0,1"
bitfld.long 0x00 4.--7. "HIRD_SW,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 0.--3. "HIRD_HW,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "EPSKIP,USB Endpoint skip"
hexmask.long.word 0x00 0.--9. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software"
group.long 0x18++0x03
line.long 0x00 "EPINUSE,USB Endpoint Buffer in use"
abitfld.long 0x00 2.--9. "BUF,Buffer in use: This register has one bit per physical endpoint" "0x00=0: HW is accessing buffer 0,0x01=1: HW is accessing buffer 1"
group.long 0x1C++0x03
line.long 0x00 "EPBUFCFG,USB Endpoint Buffer Configuration register"
abitfld.long 0x00 2.--9. "BUF_SB,Buffer usage: This register has one bit per physical endpoint" "0x00=0: Single-buffer,0x01=1: Double-buffer"
group.long 0x20++0x03
line.long 0x00 "INTSTAT,USB interrupt status register"
bitfld.long 0x00 31. "DEV_INT,Device status interrupt" "0,1"
bitfld.long 0x00 30. "FRAME_INT,Frame interrupt" "0,1"
newline
bitfld.long 0x00 9. "EP4IN,Interrupt status register bit for the EP4 IN direction" "0,1"
bitfld.long 0x00 8. "EP4OUT,Interrupt status register bit for the EP4 OUT direction" "0,1"
newline
bitfld.long 0x00 7. "EP3IN,Interrupt status register bit for the EP3 IN direction" "0,1"
bitfld.long 0x00 6. "EP3OUT,Interrupt status register bit for the EP3 OUT direction" "0,1"
newline
bitfld.long 0x00 5. "EP2IN,Interrupt status register bit for the EP2 IN direction" "0,1"
bitfld.long 0x00 4. "EP2OUT,Interrupt status register bit for the EP2 OUT direction" "0,1"
newline
bitfld.long 0x00 3. "EP1IN,Interrupt status register bit for the EP1 IN direction" "0,1"
bitfld.long 0x00 2. "EP1OUT,Interrupt status register bit for the EP1 OUT direction" "0,1"
newline
bitfld.long 0x00 1. "EP0IN,Interrupt status register bit for the Control EP0 IN direction" "0,1"
bitfld.long 0x00 0. "EP0OUT,Interrupt status register bit for the Control EP0 OUT direction" "0,1"
group.long 0x24++0x03
line.long 0x00 "INTEN,USB interrupt enable register"
bitfld.long 0x00 31. "DEV_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" "0,1"
bitfld.long 0x00 30. "FRAME_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit" "0,1"
newline
hexmask.long.word 0x00 0.--9. 1. "EP_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit"
group.long 0x28++0x03
line.long 0x00 "INTSETSTAT,USB set interrupt status register"
bitfld.long 0x00 31. "DEV_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1"
bitfld.long 0x00 30. "FRAME_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1"
newline
hexmask.long.word 0x00 0.--9. 1. "EP_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set"
group.long 0x34++0x03
line.long 0x00 "EPTOGGLE,USB Endpoint toggle register"
hexmask.long.word 0x00 0.--9. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint"
tree.end
tree "USBFSH (USB0 Full-speed Host controller)"
base ad:0x400A2000
rgroup.long 0x00++0x03
line.long 0x00 "HCREVISION,BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC)"
hexmask.long.byte 0x00 0.--7. 1. "REV,Revision"
group.long 0x04++0x03
line.long 0x00 "HCCONTROL,Defines the operating modes of the HC"
bitfld.long 0x00 10. "RWE,RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling" "0,1"
bitfld.long 0x00 9. "RWC,RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling" "0,1"
bitfld.long 0x00 8. "IR,InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus" "0,1"
bitfld.long 0x00 6.--7. "HCFS,HostControllerFunctionalState for USB" "0: USBRESET,1: USBRESUME,2: USBOPERATIONAL,3: USBSUSPEND A transition to"
bitfld.long 0x00 5. "BLE,BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame" "0,1"
bitfld.long 0x00 4. "CLE,ControlListEnable" "0,1"
newline
bitfld.long 0x00 3. "IE,IsochronousEnable" "0,1"
bitfld.long 0x00 2. "PLE,PeriodicListEnable" "0,1"
bitfld.long 0x00 0.--1. "CBSR,ControlBulkServiceRatio" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "HCCOMMANDSTATUS,This register is used to receive the commands from the Host Controller Driver (HCD)"
bitfld.long 0x00 6.--7. "SOC,SchedulingOverrunCount These bits are incremented on each scheduling overrun error" "0,1,2,3"
bitfld.long 0x00 3. "OCR,OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC" "0,1"
bitfld.long 0x00 2. "BLF,BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list" "0,1"
bitfld.long 0x00 1. "CLF,ControlListFilled This bit is used to indicate whether there are any TDs on the Control list" "0,1"
bitfld.long 0x00 0. "HCR,HostControllerReset This bit is set by HCD to initiate a software reset of HC" "0,1"
group.long 0x0C++0x03
line.long 0x00 "HCINTERRUPTSTATUS,Indicates the status on various events that cause hardware interrupts by setting the appropriate bits"
hexmask.long.tbyte 0x00 10.--31. 1. "OC,OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus"
bitfld.long 0x00 6. "RHSC,RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed" "0,1"
bitfld.long 0x00 5. "FNO,FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value from 0 to 1 or from 1 to 0 and after HccaFrameNumber has been updated" "0,1"
bitfld.long 0x00 4. "UE,UnrecoverableError This bit is set when HC detects a system error not related to USB" "0,1"
bitfld.long 0x00 3. "RD,ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling" "0,1"
bitfld.long 0x00 2. "SF,StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber" "0,1"
newline
bitfld.long 0x00 1. "WDH,WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead" "0,1"
bitfld.long 0x00 0. "SO,SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber" "0,1"
group.long 0x10++0x03
line.long 0x00 "HCINTERRUPTENABLE,Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt"
bitfld.long 0x00 31. "MIE,Master Interrupt Enable" "0,1"
bitfld.long 0x00 30. "OC,Ownership Change interrupt" "0,1"
bitfld.long 0x00 6. "RHSC,Root Hub Status Change interrupt" "0,1"
bitfld.long 0x00 5. "FNO,Frame Number Overflow interrupt" "0,1"
bitfld.long 0x00 4. "UE,Unrecoverable Error interrupt" "0,1"
bitfld.long 0x00 3. "RD,Resume Detect interrupt" "0,1"
newline
bitfld.long 0x00 2. "SF,Start of Frame interrupt" "0,1"
bitfld.long 0x00 1. "WDH,HcDoneHead Writeback interrupt" "0,1"
bitfld.long 0x00 0. "SO,Scheduling Overrun interrupt" "0,1"
group.long 0x14++0x03
line.long 0x00 "HCINTERRUPTDISABLE,The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt"
bitfld.long 0x00 31. "MIE,A 0 written to this field is ignored by HC" "0,1"
bitfld.long 0x00 30. "OC,Ownership Change interrupt" "0,1"
bitfld.long 0x00 6. "RHSC,Root Hub Status Change interrupt" "0,1"
bitfld.long 0x00 5. "FNO,Frame Number Overflow interrupt" "0,1"
bitfld.long 0x00 4. "UE,Unrecoverable Error interrupt" "0,1"
bitfld.long 0x00 3. "RD,Resume Detect interrupt" "0,1"
newline
bitfld.long 0x00 2. "SF,Start of Frame interrupt" "0,1"
bitfld.long 0x00 1. "WDH,HcDoneHead Writeback interrupt" "0,1"
bitfld.long 0x00 0. "SO,Scheduling Overrun interrupt" "0,1"
group.long 0x18++0x03
line.long 0x00 "HCHCCA,Contains the physical address of the host controller communication area"
hexmask.long.tbyte 0x00 8.--31. 1. "HCCA,Base address of the Host Controller Communication Area"
group.long 0x1C++0x03
line.long 0x00 "HCPERIODCURRENTED,Contains the physical address of the current isochronous or interrupt endpoint descriptor"
hexmask.long 0x00 4.--31. 1. "PCED,The content of this register is updated by HC after a periodic ED is processed"
group.long 0x20++0x03
line.long 0x00 "HCCONTROLHEADED,Contains the physical address of the first endpoint descriptor of the control list"
hexmask.long 0x00 4.--31. 1. "CHED,HC traverses the Control list starting with the HcControlHeadED pointer"
group.long 0x24++0x03
line.long 0x00 "HCCONTROLCURRENTED,Contains the physical address of the current endpoint descriptor of the control list"
hexmask.long 0x00 4.--31. 1. "CCED,ControlCurrentED"
group.long 0x28++0x03
line.long 0x00 "HCBULKHEADED,Contains the physical address of the first endpoint descriptor of the bulk list"
hexmask.long 0x00 4.--31. 1. "BHED,BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer"
group.long 0x2C++0x03
line.long 0x00 "HCBULKCURRENTED,Contains the physical address of the current endpoint descriptor of the bulk list"
hexmask.long 0x00 4.--31. 1. "BCED,BulkCurrentED This is advanced to the next ED after the HC has served the current one"
group.long 0x30++0x03
line.long 0x00 "HCDONEHEAD,Contains the physical address of the last transfer descriptor added to the 'Done' queue"
hexmask.long 0x00 4.--31. 1. "DH,DoneHead When a TD is completed HC writes the content of HcDoneHead to the NextTD field of the TD"
group.long 0x34++0x03
line.long 0x00 "HCFMINTERVAL,Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun"
bitfld.long 0x00 31. "FIT,FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval" "0,1"
hexmask.long.word 0x00 16.--30. 1. "FSMPS,FSLargestDataPacket This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame"
hexmask.long.word 0x00 0.--13. 1. "FI,FrameInterval This specifies the interval between two consecutive SOFs in bit times"
group.long 0x38++0x03
line.long 0x00 "HCFMREMAINING,A 14-bit counter showing the bit time remaining in the current frame"
rbitfld.long 0x00 31. "FRT,FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0" "0,1"
hexmask.long.word 0x00 0.--13. 1. "FR,FrameRemaining This counter is decremented at each bit time"
group.long 0x3C++0x03
line.long 0x00 "HCFMNUMBER,Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD"
hexmask.long.word 0x00 0.--15. 1. "FN,FrameNumber This is incremented when HcFmRemaining is re-loaded"
group.long 0x40++0x03
line.long 0x00 "HCPERIODICSTART,Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list"
hexmask.long.word 0x00 0.--13. 1. "PS,PeriodicStart After a hardware reset this field is cleared and then set by HCD during the HC initialization"
group.long 0x44++0x03
line.long 0x00 "HCLSTHRESHOLD,Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF"
hexmask.long.word 0x00 0.--11. 1. "LST,LSThreshold This field contains a value which is compared to the FrameRemaining field prior to initiating a Low Speed transaction"
group.long 0x48++0x03
line.long 0x00 "HCRHDESCRIPTORA,First of the two registers which describes the characteristics of the root hub"
hexmask.long.byte 0x00 24.--31. 1. "POTPGT,PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before accessing a powered-on port of the root hub"
bitfld.long 0x00 12. "NOCP,NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported" "0,1"
bitfld.long 0x00 11. "OCPM,OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported" "0,1"
bitfld.long 0x00 10. "DT,DeviceType This bit specifies that the root hub is not a compound device" "0,1"
bitfld.long 0x00 9. "NPS,NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered" "0,1"
bitfld.long 0x00 8. "PSM,PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "NDP,NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub"
group.long 0x4C++0x03
line.long 0x00 "HCRHDESCRIPTORB,Second of the two registers which describes the characteristics of the Root Hub"
hexmask.long.word 0x00 16.--31. 1. "PPCM,PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set"
hexmask.long.word 0x00 0.--15. 1. "DR,DeviceRemovable Each bit is dedicated to a port of the Root Hub"
group.long 0x50++0x03
line.long 0x00 "HCRHSTATUS,This register is divided into two parts"
bitfld.long 0x00 31. "CRWE,(write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable" "0,1"
bitfld.long 0x00 17. "OCIC,OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register" "0,1"
bitfld.long 0x00 16. "LPSC,(read) LocalPowerStatusChange The root hub does not support the local power status feature" "0,1"
bitfld.long 0x00 15. "DRWE,(read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected interrupt" "0,1"
bitfld.long 0x00 1. "OCI,OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented" "0,1"
bitfld.long 0x00 0. "LPS,(read) LocalPowerStatus The Root Hub does not support the local power status feature thus this bit is always read as 0" "0,1"
group.long 0x54++0x03
line.long 0x00 "HCRHPORTSTATUS,Controls and reports the port events on a per-port basis"
bitfld.long 0x00 20. "PRSC,PortResetStatusChange This bit is set at the end of the 10 ms port reset signal" "0,1"
bitfld.long 0x00 19. "OCIC,PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis" "0,1"
bitfld.long 0x00 18. "PSSC,PortSuspendStatusChange This bit is set when the full resume sequence is completed" "0,1"
bitfld.long 0x00 17. "PESC,PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared" "0,1"
bitfld.long 0x00 16. "CSC,ConnectStatusChange This bit is set whenever a connect or disconnect event occurs" "0,1"
bitfld.long 0x00 9. "LSDA,(read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port" "0,1"
newline
bitfld.long 0x00 8. "PPS,(read) PortPowerStatus This bit reflects the porta's power status regardless of the type of power switching implemented" "0,1"
bitfld.long 0x00 4. "PRS,(read) PortResetStatus When this bit is set by a write to SetPortReset port reset signaling is asserted" "0,1"
bitfld.long 0x00 3. "POCI,(read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis" "0,1"
bitfld.long 0x00 2. "PSS,(read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence" "0,1"
bitfld.long 0x00 1. "PES,(read) PortEnableStatus This bit indicates whether the port is enabled or disabled" "0,1"
bitfld.long 0x00 0. "CCS,(read) CurrentConnectStatus This bit reflects the current state of the downstream port" "0,1"
group.long 0x5C++0x03
line.long 0x00 "PORTMODE,Controls the port if it is attached to the host block or the device block"
bitfld.long 0x00 16. "DEV_ENABLE," "0,1"
bitfld.long 0x00 8. "ID_EN,Port ID pin pull-up enable" "0,1"
bitfld.long 0x00 0. "ID,Port ID pin value" "0,1"
tree.end
tree "USBHSD (USB1 High-speed Device Controller)"
base ad:0x40094000
group.long 0x00++0x03
line.long 0x00 "DEVCMDSTAT,USB Device Command/Status register"
bitfld.long 0x00 29.--31. "PHY_TEST_MODE,This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification" "0: Test mode disabled,1: Test_J,2: Test_K,3: Test_SE0_NAK,4: Test_Packet,5: Test_Force_Enable,?..."
rbitfld.long 0x00 28. "VBUS_DEBOUNCED,This bit indicates if VBUS is detected or not" "0,1"
bitfld.long 0x00 26. "DRES_C,Device status - reset change" "0,1"
bitfld.long 0x00 25. "DSUS_C,Device status - suspend change" "0,1"
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bitfld.long 0x00 24. "DCON_C,Device status - connect change" "0,1"
rbitfld.long 0x00 22.--23. "Speed,This field indicates the speed at which the device operates" "0: reserved,1: full-speed,2: high-speed,3: super-speed (reserved for"
rbitfld.long 0x00 20. "LPM_REWP,LPM Remote Wake-up Enabled by USB host" "0,1"
bitfld.long 0x00 19. "LPM_SUS,Device status - LPM Suspend" "0,1"
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bitfld.long 0x00 17. "DSUS,Device status - suspend" "0,1"
bitfld.long 0x00 16. "DCON,Device status - connect" "0,1"
bitfld.long 0x00 15. "INTONNAK_CI,Interrupt on NAK for control IN EP" "0,1"
bitfld.long 0x00 14. "INTONNAK_CO,Interrupt on NAK for control OUT EP" "0,1"
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bitfld.long 0x00 13. "INTONNAK_AI,Interrupt on NAK for interrupt and bulk IN EP" "0,1"
bitfld.long 0x00 12. "INTONNAK_AO,Interrupt on NAK for interrupt and bulk OUT EP" "0,1"
bitfld.long 0x00 11. "LPM_SUP,LPM Supported" "0,1"
bitfld.long 0x00 9. "FORCE_NEEDCLK,Forces the NEEDCLK output to always be on" "0,1"
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bitfld.long 0x00 8. "SETUP,SETUP token received" "0,1"
bitfld.long 0x00 7. "DEV_EN,USB device enable" "0,1"
hexmask.long.byte 0x00 0.--6. 1. "DEV_ADDR,USB device address"
rgroup.long 0x04++0x03
line.long 0x00 "INFO,USB Info register"
hexmask.long.byte 0x00 24.--31. 1. "MAJREV,Major revision"
hexmask.long.byte 0x00 16.--23. 1. "MINREV,Minor revision"
bitfld.long 0x00 11.--14. "ERR_CODE,The error code which last occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "FRAME_NR,Frame number"
group.long 0x08++0x03
line.long 0x00 "EPLISTSTART,USB EP Command/Status List start address"
hexmask.long.word 0x00 20.--31. 1. "EP_LIST_FIXED,Fixed portion of USB EP Command/Status List address"
hexmask.long.word 0x00 8.--19. 1. "EP_LIST_PRG,Programmable portion of the USB EP Command/Status List address"
group.long 0x0C++0x03
line.long 0x00 "DATABUFSTART,USB Data buffer start address"
hexmask.long 0x00 0.--31. 1. "DA_BUF,Start address of the memory page where all endpoint data buffers are located"
group.long 0x10++0x03
line.long 0x00 "LPM,USB Link Power Management register"
bitfld.long 0x00 8. "DATA_PENDING,As long as this bit is set to one and LPM supported bit is set to one HW will return a NYET handshake on every LPM token it receives" "0,1"
bitfld.long 0x00 4.--7. "HIRD_SW,Host Initiated Resume Duration - SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "HIRD_HW,Host Initiated Resume Duration - HW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "EPSKIP,USB Endpoint skip"
hexmask.long.word 0x00 0.--11. 1. "SKIP,Endpoint skip: Writing 1 to one of these bits will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software"
group.long 0x18++0x03
line.long 0x00 "EPINUSE,USB Endpoint Buffer in use"
hexmask.long.word 0x00 2.--11. 1. "BUF,Buffer in use: This register has one bit per physical endpoint"
group.long 0x1C++0x03
line.long 0x00 "EPBUFCFG,USB Endpoint Buffer Configuration register"
hexmask.long.word 0x00 2.--11. 1. "BUF_SB,Buffer usage: This register has one bit per physical endpoint"
group.long 0x20++0x03
line.long 0x00 "INTSTAT,USB interrupt status register"
bitfld.long 0x00 31. "DEV_INT,Device status interrupt" "0,1"
bitfld.long 0x00 30. "FRAME_INT,Frame interrupt" "0,1"
bitfld.long 0x00 11. "EP5IN,Interrupt status register bit for the EP5 IN direction" "0,1"
bitfld.long 0x00 10. "EP5OUT,Interrupt status register bit for the EP5 OUT direction" "0,1"
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bitfld.long 0x00 9. "EP4IN,Interrupt status register bit for the EP4 IN direction" "0,1"
bitfld.long 0x00 8. "EP4OUT,Interrupt status register bit for the EP4 OUT direction" "0,1"
bitfld.long 0x00 7. "EP3IN,Interrupt status register bit for the EP3 IN direction" "0,1"
bitfld.long 0x00 6. "EP3OUT,Interrupt status register bit for the EP3 OUT direction" "0,1"
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bitfld.long 0x00 5. "EP2IN,Interrupt status register bit for the EP2 IN direction" "0,1"
bitfld.long 0x00 4. "EP2OUT,Interrupt status register bit for the EP2 OUT direction" "0,1"
bitfld.long 0x00 3. "EP1IN,Interrupt status register bit for the EP1 IN direction" "0,1"
bitfld.long 0x00 2. "EP1OUT,Interrupt status register bit for the EP1 OUT direction" "0,1"
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bitfld.long 0x00 1. "EP0IN,Interrupt status register bit for the Control EP0 IN direction" "0,1"
bitfld.long 0x00 0. "EP0OUT,Interrupt status register bit for the Control EP0 OUT direction" "0,1"
group.long 0x24++0x03
line.long 0x00 "INTEN,USB interrupt enable register"
bitfld.long 0x00 31. "DEV_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line" "0,1"
bitfld.long 0x00 30. "FRAME_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line" "0,1"
hexmask.long.word 0x00 0.--11. 1. "EP_INT_EN,If this bit is set and the corresponding USB interrupt status bit is set a HW interrupt is generated on the interrupt line"
group.long 0x28++0x03
line.long 0x00 "INTSETSTAT,USB set interrupt status register"
bitfld.long 0x00 31. "DEV_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1"
bitfld.long 0x00 30. "FRAME_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set" "0,1"
hexmask.long.word 0x00 0.--11. 1. "EP_SET_INT,If software writes a one to one of these bits the corresponding USB interrupt status bit is set"
rgroup.long 0x34++0x03
line.long 0x00 "EPTOGGLE,USB Endpoint toggle register"
hexmask.long 0x00 0.--29. 1. "TOGGLE,Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint"
tree.end
tree "USBHSH (USB1 High-speed Host Controller)"
base ad:0x400A3000
rgroup.long 0x00++0x03
line.long 0x00 "CAPLENGTH_CHIPID,This register contains the offset value towards the start of the operational register space and the version number of the IP block"
hexmask.long.word 0x00 16.--31. 1. "CHIPID,Chip identification: indicates major and minor revision of the IP: [31:24] = Major revision [23:16] = Minor revision Major revisions used"
hexmask.long.byte 0x00 0.--7. 1. "CAPLENGTH,Capability Length: This is used as an offset"
rgroup.long 0x04++0x03
line.long 0x00 "HCSPARAMS,Host Controller Structural Parameters"
bitfld.long 0x00 16. "P_INDICATOR,This bit indicates whether the ports support port indicator control" "0,1"
bitfld.long 0x00 4. "PPC,This field indicates whether the host controller implementation includes port power control" "0,1"
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bitfld.long 0x00 0.--3. "N_PORTS,This register specifies the number of physical downstream ports implemented on this host controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x08++0x03
line.long 0x00 "HCCPARAMS,Host Controller Capability Parameters"
bitfld.long 0x00 17. "LPMC,Link Power Management Capability" "0,1"
group.long 0x0C++0x03
line.long 0x00 "FLADJ_FRINDEX,Frame Length Adjustment"
hexmask.long.word 0x00 16.--29. 1. "FRINDEX,Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet"
bitfld.long 0x00 0.--5. "FLADJ,Frame Length Timing Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "ATLPTD,Memory base address where ATL PTD0 is stored"
hexmask.long.tbyte 0x00 9.--31. 1. "ATL_BASE,Base address to be used by the hardware to find the start of the ATL list"
bitfld.long 0x00 4.--8. "ATL_CUR,This indicates the current PTD that is used by the hardware when it is processing the ATL list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x14++0x03
line.long 0x00 "ISOPTD,Memory base address where ISO PTD0 is stored"
hexmask.long.tbyte 0x00 10.--31. 1. "ISO_BASE,Base address to be used by the hardware to find the start of the ISO list"
bitfld.long 0x00 5.--9. "ISO_FIRST,This indicates the first PTD that is used by the hardware when it is processing the ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x18++0x03
line.long 0x00 "INTPTD,Memory base address where INT PTD0 is stored"
hexmask.long.tbyte 0x00 10.--31. 1. "INT_BASE,Base address to be used by the hardware to find the start of the INT list"
bitfld.long 0x00 5.--9. "INT_FIRST,This indicates the first PTD that is used by the hardware when it is processing the INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C++0x03
line.long 0x00 "DATAPAYLOAD,Memory base address that indicates the start of the data payload buffers"
hexmask.long.word 0x00 16.--31. 1. "DAT_BASE,Base address to be used by the hardware to find the start of the data payload section"
group.long 0x20++0x03
line.long 0x00 "USBCMD,USB Command register"
bitfld.long 0x00 10. "INT_EN,INT List enabled" "0,1"
bitfld.long 0x00 9. "ISO_EN,ISO List enabled" "0,1"
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bitfld.long 0x00 8. "ATL_EN,ATL List enabled" "0,1"
bitfld.long 0x00 7. "LHCR,Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports" "0,1"
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bitfld.long 0x00 2.--3. "FLS,Frame List Size: This field specifies the size of the frame list" "0,1,2,3"
bitfld.long 0x00 1. "HCRESET,Host Controller Reset: This control bit is used by the software to reset the host controller" "0,1"
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bitfld.long 0x00 0. "RS,Run/Stop" "0,1"
group.long 0x20++0x03
line.long 0x00 "USBCMD,USB Command register"
bitfld.long 0x00 28. "LPM_RWU,bRemoteWake field" "0,1"
bitfld.long 0x00 24.--27. "HIRD,Host-Initiated Resume Duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10. "INT_EN,INT List enabled" "0,1"
bitfld.long 0x00 9. "ISO_EN,ISO List enabled" "0,1"
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bitfld.long 0x00 8. "ATL_EN,ATL List enabled" "0,1"
bitfld.long 0x00 7. "LHCR,Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports" "0,1"
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bitfld.long 0x00 2.--3. "FLS,Frame List Size: This field specifies the size of the frame list" "0,1,2,3"
bitfld.long 0x00 1. "HCRESET,Host Controller Reset: This control bit is used by the software to reset the host controller" "0,1"
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bitfld.long 0x00 0. "RS,Run/Stop" "0,1"
group.long 0x24++0x03
line.long 0x00 "USBSTS,USB Interrupt Status register"
bitfld.long 0x00 19. "SOF_IRQ,SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus this bit is set" "0,1"
bitfld.long 0x00 18. "INT_IRQ,INT IRQ: Indicates that an INT PTD (with I-bit set) was completed" "0,1"
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bitfld.long 0x00 17. "ISO_IRQ,ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed" "0,1"
bitfld.long 0x00 16. "ATL_IRQ,ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed" "0,1"
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bitfld.long 0x00 3. "FLR,Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over its maximum value to 0" "0,1"
bitfld.long 0x00 2. "PCD,Port Change Detect: The host controller sets this bit to logic 1 when any port has a change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a result of a J-K transition detected on a suspended port" "0,1"
group.long 0x28++0x03
line.long 0x00 "USBINTR,USB Interrupt Enable register"
bitfld.long 0x00 19. "SOF_E,SOF Interrupt Enable bit" "0: disable,1: enable"
bitfld.long 0x00 18. "INT_IRQ_E,INT IRQ Enable bit" "0: disable,1: enable"
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bitfld.long 0x00 17. "ISO_IRQ_E,ISO IRQ Enable bit" "0: disable,1: enable"
bitfld.long 0x00 16. "ATL_IRQ_E,ATL IRQ Enable bit" "0: disable,1: enable"
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bitfld.long 0x00 3. "FLRE,Frame List Rollover Interrupt Enable" "0: disable,1: enable"
bitfld.long 0x00 2. "PCDE,Port Change Detect Interrupt Enable" "0: disable,1: enable"
group.long 0x2C++0x03
line.long 0x00 "PORTSC1,Port Status and Control register"
hexmask.long.byte 0x00 25.--31. 1. "DEV_ADD,Device Address for LPM tokens"
bitfld.long 0x00 23.--24. "SUS_STAT,These two bits are used by software to determine whether the most recent L1 suspend request was successful" "0: Success-state transition was successful (ACK),1: Not Yet - Device was unable to enter the L1,2: Not supported - Device does not support the L1,3: Timeout/Error - Device failed to respond or an"
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bitfld.long 0x00 22. "WOO,Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events" "0,1"
bitfld.long 0x00 20.--21. "PSPD,Port Speed" "0: Low-speed,1: Full-speed,2: High-speed,3: Reserved"
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bitfld.long 0x00 16.--19. "PTC,Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "PIC,Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0" "0,1,2,3"
newline
bitfld.long 0x00 12. "PP,Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register" "0,1"
rbitfld.long 0x00 10.--11. "LS,Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines" "0,1,2,3"
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bitfld.long 0x00 9. "SUS_L1,Suspend using L1" "0: Suspend using L2,1: Suspend using L1 When this bit is set to a 1"
bitfld.long 0x00 8. "PR,Port Reset: Logic 1 means the port is in the reset state" "0,1"
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bitfld.long 0x00 7. "SUSP,Suspend: Logic 1 means port is in the suspend state" "0,1"
bitfld.long 0x00 6. "FPR,Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port" "0,1"
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bitfld.long 0x00 5. "OCC,Over-current change: Logic 1 means that the value of OCA has changed" "0,1"
bitfld.long 0x00 4. "OCA,Over-current active: Logic 1 means that this port has an over-current condition" "0,1"
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bitfld.long 0x00 3. "PEDC,Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed" "0,1"
bitfld.long 0x00 2. "PED,Port Enabled/Disabled" "0,1"
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bitfld.long 0x00 1. "CSC,Connect Status Change: Logic 1 means that the value of CCS has changed" "0,1"
bitfld.long 0x00 0. "CCS,Current Connect Status: Logic 1 indicates a device is present on the port" "0,1"
group.long 0x2C++0x03
line.long 0x00 "PORTSC1,Port Status and Control register"
bitfld.long 0x00 22. "WOO,Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to overcurrent conditions as wake-up events" "0,1"
bitfld.long 0x00 20.--21. "PSPD,Port Speed" "0: Low-speed,1: Full-speed,2: High-speed,3: Reserved"
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bitfld.long 0x00 16.--19. "PTC,Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "PIC,Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0" "0,1,2,3"
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bitfld.long 0x00 12. "PP,Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register" "0,1"
rbitfld.long 0x00 10.--11. "LS,Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines" "0,1,2,3"
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bitfld.long 0x00 8. "PR,Port Reset: Logic 1 means the port is in the reset state" "0,1"
bitfld.long 0x00 7. "SUSP,Suspend: Logic 1 means port is in the suspend state" "0,1"
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bitfld.long 0x00 6. "FPR,Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port" "0,1"
bitfld.long 0x00 5. "OCC,Over-current change: Logic 1 means that the value of OCA has changed" "0,1"
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bitfld.long 0x00 4. "OCA,Over-current active: Logic 1 means that this port has an over-current condition" "0,1"
bitfld.long 0x00 3. "PEDC,Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed" "0,1"
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bitfld.long 0x00 2. "PED,Port Enabled/Disabled" "0,1"
bitfld.long 0x00 1. "CSC,Connect Status Change: Logic 1 means that the value of CCS has changed" "0,1"
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bitfld.long 0x00 0. "CCS,Current Connect Status: Logic 1 indicates a device is present on the port" "0,1"
group.long 0x30++0x03
line.long 0x00 "ATLPTDD,Done map for each ATL PTD"
hexmask.long 0x00 0.--31. 1. "ATL_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed"
group.long 0x34++0x03
line.long 0x00 "ATLPTDS,Skip map for each ATL PTD"
hexmask.long 0x00 0.--31. 1. "ATL_SKIP,When a bit in the PTD Skip Map is set to logic 1 the corresponding PTD will be skipped independent of the V bit setting"
group.long 0x38++0x03
line.long 0x00 "ISOPTDD,Done map for each ISO PTD"
hexmask.long 0x00 0.--31. 1. "ISO_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed"
group.long 0x3C++0x03
line.long 0x00 "ISOPTDS,Skip map for each ISO PTD"
hexmask.long 0x00 0.--31. 1. "ISO_SKIP,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed"
group.long 0x40++0x03
line.long 0x00 "INTPTDD,Done map for each INT PTD"
hexmask.long 0x00 0.--31. 1. "INT_DONE,The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed"
group.long 0x44++0x03
line.long 0x00 "INTPTDS,Skip map for each INT PTD"
hexmask.long 0x00 0.--31. 1. "INT_SKIP,When a bit in the PTD Skip Map is set to logic 1 the corresponding PTD will be skipped independent of the V bit setting"
group.long 0x48++0x03
line.long 0x00 "LASTPTD,Marks the last PTD in the list for ISO INT and ATL"
bitfld.long 0x00 16.--20. "INT_LAST,This indicates the last PTD in the INT list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "ISO_LAST,This indicates the last PTD in the ISO list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "ATL_LAST,If hardware has reached this PTD and the J bit is not set it will go to PTD0 as the next PTD to be processed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x50++0x03
line.long 0x00 "PORTMODE,Controls the port if it is attached to the host block or the device block"
bitfld.long 0x00 19. "SW_PDCOM,This bit is only used when SW_CTRL_PDCOM is set to 1b" "0,1"
bitfld.long 0x00 18. "SW_CTRL_PDCOM,This bit indicates if the PHY power-down input is controlled by software or by hardware" "0,1"
newline
bitfld.long 0x00 16. "DEV_ENABLE,If this bit is set to one one of the ports will behave as a USB device" "0,1"
tree.end
tree "USBPHY (Universal System Bus Physical Layer)"
base ad:0x40038000
group.long 0x00++0x03
line.long 0x00 "PWD,USB PHY Power-Down Register"
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
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bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
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bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
newline
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
newline
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
newline
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x04++0x03
line.long 0x00 "PWD_SET,USB PHY Power-Down Register"
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
newline
bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
newline
bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
newline
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
newline
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
newline
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x08++0x03
line.long 0x00 "PWD_CLR,USB PHY Power-Down Register"
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
newline
bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
newline
bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
newline
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
newline
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
newline
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x0C++0x03
line.long 0x00 "PWD_TOG,USB PHY Power-Down Register"
bitfld.long 0x00 20. "RXPWDRX,This bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the entire USB PHY receiver block.."
newline
bitfld.long 0x00 19. "RXPWDDIFF,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed differential.."
newline
bitfld.long 0x00 18. "RXPWD1PT1,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed differential.."
newline
bitfld.long 0x00 17. "RXPWDENV,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB high-speed receiver.."
newline
bitfld.long 0x00 12. "TXPWDV2I,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY transmit V-to-I.."
newline
bitfld.long 0x00 11. "TXPWDIBIAS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB PHY current bias block for.."
newline
bitfld.long 0x00 10. "TXPWDFS,Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of CTRL is enabled" "0: Normal operation,1: Power-down the USB full-speed drivers"
group.long 0x10++0x03
line.long 0x00 "TX,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1"
newline
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
group.long 0x14++0x03
line.long 0x00 "TX_SET,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1"
newline
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
group.long 0x18++0x03
line.long 0x00 "TX_CLR,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1"
newline
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
group.long 0x1C++0x03
line.long 0x00 "TX_TOG,USB PHY Transmitter Control Register"
bitfld.long 0x00 21. "TXENCAL45DP,Enable resistance calibration on DP" "0,1"
newline
bitfld.long 0x00 16.--19. "TXCAL45DP,Decode to trim the nominal 45ohm series termination resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "TXENCAL45DN,Enable resistance calibration on DN" "0,1"
newline
bitfld.long 0x00 8.--11. "TXCAL45DM,Decode to trim the nominal 45ohm series termination resistance to the USB_DM output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "D_CAL,Decode to trim the nominal 17" "0: Maximum current approximately 19% above nominal,?,?,?,?,?,?,7: Nominal,?,?,?,?,?,?,?,15: Minimum current approximately 19% below.."
group.long 0x20++0x03
line.long 0x00 "RX,USB PHY Receiver Control Register"
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
newline
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
group.long 0x24++0x03
line.long 0x00 "RX_SET,USB PHY Receiver Control Register"
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
newline
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
group.long 0x28++0x03
line.long 0x00 "RX_CLR,USB PHY Receiver Control Register"
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
newline
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
group.long 0x2C++0x03
line.long 0x00 "RX_TOG,USB PHY Receiver Control Register"
bitfld.long 0x00 22. "RXDBYPASS,This test mode is intended for lab use only replace FS differential receiver with DP single ended receiver" "0: Normal operation,1: Use the output of the USB_DP single-ended.."
newline
bitfld.long 0x00 4.--6. "DISCONADJ,The DISCONADJ field adjusts the trip point for the disconnect detector" "0: Trip-Level Voltage is 0.56875 V,1: Trip-Level Voltage is 0.55000 V,2: Trip-Level Voltage is 0.58125 V,3: Trip-Level Voltage is 0.60000 V,?..."
newline
bitfld.long 0x00 0.--2. "ENVADJ,The ENVADJ field adjusts the trip point for the envelope detector" "0: Trip-Level Voltage is 0.1000 V,1: Trip-Level Voltage is 0.1125 V,2: Trip-Level Voltage is 0.1250 V,3: Trip-Level Voltage is 0.0875 V,?..."
group.long 0x30++0x03
line.long 0x00 "CTRL,USB PHY General Control Register"
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1"
newline
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
newline
bitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
newline
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
newline
bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
newline
bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
newline
bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1"
newline
bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
newline
bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
newline
bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1"
newline
bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
newline
bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1"
newline
bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1"
newline
bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
newline
bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
newline
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
newline
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
newline
bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
newline
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
group.long 0x34++0x03
line.long 0x00 "CTRL_SET,USB PHY General Control Register"
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1"
newline
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
newline
rbitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
newline
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
newline
bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
newline
bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
newline
bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1"
newline
bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
newline
bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
newline
bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1"
newline
bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
newline
bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1"
newline
bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1"
newline
bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
newline
bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
newline
bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
newline
bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
newline
bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
newline
bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
group.long 0x38++0x03
line.long 0x00 "CTRL_CLR,USB PHY General Control Register"
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1"
newline
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
newline
bitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
newline
bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
newline
bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
newline
bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
newline
bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1"
newline
bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
newline
bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
newline
bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1"
newline
bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
newline
bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1"
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bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1"
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bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
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bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
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bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
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bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
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bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
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bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
group.long 0x3C++0x03
line.long 0x00 "CTRL_TOG,USB PHY General Control Register"
bitfld.long 0x00 31. "SFTRST,Writing a 1 to this bit will soft-reset the PWD TX RX and CTRL registers" "0,1"
newline
bitfld.long 0x00 30. "CLKGATE,Gate UTMI Clocks" "0,1"
newline
bitfld.long 0x00 29. "UTMI_SUSPENDM,Used by the PHY to indicate a powered-down state" "0,1"
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bitfld.long 0x00 28. "HOST_FORCE_LS_SE0,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "0,1"
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bitfld.long 0x00 26. "ENAUTOSET_USBCLKS,Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
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bitfld.long 0x00 25. "ENAUTOCLR_USBCLKGATE,Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended" "0,1"
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bitfld.long 0x00 23. "ENVBUSCHG_WKUP,Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended" "0,1"
newline
bitfld.long 0x00 21. "ENDPDMCHG_WKUP,Enable DP DM change wake-up: Not for customer use" "0,1"
newline
bitfld.long 0x00 20. "ENAUTOCLR_PHY_PWD,Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended" "0,1"
newline
bitfld.long 0x00 19. "ENAUTOCLR_CLKGATE,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "0,1"
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bitfld.long 0x00 18. "AUTORESUME_EN,Enable the auto resume feature when set HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)" "0,1"
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bitfld.long 0x00 17. "WAKEUP_IRQ,Wake-up IRQ: Indicates that there is a wak-eup event" "0,1"
newline
bitfld.long 0x00 16. "ENIRQWAKEUP,Enable wake-up IRQ: Enables interrupt for the wake-up events" "0,1"
newline
bitfld.long 0x00 15. "ENUTMILEVEL3,Enables UTMI+ Level 3 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 14. "ENUTMILEVEL2,Enables UTMI+ Level 2 operation for the USB HS PHY" "0,1"
newline
bitfld.long 0x00 12. "DEVPLUGIN_IRQ,Indicates that the device is connected" "0,1"
newline
bitfld.long 0x00 10. "RESUME_IRQ,Resume IRQ: Indicates that the host is sending a wake-up after suspend" "0,1"
newline
bitfld.long 0x00 9. "ENIRQRESUMEDETECT,Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line" "0,1"
newline
bitfld.long 0x00 8. "RESUMEIRQSTICKY,Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it" "0,1"
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bitfld.long 0x00 5. "DEVPLUGIN_POLARITY,Device plugin polarity: For device mode if this bit is cleared to 0 then it trips the interrupt if the device is plugged in" "0,1"
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bitfld.long 0x00 4. "ENDEVPLUGINDET,Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode" "0: Disables 200kohm pullup resistors on USB_DP..,1: Enables 200kohm pullup resistors on USB_DP.."
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bitfld.long 0x00 3. "HOSTDISCONDETECT_IRQ,Indicates that the device has disconnected in High-Speed mode" "0,1"
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bitfld.long 0x00 2. "ENIRQHOSTDISCON,Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode" "0,1"
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bitfld.long 0x00 1. "ENHOSTDISCONDETECT,For host mode enables high-speed disconnect detector" "0,1"
group.long 0x40++0x03
line.long 0x00 "STATUS,USB PHY Status Register"
rbitfld.long 0x00 10. "RESUME_STATUS,Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt" "0,1"
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rbitfld.long 0x00 6. "DEVPLUGIN_STATUS,Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4]" "0: No attachment to a USB host is detected,1: Cable attachment to a USB host is detected"
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rbitfld.long 0x00 3. "HOSTDISCONDETECT_STATUS,Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode" "0: USB cable disconnect has not been detected at..,1: USB cable disconnect has been detected at the.."
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rbitfld.long 0x00 0. "OK_STATUS_3V,Indicates the USB 3v power rails are in range" "0,1"
group.long 0xA0++0x03
line.long 0x00 "PLL_SIC,USB PHY PLL Control/Status Register"
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
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bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1"
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bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240"
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bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
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bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
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bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
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bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
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bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
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bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xA4++0x03
line.long 0x00 "PLL_SIC_SET,USB PHY PLL Control/Status Register"
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
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bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1"
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bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240"
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bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
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bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
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bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
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bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
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bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
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bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xA8++0x03
line.long 0x00 "PLL_SIC_CLR,USB PHY PLL Control/Status Register"
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
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bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1"
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bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240"
newline
bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
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bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
newline
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
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bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
newline
bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
newline
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xAC++0x03
line.long 0x00 "PLL_SIC_TOG,USB PHY PLL Control/Status Register"
rbitfld.long 0x00 31. "PLL_LOCK,USB PLL lock status indicator" "0: PLL is not currently locked,1: PLL is currently locked"
newline
bitfld.long 0x00 30. "PLL_PREDIV,This is selection between /1 or /2 to expand the range of ref input clock" "0,1"
newline
bitfld.long 0x00 22.--24. "PLL_DIV_SEL,This field controls the USB PLL feedback loop divider" "0: Divide by 13,1: Divide by 15,2: Divide by 16,3: Divide by 20,4: Divide by 22,5: Divide by 25,6: Divide by 30,7: Divide by 240"
newline
bitfld.long 0x00 21. "PLL_REG_ENABLE,This field controls the USB PLL regulator set to enable the regulator" "0,1"
newline
bitfld.long 0x00 20. "REFBIAS_PWD,Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1" "0,1"
newline
bitfld.long 0x00 19. "REFBIAS_PWD_SEL,Reference bias power down select" "0: Selects PLL_POWER to control the reference bias,1: Selects REFBIAS_PWD to control the reference.."
newline
bitfld.long 0x00 13. "PLL_ENABLE,Enables the clock output from the USB PLL" "0,1"
newline
bitfld.long 0x00 12. "PLL_POWER,Power up the USB PLL" "0,1"
newline
bitfld.long 0x00 6. "PLL_EN_USB_CLKS,Enables the USB clock from PLL to USB PHY" "0,1"
group.long 0xC0++0x03
line.long 0x00 "USB1_VBUS_DETECT,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
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bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)"
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sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1"
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endif
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
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bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external VBUS VALID value"
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bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external ID value"
newline
bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1"
newline
bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1"
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bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
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bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
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bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1"
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bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
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bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7"
group.long 0xC4++0x03
line.long 0x00 "USB1_VBUS_DETECT_SET,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
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bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)"
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sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1"
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endif
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
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bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external VBUS VALID value"
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bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external ID value"
newline
bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1"
newline
bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1"
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bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
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bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
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bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1"
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bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
newline
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
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bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7"
group.long 0xC8++0x03
line.long 0x00 "USB1_VBUS_DETECT_CLR,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
newline
bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)"
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sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1"
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endif
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
newline
bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pin muxed value" "0: Select the muxed value chosen using..,1: Select the external VBUS VALID value"
newline
bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pinmuxed value" "0: Select the Muxed value chosen using..,1: Select the external ID value"
newline
bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1"
newline
bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1"
newline
bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
newline
bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
newline
bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1"
newline
bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
newline
bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
newline
bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
newline
bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
newline
bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7"
group.long 0xCC++0x03
line.long 0x00 "USB1_VBUS_DETECT_TOG,USB PHY VBUS Detect Control Register"
bitfld.long 0x00 26. "DISCHARGE_VBUS,Controls VBUS discharge resistor This bit field controls a nominal 22kohm resistor between the USB1_VBUS pin and ground" "0: VBUS discharge resistor is disabled (Default),1: VBUS discharge resistor is enabled"
newline
bitfld.long 0x00 20.--22. "PWRUP_CMPS,Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector" "0: Powers down the VBUS_VALID comparator,?,?,?,?,?,?,7: Enables the VBUS_VALID comparator (default)"
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sif cpuis("LPC55S26*")||cpuis("LPC55S28*")||cpuis("LPC55S66*")||cpuis("LPC55S69*")
bitfld.long 0x00 19. "VBUSVALID_5VDETECT,no description available" "0,1"
newline
endif
bitfld.long 0x00 18. "VBUSVALID_TO_SESSVALID,Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator" "0: Use the VBUS_VALID comparator for VBUS_VALID..,1: Use the Session End comparator for VBUS_VALID.."
newline
bitfld.long 0x00 14. "EXT_VBUS_OVERRIDE_EN,Enable VBUS override using the pin muxed value" "0: Select the Muxed value chosen using..,1: Select the external VBUS VALID value"
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bitfld.long 0x00 13. "EXT_ID_OVERRIDE_EN,Enable ID override using the pin muxed value" "0: Select the muxed value chosen using..,1: Select the external ID value"
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bitfld.long 0x00 12. "ID_OVERRIDE,ID override value" "0,1"
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bitfld.long 0x00 11. "ID_OVERRIDE_EN,Enable ID override using the register field" "0,1"
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bitfld.long 0x00 9.--10. "VBUS_SOURCE_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the Session Valid comparator results for..,2: Use the Session Valid comparator results for..,?..."
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bitfld.long 0x00 8. "VBUSVALID_SEL,Selects the source of the VBUS_VALID signal reported to the USB controller This is one of the bit fields that selects the source of the VBUS_VALID signal reported to the USB controller" "0: Use the VBUS_VALID comparator results for..,1: Use the VBUS_VALID_3V detector results for.."
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bitfld.long 0x00 7. "VBUSVALID_OVERRIDE,Override value for VBUS_VALID signal sent to USB controller The bit field provides the value for VBUS_VALID reported to the USB controller if the value of USB1_VBUS_DETECT[3] is set to 1'b1" "0,1"
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bitfld.long 0x00 6. "AVALID_OVERRIDE,Override value for A-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[2] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 5. "BVALID_OVERRIDE,Override value for B-Device Session Valid The bit field provides the value for USB1_VBUS_DET_STAT[1] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 4. "SESSEND_OVERRIDE,Override value for SESSEND The bit field provides the value for USB1_VBUS_DET_STAT[0] if USB_VBUS_DETECT[3] is set to value 1'b1" "0,1"
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bitfld.long 0x00 3. "VBUS_OVERRIDE_EN,VBUS detect signal override enable" "0: Use the results of the internal VBUS_VALID..,1: Use the override values for VBUS_VALID AVALID.."
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bitfld.long 0x00 0.--2. "VBUSVALID_THRESH,Sets the threshold for the VBUSVALID comparator" "0: value0,1: value1,2: value2,3: value3,4: 4.4V(Default),5: value5,6: value6,7: value7"
rgroup.long 0xD0++0x03
line.long 0x00 "USB1_VBUS_DET_STAT,USB PHY VBUS Detector Status Register"
bitfld.long 0x00 4. "VBUS_VALID_3V,VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on the USB1_VBUS pin than either the Session Valid or VBUS_VALID comparators" "0: VBUS voltage is below VBUS_VALID_3V threshold,1: VBUS voltage is above VBUS_VALID_3V threshold"
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bitfld.long 0x00 3. "VBUS_VALID,VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin" "0: VBUS is below the comparator threshold,1: VBUS is above the comparator threshold"
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bitfld.long 0x00 2. "AVALID,A-Device Session Valid status A-Device Session Valid status determined by the Session Valid comparator" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.."
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bitfld.long 0x00 1. "BVALID,B-Device Session Valid status B-Device Session Valid status determined by the Session Valid comparator" "0: The VBUS voltage is below the Session Valid..,1: The VBUS voltage is above the Session Valid.."
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bitfld.long 0x00 0. "SESSEND,Session End indicator Session End status value inverted from Session Valid comparator" "0: The VBUS voltage is above the Session Valid..,1: The VBUS voltage is below the Session Valid.."
group.long 0x100++0x03
line.long 0x00 "ANACTRL,USB PHY Analog Control Register"
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
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bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3"
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bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1"
group.long 0x104++0x03
line.long 0x00 "ANACTRL_SET,USB PHY Analog Control Register"
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
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bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3"
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bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1"
group.long 0x108++0x03
line.long 0x00 "ANACTRL_CLR,USB PHY Analog Control Register"
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
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bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3"
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bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1"
group.long 0x10C++0x03
line.long 0x00 "ANACTRL_TOG,USB PHY Analog Control Register"
bitfld.long 0x00 10. "DEV_PULLDOWN,Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins" "0: The 15kohm nominal pulldowns on the USB_DP..,1: The 15kohm nominal pulldowns on the USB_DP.."
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bitfld.long 0x00 2.--3. "PFD_CLK_SEL,For normal USB operation this bit field must remain at value 2'b00" "0,1,2,3"
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bitfld.long 0x00 1. "LVI_EN,Vow voltage detector enable bit" "0,1"
tree.end
endif
tree "UTICK (Micro-tick Timer)"
base ad:0x4000E000
group.long 0x00++0x03
line.long 0x00 "CTRL,Control register"
bitfld.long 0x00 31. "REPEAT,Repeat delay" "0: One-time delay,1: Delay repeats continuously"
hexmask.long 0x00 0.--30. 1. "DELAYVAL,Tick interval value"
group.long 0x04++0x03
line.long 0x00 "STAT,Status register"
bitfld.long 0x00 1. "ACTIVE,Active flag" "0: The Micro-Tick Timer is stopped,1: The Micro-Tick Timer is currently active"
bitfld.long 0x00 0. "INTR,Interrupt flag" "0: No interrupt is pending,1: An interrupt is pending"
group.long 0x08++0x03
line.long 0x00 "CFG,Capture configuration register"
bitfld.long 0x00 11. "CAPPOL3,Capture Polarity 3" "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x00 10. "CAPPOL2,Capture Polarity 2" "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x00 9. "CAPPOL1,Capture Polarity 1" "0: Positive edge capture,1: Negative edge capture"
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bitfld.long 0x00 8. "CAPPOL0,Capture Polarity 0" "0: Positive edge capture,1: Negative edge capture"
bitfld.long 0x00 3. "CAPEN3,Enable Capture 3" "0: Disabled,1: Enabled"
bitfld.long 0x00 2. "CAPEN2,Enable Capture 2" "0: Disabled,1: Enabled"
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bitfld.long 0x00 1. "CAPEN1,Enable Capture 1" "0: Disabled,1: Enabled"
bitfld.long 0x00 0. "CAPEN0,Enable Capture 0" "0: Disabled,1: Enabled"
wgroup.long 0x0C++0x03
line.long 0x00 "CAPCLR,Capture clear register"
bitfld.long 0x00 3. "CAPCLR3,Clear capture 3" "0,1"
bitfld.long 0x00 2. "CAPCLR2,Clear capture 2" "0,1"
bitfld.long 0x00 1. "CAPCLR1,Clear capture 1" "0,1"
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bitfld.long 0x00 0. "CAPCLR0,Clear capture 0" "0,1"
repeat 4. (increment 0 1) (increment 0 0x4)
rgroup.long ($2+0x10)++0x03
line.long 0x00 "CAP[$1],Capture register $1"
bitfld.long 0x00 31. "VALID,Capture Valid" "0,1"
hexmask.long 0x00 0.--30. 1. "CAP_VALUE,Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower than the actual value of the Micro-tick Timer at the moment of the capture event"
repeat.end
tree.end
tree "WWDT (Windowed Watchdog Timer)"
base ad:0x4000C000
group.long 0x00++0x03
line.long 0x00 "MOD,Watchdog mode register"
bitfld.long 0x00 4. "WDPROTECT,Watchdog update mode" "0: Flexible,1: Threshold"
bitfld.long 0x00 3. "WDINT,Warning interrupt flag" "0,1"
bitfld.long 0x00 2. "WDTOF,Watchdog time-out flag" "0,1"
bitfld.long 0x00 1. "WDRESET,Watchdog reset enable bit" "0: Interrupt,1: Reset"
bitfld.long 0x00 0. "WDEN,Watchdog enable bit" "0: Stop,1: Run"
group.long 0x04++0x03
line.long 0x00 "TC,Watchdog timer constant register"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Watchdog time-out value"
wgroup.long 0x08++0x03
line.long 0x00 "FEED,Watchdog feed sequence register"
hexmask.long.byte 0x00 0.--7. 1. "FEED,Feed value should be 0xAA followed by 0x55"
rgroup.long 0x0C++0x03
line.long 0x00 "TV,Watchdog timer value register"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Counter timer value"
group.long 0x14++0x03
line.long 0x00 "WARNINT,Watchdog Warning Interrupt compare value"
hexmask.long.word 0x00 0.--9. 1. "WARNINT,Watchdog warning interrupt compare value"
group.long 0x18++0x03
line.long 0x00 "WINDOW,Watchdog Window compare value"
hexmask.long.tbyte 0x00 0.--23. 1. "WINDOW,Watchdog window value"
tree.end
autoindent.off
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