; -------------------------------------------------------------------------------- ; @Title: LPC11Uxx On-Chip Peripherals ; @Props: Released ; @Author: PID, LST ; @Changelog: 2019-01-08 LST ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: LPC11U1x_LPC11U2x_LPC11U3x_UM10462.pdf (Rev. 5.5, 2016-12) ; LPC11U6x_UM10732.pdf (Rev. 1.8, 2016-12) ; LPC11U6x_DS.pdf (Rev. 1.3, 2016-09) ; LPC11U1x_DS.pdf (Rev. 2.2, 2014-03) ; LPC11U2x_DS.pdf (Rev. 2.3, 2014-03) ; LPC11U3x_DS.pdf (Rev. 2.3, 2017-02) ; @Core: Cortex-M0P, Cortex-M0 ; @Chip: LPC11U12/201, LPC11U13/201, LPC11U14/201, LPC11U22FBD48, LPC11U23/301, ; LPC11U24/301, LPC11U24/401, LPC11U34FBD48, LPC11U34FHN33, LPC11U35FBD48, ; LPC11U35FBD64, LPC11U35FET48, LPC11U35FHI33, LPC11U35FHN33, ; LPC11U36FBD48, LPC11U36FBD64, LPC11U37FBD48, LPC11U37FBD64, ; LPC11U37HFBD64, LPC11U66JBD48, LPC11U67JBD100, LPC11U67JBD48, ; LPC11U67JBD64, LPC11U68JBD100, LPC11U68JBD48, LPC11U68JBD64 ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perlpc11uxx.per 10343 2019-03-20 14:53:39Z kwitkowski $ ; Known problems: ; Module Register Description ; -------------------------------------------------------------------------------- ; SysCon DEVICE_ID Misleading offset in LPC11U6x manual ; DMAC Configuration Registers Two different addresses in registers map and register description. ; FMC FMSW3 Two different addresses in registers map and register description. ; CT32B0/1 CCR Two different descriptions and symbols on the same bits (3,4,5). ; CT32B0/1 CTCR In LPC11U6x SELCC bits description says that values 0x2 and 0x3 are reserved. config 16. 8. sif (CORENAME()=="CORTEXM0") tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end elif (CORENAME()=="CORTEXM0+") tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif tree "SysCon (System Control Block)" base ad:0x40048000 width 15. group.long 0x00++0x0B line.long 0x00 "SYSMEMREMAP,System Memory Remap Register" bitfld.long 0x00 0.--1. " MAP ,System memory remap" "Boot Loader Mode,User RAM Mode,User Flash Mode,?..." line.long 0x04 "PRESETCTRL,Peripheral Reset Control Register" sif cpuis("LPC11U6*") bitfld.long 0x04 10. " SCT1_RST_N ,SCT1 reset control" "Reset,No reset" bitfld.long 0x04 9. " SCT0_RST_N ,SCT0 reset control" "Reset,No reset" bitfld.long 0x04 8. " USART4_RST_N ,USART4 reset control" "Reset,No reset" bitfld.long 0x04 7. " USART3_RST_N ,USART3 reset control" "Reset,No reset" newline bitfld.long 0x04 6. " USART2_RST_N ,USART2 reset control" "Reset,No reset" bitfld.long 0x04 5. " USART1_RST_N ,USART1 reset control" "Reset,No reset" bitfld.long 0x04 4. " FRG_RST_N ,FRG reset control" "Reset,No reset" bitfld.long 0x04 3. " I2C1_RST_N ,I2C1 reset control" "Reset,No reset" newline bitfld.long 0x04 2. " SSP1_RST_N ,SSP0 reset control" "Reset,No reset" bitfld.long 0x04 1. " I2C0_RST_N ,I2C0 reset control" "Reset,No reset" bitfld.long 0x04 0. " SSP0_RST_N ,SSP0 reset control" "Reset,No reset" else bitfld.long 0x04 2. " SSP1_RST_N ,SSP1 reset control" "Reset,No reset" bitfld.long 0x04 1. " I2C_RST_N ,I2C reset control" "Reset,No reset" bitfld.long 0x04 0. " SSP0_RST_N ,SSP0 reset control" "Reset,No reset" endif line.long 0x08 "SYSPLLCTRL,System PLL Control Register" bitfld.long 0x08 5.--6. " PSEL ,Post divider ratio" "1,2,4,8" bitfld.long 0x08 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" rgroup.long 0x0C++0x03 line.long 0x00 "SYSPLLSTAT,System PLL Status Register" bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked" group.long 0x10++0x03 line.long 0x00 "USBPLLCTRL,USB PLL Control Register" bitfld.long 0x00 5.--6. " PSEL ,Post divider ratio" "1,2,4,8" bitfld.long 0x00 0.--4. " MSEL ,Feedback divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" rgroup.long 0x14++0x03 line.long 0x00 "USBPLLSTAT,USB PLL Status Register" bitfld.long 0x00 0. " LOCK ,PLL lock status" "Not locked,Locked" sif (cpuis("LPC11U6*")) group.long 0x1C++0x03 line.long 0x00 "RTCOSCCTRL,RTC Oscillator 32 kHz Output Control Register" bitfld.long 0x00 0. " RTCOSCEN ,RTC 32 kHz output enable" "Disabled,Enabled" endif group.long 0x20++0x0B line.long 0x00 "SYSOSCCTRL,System Oscillator Control Register" bitfld.long 0x00 1. " FREQRANGE ,Frequency range" "1-20MHz,15-25MHz" bitfld.long 0x00 0. " BYPASS ,Bypass system oscillator" "Disabled,Enabled" line.long 0x04 "WDTOSCCTRL,Watchdog Oscillator Control Register" bitfld.long 0x04 5.--8. " FREQSEL ,Watchdog oscillator analog output frequency Fclkana" ",0.6 MHz,1.05 MHz,1.4 MHz,1.75 MHz,2.1 MHz,2.4 MHz,2.7 MHz,3.0 MHz,3.25 MHz,3.5 MHz,3.75 MHz,4.0 MHz,4.2 MHz,4.4 MHz,4.6 MHz" bitfld.long 0x04 0.--4. " DIVSEL ,Select divider for Fclkana" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64" line.long 0x08 "IRCCTRL,Internal Resonant Crystal Control Register" hexmask.long.byte 0x08 0.--7. 1. " TRIM ,Trim value" group.long 0x30++0x03 line.long 0x00 "SYSRSTSTAT,System Reset Status Register" eventfld.long 0x00 4. " SYSRST ,Software system reset" "No reset,Reset" eventfld.long 0x00 3. " BOD ,Brown-out detect reset" "No reset,Reset" eventfld.long 0x00 2. " WDT ,Watchdog reset" "No reset,Reset" eventfld.long 0x00 1. " EXTRST ,External reset" "No reset,Reset" newline eventfld.long 0x00 0. " POR ,POR reset" "No reset,Reset" group.long 0x40++0x0F line.long 0x00 "SYSPLLCLKSEL,System PLL Clock Source Select Register" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC,SYSOSC,,32kHz clock" else bitfld.long 0x00 0.--1. " SEL ,System PLL clock source" "IRC,SYSOSC,?..." endif line.long 0x04 "SYSPLLCLKUEN,System PLL Clock Source Update Register" bitfld.long 0x04 0. " ENA ,Enable system PLL clock source update" "Disabled,Enabled" line.long 0x08 "USBPLLCLKSEL,USB PLL Clock Source Select Register" bitfld.long 0x08 0.--1. " SEL ,USB PLL clock source" "IRC,SYSOSC,?..." line.long 0x0C "USBPLLCLKUEN,USB PLL Clock Source Update Enable Register" bitfld.long 0x0C 0. " ENA ,USB PLL clock source update enable" "Disabled,Enabled" group.long 0x70++0x0B line.long 0x00 "MAINCLKSEL,Main Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,Clock source for main clock" "IRC,PLL input,WDT oscillator,PLL output" line.long 0x04 "MAINCLKUEN,Main Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,Enable main clock source update" "Disabled,Enabled" line.long 0x08 "SYSAHBCLKDIV,System AHB Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,System AHB clock divider values" group.long 0x80++0x03 line.long 0x00 "SYSAHBCLKCTRL,System AHB Clock Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 31. " SCT0_1 ,Clock for SCT0 and SCT1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " RTC ,Clock for RTC register interface enable" "Disabled,Enabled" bitfld.long 0x00 29. " DMA ,Clock for DMA enable" "Disabled,Enabled" bitfld.long 0x00 28. " CRC ,Clock for CRC enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " USBSRAM ,USB SRAM/SRAM2 block enable" "Disabled,Enabled" bitfld.long 0x00 26. " RAM1 ,Block for SRAM1 enable" "Disabled,Enabled" bitfld.long 0x00 25. " I2C1 ,Clock for I2C1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " GROUP1INT ,Clock to GPIO GROUP1 interrupt register interface enable" "Disabled,Enabled" newline bitfld.long 0x00 23. " GROUP0INT ,Clock to GPIO GROUP0 interrupt register interface enable" "Disabled,Enabled" bitfld.long 0x00 22. " USART3_4 ,Enables clock to USART3 and USART4 register interfaces." "Disabled,Enabled" bitfld.long 0x00 21. " USART2 ,Enables clock to USART2 register interface" "Disabled,Enabled" bitfld.long 0x00 20. " USART1 ,Enables clock to USART1 register interface" "Disabled,Enabled" newline bitfld.long 0x00 19. " PINT ,Clock to GPIO Pin interrupts register interface enable" "Disabled,Enabled" bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled" else bitfld.long 0x00 27. " USBRAM ,USB SRAM1 block enable" "Disabled,Enabled" bitfld.long 0x00 26. " RAM1 ,Block for SRAM1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " GROUP1INT ,Clock to GPIO GROUP1 interrupt register interface enable" "Disabled,Enabled" bitfld.long 0x00 23. " GROUP0INT ,Clock to GPIO GROUP0 interrupt register interface enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " PINT ,Clock to GPIO Pin interrupts register interface enable" "Disabled,Enabled" bitfld.long 0x00 18. " SSP1 ,Clock for SPI1 enable" "Disabled,Enabled" endif bitfld.long 0x00 16. " IOCON ,Clock for IO configuration block enable" "Disabled,Enabled" bitfld.long 0x00 15. " WWDT ,Clock for WWDT enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " USB ,Clock to the USB register interface enable" "Disabled,Enabled" bitfld.long 0x00 13. " ADC ,Clock for ADC enable" "Disabled,Enabled" bitfld.long 0x00 12. " USART0 ,Clock for USART0 enable" "Disabled,Enabled" bitfld.long 0x00 11. " SSP0 ,Clock for SSP0 enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " CT32B1 ,Clock for 32-bit counter/timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 9. " CT32B0 ,Clock for 32-bit counter/timer 0 enable" "Disabled,Enabled" bitfld.long 0x00 8. " CT16B1 ,Clock for 16-bit counter/timer 1 enable" "Disabled,Enabled" bitfld.long 0x00 7. " CT16B0 ,Clock for 16-bit counter/timer 0 enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " GPIO ,Clock for GPIO port registers enable" "Disabled,Enabled" bitfld.long 0x00 5. " I2C0 ,Clock for I2C enable" "Disabled,Enabled" bitfld.long 0x00 4. " FLASHARRAY ,Clock for flash access" "Disabled,Enabled" bitfld.long 0x00 3. " FLASHREG ,Clock for flash register interface enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " RAM0 ,Clock for main SRAM0 enable" "Disabled,Enabled" bitfld.long 0x00 1. " ROM ,Clock for ROM enable" "Disabled,Enabled" rbitfld.long 0x00 0. " SYS ,Always-on clock for the AHB configuration" "Disabled,Enabled" group.long 0x94++0x03 line.long 0x00 "SPI0CLKDIV,SPI0 Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,SPI0_PCLK clock divider values" sif cpuis("LPC11U6*") group.long 0x98++0x03 line.long 0x00 "USART0CLKDIV,USART0 Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,UART_PCLK clock divider values" else group.long 0x98++0x03 line.long 0x00 "USARTCLKDIV,USART Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,UART_PCLK clock divider values" endif group.long 0x9C++0x03 line.long 0x00 "SSP1CLKDIV,SSP1 Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,SSP1_PCLK clock divider values" sif cpuis("LPC11U6*") group.long 0xA0++0x03 line.long 0x00 "FRGCLKDIV,UART Fractional Baud Rate Clock Divider Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,USART fractional baud rate generator clock divider values" endif group.long 0xC0++0x0B line.long 0x00 "USBCLKSEL,USB Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,USB clock source" "USB PLL out,Main clock,?..." line.long 0x04 "USBCLKUEN,USB Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,USB clock source update enable" "Disabled,Enabled" line.long 0x08 "USBCLKDIV,USB Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,USB clock divider values" group.long 0xE0++0x0B line.long 0x00 "CLKOUTSEL,CLKOUT Clock Source Select Register" bitfld.long 0x00 0.--1. " SEL ,CLKOUT clock source" "IRC oscillator,SYSOSC,WDTOSC,Main clock" line.long 0x04 "CLKOUTUEN,CLKOUT Clock Source Update Enable Register" bitfld.long 0x04 0. " ENA ,CLKOUT clock source update enable" "Disabled,Enabled" line.long 0x08 "CLKOUTDIV,CLKOUT Clock Divider Register" hexmask.long.byte 0x08 0.--7. 1. " DIV ,CLKOUT clock divider values" sif cpuis("LPC11U6*") group.long 0xF0++0x07 line.long 0x00 "UARTFRGDIV,USART Fractional Generator Divide Value Register" hexmask.long.byte 0x00 0.--7. 1. " DIV ,Denominator of the fractional divider" line.long 0x04 "UARTFRGMULT,USART Fractional Generator Multiplier Value Register" hexmask.long.byte 0x04 0.--7. 1. " MULT ,Numerator of the fractional divider" group.long 0xFC++0x03 line.long 0x00 "EXTTRACECMD,External Trace Buffer Command Register" bitfld.long 0x00 1. " STOP ,Trace stop command" "Not stopped,Stopped" bitfld.long 0x00 0. " START ,Trace start command" "Not started,Started" endif rgroup.long 0x100++0x07 line.long 0x00 "PIOPORCAP0,POR Captured PIO Status Register 0" bitfld.long 0x00 23. " CAPPIO0_23 ,Raw reset status input PIO0_23" "Low,High" bitfld.long 0x00 22. " CAPPIO0_22 ,Raw reset status input PIO0_22" "Low,High" bitfld.long 0x00 21. " CAPPIO0_21 ,Raw reset status input PIO0_21" "Low,High" bitfld.long 0x00 20. " CAPPIO0_20 ,Raw reset status input PIO0_20" "Low,High" newline bitfld.long 0x00 19. " CAPPIO0_19 ,Raw reset status input PIO0_19" "Low,High" bitfld.long 0x00 18. " CAPPIO0_18 ,Raw reset status input PIO0_18" "Low,High" bitfld.long 0x00 17. " CAPPIO0_17 ,Raw reset status input PIO0_17" "Low,High" bitfld.long 0x00 16. " CAPPIO0_16 ,Raw reset status input PIO0_16" "Low,High" newline bitfld.long 0x00 15. " CAPPIO0_15 ,Raw reset status input PIO0_15" "Low,High" bitfld.long 0x00 14. " CAPPIO0_14 ,Raw reset status input PIO0_14" "Low,High" bitfld.long 0x00 13. " CAPPIO0_13 ,Raw reset status input PIO0_13" "Low,High" bitfld.long 0x00 12. " CAPPIO0_12 ,Raw reset status input PIO0_12" "Low,High" newline bitfld.long 0x00 11. " CAPPIO0_11 ,Raw reset status input PIO0_11" "Low,High" bitfld.long 0x00 10. " CAPPIO0_10 ,Raw reset status input PIO0_10" "Low,High" bitfld.long 0x00 9. " CAPPIO0_9 ,Raw reset status input PIO0_9" "Low,High" bitfld.long 0x00 8. " CAPPIO0_8 ,Raw reset status input PIO0_8" "Low,High" newline bitfld.long 0x00 7. " CAPPIO0_7 ,Raw reset status input PIO0_7" "Low,High" bitfld.long 0x00 6. " CAPPIO0_6 ,Raw reset status input PIO0_6" "Low,High" bitfld.long 0x00 5. " CAPPIO0_5 ,Raw reset status input PIO0_5" "Low,High" bitfld.long 0x00 4. " CAPPIO0_4 ,Raw reset status input PIO0_4" "Low,High" newline bitfld.long 0x00 3. " CAPPIO0_3 ,Raw reset status input PIO0_3" "Low,High" bitfld.long 0x00 2. " CAPPIO0_2 ,Raw reset status input PIO0_2" "Low,High" bitfld.long 0x00 1. " CAPPIO0_1 ,Raw reset status input PIO0_1" "Low,High" bitfld.long 0x00 0. " CAPPIO0_0 ,Raw reset status input PIO0_0" "Low,High" line.long 0x04 "PIOPORCAP1,POR Captured PIO Status Register 1" bitfld.long 0x04 31. " CAPPIO1_31 ,Raw reset status input PIO1_31" "Low,High" bitfld.long 0x04 30. " CAPPIO1_30 ,Raw reset status input PIO1_30" "Low,High" bitfld.long 0x04 29. " CAPPIO1_29 ,Raw reset status input PIO1_29" "Low,High" bitfld.long 0x04 28. " CAPPIO1_28 ,Raw reset status input PIO1_28" "Low,High" newline bitfld.long 0x04 27. " CAPPIO1_27 ,Raw reset status input PIO1_27" "Low,High" bitfld.long 0x04 26. " CAPPIO1_26 ,Raw reset status input PIO1_26" "Low,High" bitfld.long 0x04 25. " CAPPIO1_25 ,Raw reset status input PIO1_25" "Low,High" bitfld.long 0x04 24. " CAPPIO1_24 ,Raw reset status input PIO1_24" "Low,High" newline bitfld.long 0x04 23. " CAPPIO1_23 ,Raw reset status input PIO1_23" "Low,High" bitfld.long 0x04 22. " CAPPIO1_22 ,Raw reset status input PIO1_22" "Low,High" bitfld.long 0x04 21. " CAPPIO1_21 ,Raw reset status input PIO1_21" "Low,High" bitfld.long 0x04 20. " CAPPIO1_20 ,Raw reset status input PIO1_20" "Low,High" newline bitfld.long 0x04 19. " CAPPIO1_19 ,Raw reset status input PIO1_19" "Low,High" bitfld.long 0x04 18. " CAPPIO1_18 ,Raw reset status input PIO1_18" "Low,High" bitfld.long 0x04 17. " CAPPIO1_17 ,Raw reset status input PIO1_17" "Low,High" bitfld.long 0x04 16. " CAPPIO1_16 ,Raw reset status input PIO1_16" "Low,High" newline bitfld.long 0x04 15. " CAPPIO1_15 ,Raw reset status input PIO1_15" "Low,High" bitfld.long 0x04 14. " CAPPIO1_14 ,Raw reset status input PIO1_14" "Low,High" bitfld.long 0x04 13. " CAPPIO1_13 ,Raw reset status input PIO1_13" "Low,High" bitfld.long 0x04 12. " CAPPIO1_12 ,Raw reset status input PIO1_12" "Low,High" newline bitfld.long 0x04 11. " CAPPIO1_11 ,Raw reset status input PIO1_11" "Low,High" bitfld.long 0x04 10. " CAPPIO1_10 ,Raw reset status input PIO1_10" "Low,High" bitfld.long 0x04 9. " CAPPIO1_9 ,Raw reset status input PIO1_9" "Low,High" bitfld.long 0x04 8. " CAPPIO1_8 ,Raw reset status input PIO1_8" "Low,High" newline bitfld.long 0x04 7. " CAPPIO1_7 ,Raw reset status input PIO1_7" "Low,High" bitfld.long 0x04 6. " CAPPIO1_6 ,Raw reset status input PIO1_6" "Low,High" bitfld.long 0x04 5. " CAPPIO1_5 ,Raw reset status input PIO1_5" "Low,High" bitfld.long 0x04 4. " CAPPIO1_4 ,Raw reset status input PIO1_4" "Low,High" newline bitfld.long 0x04 3. " CAPPIO1_3 ,Raw reset status input PIO1_3" "Low,High" bitfld.long 0x04 2. " CAPPIO1_2 ,Raw reset status input PIO1_2" "Low,High" bitfld.long 0x04 1. " CAPPIO1_1 ,Raw reset status input PIO1_1" "Low,High" bitfld.long 0x04 0. " CAPPIO1_0 ,Raw reset status input PIO1_0" "Low,High" sif cpuis("LPC11U6*") rgroup.long 0x108++0x03 line.long 0x00 "PIOPORCAP2,POR Captured PIO Status Register 2" bitfld.long 0x00 23. " CAPPIO2_23 ,Raw reset status input PIO2_23" "Low,High" bitfld.long 0x00 22. " CAPPIO2_22 ,Raw reset status input PIO2_22" "Low,High" bitfld.long 0x00 21. " CAPPIO2_21 ,Raw reset status input PIO2_21" "Low,High" bitfld.long 0x00 20. " CAPPIO2_20 ,Raw reset status input PIO2_20" "Low,High" newline bitfld.long 0x00 19. " CAPPIO2_19 ,Raw reset status input PIO2_19" "Low,High" bitfld.long 0x00 18. " CAPPIO2_18 ,Raw reset status input PIO2_18" "Low,High" bitfld.long 0x00 17. " CAPPIO2_17 ,Raw reset status input PIO2_17" "Low,High" bitfld.long 0x00 16. " CAPPIO2_16 ,Raw reset status input PIO2_16" "Low,High" newline bitfld.long 0x00 15. " CAPPIO2_15 ,Raw reset status input PIO2_15" "Low,High" bitfld.long 0x00 14. " CAPPIO2_14 ,Raw reset status input PIO2_14" "Low,High" bitfld.long 0x00 13. " CAPPIO2_13 ,Raw reset status input PIO2_13" "Low,High" bitfld.long 0x00 12. " CAPPIO2_12 ,Raw reset status input PIO2_12" "Low,High" newline bitfld.long 0x00 11. " CAPPIO2_11 ,Raw reset status input PIO2_11" "Low,High" bitfld.long 0x00 10. " CAPPIO2_10 ,Raw reset status input PIO2_10" "Low,High" bitfld.long 0x00 9. " CAPPIO2_9 ,Raw reset status input PIO2_9" "Low,High" bitfld.long 0x00 8. " CAPPIO2_8 ,Raw reset status input PIO2_8" "Low,High" newline bitfld.long 0x00 7. " CAPPIO2_7 ,Raw reset status input PIO2_7" "Low,High" bitfld.long 0x00 6. " CAPPIO2_6 ,Raw reset status input PIO2_6" "Low,High" bitfld.long 0x00 5. " CAPPIO2_5 ,Raw reset status input PIO2_5" "Low,High" bitfld.long 0x00 4. " CAPPIO2_4 ,Raw reset status input PIO2_4" "Low,High" newline bitfld.long 0x00 3. " CAPPIO2_3 ,Raw reset status input PIO2_3" "Low,High" bitfld.long 0x00 2. " CAPPIO2_2 ,Raw reset status input PIO2_2" "Low,High" bitfld.long 0x00 1. " CAPPIO2_1 ,Raw reset status input PIO2_1" "Low,High" bitfld.long 0x00 0. " CAPPIO2_0 ,Raw reset status input PIO2_0" "Low,High" endif sif cpuis("LPC11U6*") group.long 0x134++0x03 line.long 0x00 "IOCONCLKDIV6,IOCON Glitch Filter Clock Divider Register 6" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x138++0x03 line.long 0x00 "IOCONCLKDIV5,IOCON Glitch Filter Clock Divider Register 5" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x13C++0x03 line.long 0x00 "IOCONCLKDIV4,IOCON Glitch Filter Clock Divider Register 4" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x140++0x03 line.long 0x00 "IOCONCLKDIV3,IOCON Glitch Filter Clock Divider Register 3" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x144++0x03 line.long 0x00 "IOCONCLKDIV2,IOCON Glitch Filter Clock Divider Register 2" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x148++0x03 line.long 0x00 "IOCONCLKDIV1,IOCON Glitch Filter Clock Divider Register 1" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" group.long 0x14C++0x03 line.long 0x00 "IOCONCLKDIV0,IOCON Glitch Filter Clock Divider Register 0" hexmask.long.byte 0x00 0.--7. 1. " DIV ,IOCON glitch filter clock divider value" endif group.long 0x150++0x07 line.long 0x00 "BODCTRL,Brown-Out Detect Control Register" bitfld.long 0x00 4. " BODRSTENA ,BOD reset enable" "Disabled,Enabled" sif cpuis("LPC11U6*") bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",,Level 2,Level 3" else bitfld.long 0x00 2.--3. " BODINTVAL ,BOD interrupt level" ",Level 1,Level 2,Level 3" endif bitfld.long 0x00 0.--1. " BODRSTLEV ,BOD reset level" "Level 0,Level 1,Level 2,Level 3" line.long 0x04 "SYSTCKCAL,System Tick Timer Calibration Register" hexmask.long 0x04 0.--25. 1. " CAL ,System tick timer calibration value" group.long 0x170++0x07 line.long 0x00 "IRQLATENCY,IRQ Latency Register" hexmask.long.byte 0x00 0.--7. 1. " LATENCY ,8-bit latency value" line.long 0x04 "NMISRC,NMI Source Selection Register" bitfld.long 0x4 31. " NMIEN ,Non-Maskable Interrupt enable" "Disabled,Enabled" sif cpuis("LPC11U6*") bitfld.long 0x04 0.--4. " IRQN ,IRQ number of the interrupt" "PIN_INT0,PIN_INT1,PIN_INT2,PIN_INT3,PIN_INT4,PIN_INT5,PIN_INT6,PIN_INT7,GINT0,GINT1,I2C1,USART1_4,USART2_3,SCT0_1,SSP1,I2C0,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART0,USB_IRQ,USB_FIQ,ADC_A,RTC,BOD_WDT,FLASH,DMA,ADC_B,USB_WAKEUP,?..." else bitfld.long 0x04 0.--4. " IRQN ,IRQ number of the interrupt" "PIN_INT0,PIN_INT1,PIN_INT2,PIN_INT3,PIN_INT4,PIN_INT5,PIN_INT6,PIN_INT7,GINT0,GINT1,,,,,SSP1,I2C,CT16B0,CT16B1,CT32B0,CT32B1,SSP0,USART,USB_IRQ,USB_FIQ,ADC,WWDT,BOD,FLASH,,,USB_WAKEUP,IOH" endif group.long 0x178++0x03 line.long 0x00 "PINTSEL0,GPIO Pin Interrupt Select Register 0" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 0" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 0" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x17C++0x03 line.long 0x00 "PINTSEL1,GPIO Pin Interrupt Select Register 1" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 1" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 1" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x180++0x03 line.long 0x00 "PINTSEL2,GPIO Pin Interrupt Select Register 2" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 2" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 2" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x184++0x03 line.long 0x00 "PINTSEL3,GPIO Pin Interrupt Select Register 3" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 3" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 3" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x188++0x03 line.long 0x00 "PINTSEL4,GPIO Pin Interrupt Select Register 4" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 4" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 4" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x18C++0x03 line.long 0x00 "PINTSEL5,GPIO Pin Interrupt Select Register 5" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 5" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 5" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x190++0x03 line.long 0x00 "PINTSEL6,GPIO Pin Interrupt Select Register 6" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 6" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 6" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x194++0x03 line.long 0x00 "PINTSEL7,GPIO Pin Interrupt Select Register 7" sif cpuis("LPC11U6*") bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 7" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,PIO2_0,PIO2_1,PIO2_2,PIO2_3,PIO2_4,PIO2_5,PIO2_6,PIO2_7" else bitfld.long 0x00 0.--5. " INTPIN ,Pin number select for pin interrupt 7" "PIO0_0,PIO0_1,PIO0_2,PIO0_3,PIO0_4,PIO0_5,PIO0_6,PIO0_7,PIO0_8,PIO0_9,PIO0_10,PIO0_11,PIO0_12,PIO0_13,PIO0_14,PIO0_15,PIO0_16,PIO0_17,PIO0_18,PIO0_19,PIO0_20,PIO0_21,PIO0_22,PIO0_23,PIO1_0,PIO1_1,PIO1_2,PIO1_3,PIO1_4,PIO1_5,PIO1_6,PIO1_7,PIO1_8,PIO1_9,PIO1_10,PIO1_11,PIO1_12,PIO1_13,PIO1_14,PIO1_15,PIO1_16,PIO1_17,PIO1_18,PIO1_19,PIO1_20,PIO1_21,PIO1_22,PIO1_23,PIO1_24,PIO1_25,PIO1_26,PIO1_27,PIO1_28,PIO1_29,PIO1_30,PIO1_31,?..." endif group.long 0x198++0x03 line.long 0x00 "USBCLKCTRL,USB Clock Control Register" bitfld.long 0x00 1. " POL_CLK ,USB need_clock edge polarity" "Falling,Rising" bitfld.long 0x00 0. " AP_CLK ,USB need_clock signal control" "Hardware,Forced high" rgroup.long 0x19C++0x03 line.long 0x00 "USBCLKST,USB Clock Status Register" bitfld.long 0x00 0. " NEED_CLKST ,USB need_clock signal status" "Low,High" group.long 0x204++0x03 line.long 0x00 "STARTERP0,Start Logic 0 Interrupt Wake-Up Enable Register 0" bitfld.long 0x00 7. " PINT7 ,Pin interrupt 7 wake-up" "Disabled,Enabled" bitfld.long 0x00 6. " PINT6 ,Pin interrupt 6 wake-up" "Disabled,Enabled" bitfld.long 0x00 5. " PINT5 ,Pin interrupt 5 wake-up" "Disabled,Enabled" bitfld.long 0x00 4. " PINT4 ,Pin interrupt 4 wake-up" "Disabled,Enabled" newline bitfld.long 0x00 3. " PINT3 ,Pin interrupt 3 wake-up" "Disabled,Enabled" bitfld.long 0x00 2. " PINT2 ,Pin interrupt 2 wake-up" "Disabled,Enabled" bitfld.long 0x00 1. " PINT1 ,Pin interrupt 1 wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " PINT0 ,Pin interrupt 0 wake-up" "Disabled,Enabled" sif cpuis("LPC11U6*") group.long 0x214++0x03 line.long 0x00 "STARTERP1,Start Logic 1 Interrupt Wake-Up Enable Register" bitfld.long 0x00 24. " USART2_3 ,Combined USART2 and USART3 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 23. " USART1_4 ,Combined USART1 and USART4 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 21. " GROUP1INT ,GPIO GROUP1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 20. " GROUP0INT ,GPIO GROUP0 interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 19. " USB_WAKEUP ,USB need_clock signal wake-up" "Disabled,Enabled" bitfld.long 0x00 13. " WWDT_BODINT ,Combined WWDT interrupt or BOD interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 12. " RTCINT ,RTC interrupt wake-up" "Disabled,Enabled" else group.long 0x214++0x03 line.long 0x00 "STARTERP1,Interrupt Wake-Up Enable Register 1" bitfld.long 0x00 21. " GPIOINT1 ,GPIO GROUP1 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 20. " GPIOINT0 ,GPIO GROUP0 interrupt wake-up" "Disabled,Enabled" bitfld.long 0x00 19. " USB_WAKEUP ,USB need_clock signal wake-up" "Disabled,Enabled" bitfld.long 0x00 13. " BODINT ,BOD interrupt wake-up" "Disabled,Enabled" newline bitfld.long 0x00 12. " WWDTING ,WWDT interrupt wake-up" "Disabled,Enabled" endif group.long 0x230++0x0B line.long 0x00 "PDSLEEPCFG,Deep-sleep Configuration Register" bitfld.long 0x00 6. " WDTOSC_PD ,Watchdog oscillator power-down control" "Powered,Powered down" bitfld.long 0x00 3. " BOD_PD ,BOD power-down control" "Powered,Powered down" line.long 0x04 "PDAWAKECFG,Wake-up Configuration Register" sif cpuis("LPC11U6*") bitfld.long 0x04 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down" bitfld.long 0x04 10. " USBPAD_PD ,USB transceiver wake-up configuration" "Powered,Powered down" bitfld.long 0x04 8. " USBPLL_PD ,USB PLL wake-up configuration" "Powered,Powered down" bitfld.long 0x04 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down" newline bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 5. " SYSOSC_PD ,Crystal oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down" bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down" newline bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down" bitfld.long 0x04 1. " IRC_PD ,IRC oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down" else bitfld.long 0x04 10. " USBPAD_PD ,USB transceiver wake-up configuration" "Powered,Powered down" bitfld.long 0x04 8. " USBPLL_PD ,USB PLL wake-up configuration" "Powered,Powered down" bitfld.long 0x04 7. " SYSPLL_PD ,System PLL wake-up configuration" "Powered,Powered down" bitfld.long 0x04 6. " WDTOSC_PD ,Watchdog oscillator wake-up configuration" "Powered,Powered down" newline bitfld.long 0x04 5. " SYSOSC_PD ,Crystal oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 4. " ADC_PD ,ADC wake-up configuration" "Powered,Powered down" bitfld.long 0x04 3. " BOD_PD ,BOD wake-up configuration" "Powered,Powered down" bitfld.long 0x04 2. " FLASH_PD ,Flash wake-up configuration" "Powered,Powered down" newline bitfld.long 0x04 1. " IRC_PD ,IRC oscillator wake-up configuration" "Powered,Powered down" bitfld.long 0x04 0. " IRCOUT_PD ,IRC oscillator output wake-up configuration" "Powered,Powered down" endif line.long 0x08 "PDRUNCFG,Power-down Configuration Register" sif cpuis("LPC11U6*") bitfld.long 0x08 13. " TEMPSENSE_PD ,Temperature sensor wake-up configuration" "Powered,Powered down" bitfld.long 0x08 10. " USBPAD_PD ,USB transceiver power-down configuration" "Powered,Powered down" bitfld.long 0x08 8. " USBPLL_PD ,USB PLL power-down" "Powered,Powered down" bitfld.long 0x08 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down" newline bitfld.long 0x08 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down" bitfld.long 0x08 5. " SYSOSC_PD ,Crystal oscillator power-down" "Powered,Powered down" bitfld.long 0x08 4. " ADC_PD ,ADC power-down" "Powered,Powered down" bitfld.long 0x08 3. " BOD_PD ,BOD power-down" "Powered,Powered down" newline bitfld.long 0x08 2. " FLASH_PD ,Flash power-down" "Powered,Powered down" bitfld.long 0x08 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down" bitfld.long 0x08 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down" else bitfld.long 0x08 10. " USBPAD_PD ,USB transceiver power-down configuration" "Powered,Powered down" bitfld.long 0x08 8. " USBPLL_PD ,USB PLL power-down" "Powered,Powered down" bitfld.long 0x08 7. " SYSPLL_PD ,System PLL power-down" "Powered,Powered down" bitfld.long 0x08 6. " WDTOSC_PD ,Watchdog oscillator power-down" "Powered,Powered down" newline bitfld.long 0x08 5. " SYSOSC_PD ,Crystal oscillator power-down" "Powered,Powered down" bitfld.long 0x08 4. " ADC_PD ,ADC power-down" "Powered,Powered down" bitfld.long 0x08 3. " BOD_PD ,BOD power-down" "Powered,Powered down" bitfld.long 0x08 2. " FLASH_PD ,Flash power-down" "Powered,Powered down" newline bitfld.long 0x08 1. " IRC_PD ,IRC oscillator power-down" "Powered,Powered down" bitfld.long 0x08 0. " IRCOUT_PD ,IRC oscillator output power-down" "Powered,Powered down" endif rgroup.long 0x3F4++0x03 line.long 0x00 "DEVICE_ID,Device ID Register" sif cpuis("LPC11U1*")||cpuis("LPC11U2*")||cpuis("LPC11U3*") group.long (0x10-0xC000)++0x03 line.long 0x00 "FLASHCFG,Flash Configuration Register" bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 system clock,2 system clocks,3 system clocks,?..." endif width 0x0B tree.end tree "PMU (Power Management Unit)" base ad:0x40038000 width 8. group.long 0x00++0x03 line.long 0x00 "PCON,Power Control Register" sif cpuis("LPC11U*") eventfld.long 0x00 11. " DPDFLAG ,Deep power-down flag" "Not occurred,Occurred" eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not occurred,Occurred" bitfld.long 0x00 3. " NODPD ,No deep-power-down mode flag" "Not occurred,Occurred" bitfld.long 0x00 0.--2. " PM ,Power mode" "Default,Deep-sleep,Power-down,Deep-power down,?..." else bitfld.long 0x00 11. " DPDFLAG ,Deep power-down mode entry prevention" "Not prevented,Prevented" eventfld.long 0x00 8. " SLEEPFLAG ,Sleep mode flag" "Not set,Set" eventfld.long 0x00 3. " NODPD ,Sleep mode flag" "Not set,Set" endif group.long 0x4++0x03 line.long 0x00 "GPREG0,General Purpose Register 0" group.long 0x8++0x03 line.long 0x00 "GPREG1,General Purpose Register 1" group.long 0xC++0x03 line.long 0x00 "GPREG2,General Purpose Register 2" group.long 0x10++0x03 line.long 0x00 "GPREG3,General Purpose Register 3" sif cpuis("LPC11U*") group.long 0x14++0x03 line.long 0x00 "GPREG4,General Purpose Register 4" hexmask.long.tbyte 0x00 11.--31. 1. " GPDATA ,Data retained during Deep power-down mode" bitfld.long 0x00 10. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "GPREG4,General Purpose Register 4/WAKEUP pad control" hexmask.long.tbyte 0x00 10.--31. 1. " DATA ,Data retained during Deep power-down mode" bitfld.long 0x00 1. " WAKEPAD_DISABLE ,WAKEUP pin disable" "No,Yes" bitfld.long 0x00 0. " WAKEUPHYS ,WAKEUP pin hysteresis enable" "Disabled,Enabled" endif width 0x0B tree.end sif cpuis("LPC11U6*") tree "IOCON (I/O Configuration)" base ad:0x40044000 width 15. group.long 0x00++0x03 line.long 0x00 "RESET_PIO0_0,I/O Configuration For Pin RESET/PIO0_0" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "RESET,PIO0_0,?..." group.long 0x04++0x0B line.long 0x00 "PIO0_1,I/O Configuration For Pin PIO0_1/CLKOUT/CT23B0_MAT2/USB_FTOGGLE" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_1,CLKOUT,CT23B0_MAT2,USB_FTOGGLE,?..." line.long 0x04 "PIO0_2,I/O Configuration For Pin PIO0_2/SSP0_SSEL/CT16B0_CAP0/R_0" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_2,SSP0_SSEL,CT16B0_CAP0,R_0,?..." line.long 0x08 "PIO0_3,I/O Configuration For Pin PIO0_3/USB_VBUS/R_1" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_3,USB_VBUS,R_1,?..." group.long 0x10++0x07 line.long 0x00 "PIO0_4,I/O Configuration For Pin PIO0_4/I2C0_SCL/R_2" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..." bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_4,I2C0_SCL,R_2,?..." line.long 0x04 "PIO0_5,I/O Configuration For Pin PIO0_5/I2C0_SDA/R_3" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..." bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_5,I2C0_SDA,R_3,?..." group.long 0x18++0x13 line.long 0x00 "PIO0_6,I/O Configuration For Pin PIO0_6/R/SSP0_SCK/R_4" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_6,R,SSP0_SCK,R_4,?..." line.long 0x04 "PIO0_7,I/O Configuration For Pin PIO0_7/U0_nCTS/R_5/I2C1_SCL" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_7,U0_nCTS,R_5,I2C1_SCL,?..." line.long 0x08 "PIO0_8,I/O Configuration For Pin PIO0_8/SSP0_MISO/CT16B0_MAT0/R/R_6" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_8,SSP0_MISO,CT16B0_MAT0,R,R_6,?..." line.long 0x0C "PIO0_9,I/O Configuration For Pin PIO0_9/SSP0_MOSI/CT16B0_MAT1/R_7" bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_9,SSP0_MOSI,CT16B0_MAT1,R_7,?..." line.long 0x10 "PIO0_10,I/O Configuration For Pin SWCLK/PIO0_10/SSP0_SCK/CT16B0_MAT2" bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "SWCLK,PIO0_10,SSP0_SCK,CT16B0_MAT2,?..." group.long 0x2C++0x17 line.long 0x00 "TDI_PIO0_11,I/O Configuration For Pin TDI/PIO0_11/ADC_9/CT32B0_MAT3/U1_nRTS/U1_SCLK" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "TDI,PIO0_11,ADC_9,CT32B0_MAT3,U1_nRTS,U1_SCLK,?..." line.long 0x04 "TMS_PIO0_12,I/O Configuration For Pin TMS/PIO0_12/ADC_8/CT32B1_CAP0/U1_CTS/PIO0_12" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x04 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "TMS,PIO0_12,ADC_8,CT32B1_CAP0,U1_CTS,PIO0_12,?..." line.long 0x08 "TDO_PIO0_13,I/O Configuration For Pin TDO/PIO0_13/ADC_7/CT32B1_MAT0/U1_RXD/PIO0_13" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x08 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "TDO,PIO0_13,ADC_7,CT32B1_MAT0,U1_RXD,PIO0_13,?..." line.long 0x0C "TRST_PIO0_14,I/O Configuration For Pin nTRST/PIO0_14/ADC_6/CT32B1_MAT1/U1_TXD" bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x0C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "nTRST,PIO0_14,ADC_6,CT32B1_MAT1,U1_TXD,?..." line.long 0x10 "SWDIO_PIO0_15,I/O Configuration For Pin SWDIO/PIO0_15/ADC_3/CT32B1_MAT2" bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x10 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "SWDIO,PIO0_15,ADC_3,CT32B1_MAT2,?..." line.long 0x14 "PIO0_16,I/O Configuration For Pin PIO0_16/ADC_2/CT32B1_MAT3/R_8" bitfld.long 0x14 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x14 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x14 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x14 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x14 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x14 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO0_16,ADC_2,CT32B1_MAT3,R_8,?..." group.long 0x44++0x13 line.long 0x00 "PIO0_17,I/O Configuration For Pin PIO0_17/U0_nRTS/CT32B0_CAP0/U0_SCLK" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_17,U0_nRTS,CT32B0_CAP0,U0_SCLK,?..." line.long 0x04 "PIO0_18,I/O Configuration For Pin PIO0_18/U0_RXD/CT32B0_MAT0" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_18,U0_RXD,CT32B0_MAT0,?..." line.long 0x08 "PIO0_19,I/O Configuration For Pin PIO0_19/U0_TXD/CT32B0_MAT1" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_19,U0_TXD,CT32B0_MAT1,?..." line.long 0x0C "PIO0_20,I/O Configuration For Pin PIO0_20/CT16B1_CAP0/U2_RXD" bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_20,CT16B1_CAP0,U2_RXD,?..." line.long 0x10 "PIO0_21,I/O Configuration For Pin PIO0_21/CT16B1_MAT0/SSP1_MOSI" bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_21,CT16B1_MAT0,SSP1_MOSI,?..." group.long 0x58++0x07 line.long 0x00 "PIO0_22,I/O Configuration For Pin PIO0_22/ADC_11/CT16B1_CAP1/SSP1_MISO" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO0_22,ADC_11,CT16B1_CAP1,SSP1_MISO,?..." line.long 0x04 "PIO0_23,I/O Configuration For Pin PIO0_23/ADC_1/R_9/U0_nRI/SSP1_SSEL" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x04 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_23,ADC_1,R_9,U0_nRI,SSP1_SSEL,?..." sif cpuis("LPC11E*") group.long 0x60++0x03 line.long 0x00 "PIO1_0,I/O Configuration For Pin PIO1_0/CT32B1_MAT0/R_10/U2_TXD" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_0,CT32B1_MAT0,R_10,U2_TXD,?..." endif sif cpuis("LPC11E6?JBD48")||cpuis("LPC11E6?JBD100") group.long 0x64++0x07 line.long 0x00 "PIO1_1,I/O Configuration For Pin PIO1_1/CT32B1_MAT1/R_11/U0_nDTR" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_1,CT32B1_MAT1,R_11,U0_nDTR,?..." line.long 0x04 "PIO1_2,I/O Configuration For Pin PIO1_2/CT32B1_MAT2/R_12/U1_RXD" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_2,CT32B1_MAT2,R_12,U1_RXD,?..." endif sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E*") group.long 0x60++0x03 line.long 0x00 "PIO1_0,I/O Configuration For Pin PIO1_0/CT32B1_MAT0/R_10/U2_TXD" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_0,CT32B1_MAT0,R_10,U2_TXD,?..." endif sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD48")||cpuis("LPC11E6?JBD100") sif !cpuis("LPC11E*") group.long 0x64++0x07 line.long 0x00 "PIO1_1,I/O Configuration For Pin PIO1_1/CT32B1_MAT1/R_11/U0_nDTR" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_1,CT32B1_MAT1,R_11,U0_nDTR,?..." line.long 0x04 "PIO1_2,I/O Configuration For Pin PIO1_2/CT32B1_MAT2/R_12/U1_RXD" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_2,CT32B1_MAT2,R_12,U1_RXD,?..." endif group.long 0x6C++0x07 line.long 0x00 "PIO1_3,I/O Configuration For Pin PIO1_3/CT32B1_MAT3/R_13/I2C1_SDA/ADC_5" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_3,CT32B1_MAT3,R_13,I2C1_SDA,ADC_5,?..." line.long 0x04 "PIO1_4,I/O Configuration For Pin PIO1_4/CT32B1_CAP0/R_14/U0_nDSR" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x04 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_4,CT32B1_CAP0,R_14,U0_nDSR,?..." group.long 0x74++0x07 line.long 0x00 "PIO1_5,I/O Configuration For Pin PIO1_5/CT32B1_CAP1/R_15/U0_nDCD" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_5,CT32B1_CAP1,R_15,U0_nDCD,?..." line.long 0x04 "PIO1_6,I/O Configuration For Pin PIO1_6/R_16/U2_RXD/CT32B0_CAP2" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_6,R_16,U2_RXD,CT32B0_CAP2,?..." endif sif !cpuis("LPC11U6?JBD48") group.long 0x7C++0x03 line.long 0x00 "PIO1_7,I/O Configuration For Pin PIO1_7/R_17/U2_nCTS/CT16B1_CAP0" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_7,R_17,U2_nCTS,CT16B1_CAP0,?..." endif sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD48")||cpuis("LPC11E6?JBD100") group.long 0x80++0x03 line.long 0x00 "PIO1_8,I/O Configuration For Pin PIO1_8/R_18/U1_TXD/CT16B0_CAP0" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_8,R_18,U1_TXD,CT16B0_CAP0,?..." endif sif !cpuis("LPC11U6?JBD48") group.long 0x84++0x07 line.long 0x00 "PIO1_9,I/O Configuration For Pin PIO1_9/U0_nCTS/CT16B1_MAT1/ADC_0" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_9,U0_nCTS,CT16B1_MAT1,ADC_0,?..." line.long 0x04 "PIO1_10,I/O Configuration For Pin PIO1_10/U2_nRTS/U2_SCLK/CT16B1_MAT0" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_10,U2_nRTS,U2_SCLK,CT16B1_MAT0,?..." sif !cpuis("LPC11U6?JBD64")&&!cpuis("LPC11E6?JBD48")&&!cpuis("LPC11E6?JBD100")&&!cpuis("LPC11E6?JBD64") group.long 0x8C++0x07 line.long 0x00 "PIO1_11,I/O Configuration For Pin PIO1_11/I2C1_SCL/CT16B0_MAT2/U0_nRI" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_11,I2C1_SCL,CT16B0_MAT2,U0_nRI,?..." line.long 0x04 "PIO1_12,I/O Configuration For Pin PIO1_12/SSP0_MOSI/CT16B0_MAT1/R_21" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_12,SSP0_MOSI,CT16B0_MAT1,R_21,?..." endif endif group.long 0x94++0x03 line.long 0x00 "PIO1_13,I/O Configuration For Pin PIO1_13/U1_nCTS/SCT0_OUT3/R_22" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_13,U1_nCTS,SCT0_OUT3,R_22,?..." sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100") group.long 0x98++0x13 line.long 0x00 "PIO1_14,I/O Configuration For Pin PIO1_14/I2C1_SDA/CT32B1_MAT2/R_23" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_14,I2C1_SDA,CT32B1_MAT2,R_23,?..." line.long 0x04 "PIO1_15,I/O Configuration For Pin PIO1_15/SSP0_SSEL/CT32B1_MAT3/R_24" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_15,SSP0_SSEL,CT32B1_MAT3,R_24,?..." line.long 0x08 "PIO1_16,I/O Configuration For Pin PIO1_16/SSP0_MISO/CT16B0_MAT0/R_25" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_16,SSP0_MISO,CT16B0_MAT0,R_25,?..." line.long 0x0C "PIO1_17,I/O Configuration For Pin PIO1_17/CT16B0_CAP2/U0_RXD/R_26" bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_17,CT16B0_CAP2,U0_RXD,R_26,?..." line.long 0x10 "PIO1_18,I/O Configuration For Pin PIO1_18/CT16B1_CAP1/U0_TXD/R_27" bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_18,CT16B1_CAP1,U0_TXD,R_27,?..." endif sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48") group.long 0xAC++0x03 line.long 0x00 "PIO1_19,I/O Configuration For Pin PIO1_19/U2_nCTS/SCT0_OUT0/R_28" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_19,U2_nCTS,SCT0_OUT0,R_28,?..." endif group.long 0xB0++0x03 line.long 0x00 "PIO1_20,I/O Configuration For Pin PIO1_20/U0_nDSR/SSP1_SCK/CT16B0_MAT0" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_20,U0_nDSR,SSP1_SCK,CT16B0_MAT0,?..." group.long 0xB4++0x03 line.long 0x00 "PIO1_21,I/O Configuration For Pin PIO1_21/U0_nDCD/SSP1_MISO/CT16B0_CAP2" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_21,U0_nDCD,SSP1_MISO,CT16B0_CAP2,?..." sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100") group.long 0xB8++0x03 line.long 0x00 "PIO1_22,I/O Configuration For Pin PIO1_22/SSP1_MOSI/CT32B1_CAP1/ADC_4/R_29" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_22,SSP1_MOSI,CT32B1_CAP1,ADC_4,R_29,?..." endif group.long 0xBC++0x07 line.long 0x00 "PIO1_23,I/O Configuration For Pin PIO1_23/CT16B1_MAT1/SSP1_SSEL/U2_TXD" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_23,CT16B1_MAT1,SSP1_SSEL,U2_TXD,?..." line.long 0x04 "PIO1_24,I/O Configuration For Pin PIO1_24/CT32B0_MAT0/I2C1_SDA" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_24,CT32B0_MAT0,I2C1_SDA,?..." sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100") group.long 0xC4++0x03 line.long 0x00 "PIO1_25,I/O Configuration For Pin PIO1_25/U2_nRTS/U2_SCLK/SCT0_IN0/R_30" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_25,U2_nRTS,U2_SCLK,SCT0_IN0,R_30,?..." endif sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48") group.long 0xC8++0x03 line.long 0x00 "PIO1_26,I/O Configuration For Pin PIO1_26/CT32B0_MAT2/U0_RXD/R_19" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_26,CT32B0_MAT2,U0_RXD,R_19,?..." endif sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")||cpuis("LPC11U6?JBD64") group.long 0xCC++0x0B line.long 0x00 "PIO1_27,I/O Configuration For Pin PIO1_27/CT32B0_MAT3/U0_TXD/R_20/SSP1_SCK" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_27,CT32B0_MAT3,U0_TXD,R_20,SSP1_SCK,?..." line.long 0x04 "PIO1_28,I/O Configuration For Pin PIO1_28/CT32B0_CAP0/U0_SCLK/U0_nRTS" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_28,CT32B0_CAP0,U0_SCLK,U0_nRTS,?..." line.long 0x08 "PIO1_29,I/O Configuration For Pin PIO1_29/SSP0_SCK/CT32B0_CAP2/U0_nDTR/ADC_10" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x08 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_29,SSP0_SCK,CT32B0_CAP2,U0_nDTR,ADC_10,?..." endif sif !cpuis("LPC11U6?JBD48")&&cpuis("LPC11E6?JBD48") group.long 0xD8++0x03 line.long 0x00 "PIO1_30,I/O Configuration For Pin PIO1_30/I2C1_SCL/SCT0_IN3/R_31" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_30,I2C1_SCL,SCT0_IN3,R_31,?..." endif sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100") group.long 0xDC++0x03 line.long 0x00 "PIO1_31,I/O Configuration For Pin PIO1_31" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_31,?..." endif group.long 0xF0++0x07 line.long 0x00 "PIO2_0,I/O Configuration For Pin PIO2_0/XTALIN" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_0,XTALIN,?..." sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E*")||cpuis("LPC11U6?JBD64")||cpuis("LPC11U6?JBD48") group.long 0xF4++0x03 line.long 0x00 "PIO2_1,I/O Configuration For Pin PIO2_1/XTALOUT" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" newline bitfld.long 0x00 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_1,XTALOUT,?..." endif group.long 0xFC++0x03 line.long 0x00 "PIO2_2,I/O Configuration For Pin PIO2_2/U3_nRTS/U3_SCLK/SCT0_OUT1" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_2,U3_nRTS,U3_SCLK,SCT0_OUT1,?..." sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E*") group.long 0x100++0x07 line.long 0x00 "PIO2_3,I/O Configuration For Pin PIO2_3/U3_RXD/CT32B0_MAT1" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_3,U3_RXD,CT32B0_MAT1,?..." line.long 0x04 "PIO2_4,I/O Configuration For Pin PIO2_4/U3_TXD/CT32B0_MAT2" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_4,U3_TXD,CT32B0_MAT2,?..." endif group.long 0x108++0x03 line.long 0x00 "PIO2_5,I/O Configuration For Pin PIO2_5/U3_nCTS/SCT0_IN1" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_5,U3_nCTS,SCT0_IN1,?..." sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100")||cpuis("LPC11U6?JBD64") group.long 0x10C++0x03 line.long 0x00 "PIO2_6,I/O Configuration For Pin PIO2_6/U1_nRTS/U1_SCLK/SCT0_IN2" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_6,U1_nRTS,U1_SCLK,SCT0_IN2,?..." endif group.long 0x110++0x03 line.long 0x00 "PIO2_7,I/O Configuration For Pin PIO2_7/SSP0_SCK/SCT0_OUT2" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_7,SSP0_SCK,SCT0_OUT2,?..." sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100") group.long 0x114++0x1B line.long 0x00 "PIO2_8,I/O Configuration For Pin PIO2_8/SCT1_IN0" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_8,SCT1_IN0,?..." line.long 0x04 "PIO2_9,I/O Configuration For Pin PIO2_9/SCT1_IN1" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_9,SCT1_IN1,?..." line.long 0x08 "PIO2_10,I/O Configuration For Pin PIO2_10/U4_nRTS/U4_SCLK" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO2_10,U4_nRTS,U4_SCLK,?..." line.long 0x0C "PIO2_11,I/O Configuration For Pin PIO2_11/U4_RXD" bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO2_11,U4_RXD,?..." line.long 0x10 "PIO2_12,I/O Configuration For Pin PIO2_12/U4_TXD" bitfld.long 0x10 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x10 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO2_12,U4_TXD,?..." line.long 0x14 "PIO2_13,I/O Configuration For Pin PIO2_13/U4_nCTS" bitfld.long 0x14 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x14 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x14 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x14 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO2_13,U4_nCTS,?..." line.long 0x18 "PIO2_14,I/O Configuration For Pin PIO2_14/SCT1_IN2" bitfld.long 0x18 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x18 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x18 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x18 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO2_14,SCT1_IN2,?..." endif sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48") group.long 0x130++0x03 line.long 0x00 "PIO2_15,I/O Configuration For Pin PIO2_15/SCT1_IN3" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_15,SCT1_IN3,?..." endif sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100") group.long 0x134++0x07 line.long 0x00 "PIO2_16,I/O Configuration For Pin PIO2_16/SCT1_OUT0" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_16,SCT1_OUT0,?..." line.long 0x04 "PIO2_17,I/O Configuration For Pin PIO2_17/SCT1_OUT1" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_17,SCT1_OUT1,?..." endif sif !cpuis("LPC11U6?JBD48")&&!cpuis("LPC11E6?JBD48") group.long 0x13C++0x07 line.long 0x00 "PIO2_18,I/O Configuration For Pin PIO2_18/SCT1_OUT2" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_18,SCT1_OUT2,?..." line.long 0x04 "PIO2_19,I/O Configuration For Pin PIO2_19/SCT1_OUT3" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_19,SCT1_OUT3,?..." endif sif cpuis("LPC11U6?JBD100")||cpuis("LPC11E6?JBD100") group.long 0x144++0x0F line.long 0x00 "PIO2_20,I/O Configuration For Pin PIO2_20" bitfld.long 0x00 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO2_20,?..." line.long 0x04 "PIO2_21,I/O Configuration For Pin PIO2_21" bitfld.long 0x04 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x04 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO2_21,?..." line.long 0x08 "PIO2_22,I/O Configuration For Pin PIO2_22" bitfld.long 0x08 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x08 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO2_22,?..." line.long 0x0C "PIO2_23,I/O Configuration For Pin PIO2_23" bitfld.long 0x0C 13.--15. " CLKDIV ,Peripheral clock divider for input filter sampling clock select" "0,1,2,3,4,5,6,?..." bitfld.long 0x0C 11.--12. " S_MODE ,Digital filter sample mode" "Bypassed,1 clk cycle,2 clk cycles,3 clk cycles" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO2_23,?..." endif width 0x0B tree.end else tree "IOCON (I/O Configuration)" base ad:0x40044000 width 15. group.long 0x00++0x5F line.long 0x00 "RESET_PIO0_0,I/O Configuration For Pin RESET/PIO0_0" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "Reset,PIO0_0,?..." line.long 0x04 "PIO0_1,I/O Configuration For Pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO0_1,CLKOUT,CT32B0_MAT2,USB_FTOGGLE,?..." line.long 0x08 "PIO0_2,I/O Configuration For Pin PIO0_2/SSEL0/CT16B0_CAP0/IOH_0" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO0_2,SSEL0,CT16B0_CAP0,IOH_0,?..." line.long 0x0C "PIO0_3,I/O Configuration For Pin PIO0_3/USB_VBUS/IOH_1" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO0_3,USB_VBUS,IOH_1,?..." line.long 0x10 "PIO0_4,I/O Configuration For Pin PIO0_4/SCL/IOH_2" bitfld.long 0x10 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..." bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO0_4,I2C SCL,IOH_2,?..." line.long 0x14 "PIO0_5,I/O Configuration For Pin PIO0_5/SDA/IOH_3" bitfld.long 0x14 8.--9. " I2CMODE ,I2C mode select" "Fast-mode,Standard GPIO,Fast-mode plus,?..." bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO0_5,I2C SDA,IOH_3,?..." line.long 0x18 "PIO0_6,I/O Configuration For Pin PIO0_6/USB_CONNECT/SCK0/IOH_4" bitfld.long 0x18 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x18 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO0_6,USB_CONNECT,SCK0,SCK0.IOH_4,?..." line.long 0x1C "PIO0_7,I/O Configuration For Pin PIO0_7/CTS/IOH_5" bitfld.long 0x1C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x1C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x1C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x1C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x1C 0.--2. " FUNC ,Selects pin function" "PIO0_7,CTS,IOH_5,?..." line.long 0x20 "PIO0_8,I/O Configuration For Pin PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6" bitfld.long 0x20 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x20 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x20 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x20 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x20 0.--2. " FUNC ,Selects pin function" "PIO0_8,MISO0,CT16B0_MAT0,IOH_6,?..." line.long 0x24 "PIO0_9,I/O Configuration For Pin PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7" bitfld.long 0x24 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x24 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x24 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x24 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x24 0.--2. " FUNC ,Selects pin function" "PIO0_9,MOSI0,CT16B0_MAT1,IOH_7,?..." line.long 0x28 "SWCLK_PIO0_10,I/O Configuration For Pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2" bitfld.long 0x28 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x28 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x28 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x28 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x28 0.--2. " FUNC ,Selects pin function" "SWCLK,PIO0_10,SCK0,CT16B0_MAT2,?..." line.long 0x2C "TDI_PIO0_11,I/O Configuration For Pin TDI/PIO0_11/AD0/CT32B0_MAT3" bitfld.long 0x2C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x2C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x2C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x2C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x2C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x2C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x2C 0.--2. " FUNC ,Selects pin function" "TDI,PIO0_11,AD0,CT32B0_MAT3,?..." line.long 0x30 "TMS_PIO0_12,I/O Configuration For Pin TMS/PIO0_12/AD1/CT32B1_CAP0" bitfld.long 0x30 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x30 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x30 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x30 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x30 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x30 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x30 0.--2. " FUNC ,Selects pin function" "TMS,PIO0_12,AD1,CT32B1_CAP0,?..." line.long 0x34 "TDO_PIO0_13,I/O Configuration For Pin TDO/PIO0_13/AD2/CT32B1_MAT0" bitfld.long 0x34 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x34 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x34 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x34 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x34 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x34 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x34 0.--2. " FUNC ,Selects pin function" "TDO,PIO0_13,AD2,CT32B1_MAT0,?..." line.long 0x38 "TRST_PIO0_14,I/O Configuration For Pin TRST/PIO0_14/AD3/CT32B1_MAT1" bitfld.long 0x38 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x38 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x38 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x38 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x38 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x38 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x38 0.--2. " FUNC ,Selects pin function" "TRST,PIO0_14,AD3,CT32B1_MAT1,?..." line.long 0x3C "SWDIO_PIO0_15,I/O Configuration For Pin SWDIO/PIO0_15/AD4/CT32B1_MAT2" bitfld.long 0x3C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x3C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x3C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x3C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x3C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x3C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x3C 0.--2. " FUNC ,Selects pin function" "SWDIO,PIO0_15,AD4,CT32B1_MAT2,?..." line.long 0x40 "PIO0_16,I/O Configuration For Pin PIO0_16/AD5/CT32B1_MAT3/IOH_8WAKEUP" bitfld.long 0x40 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x40 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x40 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x40 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x40 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x40 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x40 0.--2. " FUNC ,Selects pin function" "PIO0_16,AD5,CT32B1_MAT3,IOH_8,?..." line.long 0x44 "PIO0_17,I/O Configuration For Pin PIO0_17/RTS/CT32B0_CAP0/SCLK" bitfld.long 0x44 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x44 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x44 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x44 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x44 0.--2. " FUNC ,Selects pin function" "PIO0_17,RTS,CT32B0_CAP0,SCLK,?..." line.long 0x48 "PIO0_18,I/O Configuration For Pin PIO0_18/RXD/CT32B0_MAT0" bitfld.long 0x48 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x48 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x48 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x48 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x48 0.--2. " FUNC ,Selects pin function" "PIO0_18,RXD,CT32B0_MAT0,?..." line.long 0x4C "PIO0_19,I/O Configuration For Pin PIO0_19/TXD/CT32B0_MAT1" bitfld.long 0x4C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x4C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x4C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x4C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x4C 0.--2. " FUNC ,Selects pin function" "PIO0_19,TXD,CT32B0_MAT1,?..." line.long 0x50 "PIO0_20,I/O Configuration For Pin PIO0_20/CT16B1_CAP0" bitfld.long 0x50 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x50 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x50 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x50 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x50 0.--2. " FUNC ,Selects pin function" "PIO0_20,CT16B1_CAP0,?..." line.long 0x54 "PIO0_21,I/O Configuration For Pin PIO0_21/CT16B1_MAT0/MOSI1" bitfld.long 0x54 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x54 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x54 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x54 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x54 0.--2. " FUNC ,Selects pin function" "PIO0_21,CT16B1_MAT0,MOSI1,?..." line.long 0x58 "PIO0_22,I/O Configuration For Pin PIO0_22/AD6/CT16B1_MAT1/MISO1" bitfld.long 0x58 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x58 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x58 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x58 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x58 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x58 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x58 0.--2. " FUNC ,Selects pin function" "PIO0_22,AD6,CT16B1_MAT1,MISO1,?..." line.long 0x5C "PIO0_23,I/O Configuration For Pin PIO0_23/AD7/IOH_9" bitfld.long 0x5C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x5C 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x5C 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x5C 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x5C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x5C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x5C 0.--2. " FUNC ,Selects pin function" "PIO0_23,AD7,IOH_9,?..." sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0x60++0x13 line.long 0x00 "PIO1_0,I/O Configuration For Pin PIO1_0/CT32B1_MAT0/IOH_10" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_0,CT32B1_MAT1,IOH_10,?..." line.long 0x04 "PIO1_1,I/O Configuration For Pin PIO1_1/CT32B1_MAT1/IOH_11" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_1,CT32B1_MAT1,IOH_11,?..." line.long 0x08 "PIO1_2,I/O Configuration For Pin PIO1_2/CT32B1_MAT2IOH_12" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_2,CT32B1_MAT2,IOH_12,?..." line.long 0x0C "PIO1_3,I/O Configuration For Pin PIO1_3/CT32B1_MAT3/IOH_13" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_3,CT32B1_MAT3,IOH_13,?..." line.long 0x10 "PIO1_4,I/O Configuration For Pin PIO1_4/CT32B1_CAP0/IOH_14" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_4,CT32B1_CAP0,IOH_14,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0x74++0x03 line.long 0x00 "PIO1_5,I/O Configuration For Pin PIO1_5/CT32B1_CAP1/IOH_15" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_5,CT32B1_CAP1,IOH_15,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0x78++0x1B line.long 0x00 "PIO1_6,I/O Configuration For Pin PIO1_6/IOH_16" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_6,IOH_16,?..." line.long 0x04 "PIO1_7,I/O Configuration For Pin PIO1_7/IOH_17" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_7,IOH_17,?..." line.long 0x08 "PIO1_8,I/O Configuration For Pin PIO1_8/IOH_18" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_8,IOH_18,?..." line.long 0x0C "PIO1_9,I/O Configuration For Pin PIO1_9" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_9,?..." line.long 0x10 "PIO1_10,I/O Configuration For Pin PIO1_10" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_10,?..." line.long 0x14 "PIO1_11,I/O Configuration For Pin PIO1_11" bitfld.long 0x14 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x14 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x14 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x14 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x14 0.--2. " FUNC ,Selects pin function" "PIO1_11,?..." line.long 0x18 "PIO1_12,I/O Configuration For Pin PIO1_12" bitfld.long 0x18 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x18 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x18 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x18 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x18 0.--2. " FUNC ,Selects pin function" "PIO1_12,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0x94++0x07 line.long 0x00 "PIO1_13,I/O Configuration For Pin PIO1_13/DTR/CT16B0_MAT0/TXD" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_13,DTR,CT16B0_MAT0,TXD,?..." line.long 0x04 "PIO1_14,I/O Configuration For Pin PIO1_14/DSR/CT16B0_MAT1/RXD" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_14,DSR,CT16B0_MAT1,RXD,?..." endif sif !cpuis("LPC11U??/?01")&&!cpuis("LPC11U36FBD48") group.long 0x9C++0x03 line.long 0x00 "PIO1_15,I/O Configuration For Pin PIO1_15/DCD/CT16B0_MAT2/SCK1" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_15,DCD,CT16B0_MAT2,SCK1,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0xA0++0x03 line.long 0x00 "PIO1_16,I/O Configuration For Pin PIO1_16/RI/CT16B0_CAP0" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_16,RI,CT16B0_CAP0,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0xA4++0x07 line.long 0x00 "PIO1_17,I/O Configuration For Pin PIO1_17/CT16B0_CAP1/RXD" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_17,CT16B0_CAP1,RXD,?..." line.long 0x04 "PIO1_18,I/O Configuration For Pin PIO1_18/CT16B1_CAP1/TXD" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_18,CT16B1_CAP1,TXD,?..." endif sif !cpuis("LPC11U??/?01")&&!cpuis("LPC11U36FBD48") group.long 0xAC++0x03 line.long 0x00 "PIO1_19,I/O Configuration For Pin PIO1_19/DTR/SSEL1" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_19,DTR,SSEL1,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0xB0++0x27 line.long 0x00 "PIO1_20,I/O Configuration For Pin PIO1_20/DSR/SCK1" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_20,DSR,SCK1,?..." line.long 0x04 "PIO1_21,I/O Configuration For Pin PIO1_21/DCD/MISO1" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_21,DCD,MISO1,?..." line.long 0x08 "PIO1_22,I/O Configuration For Pin PIO1_22/RI/MOSI1" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_22,RI,MOSI1,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E1*")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0xBC++0x07 line.long 0x00 "PIO1_23,I/O Configuration For Pin PIO1_23/CT16B1_MAT1/SSEL1" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_23,CT16B1_MAT1,SSEL1,?..." line.long 0x04 "PIO1_24,I/O Configuration For Pin PIO1_24/CT32B0_MAT0" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_24,CT32B0_MAT0,?..." endif sif cpuis("LPC11U??FBD64*")||cpuis("LPC11U??HFBD64*")||cpuis("LPC11U35FET48*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U??FBD48*")||cpuis("LPC11U24/401")||cpuis("LPC11U36FBD48")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13")||cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37*") group.long 0xC4++0x13 line.long 0x00 "PIO1_25,I/O Configuration For Pin PIO1_25/CT32B0_MAT1" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_25,CT32B0_MAT1,?..." line.long 0x04 "PIO1_26,I/O Configuration For Pin PIO1_26/CT32B0_MAT2/RXD/IOH_19" bitfld.long 0x04 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x04 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x04 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x04 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x04 0.--2. " FUNC ,Selects pin function" "PIO1_26,CT32B0_MAT2,RXD,IOH_19,?..." line.long 0x08 "PIO1_27,I/O Configuration For Pin PIO1_27/CT32B0_MAT3/TXD/IOH_20" bitfld.long 0x08 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x08 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x08 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x08 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x08 0.--2. " FUNC ,Selects pin function" "PIO1_27,CT32B0_MAT3,TXD,IOH_20,?..." line.long 0x0C "PIO1_28,I/O Configuration For Pin PIO1_28/CT32B0_CAP0/SCLK" bitfld.long 0x0C 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x0C 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x0C 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x0C 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x0C 0.--2. " FUNC ,Selects pin function" "PIO1_28,CT32B0_CAP0,SCLK,?..." line.long 0x10 "PIO1_29,I/O Configuration For Pin PIO1_29/SCK0/CT32B0_CAP1" bitfld.long 0x10 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x10 8. " FILTR ,Fixed 10ns input glitch filter select" "Enabled,Disabled" bitfld.long 0x10 7. " ADMODE ,Analog mode" "Analog input,Digital I/O" bitfld.long 0x10 6. " INV ,Invert input" "Not inverted,Inverted" newline bitfld.long 0x10 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x10 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" bitfld.long 0x10 0.--2. " FUNC ,Selects pin function" "PIO1_29,SCK0,CT32B0_CAP1,?..." endif sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U??/201")||cpuis("LPC11U??/301")||cpuis("LPC11E12")||cpuis("LPC11E13") group.long 0xDC++0x03 line.long 0x00 "PIO1_31,I/O Configuration For Pin PIO1_31" bitfld.long 0x00 10. " OD ,Open-drain mode" "Disabled,Enabled" bitfld.long 0x00 6. " INV ,Invert input" "Not inverted,Inverted" bitfld.long 0x00 5. " HYS ,Hysteresis" "Disabled,Enabled" bitfld.long 0x00 3.--4. " MODE ,Selects function mode" "Inactive,Pull-down,Pull-up,Repeater" newline bitfld.long 0x00 0.--2. " FUNC ,Selects pin function" "PIO1_31,?..." endif width 0x0B tree.end endif tree "GPIO (General-Purpose I/O)" tree "GPIO Port Block Registers" sif cpuis("LPC11U6?JBD*") base ad:0xA0000000 width 7. tree "Byte Pin Registers" group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin P0_0" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_0" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin P0_1" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_1" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin P0_2" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_2" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin P0_3" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_3" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin P0_4" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_4" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin P0_5" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_5" "Low,High" group.byte 0x6++0x00 line.byte 0x00 "B6,Byte Pin Register Port 0 Pin P0_6" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_6" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin P0_7" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_7" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin P0_8" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_8" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin P0_9" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_9" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin P0_10" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_10" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin P0_11" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_11" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin P0_12" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_12" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin P0_13" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_13" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin P0_14" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_14" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin P0_15" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_15" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin P0_16" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_16" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin P0_17" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_17" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin P0_18" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_18" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin P0_19" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_19" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin P0_20" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_20" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin P0_21" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_21" "Low,High" group.byte 0x16++0x00 line.byte 0x00 "B22,Byte Pin Register Port 0 Pin P0_22" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_22" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin P0_23" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_23" "Low,High" sif !cpuis("LPC11U6?JBD48") group.byte 0x20++0x00 line.byte 0x00 "B32,Byte Pin Register Port 1 Pin P1_0" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_0" "Low,High" endif sif cpuis("LPC11U6?JBD100") group.byte 0x21++0x05 line.byte 0x00 "B33,Byte Pin Register Port 1 Pin P1_1" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_1" "Low,High" line.byte 0x01 "B34,Byte Pin Register Port 1 Pin P1_2" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_2" "Low,High" line.byte 0x02 "B35,Byte Pin Register Port 1 Pin P1_3" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_3" "Low,High" line.byte 0x03 "B36,Byte Pin Register Port 1 Pin P1_4" bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_4" "Low,High" line.byte 0x04 "B37,Byte Pin Register Port 1 Pin P1_5" bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO1_5" "Low,High" line.byte 0x05 "B38,Byte Pin Register Port 1 Pin P1_6" bitfld.byte 0x05 0. " PBYTE ,State of the pin PIO1_6" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x27++0x00 line.byte 0x00 "B39,Byte Pin Register Port 1 Pin P1_7" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_7" "Low,High" endif sif cpuis("LPC11U6?JBD100") group.byte 0x28++0x00 line.byte 0x00 "B40,Byte Pin Register Port 1 Pin P1_8" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_8" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x29++0x01 line.byte 0x00 "B41,Byte Pin Register Port 1 Pin P1_9" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_9" "Low,High" line.byte 0x01 "B42,Byte Pin Register Port 1 Pin P1_10" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_10" "Low,High" endif sif cpuis("LPC11U6?JBD100") group.byte 0x2B++0x01 line.byte 0x00 "B43,Byte Pin Register Port 1 Pin P1_11" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_11" "Low,High" line.byte 0x01 "B44,Byte Pin Register Port 1 Pin P1_12" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_12" "Low,High" endif group.byte 0x2D++0x00 line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_13" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High" sif cpuis("LPC11U6?JBD100") group.byte 0x2E++0x04 line.byte 0x00 "B46,Byte Pin Register Port 1 Pin P1_14" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_14" "Low,High" line.byte 0x01 "B47,Byte Pin Register Port 1 Pin P1_15" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_15" "Low,High" line.byte 0x02 "B48,Byte Pin Register Port 1 Pin P1_16" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_16" "Low,High" line.byte 0x03 "B49,Byte Pin Register Port 1 Pin P1_17" bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_17" "Low,High" line.byte 0x04 "B50,Byte Pin Register Port 1 Pin P1_18" bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO1_18" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x33++0x00 line.byte 0x00 "B51,Byte Pin Register Port 1 Pin P1_19" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_19" "Low,High" endif group.byte 0x34++0x01 line.byte 0x00 "B52,Byte Pin Register Port 1 Pin P1_20" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_20" "Low,High" line.byte 0x01 "B53,Byte Pin Register Port 1 Pin P1_21" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_21" "Low,High" sif cpuis("LPC11U6?JBD100") group.byte 0x36++0x00 line.byte 0x00 "B54,Byte Pin Register Port 1 Pin P1_22" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_22" "Low,High" endif group.byte 0x37++0x01 line.byte 0x00 "B55,Byte Pin Register Port 1 Pin P1_23" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_23" "Low,High" line.byte 0x01 "B56,Byte Pin Register Port 1 Pin P1_24" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_24" "Low,High" sif cpuis("LPC11U6?JBD100") group.byte 0x39++0x00 line.byte 0x00 "B57,Byte Pin Register Port 1 Pin P1_25" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_25" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x3A++0x00 line.byte 0x00 "B58,Byte Pin Register Port 1 Pin P1_26" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_26" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x3B++0x02 line.byte 0x00 "B59,Byte Pin Register Port 1 Pin P1_27" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_27" "Low,High" line.byte 0x01 "B60,Byte Pin Register Port 1 Pin P1_28" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_28" "Low,High" line.byte 0x02 "B61,Byte Pin Register Port 1 Pin P1_29" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_29" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x3E++0x00 line.byte 0x00 "B62,Byte Pin Register Port 1 Pin P1_30" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_30" "Low,High" endif sif cpuis("LPC11U6?JBD100") group.byte 0x3F++0x00 line.byte 0x00 "B63,Byte Pin Register Port 1 Pin P1_31" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_31" "Low,High" endif group.byte 0x40++0x02 line.byte 0x00 "B64,Byte Pin Register Port 2 Pin P2_0" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_0" "Low,High" line.byte 0x01 "B65,Byte Pin Register Port 2 Pin P2_1" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_1" "Low,High" line.byte 0x02 "B66,Byte Pin Register Port 2 Pin P2_2" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO2_2" "Low,High" sif cpuis("LPC11U6?JBD100") group.byte 0x43++0x01 line.byte 0x00 "B67,Byte Pin Register Port 2 Pin P2_3" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_3" "Low,High" line.byte 0x01 "B68,Byte Pin Register Port 2 Pin P2_4" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_4" "Low,High" endif group.byte 0x45++0x00 line.byte 0x00 "B69,Byte Pin Register Port 2 Pin P2_5" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_5" "Low,High" sif !cpuis("LPC11U6?JBD48") group.byte 0x46++0x00 line.byte 0x00 "B70,Byte Pin Register Port 2 Pin P2_6" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_6" "Low,High" endif group.byte 0x47++0x00 line.byte 0x00 "B71,Byte Pin Register Port 2 Pin P2_7" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_7" "Low,High" sif cpuis("LPC11U6?JBD100") group.byte 0x48++0x06 line.byte 0x00 "B72,Byte Pin Register Port 2 Pin P2_8" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_8" "Low,High" line.byte 0x01 "B73,Byte Pin Register Port 2 Pin P2_9" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_9" "Low,High" line.byte 0x02 "B74,Byte Pin Register Port 2 Pin P2_10" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO2_10" "Low,High" line.byte 0x03 "B75,Byte Pin Register Port 2 Pin P2_11" bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO2_11" "Low,High" line.byte 0x04 "B76,Byte Pin Register Port 2 Pin P2_12" bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO2_12" "Low,High" line.byte 0x05 "B77,Byte Pin Register Port 2 Pin P2_13" bitfld.byte 0x05 0. " PBYTE ,State of the pin PIO2_13" "Low,High" line.byte 0x06 "B78,Byte Pin Register Port 2 Pin P2_14" bitfld.byte 0x06 0. " PBYTE ,State of the pin PIO2_14" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x4F++0x00 line.byte 0x00 "B79,Byte Pin Register Port 2 Pin P2_15" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_15" "Low,High" endif sif cpuis("LPC11U6?JBD100") group.byte 0x50++0x01 line.byte 0x00 "B80,Byte Pin Register Port 2 Pin P2_16" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_16" "Low,High" line.byte 0x01 "B81,Byte Pin Register Port 2 Pin P2_17" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_17" "Low,High" endif sif !cpuis("LPC11U6?JBD48") group.byte 0x52++0x01 line.byte 0x00 "B82,Byte Pin Register Port 2 Pin P2_18" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_18" "Low,High" line.byte 0x01 "B83,Byte Pin Register Port 2 Pin P2_19" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_19" "Low,High" endif sif cpuis("LPC11U6?JBD100") group.byte 0x54++0x03 line.byte 0x00 "B84,Byte Pin Register Port 2 Pin P2_20" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO2_20" "Low,High" line.byte 0x01 "B85,Byte Pin Register Port 2 Pin P2_21" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO2_21" "Low,High" line.byte 0x02 "B86,Byte Pin Register Port 2 Pin P2_22" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO2_22" "Low,High" line.byte 0x03 "B87,Byte Pin Register Port 2 Pin P2_23" bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO2_23" "Low,High" endif tree.end tree "Word Pin Registers" group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin P0_0x1000" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin P0_0x1004" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin P0_0x1008" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin P0_0x100C" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin P0_0x1010" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin P0_0x1014" group.long 0x1018++0x03 line.long 0x00 "W6,Word Pin Register Port 0 Pin P0_0x1018" group.long 0x101C++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin P0_0x101C" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin P0_0x1020" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin P0_0x1024" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin P0_0x1028" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin P0_0x102C" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin P0_0x1030" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin P0_0x1034" group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin P0_0x1038" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin P0_0x103C" group.long 0x1040++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin P0_0x1040" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin P0_0x1044" group.long 0x1048++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin P0_0x1048" group.long 0x104C++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin P0_0x104C" group.long 0x1050++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin P0_0x1050" group.long 0x1054++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin P0_0x1054" group.long 0x1058++0x03 line.long 0x00 "W22,Word Pin Register Port 0 Pin P0_0x1058" group.long 0x105C++0x03 line.long 0x00 "W23,Word Pin Register Port 0 Pin P0_0x105C" sif !cpuis("LPC11U6?JBD48") group.long 0x1080++0x03 line.long 0x00 "W32,Word Pin Register Port 1 Pin P1_0" endif sif cpuis("LPC11U6?JBD100") group.long 0x1084++0x17 line.long 0x00 "W33,Word Pin Register Port 1 Pin P1_1" line.long 0x04 "W34,Word Pin Register Port 1 Pin P1_2" line.long 0x08 "W35,Word Pin Register Port 1 Pin P1_3" line.long 0x0C "W36,Word Pin Register Port 1 Pin P1_4" line.long 0x10 "W37,Word Pin Register Port 1 Pin P1_5" line.long 0x14 "W38,Word Pin Register Port 1 Pin P1_6" endif sif !cpuis("LPC11U6?JBD48") group.long 0x109C++0x03 line.long 0x00 "W39,Word Pin Register Port 1 Pin P1_7" endif sif cpuis("LPC11U6?JBD100") group.long 0x10A0++0x03 line.long 0x00 "W40,Word Pin Register Port 1 Pin P1_8" endif sif !cpuis("LPC11U6?JBD48") group.long 0x10A4++0x07 line.long 0x00 "W41,Word Pin Register Port 1 Pin P1_9" line.long 0x04 "W42,Word Pin Register Port 1 Pin P1_10" endif sif cpuis("LPC11U6?JBD100") group.long 0x10AC++0x07 line.long 0x00 "W43,Word Pin Register Port 1 Pin P1_11" line.long 0x04 "W44,Word Pin Register Port 1 Pin P1_12" endif group.long 0x10B4++0x03 line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_13" sif cpuis("LPC11U6?JBD100") group.long 0x10B8++0x13 line.long 0x00 "W46,Word Pin Register Port 1 Pin P1_14" line.long 0x04 "W47,Word Pin Register Port 1 Pin P1_15" line.long 0x08 "W48,Word Pin Register Port 1 Pin P1_16" line.long 0x0C "W49,Word Pin Register Port 1 Pin P1_17" line.long 0x10 "W50,Word Pin Register Port 1 Pin P1_18" endif sif !cpuis("LPC11U6?JBD48") group.long 0x10CC++0x03 line.long 0x00 "W51,Word Pin Register Port 1 Pin P1_19" endif group.long 0x10D0++0x07 line.long 0x00 "W52,Word Pin Register Port 1 Pin P1_20" line.long 0x04 "W53,Word Pin Register Port 1 Pin P1_21" sif cpuis("LPC11U6?JBD100") group.long 0x10D8++0x03 line.long 0x00 "W54,Word Pin Register Port 1 Pin P1_22" endif group.long 0x10DC++0x07 line.long 0x00 "W55,Word Pin Register Port 1 Pin P1_23" line.long 0x04 "W56,Word Pin Register Port 1 Pin P1_24" sif cpuis("LPC11U6?JBD100") group.long 0x10E4++0x03 line.long 0x00 "W57,Word Pin Register Port 1 Pin P1_25" endif sif !cpuis("LPC11U6?JBD48") group.long 0x10E8++0x03 line.long 0x00 "W58,Word Pin Register Port 1 Pin P1_26" endif sif !cpuis("LPC11U6?JBD48") group.long 0x10EC++0x0B line.long 0x00 "W59,Word Pin Register Port 1 Pin P1_27" line.long 0x04 "W60,Word Pin Register Port 1 Pin P1_28" line.long 0x08 "W61,Word Pin Register Port 1 Pin P1_29" endif sif !cpuis("LPC11U6?JBD48") group.long 0x10F8++0x03 line.long 0x00 "W62,Word Pin Register Port 1 Pin P1_30" endif sif cpuis("LPC11U6?JBD100") group.long 0x10FC++0x03 line.long 0x00 "W63,Word Pin Register Port 1 Pin P1_31" endif group.long 0x1100++0x0B line.long 0x00 "W64,Word Pin Register Port 2 Pin P2_0" line.long 0x04 "W65,Word Pin Register Port 2 Pin P2_1" line.long 0x08 "W66,Word Pin Register Port 2 Pin P2_2" sif cpuis("LPC11U6?JBD100") group.long 0x110C++0x07 line.long 0x00 "W67,Word Pin Register Port 2 Pin P2_3" line.long 0x04 "W68,Word Pin Register Port 2 Pin P2_4" endif group.long 0x1114++0x03 line.long 0x00 "W69,Word Pin Register Port 2 Pin P2_5" sif !cpuis("LPC11U6?JBD48") group.long 0x1118++0x03 line.long 0x00 "W70,Word Pin Register Port 2 Pin P2_6" endif group.long 0x111C++0x03 line.long 0x00 "W71,Word Pin Register Port 2 Pin P2_7" sif cpuis("LPC11U6?JBD100") group.long 0x1120++0x1B line.long 0x00 "W72,Word Pin Register Port 2 Pin P2_8" line.long 0x04 "W73,Word Pin Register Port 2 Pin P2_9" line.long 0x08 "W74,Word Pin Register Port 2 Pin P2_10" line.long 0x0C "W75,Word Pin Register Port 2 Pin P2_11" line.long 0x10 "W76,Word Pin Register Port 2 Pin P2_12" line.long 0x14 "W77,Word Pin Register Port 2 Pin P2_13" line.long 0x18 "W78,Word Pin Register Port 2 Pin P2_14" endif sif !cpuis("LPC11U6?JBD48") group.long 0x113C++0x03 line.long 0x00 "W79,Word Pin Register Port 2 Pin P2_15" endif sif cpuis("LPC11U6?JBD100") group.long 0x1140++0x07 line.long 0x00 "W80,Word Pin Register Port 2 Pin P2_16" line.long 0x04 "W81,Word Pin Register Port 2 Pin P2_17" endif sif !cpuis("LPC11U6?JBD48") group.long 0x1148++0x07 line.long 0x00 "W82,Word Pin Register Port 2 Pin P2_18" line.long 0x04 "W83,Word Pin Register Port 2 Pin P2_19" endif sif cpuis("LPC11U6?JBD100") group.long 0x1150++0x0F line.long 0x00 "W84,Word Pin Register Port 2 Pin P2_20" line.long 0x04 "W85,Word Pin Register Port 2 Pin P2_21" line.long 0x08 "W86,Word Pin Register Port 2 Pin P2_22" line.long 0x0C "W87,Word Pin Register Port 2 Pin P2_23" endif tree.end group.long 0x2000++0x0B line.long 0x00 "DIR0,Direction Registers Port 0" bitfld.long 0x00 23. " DIRP[23] ,PIO0_23 pin direction select" "Input,Output" bitfld.long 0x00 22. " [22] ,PIO0_22 pin direction select" "Input,Output" bitfld.long 0x00 21. " [21] ,PIO0_21 pin direction select" "Input,Output" bitfld.long 0x00 20. " [20] ,PIO0_20 pin direction select" "Input,Output" bitfld.long 0x00 19. " [19] ,PIO0_19 pin direction select" "Input,Output" bitfld.long 0x00 18. " [18] ,PIO0_18 pin direction select" "Input,Output" bitfld.long 0x00 17. " [17] ,PIO0_17 pin direction select" "Input,Output" bitfld.long 0x00 16. " [16] ,PIO0_16 pin direction select" "Input,Output" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin direction select" "Input,Output" bitfld.long 0x00 14. " [14] ,PIO0_14 pin direction select" "Input,Output" bitfld.long 0x00 13. " [13] ,PIO0_13 pin direction select" "Input,Output" bitfld.long 0x00 12. " [12] ,PIO0_12 pin direction select" "Input,Output" bitfld.long 0x00 11. " [11] ,PIO0_11 pin direction select" "Input,Output" bitfld.long 0x00 10. " [10] ,PIO0_10 pin direction select" "Input,Output" bitfld.long 0x00 9. " [9] ,PIO0_9 pin direction select" "Input,Output" bitfld.long 0x00 8. " [8] ,PIO0_8 pin direction select" "Input,Output" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin direction select" "Input,Output" bitfld.long 0x00 6. " [6] ,PIO0_6 pin direction select" "Input,Output" bitfld.long 0x00 5. " [5] ,PIO0_5 pin direction select" "Input,Output" bitfld.long 0x00 4. " [4] ,PIO0_4 pin direction select" "Input,Output" bitfld.long 0x00 3. " [3] ,PIO0_3 pin direction select" "Input,Output" bitfld.long 0x00 2. " [2] ,PIO0_2 pin direction select" "Input,Output" bitfld.long 0x00 1. " [1] ,PIO0_1 pin direction select" "Input,Output" bitfld.long 0x00 0. " [0] ,PIO0_0 pin direction select" "Input,Output" line.long 0x04 "DIR1,Direction Registers Port 1" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " DIRP[30] ,PIO1_30 pin direction select" "Input,Output" bitfld.long 0x04 29. " [29] ,PIO1_29 pin direction select" "Input,Output" bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output" bitfld.long 0x04 27. " [27] ,PIO1_27 pin direction select" "Input,Output" bitfld.long 0x04 26. " [26] ,PIO1_26 pin direction select" "Input,Output" bitfld.long 0x04 24. " [24] ,PIO1_24 pin direction select" "Input,Output" bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output" bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output" newline bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output" bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output" bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output" bitfld.long 0x04 10. " [10] ,PIO1_10 pin direction select" "Input,Output" bitfld.long 0x04 9. " [9] ,PIO1_9 pin direction select" "Input,Output" bitfld.long 0x04 7. " [7] ,PIO1_7 pin direction select" "Input,Output" bitfld.long 0x04 0. " [0] ,PIO1_0 pin direction select" "Input,Output" else bitfld.long 0x04 24. " DIRP[24] ,PIO1_24 pin direction select" "Input,Output" bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output" bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output" bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output" bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output" endif else bitfld.long 0x04 31. " DIRP[31] ,PIO1_31 pin direction select" "Input,Output" bitfld.long 0x04 30. " [30] ,PIO1_30 pin direction select" "Input,Output" bitfld.long 0x04 29. " [29] ,PIO1_29 pin direction select" "Input,Output" bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output" bitfld.long 0x04 27. " [27] ,PIO1_27 pin direction select" "Input,Output" bitfld.long 0x04 26. " [26] ,PIO1_26 pin direction select" "Input,Output" bitfld.long 0x04 25. " [25] ,PIO1_25 pin direction select" "Input,Output" bitfld.long 0x04 24. " [24] ,PIO1_24 pin direction select" "Input,Output" newline bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output" bitfld.long 0x04 22. " [22] ,PIO1_22 pin direction select" "Input,Output" bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output" bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output" bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output" bitfld.long 0x04 18. " [18] ,PIO1_18 pin direction select" "Input,Output" bitfld.long 0x04 17. " [17] ,PIO1_17 pin direction select" "Input,Output" bitfld.long 0x04 16. " [16] ,PIO1_16 pin direction select" "Input,Output" newline bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output" bitfld.long 0x04 14. " [14] ,PIO1_14 pin direction select" "Input,Output" bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output" bitfld.long 0x04 12. " [12] ,PIO1_12 pin direction select" "Input,Output" bitfld.long 0x04 11. " [11] ,PIO1_11 pin direction select" "Input,Output" bitfld.long 0x04 10. " [10] ,PIO1_10 pin direction select" "Input,Output" bitfld.long 0x04 9. " [9] ,PIO1_9 pin direction select" "Input,Output" bitfld.long 0x04 8. " [8] ,PIO1_8 pin direction select" "Input,Output" newline bitfld.long 0x04 7. " [7] ,PIO1_7 pin direction select" "Input,Output" bitfld.long 0x04 6. " [6] ,PIO1_6 pin direction select" "Input,Output" bitfld.long 0x04 5. " [5] ,PIO1_5 pin direction select" "Input,Output" bitfld.long 0x04 4. " [4] ,PIO1_4 pin direction select" "Input,Output" bitfld.long 0x04 3. " [3] ,PIO1_3 pin direction select" "Input,Output" bitfld.long 0x04 2. " [2] ,PIO1_2 pin direction select" "Input,Output" bitfld.long 0x04 1. " [1] ,PIO1_1 pin direction select" "Input,Output" bitfld.long 0x04 0. " [0] ,PIO1_0 pin direction select" "Input,Output" endif line.long 0x08 "DIR2,Direction Registers Port 2" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x08 19. " DIRP[19] ,PIO2_19 pin direction select" "Input,Output" bitfld.long 0x08 18. " [18] ,PIO2_18 pin direction select" "Input,Output" bitfld.long 0x08 15. " [15] ,PIO2_15 pin direction select" "Input,Output" bitfld.long 0x08 7. " [7] ,PIO2_7 pin direction select" "Input,Output" bitfld.long 0x08 6. " [6] ,PIO2_6 pin direction select" "Input,Output" bitfld.long 0x08 5. " [5] ,PIO2_5 pin direction select" "Input,Output" bitfld.long 0x08 2. " [2] ,PIO2_2 pin direction select" "Input,Output" bitfld.long 0x08 1. " [1] ,PIO2_1 pin direction select" "Input,Output" newline bitfld.long 0x08 0. " [0] ,PIO2_0 pin direction select" "Input,Output" else bitfld.long 0x08 7. " DIRP[7] ,PIO2_7 pin direction select" "Input,Output" bitfld.long 0x08 6. " [6] ,PIO2_6 pin direction select" "Input,Output" bitfld.long 0x08 5. " [5] ,PIO2_5 pin direction select" "Input,Output" bitfld.long 0x08 2. " [2] ,PIO2_2 pin direction select" "Input,Output" bitfld.long 0x08 1. " [1] ,PIO2_1 pin direction select" "Input,Output" bitfld.long 0x08 0. " [0] ,PIO2_0 pin direction select" "Input,Output" endif else bitfld.long 0x08 23. " DIRP[23] ,PIO2_23 pin direction select" "Input,Output" bitfld.long 0x08 22. " [22] ,PIO2_22 pin direction select" "Input,Output" bitfld.long 0x08 21. " [21] ,PIO2_21 pin direction select" "Input,Output" bitfld.long 0x08 20. " [20] ,PIO2_20 pin direction select" "Input,Output" bitfld.long 0x08 19. " [19] ,PIO2_19 pin direction select" "Input,Output" bitfld.long 0x08 18. " [18] ,PIO2_18 pin direction select" "Input,Output" bitfld.long 0x08 17. " [17] ,PIO2_17 pin direction select" "Input,Output" bitfld.long 0x08 16. " [16] ,PIO2_16 pin direction select" "Input,Output" newline bitfld.long 0x08 15. " [15] ,PIO2_15 pin direction select" "Input,Output" bitfld.long 0x08 14. " [14] ,PIO2_14 pin direction select" "Input,Output" bitfld.long 0x08 13. " [13] ,PIO2_13 pin direction select" "Input,Output" bitfld.long 0x08 12. " [12] ,PIO2_12 pin direction select" "Input,Output" bitfld.long 0x08 11. " [11] ,PIO2_11 pin direction select" "Input,Output" bitfld.long 0x08 10. " [10] ,PIO2_10 pin direction select" "Input,Output" bitfld.long 0x08 9. " [9] ,PIO2_9 pin direction select" "Input,Output" bitfld.long 0x08 8. " [8] ,PIO2_8 pin direction select" "Input,Output" newline bitfld.long 0x08 7. " [7] ,PIO2_7 pin direction select" "Input,Output" bitfld.long 0x08 6. " [6] ,PIO2_6 pin direction select" "Input,Output" bitfld.long 0x08 5. " [5] ,PIO2_5 pin direction select" "Input,Output" bitfld.long 0x08 4. " [4] ,PIO2_4 pin direction select" "Input,Output" bitfld.long 0x08 3. " [3] ,PIO2_3 pin direction select" "Input,Output" bitfld.long 0x08 2. " [2] ,PIO2_2 pin direction select" "Input,Output" bitfld.long 0x08 1. " [1] ,PIO2_1 pin direction select" "Input,Output" bitfld.long 0x08 0. " [0] ,PIO2_0 pin direction select" "Input,Output" endif group.long 0x2080++0x0B line.long 0x00 "MASK0,Mask Register Port 0" bitfld.long 0x00 23. " MASK[23] ,PIO0_23 pin mask bit" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,PIO0_22 pin mask bit" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,PIO0_21 pin mask bit" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,PIO0_20 pin mask bit" "Not masked,Masked" bitfld.long 0x00 19. " [19] ,PIO0_19 pin mask bit" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,PIO0_18 pin mask bit" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,PIO0_17 pin mask bit" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,PIO0_16 pin mask bit" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin mask bit" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,PIO0_14 pin mask bit" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,PIO0_13 pin mask bit" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,PIO0_12 pin mask bit" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,PIO0_11 pin mask bit" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,PIO0_10 pin mask bit" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,PIO0_9 pin mask bit" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,PIO0_8 pin mask bit" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin mask bit" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,PIO0_6 pin mask bit" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,PIO0_5 pin mask bit" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,PIO0_4 pin mask bit" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,PIO0_3 pin mask bit" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,PIO0_2 pin mask bit" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,PIO0_1 pin mask bit" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,PIO0_0 pin mask bit" "Not masked,Masked" line.long 0x04 "MASK1,Mask Register Port 1" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " MASK[30] ,PIO1_30 pin mask bit" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,PIO1_29 pin mask bit" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked" bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked" bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked" bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,PIO1_10 pin mask bit" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,PIO1_9 pin mask bit" "Not masked,Masked" bitfld.long 0x04 7. " [7] ,PIO1_7 pin mask bit" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,PIO1_0 pin mask bit" "Not masked,Masked" else bitfld.long 0x04 24. " MASK[24] ,PIO1_24 pin mask bit" "Not masked,Masked" bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked" endif else bitfld.long 0x04 31. " MASK[31] ,PIO1_31 pin mask bit" "Not masked,Masked" bitfld.long 0x04 30. " [30] ,PIO1_30 pin mask bit" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,PIO1_29 pin mask bit" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked" bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,PIO1_25 pin mask bit" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,PIO1_22 pin mask bit" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked" bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,PIO1_18 pin mask bit" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,PIO1_17 pin mask bit" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,PIO1_16 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,PIO1_14 pin mask bit" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,PIO1_12 pin mask bit" "Not masked,Masked" bitfld.long 0x04 11. " [11] ,PIO1_11 pin mask bit" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,PIO1_10 pin mask bit" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,PIO1_9 pin mask bit" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,PIO1_8 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 7. " [7] ,PIO1_7 pin mask bit" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,PIO1_6 pin mask bit" "Not masked,Masked" bitfld.long 0x04 5. " [5] ,PIO1_5 pin mask bit" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,PIO1_4 pin mask bit" "Not masked,Masked" bitfld.long 0x04 3. " [3] ,PIO1_3 pin mask bit" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,PIO1_2 pin mask bit" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,PIO1_1 pin mask bit" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,PIO1_0 pin mask bit" "Not masked,Masked" endif line.long 0x08 "MASK2,Mask Register Port 2" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x08 19. " MASK[19] ,PIO2_19 pin mask bit" "Not masked,Masked" bitfld.long 0x08 18. " [18] ,PIO2_18 pin mask bit" "Not masked,Masked" bitfld.long 0x08 15. " [15] ,PIO2_15 pin mask bit" "Not masked,Masked" bitfld.long 0x08 7. " [7] ,PIO2_7 pin mask bit" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,PIO2_6 pin mask bit" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,PIO2_5 pin mask bit" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,PIO2_2 pin mask bit" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,PIO2_1 pin mask bit" "Not masked,Masked" newline bitfld.long 0x08 0. " [0] ,PIO2_0 pin mask bit" "Not masked,Masked" else bitfld.long 0x08 7. " MASK[7] ,PIO2_7 pin mask bit" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,PIO2_5 pin mask bit" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,PIO2_2 pin mask bit" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,PIO2_1 pin mask bit" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,PIO2_0 pin mask bit" "Not masked,Masked" endif else bitfld.long 0x08 23. " MASK[23] ,PIO2_23 pin mask bit" "Not masked,Masked" bitfld.long 0x08 22. " [22] ,PIO2_22 pin mask bit" "Not masked,Masked" bitfld.long 0x08 21. " [21] ,PIO2_21 pin mask bit" "Not masked,Masked" bitfld.long 0x08 20. " [20] ,PIO2_20 pin mask bit" "Not masked,Masked" bitfld.long 0x08 19. " [19] ,PIO2_19 pin mask bit" "Not masked,Masked" bitfld.long 0x08 18. " [18] ,PIO2_18 pin mask bit" "Not masked,Masked" bitfld.long 0x08 17. " [17] ,PIO2_17 pin mask bit" "Not masked,Masked" bitfld.long 0x08 16. " [16] ,PIO2_16 pin mask bit" "Not masked,Masked" newline bitfld.long 0x08 15. " [15] ,PIO2_15 pin mask bit" "Not masked,Masked" bitfld.long 0x08 14. " [14] ,PIO2_14 pin mask bit" "Not masked,Masked" bitfld.long 0x08 13. " [13] ,PIO2_13 pin mask bit" "Not masked,Masked" bitfld.long 0x08 12. " [12] ,PIO2_12 pin mask bit" "Not masked,Masked" bitfld.long 0x08 11. " [11] ,PIO2_11 pin mask bit" "Not masked,Masked" bitfld.long 0x08 10. " [10] ,PIO2_10 pin mask bit" "Not masked,Masked" bitfld.long 0x08 9. " [9] ,PIO2_9 pin mask bit" "Not masked,Masked" bitfld.long 0x08 8. " [8] ,PIO2_8 pin mask bit" "Not masked,Masked" newline bitfld.long 0x08 7. " [7] ,PIO2_7 pin mask bit" "Not masked,Masked" bitfld.long 0x08 6. " [6] ,PIO2_6 pin mask bit" "Not masked,Masked" bitfld.long 0x08 5. " [5] ,PIO2_5 pin mask bit" "Not masked,Masked" bitfld.long 0x08 4. " [4] ,PIO2_4 pin mask bit" "Not masked,Masked" bitfld.long 0x08 3. " [3] ,PIO2_3 pin mask bit" "Not masked,Masked" bitfld.long 0x08 2. " [2] ,PIO2_2 pin mask bit" "Not masked,Masked" bitfld.long 0x08 1. " [1] ,PIO2_1 pin mask bit" "Not masked,Masked" bitfld.long 0x08 0. " [0] ,PIO2_0 pin mask bit" "Not masked,Masked" endif newline group.long 0x2100++0x0B line.long 0x00 "PIN0,Port Pin Register Port 0" bitfld.long 0x00 23. " PORT[23] ,PIO0_23 pin state" "Cleared,Set" bitfld.long 0x00 22. " [22] ,PIO0_22 pin state" "Cleared,Set" bitfld.long 0x00 21. " [21] ,PIO0_21 pin state" "Cleared,Set" bitfld.long 0x00 20. " [20] ,PIO0_20 pin state" "Cleared,Set" bitfld.long 0x00 19. " [19] ,PIO0_19 pin state" "Cleared,Set" bitfld.long 0x00 18. " [18] ,PIO0_18 pin state" "Cleared,Set" bitfld.long 0x00 17. " [17] ,PIO0_17 pin state" "Cleared,Set" bitfld.long 0x00 16. " [16] ,PIO0_16 pin state" "Cleared,Set" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin state" "Cleared,Set" bitfld.long 0x00 14. " [14] ,PIO0_14 pin state" "Cleared,Set" bitfld.long 0x00 13. " [13] ,PIO0_13 pin state" "Cleared,Set" bitfld.long 0x00 12. " [12] ,PIO0_12 pin state" "Cleared,Set" bitfld.long 0x00 11. " [11] ,PIO0_11 pin state" "Cleared,Set" bitfld.long 0x00 10. " [10] ,PIO0_10 pin state" "Cleared,Set" bitfld.long 0x00 9. " [9] ,PIO0_9 pin state" "Cleared,Set" bitfld.long 0x00 8. " [8] ,PIO0_8 pin state" "Cleared,Set" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin state" "Cleared,Set" bitfld.long 0x00 6. " [6] ,PIO0_6 pin state" "Cleared,Set" bitfld.long 0x00 5. " [5] ,PIO0_5 pin state" "Cleared,Set" bitfld.long 0x00 4. " [4] ,PIO0_4 pin state" "Cleared,Set" bitfld.long 0x00 3. " [3] ,PIO0_3 pin state" "Cleared,Set" bitfld.long 0x00 2. " [2] ,PIO0_2 pin state" "Cleared,Set" bitfld.long 0x00 1. " [1] ,PIO0_1 pin state" "Cleared,Set" bitfld.long 0x00 0. " [0] ,PIO0_0 pin state" "Cleared,Set" line.long 0x04 "PIN1,Port Pin Register Port 1" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " PORT[30] ,PIO1_30 pin state" "Cleared,Set" bitfld.long 0x04 29. " [29] ,PIO1_29 pin state" "Cleared,Set" bitfld.long 0x04 28. " [28] ,PIO1_28 pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 pin state" "Cleared,Set" newline bitfld.long 0x04 20. " [20] ,PIO1_20 pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 pin state" "Cleared,Set" bitfld.long 0x04 10. " [10] ,PIO1_10 pin state" "Cleared,Set" bitfld.long 0x04 9. " [9] ,PIO1_9 pin state" "Cleared,Set" bitfld.long 0x04 7. " [7] ,PIO1_7 pin state" "Cleared,Set" bitfld.long 0x04 0. " [0] ,PIO1_0 pin state" "Cleared,Set" else bitfld.long 0x04 24. " PORT[24] ,PIO1_24 pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 pin state" "Cleared,Set" endif else bitfld.long 0x04 31. " PORT[31] ,PIO1_31 pin state" "Cleared,Set" bitfld.long 0x04 30. " [30] ,PIO1_30 pin state" "Cleared,Set" bitfld.long 0x04 29. " [29] ,PIO1_29 pin state" "Cleared,Set" bitfld.long 0x04 28. " [28] ,PIO1_28 pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 pin state" "Cleared,Set" bitfld.long 0x04 25. " [25] ,PIO1_25 pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 pin state" "Cleared,Set" newline bitfld.long 0x04 23. " [23] ,PIO1_23 pin state" "Cleared,Set" bitfld.long 0x04 22. " [22] ,PIO1_22 pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 pin state" "Cleared,Set" bitfld.long 0x04 18. " [18] ,PIO1_18 pin state" "Cleared,Set" bitfld.long 0x04 17. " [17] ,PIO1_17 pin state" "Cleared,Set" bitfld.long 0x04 16. " [16] ,PIO1_16 pin state" "Cleared,Set" newline bitfld.long 0x04 15. " [15] ,PIO1_15 pin state" "Cleared,Set" bitfld.long 0x04 14. " [14] ,PIO1_14 pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 pin state" "Cleared,Set" bitfld.long 0x04 12. " [12] ,PIO1_12 pin state" "Cleared,Set" bitfld.long 0x04 11. " [11] ,PIO1_11 pin state" "Cleared,Set" bitfld.long 0x04 10. " [10] ,PIO1_10 pin state" "Cleared,Set" bitfld.long 0x04 9. " [9] ,PIO1_9 pin state" "Cleared,Set" bitfld.long 0x04 8. " [8] ,PIO1_8 pin state" "Cleared,Set" newline bitfld.long 0x04 7. " [7] ,PIO1_7 pin state" "Cleared,Set" bitfld.long 0x04 6. " [6] ,PIO1_6 pin state" "Cleared,Set" bitfld.long 0x04 5. " [5] ,PIO1_5 pin state" "Cleared,Set" bitfld.long 0x04 4. " [4] ,PIO1_4 pin state" "Cleared,Set" bitfld.long 0x04 3. " [3] ,PIO1_3 pin state" "Cleared,Set" bitfld.long 0x04 2. " [2] ,PIO1_2 pin state" "Cleared,Set" bitfld.long 0x04 1. " [1] ,PIO1_1 pin state" "Cleared,Set" bitfld.long 0x04 0. " [0] ,PIO1_0 pin state" "Cleared,Set" endif line.long 0x08 "PIN2,Port Pin Register Port 2" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x08 19. " PORT[19] ,PIO2_19 pin state" "Cleared,Set" bitfld.long 0x08 18. " [18] ,PIO2_18 pin state" "Cleared,Set" bitfld.long 0x08 15. " [15] ,PIO2_15 pin state" "Cleared,Set" bitfld.long 0x08 7. " [7] ,PIO2_7 pin state" "Cleared,Set" bitfld.long 0x08 6. " [6] ,PIO2_6 pin state" "Cleared,Set" bitfld.long 0x08 5. " [5] ,PIO2_5 pin state" "Cleared,Set" bitfld.long 0x08 2. " [2] ,PIO2_2 pin state" "Cleared,Set" bitfld.long 0x08 1. " [1] ,PIO2_1 pin state" "Cleared,Set" newline bitfld.long 0x08 0. " [0] ,PIO2_0 pin state" "Cleared,Set" else bitfld.long 0x08 7. " PORT[7] ,PIO2_7 pin state" "Cleared,Set" bitfld.long 0x08 5. " [5] ,PIO2_5 pin state" "Cleared,Set" bitfld.long 0x08 2. " [2] ,PIO2_2 pin state" "Cleared,Set" bitfld.long 0x08 1. " [1] ,PIO2_1 pin state" "Cleared,Set" bitfld.long 0x08 0. " [0] ,PIO2_0 pin state" "Cleared,Set" endif else bitfld.long 0x08 23. " PORT[23] ,PIO2_23 pin state" "Cleared,Set" bitfld.long 0x08 22. " [22] ,PIO2_22 pin state" "Cleared,Set" bitfld.long 0x08 21. " [21] ,PIO2_21 pin state" "Cleared,Set" bitfld.long 0x08 20. " [20] ,PIO2_20 pin state" "Cleared,Set" bitfld.long 0x08 19. " [19] ,PIO2_19 pin state" "Cleared,Set" bitfld.long 0x08 18. " [18] ,PIO2_18 pin state" "Cleared,Set" bitfld.long 0x08 17. " [17] ,PIO2_17 pin state" "Cleared,Set" bitfld.long 0x08 16. " [16] ,PIO2_16 pin state" "Cleared,Set" newline bitfld.long 0x08 15. " [15] ,PIO2_15 pin state" "Cleared,Set" bitfld.long 0x08 14. " [14] ,PIO2_14 pin state" "Cleared,Set" bitfld.long 0x08 13. " [13] ,PIO2_13 pin state" "Cleared,Set" bitfld.long 0x08 12. " [12] ,PIO2_12 pin state" "Cleared,Set" bitfld.long 0x08 11. " [11] ,PIO2_11 pin state" "Cleared,Set" bitfld.long 0x08 10. " [10] ,PIO2_10 pin state" "Cleared,Set" bitfld.long 0x08 9. " [9] ,PIO2_9 pin state" "Cleared,Set" bitfld.long 0x08 8. " [8] ,PIO2_8 pin state" "Cleared,Set" newline bitfld.long 0x08 7. " [7] ,PIO2_7 pin state" "Cleared,Set" bitfld.long 0x08 6. " [6] ,PIO2_6 pin state" "Cleared,Set" bitfld.long 0x08 5. " [5] ,PIO2_5 pin state" "Cleared,Set" bitfld.long 0x08 4. " [4] ,PIO2_4 pin state" "Cleared,Set" bitfld.long 0x08 3. " [3] ,PIO2_3 pin state" "Cleared,Set" bitfld.long 0x08 2. " [2] ,PIO2_2 pin state" "Cleared,Set" bitfld.long 0x08 1. " [1] ,PIO2_1 pin state" "Cleared,Set" bitfld.long 0x08 0. " [0] ,PIO2_0 pin state" "Cleared,Set" endif group.long 0x2180++0x0B line.long 0x00 "MPIN0,Masked Port Register Port 0" bitfld.long 0x00 23. " MPORTP[23] ,PIO0_23 masked pin state" "Cleared,Set" bitfld.long 0x00 22. " [22] ,PIO0_22 masked pin state" "Cleared,Set" bitfld.long 0x00 21. " [21] ,PIO0_21 masked pin state" "Cleared,Set" bitfld.long 0x00 20. " [20] ,PIO0_20 masked pin state" "Cleared,Set" bitfld.long 0x00 19. " [19] ,PIO0_19 masked pin state" "Cleared,Set" bitfld.long 0x00 18. " [18] ,PIO0_18 masked pin state" "Cleared,Set" bitfld.long 0x00 17. " [17] ,PIO0_17 masked pin state" "Cleared,Set" bitfld.long 0x00 16. " [16] ,PIO0_16 masked pin state" "Cleared,Set" newline bitfld.long 0x00 15. " [15] ,PIO0_15 masked pin state" "Cleared,Set" bitfld.long 0x00 14. " [14] ,PIO0_14 masked pin state" "Cleared,Set" bitfld.long 0x00 13. " [13] ,PIO0_13 masked pin state" "Cleared,Set" bitfld.long 0x00 12. " [12] ,PIO0_12 masked pin state" "Cleared,Set" bitfld.long 0x00 11. " [11] ,PIO0_11 masked pin state" "Cleared,Set" bitfld.long 0x00 10. " [10] ,PIO0_10 masked pin state" "Cleared,Set" bitfld.long 0x00 9. " [9] ,PIO0_9 masked pin state" "Cleared,Set" bitfld.long 0x00 8. " [8] ,PIO0_8 masked pin state" "Cleared,Set" newline bitfld.long 0x00 7. " [7] ,PIO0_7 masked pin state" "Cleared,Set" bitfld.long 0x00 6. " [6] ,PIO0_6 masked pin state" "Cleared,Set" bitfld.long 0x00 5. " [5] ,PIO0_5 masked pin state" "Cleared,Set" bitfld.long 0x00 4. " [4] ,PIO0_4 masked pin state" "Cleared,Set" bitfld.long 0x00 3. " [3] ,PIO0_3 masked pin state" "Cleared,Set" bitfld.long 0x00 2. " [2] ,PIO0_2 masked pin state" "Cleared,Set" bitfld.long 0x00 1. " [1] ,PIO0_1 masked pin state" "Cleared,Set" bitfld.long 0x00 0. " [0] ,PIO0_0 masked pin state" "Cleared,Set" line.long 0x04 "MPIN1,Masked Port Register Port 1" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " MPORTP[30] ,PIO1_30 masked pin state" "Cleared,Set" bitfld.long 0x04 29. " [29] ,PIO1_29 masked pin state" "Cleared,Set" bitfld.long 0x04 28. " [28] ,PIO1_28 masked pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 masked pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 masked pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 masked pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 masked pin state" "Cleared,Set" newline bitfld.long 0x04 20. " [20] ,PIO1_20 masked pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 masked pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 masked pin state" "Cleared,Set" bitfld.long 0x04 10. " [10] ,PIO1_10 masked pin state" "Cleared,Set" bitfld.long 0x04 9. " [9] ,PIO1_9 masked pin state" "Cleared,Set" bitfld.long 0x04 7. " [7] ,PIO1_7 masked pin state" "Cleared,Set" bitfld.long 0x04 0. " [0] ,PIO1_0 masked pin state" "Cleared,Set" else bitfld.long 0x04 24. " MPORTP[24] ,PIO1_24 masked pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 masked pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 masked pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 masked pin state" "Cleared,Set" endif else bitfld.long 0x04 31. " MPORTP[31] ,PIO1_31 masked masked pin state" "Cleared,Set" bitfld.long 0x04 30. " [30] ,PIO1_30 masked pin state" "Cleared,Set" bitfld.long 0x04 29. " [29] ,PIO1_29 masked pin state" "Cleared,Set" bitfld.long 0x04 28. " [28] ,PIO1_28 masked pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 masked pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 masked pin state" "Cleared,Set" bitfld.long 0x04 25. " [25] ,PIO1_25 masked pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 masked pin state" "Cleared,Set" newline bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state" "Cleared,Set" bitfld.long 0x04 22. " [22] ,PIO1_22 masked pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 masked pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 masked pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 masked pin state" "Cleared,Set" bitfld.long 0x04 18. " [18] ,PIO1_18 masked pin state" "Cleared,Set" bitfld.long 0x04 17. " [17] ,PIO1_17 masked pin state" "Cleared,Set" bitfld.long 0x04 16. " [16] ,PIO1_16 masked pin state" "Cleared,Set" newline bitfld.long 0x04 15. " [15] ,PIO1_15 masked pin state" "Cleared,Set" bitfld.long 0x04 14. " [14] ,PIO1_14 masked pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 masked pin state" "Cleared,Set" bitfld.long 0x04 12. " [12] ,PIO1_12 masked pin state" "Cleared,Set" bitfld.long 0x04 11. " [11] ,PIO1_11 masked pin state" "Cleared,Set" bitfld.long 0x04 10. " [10] ,PIO1_10 masked pin state" "Cleared,Set" bitfld.long 0x04 9. " [9] ,PIO1_9 masked pin state" "Cleared,Set" bitfld.long 0x04 8. " [8] ,PIO1_8 masked pin state" "Cleared,Set" newline bitfld.long 0x04 7. " [7] ,PIO1_7 masked pin state" "Cleared,Set" bitfld.long 0x04 6. " [6] ,PIO1_6 masked pin state" "Cleared,Set" bitfld.long 0x04 5. " [5] ,PIO1_5 masked pin state" "Cleared,Set" bitfld.long 0x04 4. " [4] ,PIO1_4 masked pin state" "Cleared,Set" bitfld.long 0x04 3. " [3] ,PIO1_3 masked pin state" "Cleared,Set" bitfld.long 0x04 2. " [2] ,PIO1_2 masked pin state" "Cleared,Set" bitfld.long 0x04 1. " [1] ,PIO1_1 masked pin state" "Cleared,Set" bitfld.long 0x04 0. " [0] ,PIO1_0 masked pin state" "Cleared,Set" endif line.long 0x08 "MPIN2,Masked Port Register Port 2" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x08 19. " MPORTP[19] ,PIO2_19 masked pin state" "Cleared,Set" bitfld.long 0x08 18. " [18] ,PIO2_18 masked pin state" "Cleared,Set" bitfld.long 0x08 15. " [15] ,PIO2_15 masked pin state" "Cleared,Set" bitfld.long 0x08 7. " [7] ,PIO2_7 masked pin state" "Cleared,Set" bitfld.long 0x08 6. " [6] ,PIO2_6 masked pin state" "Cleared,Set" bitfld.long 0x08 5. " [5] ,PIO2_5 masked pin state" "Cleared,Set" bitfld.long 0x08 2. " [2] ,PIO2_2 masked pin state" "Cleared,Set" bitfld.long 0x08 1. " [1] ,PIO2_1 masked pin state" "Cleared,Set" newline bitfld.long 0x08 0. " [0] ,PIO2_0 masked pin state" "Cleared,Set" else bitfld.long 0x08 7. " MPORTP[7] ,PIO2_7 masked pin state" "Cleared,Set" bitfld.long 0x08 5. " [5] ,PIO2_5 masked pin state" "Cleared,Set" bitfld.long 0x08 2. " [2] ,PIO2_2 masked pin state" "Cleared,Set" bitfld.long 0x08 1. " [1] ,PIO2_1 masked pin state" "Cleared,Set" bitfld.long 0x08 0. " [0] ,PIO2_0 masked pin state" "Cleared,Set" endif else bitfld.long 0x08 23. " MPORTP[23] ,PIO2_23 masked pin state" "Cleared,Set" bitfld.long 0x08 22. " [22] ,PIO2_22 masked pin state" "Cleared,Set" bitfld.long 0x08 21. " [21] ,PIO2_21 masked pin state" "Cleared,Set" bitfld.long 0x08 20. " [20] ,PIO2_20 masked pin state" "Cleared,Set" bitfld.long 0x08 19. " [19] ,PIO2_19 masked pin state" "Cleared,Set" bitfld.long 0x08 18. " [18] ,PIO2_18 masked pin state" "Cleared,Set" bitfld.long 0x08 17. " [17] ,PIO2_17 masked pin state" "Cleared,Set" bitfld.long 0x08 16. " [16] ,PIO2_16 masked pin state" "Cleared,Set" newline bitfld.long 0x08 15. " [15] ,PIO2_15 masked pin state" "Cleared,Set" bitfld.long 0x08 14. " [14] ,PIO2_14 masked pin state" "Cleared,Set" bitfld.long 0x08 13. " [13] ,PIO2_13 masked pin state" "Cleared,Set" bitfld.long 0x08 12. " [12] ,PIO2_12 masked pin state" "Cleared,Set" bitfld.long 0x08 11. " [11] ,PIO2_11 masked pin state" "Cleared,Set" bitfld.long 0x08 10. " [10] ,PIO2_10 masked pin state" "Cleared,Set" bitfld.long 0x08 9. " [9] ,PIO2_9 masked pin state" "Cleared,Set" bitfld.long 0x08 8. " [8] ,PIO2_8 masked pin state" "Cleared,Set" newline bitfld.long 0x08 7. " [7] ,PIO2_7 masked pin state" "Cleared,Set" bitfld.long 0x08 6. " [6] ,PIO2_6 masked pin state" "Cleared,Set" bitfld.long 0x08 5. " [5] ,PIO2_5 masked pin state" "Cleared,Set" bitfld.long 0x08 4. " [4] ,PIO2_4 masked pin state" "Cleared,Set" bitfld.long 0x08 3. " [3] ,PIO2_3 masked pin state" "Cleared,Set" bitfld.long 0x08 2. " [2] ,PIO2_2 masked pin state" "Cleared,Set" bitfld.long 0x08 1. " [1] ,PIO2_1 masked pin state" "Cleared,Set" bitfld.long 0x08 0. " [0] ,PIO2_0 masked pin state" "Cleared,Set" endif newline group.long 0x2200++0x0B line.long 0x00 "SET0,Set Register For Port 0" bitfld.long 0x00 23. " SETP[23] ,Read/Set output bit PIO0_23" "No operation,Set" bitfld.long 0x00 22. " [22] ,Read/Set output bit PIO0_22" "No operation,Set" bitfld.long 0x00 21. " [21] ,Read/Set output bit PIO0_21" "No operation,Set" bitfld.long 0x00 20. " [20] ,Read/Set output bit PIO0_20" "No operation,Set" bitfld.long 0x00 19. " [19] ,Read/Set output bit PIO0_19" "No operation,Set" bitfld.long 0x00 18. " [18] ,Read/Set output bit PIO0_18" "No operation,Set" bitfld.long 0x00 17. " [17] ,Read/Set output bit PIO0_17" "No operation,Set" bitfld.long 0x00 16. " [16] ,Read/Set output bit PIO0_16" "No operation,Set" newline bitfld.long 0x00 15. " [15] ,Read/Set output bit PIO0_15" "No operation,Set" bitfld.long 0x00 14. " [14] ,Read/Set output bit PIO0_14" "No operation,Set" bitfld.long 0x00 13. " [13] ,Read/Set output bit PIO0_13" "No operation,Set" bitfld.long 0x00 12. " [12] ,Read/Set output bit PIO0_12" "No operation,Set" bitfld.long 0x00 11. " [11] ,Read/Set output bit PIO0_11" "No operation,Set" bitfld.long 0x00 10. " [10] ,Read/Set output bit PIO0_10" "No operation,Set" bitfld.long 0x00 9. " [9] ,Read/Set output bit PIO0_9" "No operation,Set" bitfld.long 0x00 8. " [8] ,Read/Set output bit PIO0_8" "No operation,Set" newline bitfld.long 0x00 7. " [7] ,Read/Set output bit PIO0_7" "No operation,Set" bitfld.long 0x00 6. " [6] ,Read/Set output bit PIO0_6" "No operation,Set" bitfld.long 0x00 5. " [5] ,Read/Set output bit PIO0_5" "No operation,Set" bitfld.long 0x00 4. " [4] ,Read/Set output bit PIO0_4" "No operation,Set" bitfld.long 0x00 3. " [3] ,Read/Set output bit PIO0_3" "No operation,Set" bitfld.long 0x00 2. " [2] ,Read/Set output bit PIO0_2" "No operation,Set" bitfld.long 0x00 1. " [1] ,Read/Set output bit PIO0_1" "No operation,Set" bitfld.long 0x00 0. " [0] ,Read/Set output bit PIO0_0" "No operation,Set" line.long 0x04 "SET1,Set Register For Port 1" sif !cpuis("LPC11U6?JBD100") sif !cpuis("LPC11U6?JBD48") bitfld.long 0x04 30. " SETP[30] ,Read/Set output bit PIO1_30" "No operation,Set" bitfld.long 0x04 29. " [29] ,Read/Set output bit PIO1_29" "No operation,Set" bitfld.long 0x04 28. " [28] ,Read/Set output bit PIO1_28" "No operation,Set" bitfld.long 0x04 27. " [27] ,Read/Set output bit PIO1_27" "No operation,Set" bitfld.long 0x04 26. " [26] ,Read/Set output bit PIO1_26" "No operation,Set" bitfld.long 0x04 24. " [24] ,Read/Set output bit PIO1_24" "No operation,Set" bitfld.long 0x04 23. " [23] ,Read/Set output bit PIO1_23" "No operation,Set" bitfld.long 0x04 21. " [21] ,Read/Set output bit PIO1_21" "No operation,Set" newline bitfld.long 0x04 20. " [20] ,Read/Set output bit PIO1_20" "No operation,Set" bitfld.long 0x04 19. " [19] ,Read/Set output bit PIO1_19" "No operation,Set" bitfld.long 0x04 13. " [13] ,Read/Set output bit PIO1_13" "No operation,Set" bitfld.long 0x04 10. " [10] ,Read/Set output bit PIO1_10" "No operation,Set" bitfld.long 0x04 9. " [9] ,Read/Set output bit PIO1_9" "No operation,Set" bitfld.long 0x04 7. " [7] ,Read/Set output bit PIO1_7" "No operation,Set" bitfld.long 0x04 0. " [0] ,Read/Set output bit PIO1_0" "No operation,Set" else bitfld.long 0x04 24. " SETP[24] ,Read/Set output bit PIO1_24" "No operation,Set" bitfld.long 0x04 23. " [23] ,Read/Set output bit PIO1_23" "No operation,Set" bitfld.long 0x04 21. " [21] ,Read/Set output bit PIO1_21" "No operation,Set" bitfld.long 0x04 20. " [20] ,Read/Set output bit PIO1_20" "No operation,Set" bitfld.long 0x04 13. " [13] ,Read/Set output bit PIO1_13" "No operation,Set" endif else bitfld.long 0x04 31. " SETP[31] ,Read/Set output bit PIO1_31" "No operation,Set" bitfld.long 0x04 30. " [30] ,Read/Set output bit PIO1_30" "No operation,Set" bitfld.long 0x04 29. " [29] ,Read/Set output bit PIO1_29" "No operation,Set" bitfld.long 0x04 28. " [28] ,Read/Set output bit PIO1_28" "No operation,Set" bitfld.long 0x04 27. " [27] ,Read/Set output bit PIO1_27" "No operation,Set" bitfld.long 0x04 26. " [26] ,Read/Set output bit PIO1_26" "No operation,Set" bitfld.long 0x04 25. " [25] ,Read/Set output bit PIO1_25" "No operation,Set" bitfld.long 0x04 24. " [24] ,Read/Set output bit PIO1_24" "No operation,Set" newline bitfld.long 0x04 23. " [23] ,Read/Set output bit PIO1_23" "No operation,Set" bitfld.long 0x04 22. " [22] ,Read/Set output bit PIO1_22" "No operation,Set" bitfld.long 0x04 21. " [21] ,Read/Set output bit PIO1_21" "No operation,Set" bitfld.long 0x04 20. " [20] ,Read/Set output bit PIO1_20" "No operation,Set" bitfld.long 0x04 19. " [19] ,Read/Set output bit PIO1_19" "No operation,Set" bitfld.long 0x04 18. " [18] ,Read/Set output bit PIO1_18" "No operation,Set" bitfld.long 0x04 17. " [17] ,Read/Set output bit PIO1_17" "No operation,Set" bitfld.long 0x04 16. " [16] ,Read/Set output bit PIO1_16" "No operation,Set" newline bitfld.long 0x04 15. " [15] ,Read/Set output bit PIO1_15" "No operation,Set" bitfld.long 0x04 14. " [14] ,Read/Set output bit PIO1_14" "No operation,Set" bitfld.long 0x04 13. " [13] ,Read/Set output bit PIO1_13" "No operation,Set" bitfld.long 0x04 12. " [12] ,Read/Set output bit PIO1_12" "No operation,Set" bitfld.long 0x04 11. " [11] ,Read/Set output bit PIO1_11" "No operation,Set" bitfld.long 0x04 10. " [10] ,Read/Set output bit PIO1_10" "No operation,Set" bitfld.long 0x04 9. " [9] ,Read/Set output bit PIO1_9" "No operation,Set" bitfld.long 0x04 8. " [8] ,Read/Set output bit PIO1_8" "No operation,Set" newline bitfld.long 0x04 7. " [7] ,Read/Set output bit PIO1_7" "No operation,Set" bitfld.long 0x04 6. " [6] ,Read/Set output bit PIO1_6" "No operation,Set" bitfld.long 0x04 5. " [5] ,Read/Set output bit PIO1_5" "No operation,Set" bitfld.long 0x04 4. " [4] ,Read/Set output bit PIO1_4" "No operation,Set" bitfld.long 0x04 3. " [3] ,Read/Set output bit PIO1_3" "No operation,Set" bitfld.long 0x04 2. " [2] ,Read/Set output bit PIO1_2" "No operation,Set" bitfld.long 0x04 1. " [1] ,Read/Set output bit PIO1_1" "No operation,Set" bitfld.long 0x04 0. " [0] ,Read/Set output bit PIO1_0" "No operation,Set" endif line.long 0x08 "SET2,Set Register For Port 2" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x08 19. " SETP[19] ,Read/Set output bit PIO2_19" "No operation,Set" bitfld.long 0x08 18. " [18] ,Read/Set output bit PIO2_18" "No operation,Set" bitfld.long 0x08 15. " [15] ,Read/Set output bit PIO2_15" "No operation,Set" bitfld.long 0x08 7. " [7] ,Read/Set output bit PIO2_7" "No operation,Set" bitfld.long 0x08 6. " [6] ,Read/Set output bit PIO2_6" "No operation,Set" bitfld.long 0x08 5. " [5] ,Read/Set output bit PIO2_5" "No operation,Set" bitfld.long 0x08 2. " [2] ,Read/Set output bit PIO2_2" "No operation,Set" bitfld.long 0x08 1. " [1] ,Read/Set output bit PIO2_1" "No operation,Set" newline bitfld.long 0x08 0. " [0] ,Read/Set output bit PIO2_0" "No operation,Set" else bitfld.long 0x08 7. " SETP[7] ,Read/Set output bit PIO2_7" "No operation,Set" bitfld.long 0x08 5. " [5] ,Read/Set output bit PIO2_5" "No operation,Set" bitfld.long 0x08 2. " [2] ,Read/Set output bit PIO2_2" "No operation,Set" bitfld.long 0x08 1. " [1] ,Read/Set output bit PIO2_1" "No operation,Set" bitfld.long 0x08 0. " [0] ,Read/Set output bit PIO2_0" "No operation,Set" endif else bitfld.long 0x08 23. " SETP[23] ,Read/Set output bit PIO2_23" "No operation,Set" bitfld.long 0x08 22. " [22] ,Read/Set output bit PIO2_22" "No operation,Set" bitfld.long 0x08 21. " [21] ,Read/Set output bit PIO2_21" "No operation,Set" bitfld.long 0x08 20. " [20] ,Read/Set output bit PIO2_20" "No operation,Set" bitfld.long 0x08 19. " [19] ,Read/Set output bit PIO2_19" "No operation,Set" bitfld.long 0x08 18. " [18] ,Read/Set output bit PIO2_18" "No operation,Set" bitfld.long 0x08 17. " [17] ,Read/Set output bit PIO2_17" "No operation,Set" bitfld.long 0x08 16. " [16] ,Read/Set output bit PIO2_16" "No operation,Set" newline bitfld.long 0x08 15. " [15] ,Read/Set output bit PIO2_15" "No operation,Set" bitfld.long 0x08 14. " [14] ,Read/Set output bit PIO2_14" "No operation,Set" bitfld.long 0x08 13. " [13] ,Read/Set output bit PIO2_13" "No operation,Set" bitfld.long 0x08 12. " [12] ,Read/Set output bit PIO2_12" "No operation,Set" bitfld.long 0x08 11. " [11] ,Read/Set output bit PIO2_11" "No operation,Set" bitfld.long 0x08 10. " [10] ,Read/Set output bit PIO2_10" "No operation,Set" bitfld.long 0x08 9. " [9] ,Read/Set output bit PIO2_9" "No operation,Set" bitfld.long 0x08 8. " [8] ,Read/Set output bit PIO2_8" "No operation,Set" newline bitfld.long 0x08 7. " [7] ,Read/Set output bit PIO2_7" "No operation,Set" bitfld.long 0x08 6. " [6] ,Read/Set output bit PIO2_6" "No operation,Set" bitfld.long 0x08 5. " [5] ,Read/Set output bit PIO2_5" "No operation,Set" bitfld.long 0x08 4. " [4] ,Read/Set output bit PIO2_4" "No operation,Set" bitfld.long 0x08 3. " [3] ,Read/Set output bit PIO2_3" "No operation,Set" bitfld.long 0x08 2. " [2] ,Read/Set output bit PIO2_2" "No operation,Set" bitfld.long 0x08 1. " [1] ,Read/Set output bit PIO2_1" "No operation,Set" bitfld.long 0x08 0. " [0] ,Read/Set output bit PIO2_0" "No operation,Set" endif wgroup.long 0x2280++0x0B line.long 0x00 "CLR0,Clear Port 0" bitfld.long 0x00 23. " CLRP[23] ,PIO0_23 clear output" "No operation,Cleared" bitfld.long 0x00 22. " [22] ,PIO0_22 clear output" "No operation,Cleared" bitfld.long 0x00 21. " [21] ,PIO0_21 clear output" "No operation,Cleared" bitfld.long 0x00 20. " [20] ,PIO0_20 clear output" "No operation,Cleared" bitfld.long 0x00 19. " [19] ,PIO0_19 clear output" "No operation,Cleared" bitfld.long 0x00 18. " [18] ,PIO0_18 clear output" "No operation,Cleared" bitfld.long 0x00 17. " [17] ,PIO0_17 clear output" "No operation,Cleared" bitfld.long 0x00 16. " [16] ,PIO0_16 clear output" "No operation,Cleared" newline bitfld.long 0x00 15. " [15] ,PIO0_15 clear output" "No operation,Cleared" bitfld.long 0x00 14. " [14] ,PIO0_14 clear output" "No operation,Cleared" bitfld.long 0x00 13. " [13] ,PIO0_13 clear output" "No operation,Cleared" bitfld.long 0x00 12. " [12] ,PIO0_12 clear output" "No operation,Cleared" bitfld.long 0x00 11. " [11] ,PIO0_11 clear output" "No operation,Cleared" bitfld.long 0x00 10. " [10] ,PIO0_10 clear output" "No operation,Cleared" bitfld.long 0x00 9. " [9] ,PIO0_9 clear output" "No operation,Cleared" bitfld.long 0x00 8. " [8] ,PIO0_8 clear output" "No operation,Cleared" newline bitfld.long 0x00 7. " [7] ,PIO0_7 clear output" "No operation,Cleared" bitfld.long 0x00 6. " [6] ,PIO0_6 clear output" "No operation,Cleared" bitfld.long 0x00 5. " [5] ,PIO0_5 clear output" "No operation,Cleared" bitfld.long 0x00 4. " [4] ,PIO0_4 clear output" "No operation,Cleared" bitfld.long 0x00 3. " [3] ,PIO0_3 clear output" "No operation,Cleared" bitfld.long 0x00 2. " [2] ,PIO0_2 clear output" "No operation,Cleared" bitfld.long 0x00 1. " [1] ,PIO0_1 clear output" "No operation,Cleared" bitfld.long 0x00 0. " [0] ,PIO0_0 clear output" "No operation,Cleared" line.long 0x04 "CLR1,Clear Port 1" sif !cpuis("LPC11U6?JBD100") sif !cpuis("LPC11U6?JBD48") bitfld.long 0x04 30. " CLRP[30] ,PIO1_30 clear output" "No operation,Cleared" bitfld.long 0x04 29. " [29] ,PIO1_29 clear output" "No operation,Cleared" bitfld.long 0x04 28. " [28] ,PIO1_28 clear output" "No operation,Cleared" bitfld.long 0x04 27. " [27] ,PIO1_27 clear output" "No operation,Cleared" bitfld.long 0x04 26. " [26] ,PIO1_26 clear output" "No operation,Cleared" bitfld.long 0x04 24. " [24] ,PIO1_24 clear output" "No operation,Cleared" bitfld.long 0x04 23. " [23] ,PIO1_23 clear output" "No operation,Cleared" bitfld.long 0x04 21. " [21] ,PIO1_21 clear output" "No operation,Cleared" newline bitfld.long 0x04 20. " [20] ,PIO1_20 clear output" "No operation,Cleared" bitfld.long 0x04 19. " [19] ,PIO1_19 clear output" "No operation,Cleared" bitfld.long 0x04 13. " [13] ,PIO1_13 clear output" "No operation,Cleared" bitfld.long 0x04 10. " [10] ,PIO1_10 clear output" "No operation,Cleared" bitfld.long 0x04 9. " [9] ,PIO1_9 clear output" "No operation,Cleared" bitfld.long 0x04 7. " [7] ,PIO1_7 clear output" "No operation,Cleared" bitfld.long 0x04 0. " [0] ,PIO1_0 clear output" "No operation,Cleared" else bitfld.long 0x04 24. " CLRP[24] ,PIO1_24 clear output" "No operation,Cleared" bitfld.long 0x04 23. " [23] ,PIO1_23 clear output" "No operation,Cleared" bitfld.long 0x04 21. " [21] ,PIO1_21 clear output" "No operation,Cleared" bitfld.long 0x04 20. " [20] ,PIO1_20 clear output" "No operation,Cleared" bitfld.long 0x04 13. " [13] ,PIO1_13 clear output" "No operation,Cleared" endif else bitfld.long 0x04 31. " CLRP[31] ,PIO1_31 clear output" "No operation,Cleared" bitfld.long 0x04 30. " [30] ,PIO1_30 clear output" "No operation,Cleared" bitfld.long 0x04 29. " [29] ,PIO1_29 clear output" "No operation,Cleared" bitfld.long 0x04 28. " [28] ,PIO1_28 clear output" "No operation,Cleared" bitfld.long 0x04 27. " [27] ,PIO1_27 clear output" "No operation,Cleared" bitfld.long 0x04 26. " [26] ,PIO1_26 clear output" "No operation,Cleared" bitfld.long 0x04 25. " [25] ,PIO1_25 clear output" "No operation,Cleared" bitfld.long 0x04 24. " [24] ,PIO1_24 clear output" "No operation,Cleared" newline bitfld.long 0x04 23. " [23] ,PIO1_23 clear output" "No operation,Cleared" bitfld.long 0x04 22. " [22] ,PIO1_22 clear output" "No operation,Cleared" bitfld.long 0x04 21. " [21] ,PIO1_21 clear output" "No operation,Cleared" bitfld.long 0x04 20. " [20] ,PIO1_20 clear output" "No operation,Cleared" bitfld.long 0x04 19. " [19] ,PIO1_19 clear output" "No operation,Cleared" bitfld.long 0x04 18. " [18] ,PIO1_18 clear output" "No operation,Cleared" bitfld.long 0x04 17. " [17] ,PIO1_17 clear output" "No operation,Cleared" bitfld.long 0x04 16. " [16] ,PIO1_16 clear output" "No operation,Cleared" newline bitfld.long 0x04 15. " [15] ,PIO1_15 clear output" "No operation,Cleared" bitfld.long 0x04 14. " [14] ,PIO1_14 clear output" "No operation,Cleared" bitfld.long 0x04 13. " [13] ,PIO1_13 clear output" "No operation,Cleared" bitfld.long 0x04 12. " [12] ,PIO1_12 clear output" "No operation,Cleared" bitfld.long 0x04 11. " [11] ,PIO1_11 clear output" "No operation,Cleared" bitfld.long 0x04 10. " [10] ,PIO1_10 clear output" "No operation,Cleared" bitfld.long 0x04 9. " [9] ,PIO1_9 clear output" "No operation,Cleared" bitfld.long 0x04 8. " [8] ,PIO1_8 clear output" "No operation,Cleared" newline bitfld.long 0x04 7. " [7] ,PIO1_7 clear output" "No operation,Cleared" bitfld.long 0x04 6. " [6] ,PIO1_6 clear output" "No operation,Cleared" bitfld.long 0x04 5. " [5] ,PIO1_5 clear output" "No operation,Cleared" bitfld.long 0x04 4. " [4] ,PIO1_4 clear output" "No operation,Cleared" bitfld.long 0x04 3. " [3] ,PIO1_3 clear output" "No operation,Cleared" bitfld.long 0x04 2. " [2] ,PIO1_2 clear output" "No operation,Cleared" bitfld.long 0x04 1. " [1] ,PIO1_1 clear output" "No operation,Cleared" bitfld.long 0x04 0. " [0] ,PIO1_0 clear output" "No operation,Cleared" endif line.long 0x08 "CLR2,Clear Port 2" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x08 19. " CLRP[19] ,PIO2_19 clear output" "No operation,Cleared" bitfld.long 0x08 18. " [18] ,PIO2_18 clear output" "No operation,Cleared" bitfld.long 0x08 15. " [15] ,PIO2_15 clear output" "No operation,Cleared" bitfld.long 0x08 7. " [7] ,PIO2_7 clear output" "No operation,Cleared" bitfld.long 0x08 6. " [6] ,PIO2_6 clear output" "No operation,Cleared" bitfld.long 0x08 5. " [5] ,PIO2_5 clear output" "No operation,Cleared" bitfld.long 0x08 2. " [2] ,PIO2_2 clear output" "No operation,Cleared" bitfld.long 0x08 1. " [1] ,PIO2_1 clear output" "No operation,Cleared" newline bitfld.long 0x08 0. " [0] ,PIO2_0 clear output" "No operation,Cleared" else bitfld.long 0x08 7. " CLRP[7] ,PIO2_7 clear output" "No operation,Cleared" bitfld.long 0x08 5. " [5] ,PIO2_5 clear output" "No operation,Cleared" bitfld.long 0x08 2. " [2] ,PIO2_2 clear output" "No operation,Cleared" bitfld.long 0x08 1. " [1] ,PIO2_1 clear output" "No operation,Cleared" bitfld.long 0x08 0. " [0] ,PIO2_0 clear output" "No operation,Cleared" endif else bitfld.long 0x08 23. " CLRP[23] ,PIO2_23 clear output" "No operation,Cleared" bitfld.long 0x08 22. " [22] ,PIO2_22 clear output" "No operation,Cleared" bitfld.long 0x08 21. " [21] ,PIO2_21 clear output" "No operation,Cleared" bitfld.long 0x08 20. " [20] ,PIO2_20 clear output" "No operation,Cleared" bitfld.long 0x08 19. " [19] ,PIO2_19 clear output" "No operation,Cleared" bitfld.long 0x08 18. " [18] ,PIO2_18 clear output" "No operation,Cleared" bitfld.long 0x08 17. " [17] ,PIO2_17 clear output" "No operation,Cleared" bitfld.long 0x08 16. " [16] ,PIO2_16 clear output" "No operation,Cleared" newline bitfld.long 0x08 15. " [15] ,PIO2_15 clear output" "No operation,Cleared" bitfld.long 0x08 14. " [14] ,PIO2_14 clear output" "No operation,Cleared" bitfld.long 0x08 13. " [13] ,PIO2_13 clear output" "No operation,Cleared" bitfld.long 0x08 12. " [12] ,PIO2_12 clear output" "No operation,Cleared" bitfld.long 0x08 11. " [11] ,PIO2_11 clear output" "No operation,Cleared" bitfld.long 0x08 10. " [10] ,PIO2_10 clear output" "No operation,Cleared" bitfld.long 0x08 9. " [9] ,PIO2_9 clear output" "No operation,Cleared" bitfld.long 0x08 8. " [8] ,PIO2_8 clear output" "No operation,Cleared" newline bitfld.long 0x08 7. " [7] ,PIO2_7 clear output" "No operation,Cleared" bitfld.long 0x08 6. " [6] ,PIO2_6 clear output" "No operation,Cleared" bitfld.long 0x08 5. " [5] ,PIO2_5 clear output" "No operation,Cleared" bitfld.long 0x08 4. " [4] ,PIO2_4 clear output" "No operation,Cleared" bitfld.long 0x08 3. " [3] ,PIO2_3 clear output" "No operation,Cleared" bitfld.long 0x08 2. " [2] ,PIO2_2 clear output" "No operation,Cleared" bitfld.long 0x08 1. " [1] ,PIO2_1 clear output" "No operation,Cleared" bitfld.long 0x08 0. " [0] ,PIO2_0 clear output" "No operation,Cleared" endif wgroup.long 0x2300++0x0B line.long 0x00 "NOT0,Toggle Port 0" bitfld.long 0x00 23. " NOTP[23] ,Toggle PIO0_23 output" "No operation,Toggled" bitfld.long 0x00 22. " [22] ,Toggle PIO0_22 output" "No operation,Toggled" bitfld.long 0x00 21. " [21] ,Toggle PIO0_21 output" "No operation,Toggled" bitfld.long 0x00 20. " [20] ,Toggle PIO0_20 output" "No operation,Toggled" bitfld.long 0x00 19. " [19] ,Toggle PIO0_19 output" "No operation,Toggled" bitfld.long 0x00 18. " [18] ,Toggle PIO0_18 output" "No operation,Toggled" bitfld.long 0x00 17. " [17] ,Toggle PIO0_17 output" "No operation,Toggled" bitfld.long 0x00 16. " [16] ,Toggle PIO0_16 output" "No operation,Toggled" newline bitfld.long 0x00 15. " [15] ,Toggle PIO0_15 output" "No operation,Toggled" bitfld.long 0x00 14. " [14] ,Toggle PIO0_14 output" "No operation,Toggled" bitfld.long 0x00 13. " [13] ,Toggle PIO0_13 output" "No operation,Toggled" bitfld.long 0x00 12. " [12] ,Toggle PIO0_12 output" "No operation,Toggled" bitfld.long 0x00 11. " [11] ,Toggle PIO0_11 output" "No operation,Toggled" bitfld.long 0x00 10. " [10] ,Toggle PIO0_10 output" "No operation,Toggled" bitfld.long 0x00 9. " [9] ,Toggle PIO0_9 output" "No operation,Toggled" bitfld.long 0x00 8. " [8] ,Toggle PIO0_8 output" "No operation,Toggled" newline bitfld.long 0x00 7. " [7] ,Toggle PIO0_7 output" "No operation,Toggled" bitfld.long 0x00 6. " [6] ,Toggle PIO0_6 output" "No operation,Toggled" bitfld.long 0x00 5. " [5] ,Toggle PIO0_5 output" "No operation,Toggled" bitfld.long 0x00 4. " [4] ,Toggle PIO0_4 output" "No operation,Toggled" bitfld.long 0x00 3. " [3] ,Toggle PIO0_3 output" "No operation,Toggled" bitfld.long 0x00 2. " [2] ,Toggle PIO0_2 output" "No operation,Toggled" bitfld.long 0x00 1. " [1] ,Toggle PIO0_1 output" "No operation,Toggled" bitfld.long 0x00 0. " [0] ,Toggle PIO0_0 output" "No operation,Toggled" line.long 0x04 "NOT1,Toggle Port 1" sif !cpuis("LPC11U6?JBD100") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " NOTP[30] ,Toggle PIO1_30 output" "No operation,Toggled" bitfld.long 0x04 29. " [29] ,Toggle PIO1_29 output" "No operation,Toggled" bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggled" bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggled" bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggled" bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggled" bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggled" bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggled" newline bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggled" bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggled" bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggled" bitfld.long 0x04 10. " [10] ,Toggle PIO1_10 output" "No operation,Toggled" bitfld.long 0x04 9. " [9] ,Toggle PIO1_9 output" "No operation,Toggled" bitfld.long 0x04 7. " [7] ,Toggle PIO1_7 output" "No operation,Toggled" bitfld.long 0x04 0. " [0] ,Toggle PIO1_0 output" "No operation,Toggled" else bitfld.long 0x04 24. " NOTP[24] ,Toggle PIO1_24 output" "No operation,Toggled" bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggled" bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggled" bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggled" bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggled" endif else bitfld.long 0x04 31. " NOTP[31] ,Toggle PIO1_31 output" "No operation,Toggled" bitfld.long 0x04 30. " [30] ,Toggle PIO1_30 output" "No operation,Toggled" bitfld.long 0x04 29. " [29] ,Toggle PIO1_29 output" "No operation,Toggled" bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggled" bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggled" bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggled" bitfld.long 0x04 25. " [25] ,Toggle PIO1_25 output" "No operation,Toggled" bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggled" newline bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggled" bitfld.long 0x04 22. " [22] ,Toggle PIO1_22 output" "No operation,Toggled" bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggled" bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggled" bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggled" bitfld.long 0x04 18. " [18] ,Toggle PIO1_18 output" "No operation,Toggled" bitfld.long 0x04 17. " [17] ,Toggle PIO1_17 output" "No operation,Toggled" bitfld.long 0x04 16. " [16] ,Toggle PIO1_16 output" "No operation,Toggled" newline bitfld.long 0x04 15. " [15] ,Toggle PIO1_15 output" "No operation,Toggled" bitfld.long 0x04 14. " [14] ,Toggle PIO1_14 output" "No operation,Toggled" bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggled" bitfld.long 0x04 12. " [12] ,Toggle PIO1_12 output" "No operation,Toggled" bitfld.long 0x04 11. " [11] ,Toggle PIO1_11 output" "No operation,Toggled" bitfld.long 0x04 10. " [10] ,Toggle PIO1_10 output" "No operation,Toggled" bitfld.long 0x04 9. " [9] ,Toggle PIO1_9 output" "No operation,Toggled" bitfld.long 0x04 8. " [8] ,Toggle PIO1_8 output" "No operation,Toggled" newline bitfld.long 0x04 7. " [7] ,Toggle PIO1_7 output" "No operation,Toggled" bitfld.long 0x04 6. " [6] ,Toggle PIO1_6 output" "No operation,Toggled" bitfld.long 0x04 5. " [5] ,Toggle PIO1_5 output" "No operation,Toggled" bitfld.long 0x04 4. " [4] ,Toggle PIO1_4 output" "No operation,Toggled" bitfld.long 0x04 3. " [3] ,Toggle PIO1_3 output" "No operation,Toggled" bitfld.long 0x04 2. " [2] ,Toggle PIO1_2 output" "No operation,Toggled" bitfld.long 0x04 1. " [1] ,Toggle PIO1_1 output" "No operation,Toggled" bitfld.long 0x04 0. " [0] ,Toggle PIO1_0 output" "No operation,Toggled" endif line.long 0x08 "NOT2,Toggle Port 2" sif !cpuis("LPC11U6?JBD100") sif !cpuis("LPC11U6?JBD48") bitfld.long 0x08 19. " NOTP[19] ,Toggle PIO2_19 output" "No operation,Toggled" bitfld.long 0x08 18. " [18] ,Toggle PIO2_18 output" "No operation,Toggled" bitfld.long 0x08 15. " [15] ,Toggle PIO2_15 output" "No operation,Toggled" bitfld.long 0x08 7. " [7] ,Toggle PIO2_7 output" "No operation,Toggled" bitfld.long 0x08 6. " [6] ,Toggle PIO2_6 output" "No operation,Toggled" bitfld.long 0x08 5. " [5] ,Toggle PIO2_5 output" "No operation,Toggled" bitfld.long 0x08 2. " [2] ,Toggle PIO2_2 output" "No operation,Toggled" bitfld.long 0x08 1. " [1] ,Toggle PIO2_1 output" "No operation,Toggled" newline bitfld.long 0x08 0. " [0] ,Toggle PIO2_0 output" "No operation,Toggled" else bitfld.long 0x08 7. " NOTP[7] ,Toggle PIO2_7 output" "No operation,Toggled" bitfld.long 0x08 5. " [5] ,Toggle PIO2_5 output" "No operation,Toggled" bitfld.long 0x08 2. " [2] ,Toggle PIO2_2 output" "No operation,Toggled" bitfld.long 0x08 1. " [1] ,Toggle PIO2_1 output" "No operation,Toggled" bitfld.long 0x08 0. " [0] ,Toggle PIO2_0 output" "No operation,Toggled" endif else bitfld.long 0x08 23. " NOTP[23] ,Toggle PIO2_23 output" "No operation,Toggled" bitfld.long 0x08 22. " [22] ,Toggle PIO2_22 output" "No operation,Toggled" bitfld.long 0x08 21. " [21] ,Toggle PIO2_21 output" "No operation,Toggled" bitfld.long 0x08 20. " [20] ,Toggle PIO2_20 output" "No operation,Toggled" bitfld.long 0x08 19. " [19] ,Toggle PIO2_19 output" "No operation,Toggled" bitfld.long 0x08 18. " [18] ,Toggle PIO2_18 output" "No operation,Toggled" bitfld.long 0x08 17. " [17] ,Toggle PIO2_17 output" "No operation,Toggled" bitfld.long 0x08 16. " [16] ,Toggle PIO2_16 output" "No operation,Toggled" newline bitfld.long 0x08 15. " [15] ,Toggle PIO2_15 output" "No operation,Toggled" bitfld.long 0x08 14. " [14] ,Toggle PIO2_14 output" "No operation,Toggled" bitfld.long 0x08 13. " [13] ,Toggle PIO2_13 output" "No operation,Toggled" bitfld.long 0x08 12. " [12] ,Toggle PIO2_12 output" "No operation,Toggled" bitfld.long 0x08 11. " [11] ,Toggle PIO2_11 output" "No operation,Toggled" bitfld.long 0x08 10. " [10] ,Toggle PIO2_10 output" "No operation,Toggled" bitfld.long 0x08 9. " [9] ,Toggle PIO2_9 output" "No operation,Toggled" bitfld.long 0x08 8. " [8] ,Toggle PIO2_8 output" "No operation,Toggled" newline bitfld.long 0x08 7. " [7] ,Toggle PIO2_7 output" "No operation,Toggled" bitfld.long 0x08 6. " [6] ,Toggle PIO2_6 output" "No operation,Toggled" bitfld.long 0x08 5. " [5] ,Toggle PIO2_5 output" "No operation,Toggled" bitfld.long 0x08 4. " [4] ,Toggle PIO2_4 output" "No operation,Toggled" bitfld.long 0x08 3. " [3] ,Toggle PIO2_3 output" "No operation,Toggled" bitfld.long 0x08 2. " [2] ,Toggle PIO2_2 output" "No operation,Toggled" bitfld.long 0x08 1. " [1] ,Toggle PIO2_1 output" "No operation,Toggled" bitfld.long 0x08 0. " [0] ,Toggle PIO2_0 output" "No operation,Toggled" endif width 0x0B else base ad:0x50000000 width 7. tree "Byte Pin Registers" group.byte 0x0++0x00 line.byte 0x00 "B0,Byte Pin Register Port 0 Pin P0_0" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_0" "Low,High" group.byte 0x1++0x00 line.byte 0x00 "B1,Byte Pin Register Port 0 Pin P0_1" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_1" "Low,High" group.byte 0x2++0x00 line.byte 0x00 "B2,Byte Pin Register Port 0 Pin P0_2" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_2" "Low,High" group.byte 0x3++0x00 line.byte 0x00 "B3,Byte Pin Register Port 0 Pin P0_3" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_3" "Low,High" group.byte 0x4++0x00 line.byte 0x00 "B4,Byte Pin Register Port 0 Pin P0_4" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_4" "Low,High" group.byte 0x5++0x00 line.byte 0x00 "B5,Byte Pin Register Port 0 Pin P0_5" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_5" "Low,High" group.byte 0x6++0x00 line.byte 0x00 "B6,Byte Pin Register Port 0 Pin P0_6" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_6" "Low,High" group.byte 0x7++0x00 line.byte 0x00 "B7,Byte Pin Register Port 0 Pin P0_7" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_7" "Low,High" group.byte 0x8++0x00 line.byte 0x00 "B8,Byte Pin Register Port 0 Pin P0_8" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_8" "Low,High" group.byte 0x9++0x00 line.byte 0x00 "B9,Byte Pin Register Port 0 Pin P0_9" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_9" "Low,High" group.byte 0xA++0x00 line.byte 0x00 "B10,Byte Pin Register Port 0 Pin P0_10" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_10" "Low,High" group.byte 0xB++0x00 line.byte 0x00 "B11,Byte Pin Register Port 0 Pin P0_11" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_11" "Low,High" group.byte 0xC++0x00 line.byte 0x00 "B12,Byte Pin Register Port 0 Pin P0_12" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_12" "Low,High" group.byte 0xD++0x00 line.byte 0x00 "B13,Byte Pin Register Port 0 Pin P0_13" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_13" "Low,High" group.byte 0xE++0x00 line.byte 0x00 "B14,Byte Pin Register Port 0 Pin P0_14" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_14" "Low,High" group.byte 0xF++0x00 line.byte 0x00 "B15,Byte Pin Register Port 0 Pin P0_15" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_15" "Low,High" group.byte 0x10++0x00 line.byte 0x00 "B16,Byte Pin Register Port 0 Pin P0_16" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_16" "Low,High" group.byte 0x11++0x00 line.byte 0x00 "B17,Byte Pin Register Port 0 Pin P0_17" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_17" "Low,High" group.byte 0x12++0x00 line.byte 0x00 "B18,Byte Pin Register Port 0 Pin P0_18" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_18" "Low,High" group.byte 0x13++0x00 line.byte 0x00 "B19,Byte Pin Register Port 0 Pin P0_19" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_19" "Low,High" group.byte 0x14++0x00 line.byte 0x00 "B20,Byte Pin Register Port 0 Pin P0_20" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_20" "Low,High" group.byte 0x15++0x00 line.byte 0x00 "B21,Byte Pin Register Port 0 Pin P0_21" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_21" "Low,High" group.byte 0x16++0x00 line.byte 0x00 "B22,Byte Pin Register Port 0 Pin P0_22" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_22" "Low,High" group.byte 0x17++0x00 line.byte 0x00 "B23,Byte Pin Register Port 0 Pin P0_23" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO0_23" "Low,High" sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.byte 0x20++0x04 line.byte 0x00 "B32,Byte Pin Register Port 1 Pin P1_0" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_0" "Low,High" line.byte 0x01 "B33,Byte Pin Register Port 1 Pin P1_1" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_1" "Low,High" line.byte 0x02 "B34,Byte Pin Register Port 1 Pin P1_2" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_2" "Low,High" line.byte 0x03 "B35,Byte Pin Register Port 1 Pin P1_3" bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_3" "Low,High" line.byte 0x04 "B36,Byte Pin Register Port 1 Pin P1_4" bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO1_4" "Low,High" endif sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.byte 0x25++0x00 line.byte 0x00 "B37,Byte Pin Register Port 1 Pin P1_5" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_5" "Low,High" endif sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.byte 0x26++0x06 line.byte 0x00 "B38,Byte Pin Register Port 1 Pin P1_6" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_6" "Low,High" line.byte 0x01 "B39,Byte Pin Register Port 1 Pin P1_7" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_7" "Low,High" line.byte 0x02 "B40,Byte Pin Register Port 1 Pin P1_8" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_8" "Low,High" line.byte 0x03 "B41,Byte Pin Register Port 1 Pin P1_9" bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_9" "Low,High" line.byte 0x04 "B42,Byte Pin Register Port 1 Pin P1_10" bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO1_10" "Low,High" line.byte 0x05 "B43,Byte Pin Register Port 1 Pin P1_11" bitfld.byte 0x05 0. " PBYTE ,State of the pin PIO1_11" "Low,High" line.byte 0x06 "B44,Byte Pin Register Port 1 Pin P1_12" bitfld.byte 0x06 0. " PBYTE ,State of the pin PIO1_12" "Low,High" endif sif !cpuis("LPC11U??FH?33*") group.byte 0x2D++0x01 line.byte 0x00 "B45,Byte Pin Register Port 1 Pin P1_13" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_13" "Low,High" line.byte 0x01 "B46,Byte Pin Register Port 1 Pin P1_14" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_14" "Low,High" endif group.byte 0x2F++0x00 line.byte 0x00 "B47,Byte Pin Register Port 1 Pin P1_15" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_15" "Low,High" sif !cpuis("LPC11U??FH?33*") group.byte 0x30++0x00 line.byte 0x00 "B48,Byte Pin Register Port 1 Pin P1_16" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_16" "Low,High" endif sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.byte 0x31++0x01 line.byte 0x00 "B49,Byte Pin Register Port 1 Pin P1_17" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_17" "Low,High" line.byte 0x01 "B50,Byte Pin Register Port 1 Pin P1_18" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_18" "Low,High" endif group.byte 0x33++0x00 line.byte 0x00 "B51,Byte Pin Register Port 1 Pin P1_19" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_19" "Low,High" sif !cpuis("LPC11U??FH?33*") group.byte 0x34++0x09 line.byte 0x00 "B52,Byte Pin Register Port 1 Pin P1_20" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_20" "Low,High" line.byte 0x01 "B53,Byte Pin Register Port 1 Pin P1_21" bitfld.byte 0x01 0. " PBYTE ,State of the pin PIO1_21" "Low,High" line.byte 0x02 "B54,Byte Pin Register Port 1 Pin P1_22" bitfld.byte 0x02 0. " PBYTE ,State of the pin PIO1_22" "Low,High" line.byte 0x03 "B55,Byte Pin Register Port 1 Pin P1_23" bitfld.byte 0x03 0. " PBYTE ,State of the pin PIO1_23" "Low,High" line.byte 0x04 "B56,Byte Pin Register Port 1 Pin P1_24" bitfld.byte 0x04 0. " PBYTE ,State of the pin PIO1_24" "Low,High" line.byte 0x05 "B57,Byte Pin Register Port 1 Pin P1_25" bitfld.byte 0x05 0. " PBYTE ,State of the pin PIO1_25" "Low,High" line.byte 0x06 "B58,Byte Pin Register Port 1 Pin P1_26" bitfld.byte 0x06 0. " PBYTE ,State of the pin PIO1_26" "Low,High" line.byte 0x07 "B59,Byte Pin Register Port 1 Pin P1_27" bitfld.byte 0x07 0. " PBYTE ,State of the pin PIO1_27" "Low,High" line.byte 0x08 "B60,Byte Pin Register Port 1 Pin P1_28" bitfld.byte 0x08 0. " PBYTE ,State of the pin PIO1_28" "Low,High" line.byte 0x09 "B61,Byte Pin Register Port 1 Pin P1_29" bitfld.byte 0x09 0. " PBYTE ,State of the pin PIO1_29" "Low,High" endif sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2*") group.byte 0x3F++0x00 line.byte 0x00 "B63,Byte Pin Register Port 1 Pin P1_31" bitfld.byte 0x00 0. " PBYTE ,State of the pin PIO1_31" "Low,High" endif tree.end tree "Word Pin Registers" group.long 0x1000++0x03 line.long 0x00 "W0,Word Pin Register Port 0 Pin P0_0" group.long 0x1004++0x03 line.long 0x00 "W1,Word Pin Register Port 0 Pin P0_1" group.long 0x1008++0x03 line.long 0x00 "W2,Word Pin Register Port 0 Pin P0_2" group.long 0x100C++0x03 line.long 0x00 "W3,Word Pin Register Port 0 Pin P0_3" group.long 0x1010++0x03 line.long 0x00 "W4,Word Pin Register Port 0 Pin P0_4" group.long 0x1014++0x03 line.long 0x00 "W5,Word Pin Register Port 0 Pin P0_5" group.long 0x1018++0x03 line.long 0x00 "W6,Word Pin Register Port 0 Pin P0_6" group.long 0x101C++0x03 line.long 0x00 "W7,Word Pin Register Port 0 Pin P0_7" group.long 0x1020++0x03 line.long 0x00 "W8,Word Pin Register Port 0 Pin P0_8" group.long 0x1024++0x03 line.long 0x00 "W9,Word Pin Register Port 0 Pin P0_9" group.long 0x1028++0x03 line.long 0x00 "W10,Word Pin Register Port 0 Pin P0_10" group.long 0x102C++0x03 line.long 0x00 "W11,Word Pin Register Port 0 Pin P0_11" group.long 0x1030++0x03 line.long 0x00 "W12,Word Pin Register Port 0 Pin P0_12" group.long 0x1034++0x03 line.long 0x00 "W13,Word Pin Register Port 0 Pin P0_13" group.long 0x1038++0x03 line.long 0x00 "W14,Word Pin Register Port 0 Pin P0_14" group.long 0x103C++0x03 line.long 0x00 "W15,Word Pin Register Port 0 Pin P0_15" group.long 0x1040++0x03 line.long 0x00 "W16,Word Pin Register Port 0 Pin P0_16" group.long 0x1044++0x03 line.long 0x00 "W17,Word Pin Register Port 0 Pin P0_17" group.long 0x1048++0x03 line.long 0x00 "W18,Word Pin Register Port 0 Pin P0_18" group.long 0x104C++0x03 line.long 0x00 "W19,Word Pin Register Port 0 Pin P0_19" group.long 0x1050++0x03 line.long 0x00 "W20,Word Pin Register Port 0 Pin P0_20" group.long 0x1054++0x03 line.long 0x00 "W21,Word Pin Register Port 0 Pin P0_21" group.long 0x1058++0x03 line.long 0x00 "W22,Word Pin Register Port 0 Pin P0_22" group.long 0x105C++0x03 line.long 0x00 "W23,Word Pin Register Port 0 Pin P0_23" sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.long 0x1080++0x13 line.long 0x00 "W32,Word Pin Register Port 1 Pin P1_0" line.long 0x04 "W33,Word Pin Register Port 1 Pin P1_1" line.long 0x08 "W34,Word Pin Register Port 1 Pin P1_2" line.long 0x0C "W35,Word Pin Register Port 1 Pin P1_3" line.long 0x10 "W36,Word Pin Register Port 1 Pin P1_4" endif sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U??FET48*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.long 0x1094++0x03 line.long 0x00 "W37,Word Pin Register Port 1 Pin P1_5" endif sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.long 0x1098++0x1B line.long 0x00 "W38,Word Pin Register Port 1 Pin P1_6" line.long 0x04 "W39,Word Pin Register Port 1 Pin P1_7" line.long 0x08 "W40,Word Pin Register Port 1 Pin P1_8" line.long 0x0C "W41,Word Pin Register Port 1 Pin P1_9" line.long 0x10 "W42,Word Pin Register Port 1 Pin P1_10" line.long 0x14 "W43,Word Pin Register Port 1 Pin P1_11" line.long 0x18 "W44,Word Pin Register Port 1 Pin P1_12" endif sif !cpuis("LPC11U??FH?33*") group.long 0x10B4++0x07 line.long 0x00 "W45,Word Pin Register Port 1 Pin P1_13" line.long 0x04 "W46,Word Pin Register Port 1 Pin P1_14" endif group.long 0x10BC++0x03 line.long 0x00 "W47,Word Pin Register Port 1 Pin P1_15" sif !cpuis("LPC11U??FH?33*") group.long 0x10C0++0x03 line.long 0x00 "W48,Word Pin Register Port 1 Pin P1_16" endif sif cpuis("LPC11U??FGB64*")||cpuis("LPC11U37HFBD64*")||cpuis("LPC11U24/401")||cpuis("LPC11U3?FBD64") group.long 0x10C4++0x07 line.long 0x00 "W49,Word Pin Register Port 1 Pin P1_17" line.long 0x04 "W50,Word Pin Register Port 1 Pin P1_18" endif group.long 0x10CC++0x03 line.long 0x00 "W51,Word Pin Register Port 1 Pin P1_19" sif !cpuis("LPC11U??FH?33*") group.long 0x10D0++0x27 line.long 0x00 "W52,Word Pin Register Port 1 Pin P1_20" line.long 0x04 "W53,Word Pin Register Port 1 Pin P1_21" line.long 0x08 "W54,Word Pin Register Port 1 Pin P1_22" line.long 0x0C "W55,Word Pin Register Port 1 Pin P1_23" line.long 0x10 "W56,Word Pin Register Port 1 Pin P1_24" line.long 0x14 "W57,Word Pin Register Port 1 Pin P1_25" line.long 0x18 "W58,Word Pin Register Port 1 Pin P1_26" line.long 0x1C "W59,Word Pin Register Port 1 Pin P1_27" line.long 0x20 "W60,Word Pin Register Port 1 Pin P1_28" line.long 0x24 "W61,Word Pin Register Port 1 Pin P1_29" endif sif cpuis("LPC11U??FBD48*") group.long 0x10FC++0x03 line.long 0x00 "W63,Word Pin Register Port 1 Pin P1_31" endif tree.end group.long 0x2000++0x07 line.long 0x00 "DIR0,Direction Port 0 Register" bitfld.long 0x00 23. " DIRP[23] ,PIO0_23 pin direction select" "Input,Output" bitfld.long 0x00 22. " [22] ,PIO0_22 pin direction select" "Input,Output" bitfld.long 0x00 21. " [21] ,PIO0_21 pin direction select" "Input,Output" bitfld.long 0x00 20. " [20] ,PIO0_20 pin direction select" "Input,Output" bitfld.long 0x00 19. " [19] ,PIO0_19 pin direction select" "Input,Output" bitfld.long 0x00 18. " [18] ,PIO0_18 pin direction select" "Input,Output" bitfld.long 0x00 17. " [17] ,PIO0_17 pin direction select" "Input,Output" bitfld.long 0x00 16. " [16] ,PIO0_16 pin direction select" "Input,Output" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin direction select" "Input,Output" bitfld.long 0x00 14. " [14] ,PIO0_14 pin direction select" "Input,Output" bitfld.long 0x00 13. " [13] ,PIO0_13 pin direction select" "Input,Output" bitfld.long 0x00 12. " [12] ,PIO0_12 pin direction select" "Input,Output" bitfld.long 0x00 11. " [11] ,PIO0_11 pin direction select" "Input,Output" bitfld.long 0x00 10. " [10] ,PIO0_10 pin direction select" "Input,Output" bitfld.long 0x00 9. " [9] ,PIO0_9 pin direction select" "Input,Output" bitfld.long 0x00 8. " [8] ,PIO0_8 pin direction select" "Input,Output" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin direction select" "Input,Output" bitfld.long 0x00 6. " [6] ,PIO0_6 pin direction select" "Input,Output" bitfld.long 0x00 5. " [5] ,PIO0_5 pin direction select" "Input,Output" bitfld.long 0x00 4. " [4] ,PIO0_4 pin direction select" "Input,Output" bitfld.long 0x00 3. " [3] ,PIO0_3 pin direction select" "Input,Output" bitfld.long 0x00 2. " [2] ,PIO0_2 pin direction select" "Input,Output" bitfld.long 0x00 1. " [1] ,PIO0_1 pin direction select" "Input,Output" bitfld.long 0x00 0. " [0] ,PIO0_0 pin direction select" "Input,Output" line.long 0x04 "DIR1,Direction Port 1 Register" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " DIRP[31] ,PIO1_31 pin direction select" "Input,Output" bitfld.long 0x04 29. " [29] ,PIO1_29 pin direction select" "Input,Output" else bitfld.long 0x04 29. " DIRP[29] ,PIO1_29 pin direction select" "Input,Output" endif bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output" bitfld.long 0x04 27. " [27] ,PIO1_17 pin direction select" "Input,Output" bitfld.long 0x04 26. " [26] ,PIO1_16 pin direction select" "Input,Output" bitfld.long 0x04 25. " [25] ,PIO1_15 pin direction select" "Input,Output" bitfld.long 0x04 24. " [24] ,PIO1_14 pin direction select" "Input,Output" bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output" newline bitfld.long 0x04 22. " [22] ,PIO1_22 pin direction select" "Input,Output" bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output" bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output" bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output" bitfld.long 0x04 16. " [16] ,PIO1_16 pin direction select" "Input,Output" bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output" bitfld.long 0x04 14. " [14] ,PIO1_14 pin direction select" "Input,Output" bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output" sif cpuis("LPC11U??FET48*") newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin direction select" "Input,Output" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " DIRP[29] ,PIO1_29 pin direction select" "Input,Output" bitfld.long 0x04 28. " [28] ,PIO1_28 pin direction select" "Input,Output" bitfld.long 0x04 27. " [27] ,PIO1_17 pin direction select" "Input,Output" bitfld.long 0x04 26. " [26] ,PIO1_16 pin direction select" "Input,Output" bitfld.long 0x04 25. " [25] ,PIO1_15 pin direction select" "Input,Output" bitfld.long 0x04 24. " [24] ,PIO1_14 pin direction select" "Input,Output" bitfld.long 0x04 23. " [23] ,PIO1_23 pin direction select" "Input,Output" bitfld.long 0x04 22. " [22] ,PIO1_22 pin direction select" "Input,Output" newline bitfld.long 0x04 21. " [21] ,PIO1_21 pin direction select" "Input,Output" bitfld.long 0x04 20. " [20] ,PIO1_20 pin direction select" "Input,Output" bitfld.long 0x04 19. " [19] ,PIO1_19 pin direction select" "Input,Output" bitfld.long 0x04 18. " [18] ,PIO1_18 pin direction select" "Input,Output" bitfld.long 0x04 17. " [17] ,PIO1_17 pin direction select" "Input,Output" bitfld.long 0x04 16. " [16] ,PIO1_16 pin direction select" "Input,Output" bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output" bitfld.long 0x04 14. " [14] ,PIO1_14 pin direction select" "Input,Output" newline bitfld.long 0x04 13. " [13] ,PIO1_13 pin direction select" "Input,Output" bitfld.long 0x04 12. " [12] ,PIO1_12 pin direction select" "Input,Output" bitfld.long 0x04 11. " [11] ,PIO1_11 pin direction select" "Input,Output" bitfld.long 0x04 10. " [10] ,PIO1_10 pin direction select" "Input,Output" bitfld.long 0x04 9. " [9] ,PIO1_9 pin direction select" "Input,Output" bitfld.long 0x04 8. " [8] ,PIO1_8 pin direction select" "Input,Output" bitfld.long 0x04 7. " [7] ,PIO1_7 pin direction select" "Input,Output" bitfld.long 0x04 6. " [6] ,PIO1_6 pin direction select" "Input,Output" newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin direction select" "Input,Output" bitfld.long 0x04 4. " [4] ,PIO1_4 pin direction select" "Input,Output" bitfld.long 0x04 3. " [3] ,PIO1_3 pin direction select" "Input,Output" bitfld.long 0x04 2. " [2] ,PIO1_2 pin direction select" "Input,Output" bitfld.long 0x04 1. " [1] ,PIO1_1 pin direction select" "Input,Output" bitfld.long 0x04 0. " [0] ,PIO1_0 pin direction select" "Input,Output" else bitfld.long 0x04 19. " DIRP[19] ,PIO1_19 pin direction select" "Input,Output" bitfld.long 0x04 15. " [15] ,PIO1_15 pin direction select" "Input,Output" endif endif group.long 0x2080++0x07 line.long 0x00 "MASK0,Mask Port 0 Register" bitfld.long 0x00 23. " MASK[23] ,PIO0_23 pin mask bit" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,PIO0_22 pin mask bit" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,PIO0_21 pin mask bit" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,PIO0_20 pin mask bit" "Not masked,Masked" bitfld.long 0x00 19. " [19] ,PIO0_19 pin mask bit" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,PIO0_18 pin mask bit" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,PIO0_17 pin mask bit" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,PIO0_16 pin mask bit" "Not masked,Masked" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin mask bit" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,PIO0_14 pin mask bit" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,PIO0_13 pin mask bit" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,PIO0_12 pin mask bit" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,PIO0_11 pin mask bit" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,PIO0_10 pin mask bit" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,PIO0_9 pin mask bit" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,PIO0_8 pin mask bit" "Not masked,Masked" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin mask bit" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,PIO0_6 pin mask bit" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,PIO0_5 pin mask bit" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,PIO0_4 pin mask bit" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,PIO0_3 pin mask bit" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,PIO0_2 pin mask bit" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,PIO0_1 pin mask bit" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,PIO0_0 pin mask bit" "Not masked,Masked" line.long 0x04 "MASK1,Mask Port 1 Register" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " MASK[31] ,PIO1_31 pin mask bit" "Not masked,Masked" bitfld.long 0x04 29. " [29] ,PIO1_29 pin mask bit" "Not masked,Masked" else bitfld.long 0x04 29. " MASK[29] ,PIO1_29 pin mask bit" "Not masked,Masked" endif bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked" bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,PIO1_25 pin mask bit" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked" bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 22. " [22] ,PIO1_22 pin mask bit" "Not masked,Masked" bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked" bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,PIO1_16 pin mask bit" "Not masked,Masked" bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,PIO1_14 pin mask bit" "Not masked,Masked" bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked" sif cpuis("LPC11U??FET48*") newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin mask bit" "Not masked,Masked" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " MASK[29] ,PIO1_29 pin mask bit" "Not masked,Masked" bitfld.long 0x04 28. " [28] ,PIO1_28 pin mask bit" "Not masked,Masked" bitfld.long 0x04 27. " [27] ,PIO1_27 pin mask bit" "Not masked,Masked" bitfld.long 0x04 26. " [26] ,PIO1_26 pin mask bit" "Not masked,Masked" bitfld.long 0x04 25. " [25] ,PIO1_25 pin mask bit" "Not masked,Masked" bitfld.long 0x04 24. " [24] ,PIO1_24 pin mask bit" "Not masked,Masked" bitfld.long 0x04 23. " [23] ,PIO1_23 pin mask bit" "Not masked,Masked" bitfld.long 0x04 22. " [22] ,PIO1_22 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 21. " [21] ,PIO1_21 pin mask bit" "Not masked,Masked" bitfld.long 0x04 20. " [20] ,PIO1_20 pin mask bit" "Not masked,Masked" bitfld.long 0x04 19. " [19] ,PIO1_19 pin mask bit" "Not masked,Masked" bitfld.long 0x04 18. " [18] ,PIO1_18 pin mask bit" "Not masked,Masked" bitfld.long 0x04 17. " [17] ,PIO1_17 pin mask bit" "Not masked,Masked" bitfld.long 0x04 16. " [16] ,PIO1_16 pin mask bit" "Not masked,Masked" bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked" bitfld.long 0x04 14. " [14] ,PIO1_14 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 13. " [13] ,PIO1_13 pin mask bit" "Not masked,Masked" bitfld.long 0x04 12. " [12] ,PIO1_12 pin mask bit" "Not masked,Masked" bitfld.long 0x04 11. " [11] ,PIO1_11 pin mask bit" "Not masked,Masked" bitfld.long 0x04 10. " [10] ,PIO1_10 pin mask bit" "Not masked,Masked" bitfld.long 0x04 9. " [9] ,PIO1_9 pin mask bit" "Not masked,Masked" bitfld.long 0x04 8. " [8] ,PIO1_8 pin mask bit" "Not masked,Masked" bitfld.long 0x04 7. " [7] ,PIO1_7 pin mask bit" "Not masked,Masked" bitfld.long 0x04 6. " [6] ,PIO1_6 pin mask bit" "Not masked,Masked" newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin mask bit" "Not masked,Masked" bitfld.long 0x04 4. " [4] ,PIO1_4 pin mask bit" "Not masked,Masked" bitfld.long 0x04 3. " [3] ,PIO1_3 pin mask bit" "Not masked,Masked" bitfld.long 0x04 2. " [2] ,PIO1_2 pin mask bit" "Not masked,Masked" bitfld.long 0x04 1. " [1] ,PIO1_1 pin mask bit" "Not masked,Masked" bitfld.long 0x04 0. " [0] ,PIO1_0 pin mask bit" "Not masked,Masked" else bitfld.long 0x04 19. " MASK[19] ,PIO1_19 pin mask bit" "Not masked,Masked" bitfld.long 0x04 15. " [15] ,PIO1_15 pin mask bit" "Not masked,Masked" endif endif newline group.long 0x2100++0x07 line.long 0x00 "PIN0,Port Pin Register Port 0" bitfld.long 0x00 23. " PORT[23] ,PIO0_23 pin state" "Cleared,Set" bitfld.long 0x00 22. " [22] ,PIO0_22 pin state" "Cleared,Set" bitfld.long 0x00 21. " [21] ,PIO0_21 pin state" "Cleared,Set" bitfld.long 0x00 20. " [20] ,PIO0_20 pin state" "Cleared,Set" bitfld.long 0x00 19. " [19] ,PIO0_19 pin state" "Cleared,Set" bitfld.long 0x00 18. " [18] ,PIO0_18 pin state" "Cleared,Set" bitfld.long 0x00 17. " [17] ,PIO0_17 pin state" "Cleared,Set" bitfld.long 0x00 16. " [16] ,PIO0_16 pin state" "Cleared,Set" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin state" "Cleared,Set" bitfld.long 0x00 14. " [14] ,PIO0_14 pin state" "Cleared,Set" bitfld.long 0x00 13. " [13] ,PIO0_13 pin state" "Cleared,Set" bitfld.long 0x00 12. " [12] ,PIO0_12 pin state" "Cleared,Set" bitfld.long 0x00 11. " [11] ,PIO0_11 pin state" "Cleared,Set" bitfld.long 0x00 10. " [10] ,PIO0_10 pin state" "Cleared,Set" bitfld.long 0x00 9. " [9] ,PIO0_9 pin state" "Cleared,Set" bitfld.long 0x00 8. " [8] ,PIO0_8 pin state" "Cleared,Set" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin state" "Cleared,Set" bitfld.long 0x00 6. " [6] ,PIO0_6 pin state" "Cleared,Set" bitfld.long 0x00 5. " [5] ,PIO0_5 pin state" "Cleared,Set" bitfld.long 0x00 4. " [4] ,PIO0_4 pin state" "Cleared,Set" bitfld.long 0x00 3. " [3] ,PIO0_3 pin state" "Cleared,Set" bitfld.long 0x00 2. " [2] ,PIO0_2 pin state" "Cleared,Set" bitfld.long 0x00 1. " [1] ,PIO0_1 pin state" "Cleared,Set" bitfld.long 0x00 0. " [0] ,PIO0_0 pin state" "Cleared,Set" line.long 0x04 "PIN1,Port Pin Register Port 1" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " PORT[31] ,PIO1_31 pin state" "Cleared,Set" bitfld.long 0x04 29. " [29] ,PIO1_29 pin state" "Cleared,Set" else bitfld.long 0x04 29. " PORT[29] ,PIO1_29 pin state" "Cleared,Set" endif bitfld.long 0x04 28. " [28] ,PIO1_28 pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 pin state" "Cleared,Set" bitfld.long 0x04 25. " [25] ,PIO1_25 pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 pin state" "Cleared,Set" newline bitfld.long 0x04 22. " [22] ,PIO1_22 pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 pin state" "Cleared,Set" bitfld.long 0x04 16. " [16] ,PIO1_16 pin state" "Cleared,Set" bitfld.long 0x04 15. " [15] ,PIO1_15 pin state" "Cleared,Set" bitfld.long 0x04 14. " [14] ,PIO1_14 pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 pin state" "Cleared,Set" sif cpuis("LPC11U??FET48*") newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin state" "Cleared,Set" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " PORT[29] ,PIO1_29 pin state" "Cleared,Set" bitfld.long 0x04 28. " [28] ,PIO1_28 pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 pin state" "Cleared,Set" bitfld.long 0x04 25. " [25] ,PIO1_25 pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 pin state" "Cleared,Set" bitfld.long 0x04 22. " [22] ,PIO1_22 pin state" "Cleared,Set" newline bitfld.long 0x04 21. " [21] ,PIO1_21 pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 pin state" "Cleared,Set" bitfld.long 0x04 18. " [18] ,PIO1_18 pin state" "Cleared,Set" bitfld.long 0x04 17. " [17] ,PIO1_17 pin state" "Cleared,Set" bitfld.long 0x04 16. " [16] ,PIO1_16 pin state" "Cleared,Set" bitfld.long 0x04 15. " [15] ,PIO1_15 pin state" "Cleared,Set" bitfld.long 0x04 14. " [14] ,PIO1_14 pin state" "Cleared,Set" newline bitfld.long 0x04 13. " [13] ,PIO1_13 pin state" "Cleared,Set" bitfld.long 0x04 12. " [12] ,PIO1_12 pin state" "Cleared,Set" bitfld.long 0x04 11. " [11] ,PIO1_11 pin state" "Cleared,Set" bitfld.long 0x04 10. " [10] ,PIO1_10 pin state" "Cleared,Set" bitfld.long 0x04 9. " [9] ,PIO1_9 pin state" "Cleared,Set" bitfld.long 0x04 8. " [8] ,PIO1_8 pin state" "Cleared,Set" bitfld.long 0x04 7. " [7] ,PIO1_7 pin state" "Cleared,Set" bitfld.long 0x04 6. " [6] ,PIO1_6 pin state" "Cleared,Set" newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin state" "Cleared,Set" bitfld.long 0x04 4. " [4] ,PIO1_4 pin state" "Cleared,Set" bitfld.long 0x04 3. " [3] ,PIO1_3 pin state" "Cleared,Set" bitfld.long 0x04 2. " [2] ,PIO1_2 pin state" "Cleared,Set" bitfld.long 0x04 1. " [1] ,PIO1_1 pin state" "Cleared,Set" bitfld.long 0x04 0. " [0] ,PIO1_0 pin state" "Cleared,Set" else bitfld.long 0x04 19. " PORT[19] ,PIO1_19 pin state" "Cleared,Set" bitfld.long 0x04 15. " [15] ,PIO1_15 pin state" "Cleared,Set" endif endif group.long 0x2180++0x07 line.long 0x00 "MPIN0,Masked Port Register Port 0" bitfld.long 0x00 23. " MPORTP[23] ,PIO0_23 masked pin state" "Cleared,Set" bitfld.long 0x00 22. " [22] ,PIO0_22 masked pin state" "Cleared,Set" bitfld.long 0x00 21. " [21] ,PIO0_21 masked pin state" "Cleared,Set" bitfld.long 0x00 20. " [20] ,PIO0_20 masked pin state" "Cleared,Set" bitfld.long 0x00 19. " [19] ,PIO0_19 masked pin state" "Cleared,Set" bitfld.long 0x00 18. " [18] ,PIO0_18 masked pin state" "Cleared,Set" bitfld.long 0x00 17. " [17] ,PIO0_17 masked pin state" "Cleared,Set" bitfld.long 0x00 16. " [16] ,PIO0_16 masked pin state" "Cleared,Set" newline bitfld.long 0x00 15. " [15] ,PIO0_15 masked pin state" "Cleared,Set" bitfld.long 0x00 14. " [14] ,PIO0_14 masked pin state" "Cleared,Set" bitfld.long 0x00 13. " [13] ,PIO0_13 masked pin state" "Cleared,Set" bitfld.long 0x00 12. " [12] ,PIO0_12 masked pin state" "Cleared,Set" bitfld.long 0x00 11. " [11] ,PIO0_11 masked pin state" "Cleared,Set" bitfld.long 0x00 10. " [10] ,PIO0_10 masked pin state" "Cleared,Set" bitfld.long 0x00 9. " [9] ,PIO0_9 masked pin state" "Cleared,Set" bitfld.long 0x00 8. " [8] ,PIO0_8 masked pin state" "Cleared,Set" newline bitfld.long 0x00 7. " [7] ,PIO0_7 masked pin state" "Cleared,Set" bitfld.long 0x00 6. " [6] ,PIO0_6 masked pin state" "Cleared,Set" bitfld.long 0x00 5. " [5] ,PIO0_5 masked pin state" "Cleared,Set" bitfld.long 0x00 4. " [4] ,PIO0_4 masked pin state" "Cleared,Set" bitfld.long 0x00 3. " [3] ,PIO0_3 masked pin state" "Cleared,Set" bitfld.long 0x00 2. " [2] ,PIO0_2 masked pin state" "Cleared,Set" bitfld.long 0x00 1. " [1] ,PIO0_1 masked pin state" "Cleared,Set" bitfld.long 0x00 0. " [0] ,PIO0_0 masked pin state" "Cleared,Set" line.long 0x04 "MPIN1,Masked Port Register Port 1" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " MPORTP[31] ,PIO1_31 masked masked pin state" "Cleared,Set" bitfld.long 0x04 29. " [29] ,PIO1_29 masked pin state" "Cleared,Set" else bitfld.long 0x04 29. " MPORTP[29] ,PIO1_29 masked pin state" "Cleared,Set" endif bitfld.long 0x04 28. " [28] ,PIO1_28 masked pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 masked pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 masked pin state" "Cleared,Set" bitfld.long 0x04 25. " [25] ,PIO1_25 masked pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 masked pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state" "Cleared,Set" newline bitfld.long 0x04 22. " [22] ,PIO1_22 masked pin state" "Cleared,Set" bitfld.long 0x04 21. " [21] ,PIO1_21 masked pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 masked pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 masked pin state" "Cleared,Set" bitfld.long 0x04 16. " [16] ,PIO1_16 masked pin state" "Cleared,Set" bitfld.long 0x04 15. " [15] ,PIO1_15 masked pin state" "Cleared,Set" bitfld.long 0x04 14. " [14] ,PIO1_14 masked pin state" "Cleared,Set" bitfld.long 0x04 13. " [13] ,PIO1_13 masked pin state" "Cleared,Set" sif cpuis("LPC11U??FET48*") newline bitfld.long 0x04 5. " [5] ,PIO1_5 masked pin state" "Cleared,Set" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " MPORTP[29] ,PIO1_29 masked pin state" "Cleared,Set" bitfld.long 0x04 28. " [28] ,PIO1_28 masked pin state" "Cleared,Set" bitfld.long 0x04 27. " [27] ,PIO1_27 masked pin state" "Cleared,Set" bitfld.long 0x04 26. " [26] ,PIO1_26 masked pin state" "Cleared,Set" bitfld.long 0x04 25. " [25] ,PIO1_25 masked pin state" "Cleared,Set" bitfld.long 0x04 24. " [24] ,PIO1_24 masked pin state" "Cleared,Set" bitfld.long 0x04 23. " [23] ,PIO1_23 masked pin state" "Cleared,Set" bitfld.long 0x04 22. " [22] ,PIO1_22 masked pin state" "Cleared,Set" newline bitfld.long 0x04 21. " [21] ,PIO1_21 masked pin state" "Cleared,Set" bitfld.long 0x04 20. " [20] ,PIO1_20 masked pin state" "Cleared,Set" bitfld.long 0x04 19. " [19] ,PIO1_19 masked pin state" "Cleared,Set" bitfld.long 0x04 18. " [18] ,PIO1_18 masked pin state" "Cleared,Set" bitfld.long 0x04 17. " [17] ,PIO1_17 masked pin state" "Cleared,Set" bitfld.long 0x04 16. " [16] ,PIO1_16 masked pin state" "Cleared,Set" bitfld.long 0x04 15. " [15] ,PIO1_15 masked pin state" "Cleared,Set" bitfld.long 0x04 14. " [14] ,PIO1_14 masked pin state" "Cleared,Set" newline bitfld.long 0x04 13. " [13] ,PIO1_13 masked pin state" "Cleared,Set" bitfld.long 0x04 12. " [12] ,PIO1_12 masked pin state" "Cleared,Set" bitfld.long 0x04 11. " [11] ,PIO1_11 masked pin state" "Cleared,Set" bitfld.long 0x04 10. " [10] ,PIO1_10 masked pin state" "Cleared,Set" bitfld.long 0x04 9. " [9] ,PIO1_9 masked pin state" "Cleared,Set" bitfld.long 0x04 8. " [8] ,PIO1_8 masked pin state" "Cleared,Set" bitfld.long 0x04 7. " [7] ,PIO1_7 masked pin state" "Cleared,Set" bitfld.long 0x04 6. " [6] ,PIO1_6 masked pin state" "Cleared,Set" newline bitfld.long 0x04 5. " [5] ,PIO1_5 masked pin state" "Cleared,Set" bitfld.long 0x04 4. " [4] ,PIO1_4 masked pin state" "Cleared,Set" bitfld.long 0x04 3. " [3] ,PIO1_3 masked pin state" "Cleared,Set" bitfld.long 0x04 2. " [2] ,PIO1_2 masked pin state" "Cleared,Set" bitfld.long 0x04 1. " [1] ,PIO1_1 masked pin state" "Cleared,Set" bitfld.long 0x04 0. " [0] ,PIO1_0 masked pin state" "Cleared,Set" else bitfld.long 0x04 19. " MPORTP[19] ,PIO1_19 masked pin state" "Cleared,Set" bitfld.long 0x04 15. " [15] ,PIO1_15 masked pin state" "Cleared,Set" endif endif newline group.long 0x2200++0x07 line.long 0x00 "SET0,Set Register For Port 0" bitfld.long 0x00 23. " SETP[23] ,Read/Set output bit PIO0_23" "No operation,Set" bitfld.long 0x00 22. " [22] ,Read/Set output bit PIO0_22" "No operation,Set" bitfld.long 0x00 21. " [21] ,Read/Set output bit PIO0_21" "No operation,Set" bitfld.long 0x00 20. " [20] ,Read/Set output bit PIO0_20" "No operation,Set" bitfld.long 0x00 19. " [19] ,Read/Set output bit PIO0_19" "No operation,Set" bitfld.long 0x00 18. " [18] ,Read/Set output bit PIO0_18" "No operation,Set" bitfld.long 0x00 17. " [17] ,Read/Set output bit PIO0_17" "No operation,Set" bitfld.long 0x00 16. " [16] ,Read/Set output bit PIO0_16" "No operation,Set" newline bitfld.long 0x00 15. " [15] ,Read/Set output bit PIO0_15" "No operation,Set" bitfld.long 0x00 14. " [14] ,Read/Set output bit PIO0_14" "No operation,Set" bitfld.long 0x00 13. " [13] ,Read/Set output bit PIO0_13" "No operation,Set" bitfld.long 0x00 12. " [12] ,Read/Set output bit PIO0_12" "No operation,Set" bitfld.long 0x00 11. " [11] ,Read/Set output bit PIO0_11" "No operation,Set" bitfld.long 0x00 10. " [10] ,Read/Set output bit PIO0_10" "No operation,Set" bitfld.long 0x00 9. " [9] ,Read/Set output bit PIO0_9" "No operation,Set" bitfld.long 0x00 8. " [8] ,Read/Set output bit PIO0_8" "No operation,Set" newline bitfld.long 0x00 7. " [7] ,Read/Set output bit PIO0_7" "No operation,Set" bitfld.long 0x00 6. " [6] ,Read/Set output bit PIO0_6" "No operation,Set" bitfld.long 0x00 5. " [5] ,Read/Set output bit PIO0_5" "No operation,Set" bitfld.long 0x00 4. " [4] ,Read/Set output bit PIO0_4" "No operation,Set" bitfld.long 0x00 3. " [3] ,Read/Set output bit PIO0_3" "No operation,Set" bitfld.long 0x00 2. " [2] ,Read/Set output bit PIO0_2" "No operation,Set" bitfld.long 0x00 1. " [1] ,Read/Set output bit PIO0_1" "No operation,Set" bitfld.long 0x00 0. " [0] ,Read/Set output bit PIO0_0" "No operation,Set" line.long 0x04 "SET1,Set Register For Port 1" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " SETP[31] ,Read/Set output bit PIO1_31" "No operation,Set" bitfld.long 0x04 29. " [29] ,Read/Set output bit PIO1_29" "No operation,Set" else bitfld.long 0x04 29. " SETP[29] ,Read/Set output bit PIO1_29" "No operation,Set" endif bitfld.long 0x04 28. " [28] ,Read/Set output bit PIO1_28" "No operation,Set" bitfld.long 0x04 27. " [27] ,Read/Set output bit PIO1_27" "No operation,Set" bitfld.long 0x04 26. " [26] ,Read/Set output bit PIO1_26" "No operation,Set" bitfld.long 0x04 25. " [25] ,Read/Set output bit PIO1_25" "No operation,Set" bitfld.long 0x04 24. " [24] ,Read/Set output bit PIO1_24" "No operation,Set" bitfld.long 0x04 23. " [23] ,Read/Set output bit PIO1_23" "No operation,Set" newline bitfld.long 0x04 22. " [22] ,Read/Set output bit PIO1_22" "No operation,Set" bitfld.long 0x04 21. " [21] ,Read/Set output bit PIO1_21" "No operation,Set" bitfld.long 0x04 20. " [20] ,Read/Set output bit PIO1_20" "No operation,Set" bitfld.long 0x04 19. " [19] ,Read/Set output bit PIO1_19" "No operation,Set" bitfld.long 0x04 16. " [16] ,Read/Set output bit PIO1_16" "No operation,Set" bitfld.long 0x04 15. " [15] ,Read/Set output bit PIO1_15" "No operation,Set" bitfld.long 0x04 14. " [14] ,Read/Set output bit PIO1_14" "No operation,Set" bitfld.long 0x04 13. " [13] ,Read/Set output bit PIO1_13" "No operation,Set" sif cpuis("LPC11U??FET48*") newline bitfld.long 0x04 5. " [5] ,Read/Set output bit PIO1_5" "No operation,Set" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " SETP[29] ,Read/Set output bit PIO1_29" "No operation,Set" bitfld.long 0x04 28. " [28] ,Read/Set output bit PIO1_28" "No operation,Set" bitfld.long 0x04 27. " [27] ,Read/Set output bit PIO1_27" "No operation,Set" bitfld.long 0x04 26. " [26] ,Read/Set output bit PIO1_26" "No operation,Set" bitfld.long 0x04 25. " [25] ,Read/Set output bit PIO1_25" "No operation,Set" bitfld.long 0x04 24. " [24] ,Read/Set output bit PIO1_24" "No operation,Set" bitfld.long 0x04 23. " [23] ,Read/Set output bit PIO1_23" "No operation,Set" bitfld.long 0x04 22. " [22] ,Read/Set output bit PIO1_22" "No operation,Set" newline bitfld.long 0x04 21. " [21] ,Read/Set output bit PIO1_21" "No operation,Set" bitfld.long 0x04 20. " [20] ,Read/Set output bit PIO1_20" "No operation,Set" bitfld.long 0x04 19. " [19] ,Read/Set output bit PIO1_19" "No operation,Set" bitfld.long 0x04 18. " [18] ,Read/Set output bit PIO1_18" "No operation,Set" bitfld.long 0x04 17. " [17] ,Read/Set output bit PIO1_17" "No operation,Set" bitfld.long 0x04 16. " [16] ,Read/Set output bit PIO1_16" "No operation,Set" bitfld.long 0x04 15. " [15] ,Read/Set output bit PIO1_15" "No operation,Set" bitfld.long 0x04 14. " [14] ,Read/Set output bit PIO1_14" "No operation,Set" newline bitfld.long 0x04 13. " [13] ,Read/Set output bit PIO1_13" "No operation,Set" bitfld.long 0x04 12. " [12] ,Read/Set output bit PIO1_12" "No operation,Set" bitfld.long 0x04 11. " [11] ,Read/Set output bit PIO1_11" "No operation,Set" bitfld.long 0x04 10. " [10] ,Read/Set output bit PIO1_10" "No operation,Set" bitfld.long 0x04 9. " [9] ,Read/Set output bit PIO1_9" "No operation,Set" bitfld.long 0x04 8. " [8] ,Read/Set output bit PIO1_8" "No operation,Set" bitfld.long 0x04 7. " [7] ,Read/Set output bit PIO1_7" "No operation,Set" bitfld.long 0x04 6. " [6] ,Read/Set output bit PIO1_6" "No operation,Set" newline bitfld.long 0x04 5. " [5] ,Read/Set output bit PIO1_5" "No operation,Set" bitfld.long 0x04 4. " [4] ,Read/Set output bit PIO1_4" "No operation,Set" bitfld.long 0x04 3. " [3] ,Read/Set output bit PIO1_3" "No operation,Set" bitfld.long 0x04 2. " [2] ,Read/Set output bit PIO1_2" "No operation,Set" bitfld.long 0x04 1. " [1] ,Read/Set output bit PIO1_1" "No operation,Set" bitfld.long 0x04 0. " [0] ,Read/Set output bit PIO1_0" "No operation,Set" else bitfld.long 0x04 19. " SETP[19] ,Read/Set output bit PIO1_19" "No operation,Set" bitfld.long 0x04 15. " [15] ,Read/Set output bit PIO1_15" "No operation,Set" endif endif wgroup.long 0x2280++0x07 line.long 0x00 "CLR0,Clear Port 0" bitfld.long 0x00 23. " CLRP[23] ,PIO0_23 clear output" "No operation,Cleared" bitfld.long 0x00 22. " [22] ,PIO0_22 clear output" "No operation,Cleared" bitfld.long 0x00 21. " [21] ,PIO0_21 clear output" "No operation,Cleared" bitfld.long 0x00 20. " [20] ,PIO0_20 clear output" "No operation,Cleared" bitfld.long 0x00 19. " [19] ,PIO0_19 clear output" "No operation,Cleared" bitfld.long 0x00 18. " [18] ,PIO0_18 clear output" "No operation,Cleared" bitfld.long 0x00 17. " [17] ,PIO0_17 clear output" "No operation,Cleared" bitfld.long 0x00 16. " [16] ,PIO0_16 clear output" "No operation,Cleared" newline bitfld.long 0x00 15. " [15] ,PIO0_15 clear output" "No operation,Cleared" bitfld.long 0x00 14. " [14] ,PIO0_14 clear output" "No operation,Cleared" bitfld.long 0x00 13. " [13] ,PIO0_13 clear output" "No operation,Cleared" bitfld.long 0x00 12. " [12] ,PIO0_12 clear output" "No operation,Cleared" bitfld.long 0x00 11. " [11] ,PIO0_11 clear output" "No operation,Cleared" bitfld.long 0x00 10. " [10] ,PIO0_10 clear output" "No operation,Cleared" bitfld.long 0x00 9. " [9] ,PIO0_9 clear output" "No operation,Cleared" bitfld.long 0x00 8. " [8] ,PIO0_8 clear output" "No operation,Cleared" newline bitfld.long 0x00 7. " [7] ,PIO0_7 clear output" "No operation,Cleared" bitfld.long 0x00 6. " [6] ,PIO0_6 clear output" "No operation,Cleared" bitfld.long 0x00 5. " [5] ,PIO0_5 clear output" "No operation,Cleared" bitfld.long 0x00 4. " [4] ,PIO0_4 clear output" "No operation,Cleared" bitfld.long 0x00 3. " [3] ,PIO0_3 clear output" "No operation,Cleared" bitfld.long 0x00 2. " [2] ,PIO0_2 clear output" "No operation,Cleared" bitfld.long 0x00 1. " [1] ,PIO0_1 clear output" "No operation,Cleared" bitfld.long 0x00 0. " [0] ,PIO0_0 clear output" "No operation,Cleared" line.long 0x04 "CLR1,Clear Port 1" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " CLRP[31] ,PIO1_31 clear output" "No operation,Cleared" bitfld.long 0x04 29. " [29] ,PIO1_29 clear output" "No operation,Cleared" else bitfld.long 0x04 29. " CLRP[29] ,PIO1_29 clear output" "No operation,Cleared" endif bitfld.long 0x04 28. " [28] ,PIO1_28 clear output" "No operation,Cleared" bitfld.long 0x04 27. " [27] ,PIO1_27 clear output" "No operation,Cleared" bitfld.long 0x04 26. " [26] ,PIO1_26 clear output" "No operation,Cleared" bitfld.long 0x04 25. " [25] ,PIO1_25 clear output" "No operation,Cleared" bitfld.long 0x04 24. " [24] ,PIO1_24 clear output" "No operation,Cleared" bitfld.long 0x04 23. " [23] ,PIO1_23 clear output" "No operation,Cleared" newline bitfld.long 0x04 22. " [22] ,PIO1_22 clear output" "No operation,Cleared" bitfld.long 0x04 21. " [21] ,PIO1_21 clear output" "No operation,Cleared" bitfld.long 0x04 20. " [20] ,PIO1_20 clear output" "No operation,Cleared" bitfld.long 0x04 19. " [19] ,PIO1_19 clear output" "No operation,Cleared" bitfld.long 0x04 16. " [16] ,PIO1_16 clear output" "No operation,Cleared" bitfld.long 0x04 15. " [15] ,PIO1_15 clear output" "No operation,Cleared" bitfld.long 0x04 14. " [14] ,PIO1_14 clear output" "No operation,Cleared" bitfld.long 0x04 13. " [13] ,PIO1_13 clear output" "No operation,Cleared" sif cpuis("LPC11U??FET48*") newline bitfld.long 0x04 5. " [5] ,PIO1_5 clear output" "No operation,Cleared" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " CLRP[29] ,PIO1_29 clear output" "No operation,Cleared" bitfld.long 0x04 28. " [28] ,PIO1_28 clear output" "No operation,Cleared" bitfld.long 0x04 27. " [27] ,PIO1_27 clear output" "No operation,Cleared" bitfld.long 0x04 26. " [26] ,PIO1_26 clear output" "No operation,Cleared" bitfld.long 0x04 25. " [25] ,PIO1_25 clear output" "No operation,Cleared" bitfld.long 0x04 24. " [24] ,PIO1_24 clear output" "No operation,Cleared" bitfld.long 0x04 23. " [23] ,PIO1_23 clear output" "No operation,Cleared" bitfld.long 0x04 22. " [22] ,PIO1_22 clear output" "No operation,Cleared" newline bitfld.long 0x04 21. " [21] ,PIO1_21 clear output" "No operation,Cleared" bitfld.long 0x04 20. " [20] ,PIO1_20 clear output" "No operation,Cleared" bitfld.long 0x04 19. " [19] ,PIO1_19 clear output" "No operation,Cleared" bitfld.long 0x04 18. " [18] ,PIO1_18 clear output" "No operation,Cleared" bitfld.long 0x04 17. " [17] ,PIO1_17 clear output" "No operation,Cleared" bitfld.long 0x04 16. " [16] ,PIO1_16 clear output" "No operation,Cleared" bitfld.long 0x04 15. " [15] ,PIO1_15 clear output" "No operation,Cleared" bitfld.long 0x04 14. " [14] ,PIO1_14 clear output" "No operation,Cleared" newline bitfld.long 0x04 13. " [13] ,PIO1_13 clear output" "No operation,Cleared" bitfld.long 0x04 12. " [12] ,PIO1_12 clear output" "No operation,Cleared" bitfld.long 0x04 11. " [11] ,PIO1_11 clear output" "No operation,Cleared" bitfld.long 0x04 10. " [10] ,PIO1_10 clear output" "No operation,Cleared" bitfld.long 0x04 9. " [9] ,PIO1_9 clear output" "No operation,Cleared" bitfld.long 0x04 8. " [8] ,PIO1_8 clear output" "No operation,Cleared" bitfld.long 0x04 7. " [7] ,PIO1_7 clear output" "No operation,Cleared" bitfld.long 0x04 6. " [6] ,PIO1_6 clear output" "No operation,Cleared" newline bitfld.long 0x04 5. " [5] ,PIO1_5 clear output" "No operation,Cleared" bitfld.long 0x04 4. " [4] ,PIO1_4 clear output" "No operation,Cleared" bitfld.long 0x04 3. " [3] ,PIO1_3 clear output" "No operation,Cleared" bitfld.long 0x04 2. " [2] ,PIO1_2 clear output" "No operation,Cleared" bitfld.long 0x04 1. " [1] ,PIO1_1 clear output" "No operation,Cleared" bitfld.long 0x04 0. " [0] ,PIO1_0 clear output" "No operation,Cleared" else bitfld.long 0x04 19. " CLRP[19] ,PIO1_19 clear output" "No operation,Cleared" bitfld.long 0x04 15. " [15] ,PIO1_15 clear output" "No operation,Cleared" endif endif wgroup.long 0x2300++0x07 line.long 0x00 "NOT0,Toggle Port 0" bitfld.long 0x00 23. " NOTP[23] ,Toggle PIO0_23 output" "No operation,Toggled" bitfld.long 0x00 22. " [22] ,Toggle PIO0_22 output" "No operation,Toggled" bitfld.long 0x00 21. " [21] ,Toggle PIO0_21 output" "No operation,Toggled" bitfld.long 0x00 20. " [20] ,Toggle PIO0_20 output" "No operation,Toggled" bitfld.long 0x00 19. " [19] ,Toggle PIO0_19 output" "No operation,Toggled" bitfld.long 0x00 18. " [18] ,Toggle PIO0_18 output" "No operation,Toggled" bitfld.long 0x00 17. " [17] ,Toggle PIO0_17 output" "No operation,Toggled" bitfld.long 0x00 16. " [16] ,Toggle PIO0_16 output" "No operation,Toggled" newline bitfld.long 0x00 15. " [15] ,Toggle PIO0_15 output" "No operation,Toggled" bitfld.long 0x00 14. " [14] ,Toggle PIO0_14 output" "No operation,Toggled" bitfld.long 0x00 13. " [13] ,Toggle PIO0_13 output" "No operation,Toggled" bitfld.long 0x00 12. " [12] ,Toggle PIO0_12 output" "No operation,Toggled" bitfld.long 0x00 11. " [11] ,Toggle PIO0_11 output" "No operation,Toggled" bitfld.long 0x00 10. " [10] ,Toggle PIO0_10 output" "No operation,Toggled" bitfld.long 0x00 9. " [9] ,Toggle PIO0_9 output" "No operation,Toggled" bitfld.long 0x00 8. " [8] ,Toggle PIO0_8 output" "No operation,Toggled" newline bitfld.long 0x00 7. " [7] ,Toggle PIO0_7 output" "No operation,Toggled" bitfld.long 0x00 6. " [6] ,Toggle PIO0_6 output" "No operation,Toggled" bitfld.long 0x00 5. " [5] ,Toggle PIO0_5 output" "No operation,Toggled" bitfld.long 0x00 4. " [4] ,Toggle PIO0_4 output" "No operation,Toggled" bitfld.long 0x00 3. " [3] ,Toggle PIO0_3 output" "No operation,Toggled" bitfld.long 0x00 2. " [2] ,Toggle PIO0_2 output" "No operation,Toggled" bitfld.long 0x00 1. " [1] ,Toggle PIO0_1 output" "No operation,Toggled" bitfld.long 0x00 0. " [0] ,Toggle PIO0_0 output" "No operation,Toggled" line.long 0x04 "NOT1,Toggle Port 1" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " NOTP[31] ,Toggle PIO1_31 output" "No operation,Toggled" bitfld.long 0x04 29. " [29] ,Toggle PIO1_29 output" "No operation,Toggled" else bitfld.long 0x04 29. " NOTP[29] ,Toggle PIO1_29 output" "No operation,Toggled" endif bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggled" bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggled" bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggled" bitfld.long 0x04 25. " [25] ,Toggle PIO1_25 output" "No operation,Toggled" bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggled" bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggled" newline bitfld.long 0x04 22. " [22] ,Toggle PIO1_22 output" "No operation,Toggled" bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggled" bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggled" bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggled" bitfld.long 0x04 16. " [16] ,Toggle PIO1_16 output" "No operation,Toggled" bitfld.long 0x04 15. " [15] ,Toggle PIO1_15 output" "No operation,Toggled" bitfld.long 0x04 14. " [14] ,Toggle PIO1_14 output" "No operation,Toggled" bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggled" sif cpuis("LPC11U??FET48*") newline bitfld.long 0x04 5. " [5] ,Toggle PIO1_5 output" "No operation,Toggled" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " NOTP[29] ,Toggle PIO1_29 output" "No operation,Toggled" bitfld.long 0x04 28. " [28] ,Toggle PIO1_28 output" "No operation,Toggled" bitfld.long 0x04 27. " [27] ,Toggle PIO1_27 output" "No operation,Toggled" bitfld.long 0x04 26. " [26] ,Toggle PIO1_26 output" "No operation,Toggled" bitfld.long 0x04 25. " [25] ,Toggle PIO1_25 output" "No operation,Toggled" bitfld.long 0x04 24. " [24] ,Toggle PIO1_24 output" "No operation,Toggled" bitfld.long 0x04 23. " [23] ,Toggle PIO1_23 output" "No operation,Toggled" bitfld.long 0x04 22. " [22] ,Toggle PIO1_22 output" "No operation,Toggled" newline bitfld.long 0x04 21. " [21] ,Toggle PIO1_21 output" "No operation,Toggled" bitfld.long 0x04 20. " [20] ,Toggle PIO1_20 output" "No operation,Toggled" bitfld.long 0x04 19. " [19] ,Toggle PIO1_19 output" "No operation,Toggled" bitfld.long 0x04 18. " [18] ,Toggle PIO1_18 output" "No operation,Toggled" bitfld.long 0x04 17. " [17] ,Toggle PIO1_17 output" "No operation,Toggled" bitfld.long 0x04 16. " [16] ,Toggle PIO1_16 output" "No operation,Toggled" bitfld.long 0x04 15. " [15] ,Toggle PIO1_15 output" "No operation,Toggled" bitfld.long 0x04 14. " [14] ,Toggle PIO1_14 output" "No operation,Toggled" newline bitfld.long 0x04 13. " [13] ,Toggle PIO1_13 output" "No operation,Toggled" bitfld.long 0x04 12. " [12] ,Toggle PIO1_12 output" "No operation,Toggled" bitfld.long 0x04 11. " [11] ,Toggle PIO1_11 output" "No operation,Toggled" bitfld.long 0x04 10. " [10] ,Toggle PIO1_10 output" "No operation,Toggled" bitfld.long 0x04 9. " [9] ,Toggle PIO1_9 output" "No operation,Toggled" bitfld.long 0x04 8. " [8] ,Toggle PIO1_8 output" "No operation,Toggled" bitfld.long 0x04 7. " [7] ,Toggle PIO1_7 output" "No operation,Toggled" bitfld.long 0x04 6. " [6] ,Toggle PIO1_6 output" "No operation,Toggled" newline bitfld.long 0x04 5. " [5] ,Toggle PIO1_5 output" "No operation,Toggled" bitfld.long 0x04 4. " [4] ,Toggle PIO1_4 output" "No operation,Toggled" bitfld.long 0x04 3. " [3] ,Toggle PIO1_3 output" "No operation,Toggled" bitfld.long 0x04 2. " [2] ,Toggle PIO1_2 output" "No operation,Toggled" bitfld.long 0x04 1. " [1] ,Toggle PIO1_1 output" "No operation,Toggled" bitfld.long 0x04 0. " [0] ,Toggle PIO1_0 output" "No operation,Toggled" else bitfld.long 0x04 19. " NOTP[19] ,Toggle PIO1_19 output" "No operation,Toggled" bitfld.long 0x04 15. " [15] ,Toggle PIO1_15 output" "No operation,Toggled" endif endif width 0x0B endif tree.end tree "GINT (Grouped GPIO Input Interrupt)" tree "Group 0" sif cpuis("LPC11U6?JBD*") base ad:0x4005C000 width 11. group.long 0x00++0x03 line.long 0x00 "CTRL,GPIO Grouped Interrupt Control Register" bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level" bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND" bitfld.long 0x00 0. " INT ,Group interrupt status" "Pending,Active" group.long 0x20++0x07 line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity" bitfld.long 0x00 23. " POL[23] ,PIO0_23 pin polarity" "Low,High" bitfld.long 0x00 22. " [22] ,PIO0_22 pin polarity" "Low,High" bitfld.long 0x00 21. " [21] ,PIO0_21 pin polarity" "Low,High" bitfld.long 0x00 20. " [20] ,PIO0_20 pin polarity" "Low,High" bitfld.long 0x00 19. " [19] ,PIO0_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO0_18 pin polarity" "Low,High" bitfld.long 0x00 17. " [17] ,PIO0_17 pin polarity" "Low,High" bitfld.long 0x00 16. " [16] ,PIO0_16 pin polarity" "Low,High" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin polarity" "Low,High" bitfld.long 0x00 14. " [14] ,PIO0_14 pin polarity" "Low,High" bitfld.long 0x00 13. " [13] ,PIO0_13 pin polarity" "Low,High" bitfld.long 0x00 12. " [12] ,PIO0_12 pin polarity" "Low,High" bitfld.long 0x00 11. " [11] ,PIO0_11 pin polarity" "Low,High" bitfld.long 0x00 10. " [10] ,PIO0_10 pin polarity" "Low,High" bitfld.long 0x00 9. " [9] ,PIO0_9 pin polarity" "Low,High" bitfld.long 0x00 8. " [8] ,PIO0_8 pin polarity" "Low,High" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO0_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO0_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO0_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO0_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO0_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO0_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO0_0 pin polarity" "Low,High" line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" newline bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" else bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" endif elif cpuis("LPC11E11") bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" elif cpuis("LPC11E12")||cpuis("LPC11E13") bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" newline bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" elif cpuis("LPC11E35FHI33") bitfld.long 0x04 19. " POL[19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" elif cpuis("LPC11E6?JBD48") bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" elif cpuis("LPC11E6?JBD64") bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" newline bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" else bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High" sif cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37")||cpuis("LPC11E37H") textfld " " else bitfld.long 0x04 30. " [30] ,PIO1_30 pin polarity" "Low,High" endif bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" newline bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 18. " [18] ,PIO1_18 pin polarity" "Low,High" bitfld.long 0x04 17. " [17] ,PIO1_17 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" newline bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 12. " [12] ,PIO1_12 pin polarity" "Low,High" bitfld.long 0x04 11. " [11] ,PIO1_11 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 8. " [8] ,PIO1_8 pin polarity" "Low,High" newline bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 6. " [6] ,PIO1_6 pin polarity" "Low,High" bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High" bitfld.long 0x04 4. " [4] ,PIO1_4 pin polarity" "Low,High" bitfld.long 0x04 3. " [3] ,PIO1_3pin polarity" "Low,High" bitfld.long 0x04 2. " [2] ,PIO1_2 pin polarity" "Low,High" bitfld.long 0x04 1. " [1] ,PIO1_1 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" endif sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*") group.long 0x28++0x04 line.long 0x00 "PORT_POL2,GPIO Grouped Interrupt Port 2 Polarity" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High" bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High" bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" newline bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" else bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" endif elif cpuis("LPC11E6?JBD48") bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64") bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High" bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High" bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High" newline bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" else bitfld.long 0x00 23. " POL[23] ,PIO2_23 pin polarity" "Low,High" bitfld.long 0x00 22. " [22] ,PIO2_22 pin polarity" "Low,High" bitfld.long 0x00 21. " [21] ,PIO2_21 pin polarity" "Low,High" bitfld.long 0x00 20. " [20] ,PIO2_20 pin polarity" "Low,High" bitfld.long 0x00 19. " [19] ,PIO2_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High" bitfld.long 0x00 17. " [17] ,PIO2_17 pin polarity" "Low,High" bitfld.long 0x00 16. " [16] ,PIO2_16 pin polarity" "Low,High" newline bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High" bitfld.long 0x00 14. " [14] ,PIO2_14 pin polarity" "Low,High" bitfld.long 0x00 13. " [13] ,PIO2_13 pin polarity" "Low,High" bitfld.long 0x00 12. " [12] ,PIO2_12 pin polarity" "Low,High" bitfld.long 0x00 11. " [11] ,PIO2_11 pin polarity" "Low,High" bitfld.long 0x00 10. " [10] ,PIO2_10 pin polarity" "Low,High" bitfld.long 0x00 9. " [9] ,PIO2_9 pin polarity" "Low,High" bitfld.long 0x00 8. " [8] ,PIO2_8 pin polarity" "Low,High" newline bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" endif endif group.long 0x40++0x07 line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register" bitfld.long 0x00 23. " ENA[23] ,Enable PIO0_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable PIO0_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable PIO0_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable PIO0_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Enable PIO0_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO0_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable PIO0_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable PIO0_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable PIO0_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable PIO0_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable PIO0_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable PIO0_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable PIO0_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable PIO0_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable PIO0_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable PIO0_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable PIO0_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO0_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO0_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO0_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO0_3for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO0_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO0_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO0_0 for group interrupt" "Disabled,Enabled" line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" endif elif cpuis("LPC11E11") bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E12")||cpuis("LPC11E13") bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E35FHI33") bitfld.long 0x04 19. " ENA[19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E6?JBD48") bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E6?JBD64") bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled" sif !cpuis("LPC11E14")&&!cpuis("LPC11E36")&&!cpuis("LPC11E37")&&!cpuis("LPC11E37H") bitfld.long 0x04 30. " [30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled" endif bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Enable PIO1_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Enable PIO1_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,Enable PIO1_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 11. " [11] ,Enable PIO1_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,Enable PIO1_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Enable PIO1_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Enable PIO1_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,Enable PIO1_3for group interrupt" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Enable PIO1_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Enable PIO1_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" endif sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*") group.long 0x48++0x03 line.long 0x00 "PORT_ENA2,GPIO Grouped Interrupt Port 2 Enable Register" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" endif elif cpuis("LPC11E66JBD48")||cpuis("LPC11E67JBD48") bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64") bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x00 23. " ENA[23] ,Enable PIO2_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable PIO2_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable PIO2_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable PIO2_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable PIO2_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable PIO2_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable PIO2_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable PIO2_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable PIO2_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable PIO2_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable PIO2_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable PIO2_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable PIO2_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" endif endif width 0x0B else base ad:0x4005C000 width 11. group.long 0x00++0x03 line.long 0x00 "CTRL,GPIO Grouped Interrupt Control Register" bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level" bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND" bitfld.long 0x00 0. " INT ,Group interrupt status" "Pending,Active" newline group.long 0x20++0x07 line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity" bitfld.long 0x00 23. " POL[23] ,PIO0_23 pin polarity" "Low,High" bitfld.long 0x00 22. " [22] ,PIO0_22 pin polarity" "Low,High" bitfld.long 0x00 21. " [21] ,PIO0_21 pin polarity" "Low,High" bitfld.long 0x00 20. " [20] ,PIO0_20 pin polarity" "Low,High" bitfld.long 0x00 19. " [19] ,PIO0_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO0_18 pin polarity" "Low,High" bitfld.long 0x00 17. " [17] ,PIO0_17 pin polarity" "Low,High" bitfld.long 0x00 16. " [16] ,PIO0_16 pin polarity" "Low,High" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin polarity" "Low,High" bitfld.long 0x00 14. " [14] ,PIO0_14 pin polarity" "Low,High" bitfld.long 0x00 13. " [13] ,PIO0_13 pin polarity" "Low,High" bitfld.long 0x00 12. " [12] ,PIO0_12 pin polarity" "Low,High" bitfld.long 0x00 11. " [11] ,PIO0_11 pin polarity" "Low,High" bitfld.long 0x00 10. " [10] ,PIO0_10 pin polarity" "Low,High" bitfld.long 0x00 9. " [9] ,PIO0_9 pin polarity" "Low,High" bitfld.long 0x00 8. " [8] ,PIO0_8 pin polarity" "Low,High" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO0_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO0_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO0_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO0_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO0_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO0_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO0_0 pin polarity" "Low,High" line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" else bitfld.long 0x04 29. " POL[29] ,PIO1_29 pin polarity" "Low,High" endif bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" newline bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" newline sif cpuis("LPC11U??FET48*") bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " POL[29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" newline bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 18. " [18] ,PIO1_18 pin polarity" "Low,High" bitfld.long 0x04 17. " [17] ,PIO1_17 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" newline bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 12. " [12] ,PIO1_12 pin polarity" "Low,High" bitfld.long 0x04 11. " [11] ,PIO1_11 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 8. " [8] ,PIO1_8 pin polarity" "Low,High" bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 6. " [6] ,PIO1_6 pin polarity" "Low,High" newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High" bitfld.long 0x04 4. " [4] ,PIO1_4 pin polarity" "Low,High" bitfld.long 0x04 3. " [3] ,PIO1_3 pin polarity" "Low,High" bitfld.long 0x04 2. " [2] ,PIO1_2 pin polarity" "Low,High" bitfld.long 0x04 1. " [1] ,PIO1_1 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" else bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" endif endif newline group.long 0x40++0x07 line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register" bitfld.long 0x00 23. " ENA[23] ,Enable PIO0_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable PIO0_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable PIO0_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable PIO0_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Enable PIO0_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO0_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable PIO0_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable PIO0_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable PIO0_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable PIO0_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable PIO0_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable PIO0_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable PIO0_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable PIO0_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable PIO0_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable PIO0_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable PIO0_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO0_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO0_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO0_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO0_3for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO0_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO0_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO0_0 for group interrupt" "Disabled,Enabled" line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 29. " ENA[29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" endif bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" newline sif cpuis("LPC11U??FET48*") bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " ENA[29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Enable PIO1_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Enable PIO1_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,Enable PIO1_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 11. " [11] ,Enable PIO1_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,Enable PIO1_8 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Enable PIO1_6 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Enable PIO1_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,Enable PIO1_3for group interrupt" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Enable PIO1_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Enable PIO1_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 19. " ENA[19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" endif endif width 0x0B endif tree.end tree "Group 1" sif cpuis("LPC11U6?JBD*") base ad:0x40060000 width 11. group.long 0x00++0x03 line.long 0x00 "CTRL,GPIO Grouped Interrupt Control Register" bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level" bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND" bitfld.long 0x00 0. " INT ,Group interrupt status" "Pending,Active" group.long 0x20++0x07 line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity" bitfld.long 0x00 23. " POL[23] ,PIO0_23 pin polarity" "Low,High" bitfld.long 0x00 22. " [22] ,PIO0_22 pin polarity" "Low,High" bitfld.long 0x00 21. " [21] ,PIO0_21 pin polarity" "Low,High" bitfld.long 0x00 20. " [20] ,PIO0_20 pin polarity" "Low,High" bitfld.long 0x00 19. " [19] ,PIO0_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO0_18 pin polarity" "Low,High" bitfld.long 0x00 17. " [17] ,PIO0_17 pin polarity" "Low,High" bitfld.long 0x00 16. " [16] ,PIO0_16 pin polarity" "Low,High" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin polarity" "Low,High" bitfld.long 0x00 14. " [14] ,PIO0_14 pin polarity" "Low,High" bitfld.long 0x00 13. " [13] ,PIO0_13 pin polarity" "Low,High" bitfld.long 0x00 12. " [12] ,PIO0_12 pin polarity" "Low,High" bitfld.long 0x00 11. " [11] ,PIO0_11 pin polarity" "Low,High" bitfld.long 0x00 10. " [10] ,PIO0_10 pin polarity" "Low,High" bitfld.long 0x00 9. " [9] ,PIO0_9 pin polarity" "Low,High" bitfld.long 0x00 8. " [8] ,PIO0_8 pin polarity" "Low,High" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO0_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO0_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO0_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO0_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO0_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO0_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO0_0 pin polarity" "Low,High" line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" newline bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" else bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" endif elif cpuis("LPC11E11") bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" elif cpuis("LPC11E12")||cpuis("LPC11E13") bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" newline bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" elif cpuis("LPC11E35FHI33") bitfld.long 0x04 19. " POL[19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" elif cpuis("LPC11E6?JBD48") bitfld.long 0x04 24. " POL[24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" elif cpuis("LPC11E6?JBD64") bitfld.long 0x04 30. " POL[30] ,PIO1_30 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" newline bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" else bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High" sif cpuis("LPC11E14")||cpuis("LPC11E36")||cpuis("LPC11E37")||cpuis("LPC11E37H") textfld " " else bitfld.long 0x04 30. " [30] ,PIO1_30 pin polarity" "Low,High" endif bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" newline bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 18. " [18] ,PIO1_18 pin polarity" "Low,High" bitfld.long 0x04 17. " [17] ,PIO1_17 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" newline bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 12. " [12] ,PIO1_12 pin polarity" "Low,High" bitfld.long 0x04 11. " [11] ,PIO1_11 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 8. " [8] ,PIO1_8 pin polarity" "Low,High" newline bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 6. " [6] ,PIO1_6 pin polarity" "Low,High" bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High" bitfld.long 0x04 4. " [4] ,PIO1_4 pin polarity" "Low,High" bitfld.long 0x04 3. " [3] ,PIO1_3pin polarity" "Low,High" bitfld.long 0x04 2. " [2] ,PIO1_2 pin polarity" "Low,High" bitfld.long 0x04 1. " [1] ,PIO1_1 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" endif sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*") group.long 0x28++0x04 line.long 0x00 "PORT_POL2,GPIO Grouped Interrupt Port 2 Polarity" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High" bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High" bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" newline bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" else bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" endif elif cpuis("LPC11E6?JBD48") bitfld.long 0x00 7. " POL[7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64") bitfld.long 0x00 19. " POL[19] ,PIO2_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High" bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High" bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High" newline bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" else bitfld.long 0x00 23. " POL[23] ,PIO2_23 pin polarity" "Low,High" bitfld.long 0x00 22. " [22] ,PIO2_22 pin polarity" "Low,High" bitfld.long 0x00 21. " [21] ,PIO2_21 pin polarity" "Low,High" bitfld.long 0x00 20. " [20] ,PIO2_20 pin polarity" "Low,High" bitfld.long 0x00 19. " [19] ,PIO2_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO2_18 pin polarity" "Low,High" bitfld.long 0x00 17. " [17] ,PIO2_17 pin polarity" "Low,High" bitfld.long 0x00 16. " [16] ,PIO2_16 pin polarity" "Low,High" newline bitfld.long 0x00 15. " [15] ,PIO2_15 pin polarity" "Low,High" bitfld.long 0x00 14. " [14] ,PIO2_14 pin polarity" "Low,High" bitfld.long 0x00 13. " [13] ,PIO2_13 pin polarity" "Low,High" bitfld.long 0x00 12. " [12] ,PIO2_12 pin polarity" "Low,High" bitfld.long 0x00 11. " [11] ,PIO2_11 pin polarity" "Low,High" bitfld.long 0x00 10. " [10] ,PIO2_10 pin polarity" "Low,High" bitfld.long 0x00 9. " [9] ,PIO2_9 pin polarity" "Low,High" bitfld.long 0x00 8. " [8] ,PIO2_8 pin polarity" "Low,High" newline bitfld.long 0x00 7. " [7] ,PIO2_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO2_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO2_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO2_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO2_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO2_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO2_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO2_0 pin polarity" "Low,High" endif endif group.long 0x40++0x07 line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register" bitfld.long 0x00 23. " ENA[23] ,Enable PIO0_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable PIO0_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable PIO0_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable PIO0_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Enable PIO0_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO0_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable PIO0_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable PIO0_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable PIO0_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable PIO0_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable PIO0_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable PIO0_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable PIO0_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable PIO0_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable PIO0_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable PIO0_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable PIO0_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO0_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO0_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO0_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO0_3for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO0_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO0_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO0_0 for group interrupt" "Disabled,Enabled" line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" endif elif cpuis("LPC11E11") bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E12")||cpuis("LPC11E13") bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E35FHI33") bitfld.long 0x04 19. " ENA[19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E6?JBD48") bitfld.long 0x04 24. " ENA[24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E6?JBD64") bitfld.long 0x04 30. " ENA[30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled" sif !cpuis("LPC11E14")&&!cpuis("LPC11E36")&&!cpuis("LPC11E37")&&!cpuis("LPC11E37H") bitfld.long 0x04 30. " [30] ,Enable PIO1_30 for group interrupt" "Disabled,Enabled" endif bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Enable PIO1_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Enable PIO1_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,Enable PIO1_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 11. " [11] ,Enable PIO1_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,Enable PIO1_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Enable PIO1_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Enable PIO1_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,Enable PIO1_3for group interrupt" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Enable PIO1_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Enable PIO1_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" endif sif !cpuis("LPC11E1*")&&!cpuis("LPC11E3*") group.long 0x48++0x03 line.long 0x00 "PORT_ENA2,GPIO Grouped Interrupt Port 2 Enable Register" sif !cpuis("LPC11U6?JBD100")&&!cpuis("LPC11E*") sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" endif elif cpuis("LPC11E66JBD48")||cpuis("LPC11E67JBD48") bitfld.long 0x00 7. " ENA[7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" elif cpuis("LPC11E67JBD64")||cpuis("LPC11E68JBD64") bitfld.long 0x00 19. " ENA[19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x00 23. " ENA[23] ,Enable PIO2_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable PIO2_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable PIO2_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable PIO2_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Enable PIO2_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO2_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable PIO2_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable PIO2_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable PIO2_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable PIO2_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable PIO2_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable PIO2_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable PIO2_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable PIO2_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable PIO2_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable PIO2_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable PIO2_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO2_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO2_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO2_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO2_3 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO2_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO2_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO2_0 for group interrupt" "Disabled,Enabled" endif endif width 0x0B else base ad:0x40060000 width 11. group.long 0x00++0x03 line.long 0x00 "CTRL,GPIO Grouped Interrupt Control Register" bitfld.long 0x00 2. " TRIG ,Group interrupt trigger" "Edge,Level" bitfld.long 0x00 1. " COMB ,Combine enabled inputs for group interrupt" "OR,AND" bitfld.long 0x00 0. " INT ,Group interrupt status" "Pending,Active" newline group.long 0x20++0x07 line.long 0x00 "PORT_POL0,GPIO Grouped Interrupt Port 0 Polarity" bitfld.long 0x00 23. " POL[23] ,PIO0_23 pin polarity" "Low,High" bitfld.long 0x00 22. " [22] ,PIO0_22 pin polarity" "Low,High" bitfld.long 0x00 21. " [21] ,PIO0_21 pin polarity" "Low,High" bitfld.long 0x00 20. " [20] ,PIO0_20 pin polarity" "Low,High" bitfld.long 0x00 19. " [19] ,PIO0_19 pin polarity" "Low,High" bitfld.long 0x00 18. " [18] ,PIO0_18 pin polarity" "Low,High" bitfld.long 0x00 17. " [17] ,PIO0_17 pin polarity" "Low,High" bitfld.long 0x00 16. " [16] ,PIO0_16 pin polarity" "Low,High" newline bitfld.long 0x00 15. " [15] ,PIO0_15 pin polarity" "Low,High" bitfld.long 0x00 14. " [14] ,PIO0_14 pin polarity" "Low,High" bitfld.long 0x00 13. " [13] ,PIO0_13 pin polarity" "Low,High" bitfld.long 0x00 12. " [12] ,PIO0_12 pin polarity" "Low,High" bitfld.long 0x00 11. " [11] ,PIO0_11 pin polarity" "Low,High" bitfld.long 0x00 10. " [10] ,PIO0_10 pin polarity" "Low,High" bitfld.long 0x00 9. " [9] ,PIO0_9 pin polarity" "Low,High" bitfld.long 0x00 8. " [8] ,PIO0_8 pin polarity" "Low,High" newline bitfld.long 0x00 7. " [7] ,PIO0_7 pin polarity" "Low,High" bitfld.long 0x00 6. " [6] ,PIO0_6 pin polarity" "Low,High" bitfld.long 0x00 5. " [5] ,PIO0_5 pin polarity" "Low,High" bitfld.long 0x00 4. " [4] ,PIO0_4 pin polarity" "Low,High" bitfld.long 0x00 3. " [3] ,PIO0_3 pin polarity" "Low,High" bitfld.long 0x00 2. " [2] ,PIO0_2 pin polarity" "Low,High" bitfld.long 0x00 1. " [1] ,PIO0_1 pin polarity" "Low,High" bitfld.long 0x00 0. " [0] ,PIO0_0 pin polarity" "Low,High" line.long 0x04 "PORT_POL1,GPIO Grouped Interrupt Port 1 Polarity" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " POL[31] ,PIO1_31 pin polarity" "Low,High" bitfld.long 0x04 29. " [29] ,PIO1_29 pin polarity" "Low,High" else bitfld.long 0x04 29. " POL[29] ,PIO1_29 pin polarity" "Low,High" endif bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" newline bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" newline sif cpuis("LPC11U??FET48*") bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " POL[29] ,PIO1_29 pin polarity" "Low,High" bitfld.long 0x04 28. " [28] ,PIO1_28 pin polarity" "Low,High" bitfld.long 0x04 27. " [27] ,PIO1_27 pin polarity" "Low,High" bitfld.long 0x04 26. " [26] ,PIO1_26 pin polarity" "Low,High" bitfld.long 0x04 25. " [25] ,PIO1_25 pin polarity" "Low,High" bitfld.long 0x04 24. " [24] ,PIO1_24 pin polarity" "Low,High" bitfld.long 0x04 23. " [23] ,PIO1_23 pin polarity" "Low,High" bitfld.long 0x04 22. " [22] ,PIO1_22 pin polarity" "Low,High" newline bitfld.long 0x04 21. " [21] ,PIO1_21 pin polarity" "Low,High" bitfld.long 0x04 20. " [20] ,PIO1_20 pin polarity" "Low,High" bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 18. " [18] ,PIO1_18 pin polarity" "Low,High" bitfld.long 0x04 17. " [17] ,PIO1_17 pin polarity" "Low,High" bitfld.long 0x04 16. " [16] ,PIO1_16 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" bitfld.long 0x04 14. " [14] ,PIO1_14 pin polarity" "Low,High" newline bitfld.long 0x04 13. " [13] ,PIO1_13 pin polarity" "Low,High" bitfld.long 0x04 12. " [12] ,PIO1_12 pin polarity" "Low,High" bitfld.long 0x04 11. " [11] ,PIO1_11 pin polarity" "Low,High" bitfld.long 0x04 10. " [10] ,PIO1_10 pin polarity" "Low,High" bitfld.long 0x04 9. " [9] ,PIO1_9 pin polarity" "Low,High" bitfld.long 0x04 8. " [8] ,PIO1_8 pin polarity" "Low,High" bitfld.long 0x04 7. " [7] ,PIO1_7 pin polarity" "Low,High" bitfld.long 0x04 6. " [6] ,PIO1_6 pin polarity" "Low,High" newline bitfld.long 0x04 5. " [5] ,PIO1_5 pin polarity" "Low,High" bitfld.long 0x04 4. " [4] ,PIO1_4 pin polarity" "Low,High" bitfld.long 0x04 3. " [3] ,PIO1_3 pin polarity" "Low,High" bitfld.long 0x04 2. " [2] ,PIO1_2 pin polarity" "Low,High" bitfld.long 0x04 1. " [1] ,PIO1_1 pin polarity" "Low,High" bitfld.long 0x04 0. " [0] ,PIO1_0 pin polarity" "Low,High" else bitfld.long 0x04 19. " [19] ,PIO1_19 pin polarity" "Low,High" bitfld.long 0x04 15. " [15] ,PIO1_15 pin polarity" "Low,High" endif endif newline group.long 0x40++0x07 line.long 0x00 "PORT_ENA0,GPIO Grouped Interrupt Port 0 Enable Register" bitfld.long 0x00 23. " ENA[23] ,Enable PIO0_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 22. " [22] ,Enable PIO0_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable PIO0_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable PIO0_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " [19] ,Enable PIO0_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable PIO0_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable PIO0_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 16. " [16] ,Enable PIO0_16 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 15. " [15] ,Enable PIO0_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Enable PIO0_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable PIO0_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Enable PIO0_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable PIO0_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable PIO0_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Enable PIO0_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable PIO0_8 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Enable PIO0_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Enable PIO0_6 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable PIO0_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable PIO0_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Enable PIO0_3for group interrupt" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable PIO0_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable PIO0_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Enable PIO0_0 for group interrupt" "Disabled,Enabled" line.long 0x04 "PORT_ENA1,GPIO Grouped Interrupt Port 1 Enable Register" sif cpuis("LPC11U??F??48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") sif cpuis("LPC11U??FBD48*")||cpuis("LPC11U1*")||cpuis("LPC11U2?/301") bitfld.long 0x04 31. " ENA[31] ,Enable PIO1_31 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 29. " [29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 29. " ENA[29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" endif bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" newline sif cpuis("LPC11U??FET48*") bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled" endif else sif !cpuis("LPC11U??FH?33*") bitfld.long 0x04 29. " ENA[29] ,Enable PIO1_29 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 28. " [28] ,Enable PIO1_28 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 27. " [27] ,Enable PIO1_27 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 26. " [26] ,Enable PIO1_26 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 25. " [25] ,Enable PIO1_25 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 24. " [24] ,Enable PIO1_24 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 23. " [23] ,Enable PIO1_23 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 22. " [22] ,Enable PIO1_22 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 21. " [21] ,Enable PIO1_21 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 20. " [20] ,Enable PIO1_20 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 19. " [19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 18. " [18] ,Enable PIO1_18 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 17. " [17] ,Enable PIO1_17 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 16. " [16] ,Enable PIO1_16 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 14. " [14] ,Enable PIO1_14 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 13. " [13] ,Enable PIO1_13 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 12. " [12] ,Enable PIO1_12 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 11. " [11] ,Enable PIO1_11 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 10. " [10] ,Enable PIO1_10 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 9. " [9] ,Enable PIO1_9 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 8. " [8] ,Enable PIO1_8 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 7. " [7] ,Enable PIO1_7 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 6. " [6] ,Enable PIO1_6 for group interrupt" "Disabled,Enabled" newline bitfld.long 0x04 5. " [5] ,Enable PIO1_5 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 4. " [4] ,Enable PIO1_4 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 3. " [3] ,Enable PIO1_3for group interrupt" "Disabled,Enabled" bitfld.long 0x04 2. " [2] ,Enable PIO1_2 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 1. " [1] ,Enable PIO1_1 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 0. " [0] ,Enable PIO1_0 for group interrupt" "Disabled,Enabled" else bitfld.long 0x04 19. " ENA[19] ,Enable PIO1_19 for group interrupt" "Disabled,Enabled" bitfld.long 0x04 15. " [15] ,Enable PIO1_15 for group interrupt" "Disabled,Enabled" endif endif width 0x0B endif tree.end tree.end tree "PINT (Pin Interrupt And Pattern Match)" sif cpuis("LPC11U6?JBD*") base ad:0xA0004000 width 14. group.long 0x00++0x03 line.long 0x00 "ISEL,Pin Interrupt Mode Register" bitfld.long 0x00 7. " PMODE[7] ,Interrupt mode for pin 7" "Edge,Level" bitfld.long 0x00 6. " [6] ,Interrupt mode for pin 6" "Edge,Level" bitfld.long 0x00 5. " [5] ,Interrupt mode for pin 5" "Edge,Level" bitfld.long 0x00 4. " [4] ,Interrupt mode for pin 4" "Edge,Level" textline " " bitfld.long 0x00 3. " [3] ,Interrupt mode for pin 3" "Edge,Level" bitfld.long 0x00 2. " [2] ,Interrupt mode for pin 2" "Edge,Level" bitfld.long 0x00 1. " [1] ,Interrupt mode for pin 1" "Edge,Level" bitfld.long 0x00 0. " [0] ,Interrupt mode for pin 0" "Edge,Level" group.long 0x04++0x03 line.long 0x00 "IENR_SET/CLR,Pin Interrupt Level Or Rising Edge Interrupt Enable Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENRL[7] ,Interrupt for pin 7 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Interrupt for pin 6 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Interrupt for pin 5 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Interrupt for pin 4 enable level/rising" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Interrupt for pin 3 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Interrupt for pin 2 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Interrupt for pin 1 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Interrupt for pin 0 enable level/rising" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "IENF_SET/CLR,Pin Interrupt Active Level Or Falling Edge Interrupt Enable Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENAF[7] ,Interrupt for pin 7 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Interrupt for pin 6 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Interrupt for pin 5 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Interrupt for pin 4 enable falling/level" "Disabled/LOW,Enabled/HIGH" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Interrupt for pin 3 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Interrupt for pin 2 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Interrupt for pin 1 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Interrupt for pin 0 enable falling/level" "Disabled/LOW,Enabled/HIGH" group.long 0x1C++0x17 line.long 0x00 "RISE,Pin Interrupt Rising Edge Register" eventfld.long 0x00 7. " RDET[7] ,Rising edge detect for pin 7" "No effect,Cleared" eventfld.long 0x00 6. " [6] ,Rising edge detect for pin 6" "No effect,Cleared" eventfld.long 0x00 5. " [5] ,Rising edge detect for pin 5" "No effect,Cleared" eventfld.long 0x00 4. " [4] ,Rising edge detect for pin 4" "No effect,Cleared" textline " " eventfld.long 0x00 3. " [3] ,Rising edge detect for pin 3" "No effect,Cleared" eventfld.long 0x00 2. " [2] ,Rising edge detect for pin 2" "No effect,Cleared" eventfld.long 0x00 1. " [1] ,Rising edge detect for pin 1" "No effect,Cleared" eventfld.long 0x00 0. " [0] ,Rising edge detect for pin 0" "No effect,Cleared" line.long 0x04 "FALL,Pin Interrupt Falling Edge Register" eventfld.long 0x04 7. " FDET[7] ,Falling edge detect for pin 7" "No effect,Cleared" eventfld.long 0x04 6. " [6] ,Falling edge detect for pin 6" "No effect,Cleared" eventfld.long 0x04 5. " [5] ,Falling edge detect for pin 5" "No effect,Cleared" eventfld.long 0x04 4. " [4] ,Falling edge detect for pin 4" "No effect,Cleared" textline " " eventfld.long 0x04 3. " [3] ,Falling edge detect for pin 3" "No effect,Cleared" eventfld.long 0x04 2. " [2] ,Falling edge detect for pin 2" "No effect,Cleared" eventfld.long 0x04 1. " [1] ,Falling edge detect for pin 1" "No effect,Cleared" eventfld.long 0x04 0. " [0] ,Falling edge detect for pin 0" "No effect,Cleared" line.long 0x08 "IST,Pin Interrupt Status Register" eventfld.long 0x08 7. " PSTAT[7] ,Pin interrupt status for pin 7" "No effect,Cleared" eventfld.long 0x08 6. " [6] ,Pin interrupt status for pin 6" "No effect,Cleared" eventfld.long 0x08 5. " [5] ,Pin interrupt status for pin 5" "No effect,Cleared" eventfld.long 0x08 4. " [4] ,Pin interrupt status for pin 4" "No effect,Cleared" textline " " eventfld.long 0x08 3. " [3] ,Pin interrupt status for pin 3" "No effect,Cleared" eventfld.long 0x08 2. " [2] ,Pin interrupt status for pin 2" "No effect,Cleared" eventfld.long 0x08 1. " [1] ,Pin interrupt status for pin 1" "No effect,Cleared" eventfld.long 0x08 0. " [0] ,Pin interrupt status for pin 0" "No effect,Cleared" newline sif !cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*") group.long 0x28++0x0B line.long 0x00 "PMCTRL,Pattern Match Interrupt Control Register" hexmask.long.byte 0x00 24.--31. 1. " PMAT ,This field displays the current state of pattern matches" bitfld.long 0x00 1. " ENA_RXEV ,Enables the RXEV output to the ARM cpu and/or to a GPIO output under conditions" "Disabled,Enabled" bitfld.long 0x00 0. " SEL_PMATCH ,Specifies 8 pin interrupts function" "Pin,Pattern" newline line.long 0x04 "PMSRC,Pattern Match Interrupt Bit-Slice Source Register" bitfld.long 0x04 29.--31. " SRC[7] ,Selects the input source for bit slice 7" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 26.--28. " [6] ,Selects the input source for bit slice 6" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 23.--25. " [5] ,Selects the input source for bit slice 5" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 20.--22. " [4] ,Selects the input source for bit slice 4" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" textline " " bitfld.long 0x04 17.--19. " [3] ,Selects the input source for bit slice 3" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 14.--16. " [2] ,Selects the input source for bit slice 2" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 11.--13. " [1] ,Selects the input source for bit slice 1" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 8.--10. " [0] ,Selects the input source for bit slice 0" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" line.long 0x08 "PMCFG,Pattern Match Interrupt Bit Slice Configuration Register" bitfld.long 0x08 29.--31. " CFG[7] ,Specifies the match contribution condition for bit slice 7" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 26.--28. " [6] ,Specifies the match contribution condition for bit slice 6" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 23.--25. " [5] ,Specifies the match contribution condition for bit slice 5" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 20.--22. " [4] ,Specifies the match contribution condition for bit slice 4" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" textline " " bitfld.long 0x08 17.--19. " [3] ,Specifies the match contribution condition for bit slice 3" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 14.--16. " [2] ,Specifies the match contribution condition for bit slice 2" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 11.--13. " [1] ,Specifies the match contribution condition for bit slice 1" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 8.--10. " [0] ,Specifies the match contribution condition for bit slice 0" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" textline " " bitfld.long 0x08 6. " PROD_ENDPTS[6] ,Determines whether slice 6 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 5. " [5] ,Determines whether slice 5 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 4. " [4] ,Determines whether slice 4 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 3. " [3] ,Determines whether slice 3 is an endpoint" "Not endpoint,Endpoint" textline " " bitfld.long 0x08 2. " [2] ,Determines whether slice 2 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 1. " [1] ,Determines whether slice 1 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 0. " [0] ,Determines whether slice 0 is an endpoint" "Not endpoint,Endpoint" endif width 0x0B else base ad:0x4004C000 width 14. group.long 0x00++0x03 line.long 0x00 "ISEL,Pin Interrupt Mode Register" bitfld.long 0x00 7. " PMODE[7] ,Interrupt mode for pin 7" "Edge,Level" bitfld.long 0x00 6. " [6] ,Interrupt mode for pin 6" "Edge,Level" bitfld.long 0x00 5. " [5] ,Interrupt mode for pin 5" "Edge,Level" bitfld.long 0x00 4. " [4] ,Interrupt mode for pin 4" "Edge,Level" textline " " bitfld.long 0x00 3. " [3] ,Interrupt mode for pin 3" "Edge,Level" bitfld.long 0x00 2. " [2] ,Interrupt mode for pin 2" "Edge,Level" bitfld.long 0x00 1. " [1] ,Interrupt mode for pin 1" "Edge,Level" bitfld.long 0x00 0. " [0] ,Interrupt mode for pin 0" "Edge,Level" group.long 0x04++0x03 line.long 0x00 "IENR_SET/CLR,Pin Interrupt Level Or Rising Edge Interrupt Enable Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENRL[7] ,Interrupt for pin 7 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Interrupt for pin 6 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Interrupt for pin 5 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Interrupt for pin 4 enable level/rising" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Interrupt for pin 3 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Interrupt for pin 2 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Interrupt for pin 1 enable level/rising" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Interrupt for pin 0 enable level/rising" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "IENF_SET/CLR,Pin Interrupt Active Level Or Falling Edge Interrupt Enable Set/Clear Register" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ENAF[7] ,Interrupt for pin 7 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,Interrupt for pin 6 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,Interrupt for pin 5 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,Interrupt for pin 4 enable falling/level" "Disabled/LOW,Enabled/HIGH" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,Interrupt for pin 3 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Interrupt for pin 2 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Interrupt for pin 1 enable falling/level" "Disabled/LOW,Enabled/HIGH" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Interrupt for pin 0 enable falling/level" "Disabled/LOW,Enabled/HIGH" group.long 0x1C++0x17 line.long 0x00 "RISE,Pin Interrupt Rising Edge Register" eventfld.long 0x00 7. " RDET[7] ,Rising edge detect for pin 7" "No effect,Cleared" eventfld.long 0x00 6. " [6] ,Rising edge detect for pin 6" "No effect,Cleared" eventfld.long 0x00 5. " [5] ,Rising edge detect for pin 5" "No effect,Cleared" eventfld.long 0x00 4. " [4] ,Rising edge detect for pin 4" "No effect,Cleared" textline " " eventfld.long 0x00 3. " [3] ,Rising edge detect for pin 3" "No effect,Cleared" eventfld.long 0x00 2. " [2] ,Rising edge detect for pin 2" "No effect,Cleared" eventfld.long 0x00 1. " [1] ,Rising edge detect for pin 1" "No effect,Cleared" eventfld.long 0x00 0. " [0] ,Rising edge detect for pin 0" "No effect,Cleared" line.long 0x04 "FALL,Pin Interrupt Falling Edge Register" eventfld.long 0x04 7. " FDET[7] ,Falling edge detect for pin 7" "No effect,Cleared" eventfld.long 0x04 6. " [6] ,Falling edge detect for pin 6" "No effect,Cleared" eventfld.long 0x04 5. " [5] ,Falling edge detect for pin 5" "No effect,Cleared" eventfld.long 0x04 4. " [4] ,Falling edge detect for pin 4" "No effect,Cleared" textline " " eventfld.long 0x04 3. " [3] ,Falling edge detect for pin 3" "No effect,Cleared" eventfld.long 0x04 2. " [2] ,Falling edge detect for pin 2" "No effect,Cleared" eventfld.long 0x04 1. " [1] ,Falling edge detect for pin 1" "No effect,Cleared" eventfld.long 0x04 0. " [0] ,Falling edge detect for pin 0" "No effect,Cleared" line.long 0x08 "IST,Pin Interrupt Status Register" eventfld.long 0x08 7. " PSTAT[7] ,Pin interrupt status for pin 7" "No effect,Cleared" eventfld.long 0x08 6. " [6] ,Pin interrupt status for pin 6" "No effect,Cleared" eventfld.long 0x08 5. " [5] ,Pin interrupt status for pin 5" "No effect,Cleared" eventfld.long 0x08 4. " [4] ,Pin interrupt status for pin 4" "No effect,Cleared" textline " " eventfld.long 0x08 3. " [3] ,Pin interrupt status for pin 3" "No effect,Cleared" eventfld.long 0x08 2. " [2] ,Pin interrupt status for pin 2" "No effect,Cleared" eventfld.long 0x08 1. " [1] ,Pin interrupt status for pin 1" "No effect,Cleared" eventfld.long 0x08 0. " [0] ,Pin interrupt status for pin 0" "No effect,Cleared" newline sif !cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*") group.long 0x28++0x0B line.long 0x00 "PMCTRL,Pattern Match Interrupt Control Register" hexmask.long.byte 0x00 24.--31. 1. " PMAT ,This field displays the current state of pattern matches" bitfld.long 0x00 1. " ENA_RXEV ,Enables the RXEV output to the ARM cpu and/or to a GPIO output under conditions" "Disabled,Enabled" bitfld.long 0x00 0. " SEL_PMATCH ,Specifies 8 pin interrupts function" "Pin,Pattern" newline line.long 0x04 "PMSRC,Pattern Match Interrupt Bit-Slice Source Register" bitfld.long 0x04 29.--31. " SRC[7] ,Selects the input source for bit slice 7" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 26.--28. " [6] ,Selects the input source for bit slice 6" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 23.--25. " [5] ,Selects the input source for bit slice 5" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 20.--22. " [4] ,Selects the input source for bit slice 4" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" textline " " bitfld.long 0x04 17.--19. " [3] ,Selects the input source for bit slice 3" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 14.--16. " [2] ,Selects the input source for bit slice 2" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 11.--13. " [1] ,Selects the input source for bit slice 1" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" bitfld.long 0x04 8.--10. " [0] ,Selects the input source for bit slice 0" "PINTSEL0,PINTSEL1,PINTSEL2,PINTSEL3,PINTSEL4,PINTSEL5,PINTSEL6,PINTSEL7" line.long 0x08 "PMCFG,Pattern Match Interrupt Bit Slice Configuration Register" bitfld.long 0x08 29.--31. " CFG[7] ,Specifies the match contribution condition for bit slice 7" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 26.--28. " [6] ,Specifies the match contribution condition for bit slice 6" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 23.--25. " [5] ,Specifies the match contribution condition for bit slice 5" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 20.--22. " [4] ,Specifies the match contribution condition for bit slice 4" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" textline " " bitfld.long 0x08 17.--19. " [3] ,Specifies the match contribution condition for bit slice 3" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 14.--16. " [2] ,Specifies the match contribution condition for bit slice 2" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 11.--13. " [1] ,Specifies the match contribution condition for bit slice 1" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" bitfld.long 0x08 8.--10. " [0] ,Specifies the match contribution condition for bit slice 0" "Const HIGH,Sticky rising,Sticky falling,Sticky rising/falling,High,Low,Const 0,Event" textline " " bitfld.long 0x08 6. " PROD_ENDPTS[6] ,Determines whether slice 6 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 5. " [5] ,Determines whether slice 5 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 4. " [4] ,Determines whether slice 4 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 3. " [3] ,Determines whether slice 3 is an endpoint" "Not endpoint,Endpoint" textline " " bitfld.long 0x08 2. " [2] ,Determines whether slice 2 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 1. " [1] ,Determines whether slice 1 is an endpoint" "Not endpoint,Endpoint" bitfld.long 0x08 0. " [0] ,Determines whether slice 0 is an endpoint" "Not endpoint,Endpoint" endif width 0x0B endif tree.end tree.end sif cpuis("LPC11U6?JBD*") tree "DMAC (DMA Controller)" base ad:0x50004000 width 16. group.long 0x00++0x03 "Global Control And Status Registers" line.long 0x00 "CTRL,DMA Control Register" bitfld.long 0x00 0. " ENABLE ,DMA controller master enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 2. " ACTIVEERRINT ,Error interrupts pending status" "Not pending,Pending" bitfld.long 0x00 1. " ACTIVEINT ,Enabled interrupts pending status" "Not pending,Pending" group.long 0x08++0x03 line.long 0x00 "SRAMBASE,SRAM Base Address Register" hexmask.long.tbyte 0x00 8.--31. 0x01 " OFFSET ,Address bits 31:8 of the beginning of the DMA descriptor table" newline group.long 0x20++0x03 "Shared Registers" line.long 0x00 "ENABLESET/CLR0,Channel Enable Set/Clear Read Register 0" setclrfld.long 0x00 15. 0x00 15. 0x08 15. " ENA[15]_set/clr ,Enable for DMA channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14]_set/clr ,Enable for DMA channel 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13]_set/clr ,Enable for DMA channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12]_set/clr ,Enable for DMA channel 12" "Disabled,Enabled" newline setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11]_set/clr ,Enable for DMA channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10]_set/clr ,Enable for DMA channel 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9]_set/clr ,Enable for DMA channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8]_set/clr ,Enable for DMA channel 8" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7]_set/clr ,Enable for DMA channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6]_set/clr ,Enable for DMA channel 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5]_set/clr ,Enable for DMA channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4]_set/clr ,Enable for DMA channel 4" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3]_set/clr ,Enable for DMA channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2]_set/clr ,Enable for DMA channel 2" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1]_set/clr ,Enable for DMA channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0]_set/clr ,Enable for DMA channel 0" "Disabled,Enabled" newline rgroup.long 0x30++0x03 line.long 0x00 "ACTIVE0,Active Status Register 0" bitfld.long 0x00 15. " ACT[15] ,Active flag for DMA channel 15" "Not active,Active" bitfld.long 0x00 14. " [14] ,Active flag for DMA channel 14" "Not active,Active" bitfld.long 0x00 13. " [13] ,Active flag for DMA channel 13" "Not active,Active" bitfld.long 0x00 12. " [12] ,Active flag for DMA channel 12" "Not active,Active" bitfld.long 0x00 11. " [11] ,Active flag for DMA channel 11" "Not active,Active" bitfld.long 0x00 10. " [10] ,Active flag for DMA channel 10" "Not active,Active" newline bitfld.long 0x00 9. " [9] ,Active flag for DMA channel 9" "Not active,Active" bitfld.long 0x00 8. " [8] ,Active flag for DMA channel 8" "Not active,Active" bitfld.long 0x00 7. " [7] ,Active flag for DMA channel 7" "Not active,Active" bitfld.long 0x00 6. " [6] ,Active flag for DMA channel 6" "Not active,Active" bitfld.long 0x00 5. " [5] ,Active flag for DMA channel 5" "Not active,Active" bitfld.long 0x00 4. " [4] ,Active flag for DMA channel 4" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,Active flag for DMA channel 3" "Not active,Active" bitfld.long 0x00 2. " [2] ,Active flag for DMA channel 2" "Not active,Active" bitfld.long 0x00 1. " [1] ,Active flag for DMA channel 1" "Not active,Active" bitfld.long 0x00 0. " [0] ,Active flag for DMA channel 0" "Not active,Active" rgroup.long 0x38++0x03 line.long 0x00 "BUSY0,Busy Status Register 0" bitfld.long 0x00 15. " BSY[15] ,Busy flag for DMA channel 15" "Not busy,Busy" bitfld.long 0x00 14. " [14] ,Busy flag for DMA channel 14" "Not busy,Busy" bitfld.long 0x00 13. " [13] ,Busy flag for DMA channel 13" "Not busy,Busy" bitfld.long 0x00 12. " [12] ,Busy flag for DMA channel 12" "Not busy,Busy" bitfld.long 0x00 11. " [11] ,Busy flag for DMA channel 11" "Not busy,Busy" bitfld.long 0x00 10. " [10] ,Busy flag for DMA channel 10" "Not busy,Busy" newline bitfld.long 0x00 9. " [9] ,Busy flag for DMA channel 9" "Not busy,Busy" bitfld.long 0x00 8. " [8] ,Busy flag for DMA channel 8" "Not busy,Busy" bitfld.long 0x00 7. " [7] ,Busy flag for DMA channel 7" "Not busy,Busy" bitfld.long 0x00 6. " [6] ,Busy flag for DMA channel 6" "Not busy,Busy" bitfld.long 0x00 5. " [5] ,Busy flag for DMA channel 5" "Not busy,Busy" bitfld.long 0x00 4. " [4] ,Busy flag for DMA channel 4" "Not busy,Busy" newline bitfld.long 0x00 3. " [3] ,Busy flag for DMA channel 3" "Not busy,Busy" bitfld.long 0x00 2. " [2] ,Busy flag for DMA channel 2" "Not busy,Busy" bitfld.long 0x00 1. " [1] ,Busy flag for DMA channel 1" "Not busy,Busy" bitfld.long 0x00 0. " [0] ,Busy flag for DMA channel 0" "Not busy,Busy" group.long 0x40++0x03 line.long 0x00 "ERRINT0,Error Interrupt Register 0" bitfld.long 0x00 15. " ERR[15] ,Error Interrupt flag for DMA channel 15" "Not active,Active" bitfld.long 0x00 14. " [14] ,Error Interrupt flag for DMA channel 14" "Not active,Active" bitfld.long 0x00 13. " [13] ,Error Interrupt flag for DMA channel 13" "Not active,Active" bitfld.long 0x00 12. " [12] ,Error Interrupt flag for DMA channel 12" "Not active,Active" bitfld.long 0x00 11. " [11] ,Error Interrupt flag for DMA channel 11" "Not active,Active" bitfld.long 0x00 10. " [10] ,Error Interrupt flag for DMA channel 10" "Not active,Active" newline bitfld.long 0x00 9. " [9] ,Error Interrupt flag for DMA channel 9" "Not active,Active" bitfld.long 0x00 8. " [8] ,Error Interrupt flag for DMA channel 8" "Not active,Active" bitfld.long 0x00 7. " [7] ,Error Interrupt flag for DMA channel 7" "Not active,Active" bitfld.long 0x00 6. " [6] ,Error Interrupt flag for DMA channel 6" "Not active,Active" bitfld.long 0x00 5. " [5] ,Error Interrupt flag for DMA channel 5" "Not active,Active" bitfld.long 0x00 4. " [4] ,Error Interrupt flag for DMA channel 4" "Not active,Active" newline bitfld.long 0x00 3. " [3] ,Error Interrupt flag for DMA channel 3" "Not active,Active" bitfld.long 0x00 2. " [2] ,Error Interrupt flag for DMA channel 2" "Not active,Active" bitfld.long 0x00 1. " [1] ,Error Interrupt flag for DMA channel 1" "Not active,Active" bitfld.long 0x00 0. " [0] ,Error Interrupt flag for DMA channel 0" "Not active,Active" group.long 0x48++0x03 line.long 0x00 "INTENSET/CLR0,Interrupt Enable Set/Clear Read Register 0" setclrfld.long 0x00 15. 0x00 15. 0x08 15. " INTEN[15] ,Interrupt Enable for DMA channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,Interrupt Enable for DMA channel 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,Interrupt Enable for DMA channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,Interrupt Enable for DMA channel 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,Interrupt Enable for DMA channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,Interrupt Enable for DMA channel 10" "Disabled,Enabled" newline setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,Interrupt Enable for DMA channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,Interrupt Enable for DMA channel 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,Interrupt Enable for DMA channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,Interrupt Enable for DMA channel 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,Interrupt Enable for DMA channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,Interrupt Enable for DMA channel 4" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,Interrupt Enable for DMA channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,Interrupt Enable for DMA channel 2" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,Interrupt Enable for DMA channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,Interrupt Enable for DMA channel 0" "Disabled,Enabled" group.long 0x58++0x03 line.long 0x00 "INTA0,Interrupt A Register 0" bitfld.long 0x00 15. " IA[15] ,Interrupt A status for DMA channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Interrupt A status for DMA channel 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Interrupt A status for DMA channel 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Interrupt A status for DMA channel 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " [11] ,Interrupt A status for DMA channel 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Interrupt A status for DMA channel 10" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " [9] ,Interrupt A status for DMA channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Interrupt A status for DMA channel 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Interrupt A status for DMA channel 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Interrupt A status for DMA channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Interrupt A status for DMA channel 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Interrupt A status for DMA channel 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Interrupt A status for DMA channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Interrupt A status for DMA channel 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Interrupt A status for DMA channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Interrupt A status for DMA channel 0" "No interrupt,Interrupt" group.long 0x60++0x03 line.long 0x00 "INTB0,Interrupt B Register 0" bitfld.long 0x00 15. " IB[15] ,Interrupt B status for DMA channel 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Interrupt B status for DMA channel 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Interrupt B status for DMA channel 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Interrupt B status for DMA channel 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " [11] ,Interrupt B status for DMA channel 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Interrupt B status for DMA channel 10" "No interrupt,Interrupt" newline bitfld.long 0x00 9. " [9] ,Interrupt B status for DMA channel 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Interrupt B status for DMA channel 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Interrupt B status for DMA channel 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Interrupt B status for DMA channel 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Interrupt B status for DMA channel 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Interrupt B status for DMA channel 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. " [3] ,Interrupt B status for DMA channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Interrupt B status for DMA channel 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Interrupt B status for DMA channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Interrupt B status for DMA channel 0" "No interrupt,Interrupt" wgroup.long 0x68++0x03 line.long 0x00 "SETVALID0,Set Valid 0 Register" bitfld.long 0x00 15. " SV[15] ,SETVALID control for DMA channel 15" "No effect,Set" bitfld.long 0x00 14. " [14] ,SETVALID control for DMA channel 14" "No effect,Set" bitfld.long 0x00 13. " [13] ,SETVALID control for DMA channel 13" "No effect,Set" bitfld.long 0x00 12. " [12] ,SETVALID control for DMA channel 12" "No effect,Set" bitfld.long 0x00 11. " [11] ,SETVALID control for DMA channel 11" "No effect,Set" bitfld.long 0x00 10. " [10] ,SETVALID control for DMA channel 10" "No effect,Set" newline bitfld.long 0x00 9. " [9] ,SETVALID control for DMA channel 9" "No effect,Set" bitfld.long 0x00 8. " [8] ,SETVALID control for DMA channel 8" "No effect,Set" bitfld.long 0x00 7. " [7] ,SETVALID control for DMA channel 7" "No effect,Set" bitfld.long 0x00 6. " [6] ,SETVALID control for DMA channel 6" "No effect,Set" bitfld.long 0x00 5. " [5] ,SETVALID control for DMA channel 5" "No effect,Set" bitfld.long 0x00 4. " [4] ,SETVALID control for DMA channel 4" "No effect,Set" newline bitfld.long 0x00 3. " [3] ,SETVALID control for DMA channel 3" "No effect,Set" bitfld.long 0x00 2. " [2] ,SETVALID control for DMA channel 2" "No effect,Set" bitfld.long 0x00 1. " [1] ,SETVALID control for DMA channel 1" "No effect,Set" bitfld.long 0x00 0. " [0] ,SETVALID control for DMA channel 0" "No effect,Set" wgroup.long 0x70++0x03 line.long 0x00 "SETTRIG0,Set Trigger 0 Register" bitfld.long 0x00 15. " TRIG[15] ,Set Trigger control bit for DMA channel 15" "No effect,Set" bitfld.long 0x00 14. " [14] ,Set Trigger control bit for DMA channel 14" "No effect,Set" bitfld.long 0x00 13. " [13] ,Set Trigger control bit for DMA channel 13" "No effect,Set" bitfld.long 0x00 12. " [12] ,Set Trigger control bit for DMA channel 12" "No effect,Set" bitfld.long 0x00 11. " [11] ,Set Trigger control bit for DMA channel 11" "No effect,Set" bitfld.long 0x00 10. " [10] ,Set Trigger control bit for DMA channel 10" "No effect,Set" newline bitfld.long 0x00 9. " [9] ,Set Trigger control bit for DMA channel 9" "No effect,Set" bitfld.long 0x00 8. " [8] ,Set Trigger control bit for DMA channel 8" "No effect,Set" bitfld.long 0x00 7. " [7] ,Set Trigger control bit for DMA channel 7" "No effect,Set" bitfld.long 0x00 6. " [6] ,Set Trigger control bit for DMA channel 6" "No effect,Set" bitfld.long 0x00 5. " [5] ,Set Trigger control bit for DMA channel 5" "No effect,Set" bitfld.long 0x00 4. " [4] ,Set Trigger control bit for DMA channel 4" "No effect,Set" newline bitfld.long 0x00 3. " [3] ,Set Trigger control bit for DMA channel 3" "No effect,Set" bitfld.long 0x00 2. " [2] ,Set Trigger control bit for DMA channel 2" "No effect,Set" bitfld.long 0x00 1. " [1] ,Set Trigger control bit for DMA channel 1" "No effect,Set" bitfld.long 0x00 0. " [0] ,Set Trigger control bit for DMA channel 0" "No effect,Set" wgroup.long 0x78++0x03 line.long 0x00 "SETABORT0,Abort 0 Register" bitfld.long 0x00 15. " ABORTCTRL[15] ,Abort control for DMA channel 15" "No effect,Abort" bitfld.long 0x00 14. " [14] ,Abort control for DMA channel 14" "No effect,Abort" bitfld.long 0x00 13. " [13] ,Abort control for DMA channel 13" "No effect,Abort" bitfld.long 0x00 12. " [12] ,Abort control for DMA channel 12" "No effect,Abort" bitfld.long 0x00 11. " [11] ,Abort control for DMA channel 11" "No effect,Abort" bitfld.long 0x00 10. " [10] ,Abort control for DMA channel 10" "No effect,Abort" newline bitfld.long 0x00 9. " [9] ,Abort control for DMA channel 9" "No effect,Abort" bitfld.long 0x00 8. " [8] ,Abort control for DMA channel 8" "No effect,Abort" bitfld.long 0x00 7. " [7] ,Abort control for DMA channel 7" "No effect,Abort" bitfld.long 0x00 6. " [6] ,Abort control for DMA channel 6" "No effect,Abort" bitfld.long 0x00 5. " [5] ,Abort control for DMA channel 5" "No effect,Abort" bitfld.long 0x00 4. " [4] ,Abort control for DMA channel 4" "No effect,Abort" newline bitfld.long 0x00 3. " [3] ,Abort control for DMA channel 3" "No effect,Abort" bitfld.long 0x00 2. " [2] ,Abort control for DMA channel 2" "No effect,Abort" bitfld.long 0x00 1. " [1] ,Abort control for DMA channel 1" "No effect,Abort" bitfld.long 0x00 0. " [0] ,Abort control for DMA channel 0" "No effect,Abort" width 12. tree "Channels registers" if (((per.l(ad:0x50004000+0x400))&(0x20))==(0x00)) group.long 0x400++0x03 line.long 0x00 "CFG0,Configuration Register For Channel 0" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x400++0x03 line.long 0x00 "CFG0,Configuration Register For Channel 0" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x400+0x04)++0x03 line.long 0x00 "CTLSTAT0,Control And Status Register For Channel 0" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x400+0x08)++0x03 line.long 0x00 "XFERCFG0,Transfer Configuration Register For Channel 0" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x410))&(0x20))==(0x00)) group.long 0x410++0x03 line.long 0x00 "CFG1,Configuration Register For Channel 1" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x410++0x03 line.long 0x00 "CFG1,Configuration Register For Channel 1" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x410+0x04)++0x03 line.long 0x00 "CTLSTAT1,Control And Status Register For Channel 1" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x410+0x08)++0x03 line.long 0x00 "XFERCFG1,Transfer Configuration Register For Channel 1" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x420))&(0x20))==(0x00)) group.long 0x420++0x03 line.long 0x00 "CFG2,Configuration Register For Channel 2" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x420++0x03 line.long 0x00 "CFG2,Configuration Register For Channel 2" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x420+0x04)++0x03 line.long 0x00 "CTLSTAT2,Control And Status Register For Channel 2" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x420+0x08)++0x03 line.long 0x00 "XFERCFG2,Transfer Configuration Register For Channel 2" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x430))&(0x20))==(0x00)) group.long 0x430++0x03 line.long 0x00 "CFG3,Configuration Register For Channel 3" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x430++0x03 line.long 0x00 "CFG3,Configuration Register For Channel 3" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x430+0x04)++0x03 line.long 0x00 "CTLSTAT3,Control And Status Register For Channel 3" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x430+0x08)++0x03 line.long 0x00 "XFERCFG3,Transfer Configuration Register For Channel 3" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x440))&(0x20))==(0x00)) group.long 0x440++0x03 line.long 0x00 "CFG4,Configuration Register For Channel 4" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x440++0x03 line.long 0x00 "CFG4,Configuration Register For Channel 4" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x440+0x04)++0x03 line.long 0x00 "CTLSTAT4,Control And Status Register For Channel 4" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x440+0x08)++0x03 line.long 0x00 "XFERCFG4,Transfer Configuration Register For Channel 4" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x450))&(0x20))==(0x00)) group.long 0x450++0x03 line.long 0x00 "CFG5,Configuration Register For Channel 5" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x450++0x03 line.long 0x00 "CFG5,Configuration Register For Channel 5" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x450+0x04)++0x03 line.long 0x00 "CTLSTAT5,Control And Status Register For Channel 5" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x450+0x08)++0x03 line.long 0x00 "XFERCFG5,Transfer Configuration Register For Channel 5" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x460))&(0x20))==(0x00)) group.long 0x460++0x03 line.long 0x00 "CFG6,Configuration Register For Channel 6" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x460++0x03 line.long 0x00 "CFG6,Configuration Register For Channel 6" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x460+0x04)++0x03 line.long 0x00 "CTLSTAT6,Control And Status Register For Channel 6" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x460+0x08)++0x03 line.long 0x00 "XFERCFG6,Transfer Configuration Register For Channel 6" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x470))&(0x20))==(0x00)) group.long 0x470++0x03 line.long 0x00 "CFG7,Configuration Register For Channel 7" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x470++0x03 line.long 0x00 "CFG7,Configuration Register For Channel 7" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x470+0x04)++0x03 line.long 0x00 "CTLSTAT7,Control And Status Register For Channel 7" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x470+0x08)++0x03 line.long 0x00 "XFERCFG7,Transfer Configuration Register For Channel 7" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x480))&(0x20))==(0x00)) group.long 0x480++0x03 line.long 0x00 "CFG8,Configuration Register For Channel 8" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x480++0x03 line.long 0x00 "CFG8,Configuration Register For Channel 8" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x480+0x04)++0x03 line.long 0x00 "CTLSTAT8,Control And Status Register For Channel 8" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x480+0x08)++0x03 line.long 0x00 "XFERCFG8,Transfer Configuration Register For Channel 8" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x490))&(0x20))==(0x00)) group.long 0x490++0x03 line.long 0x00 "CFG9,Configuration Register For Channel 9" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x490++0x03 line.long 0x00 "CFG9,Configuration Register For Channel 9" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x490+0x04)++0x03 line.long 0x00 "CTLSTAT9,Control And Status Register For Channel 9" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x490+0x08)++0x03 line.long 0x00 "XFERCFG9,Transfer Configuration Register For Channel 9" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x4A0))&(0x20))==(0x00)) group.long 0x4A0++0x03 line.long 0x00 "CFG10,Configuration Register For Channel 10" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x4A0++0x03 line.long 0x00 "CFG10,Configuration Register For Channel 10" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x4A0+0x04)++0x03 line.long 0x00 "CTLSTAT10,Control And Status Register For Channel 10" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4A0+0x08)++0x03 line.long 0x00 "XFERCFG10,Transfer Configuration Register For Channel 10" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x4B0))&(0x20))==(0x00)) group.long 0x4B0++0x03 line.long 0x00 "CFG11,Configuration Register For Channel 11" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x4B0++0x03 line.long 0x00 "CFG11,Configuration Register For Channel 11" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x4B0+0x04)++0x03 line.long 0x00 "CTLSTAT11,Control And Status Register For Channel 11" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4B0+0x08)++0x03 line.long 0x00 "XFERCFG11,Transfer Configuration Register For Channel 11" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x4C0))&(0x20))==(0x00)) group.long 0x4C0++0x03 line.long 0x00 "CFG12,Configuration Register For Channel 12" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x4C0++0x03 line.long 0x00 "CFG12,Configuration Register For Channel 12" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x4C0+0x04)++0x03 line.long 0x00 "CTLSTAT12,Control And Status Register For Channel 12" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4C0+0x08)++0x03 line.long 0x00 "XFERCFG12,Transfer Configuration Register For Channel 12" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x4D0))&(0x20))==(0x00)) group.long 0x4D0++0x03 line.long 0x00 "CFG13,Configuration Register For Channel 13" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x4D0++0x03 line.long 0x00 "CFG13,Configuration Register For Channel 13" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x4D0+0x04)++0x03 line.long 0x00 "CTLSTAT13,Control And Status Register For Channel 13" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4D0+0x08)++0x03 line.long 0x00 "XFERCFG13,Transfer Configuration Register For Channel 13" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x4E0))&(0x20))==(0x00)) group.long 0x4E0++0x03 line.long 0x00 "CFG14,Configuration Register For Channel 14" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x4E0++0x03 line.long 0x00 "CFG14,Configuration Register For Channel 14" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x4E0+0x04)++0x03 line.long 0x00 "CTLSTAT14,Control And Status Register For Channel 14" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4E0+0x08)++0x03 line.long 0x00 "XFERCFG14,Transfer Configuration Register For Channel 14" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" if (((per.l(ad:0x50004000+0x4F0))&(0x20))==(0x00)) group.long 0x4F0++0x03 line.long 0x00 "CFG15,Configuration Register For Channel 15" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Falling,Rising" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" else group.long 0x4F0++0x03 line.long 0x00 "CFG15,Configuration Register For Channel 15" bitfld.long 0x00 16.--17. " CHPRIORITY ,Priority of this channel when multiple DMA requests are pending" "0,1,2,3" bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BURSTPOWER ,Burst power" "1,2,4,8,16,32,64,128,256,512,1024,?..." newline bitfld.long 0x00 6. " TRIGBURST ,Trigger burst transfer" "Single,Burst" bitfld.long 0x00 5. " TRIGTYPE ,Trigger type" "Edge,Level" bitfld.long 0x00 4. " TRIGPOL ,Trigger polarity" "Low active,High active" bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled" newline bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled" endif rgroup.long (0x4F0+0x04)++0x03 line.long 0x00 "CTLSTAT15,Control And Status Register For Channel 15" bitfld.long 0x00 2. " TRIG ,Trigger flag" "Not triggered,Triggered" bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel" "No effect,Valid pending" group.long (0x4F0+0x08)++0x03 line.long 0x00 "XFERCFG15,Transfer Configuration Register For Channel 15" hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed minus 1 encoded" bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 12.--13. " SRCINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1x width,2x width,4x width" bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,32-bit,?..." newline bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set" bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set" bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared" bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set" newline bitfld.long 0x00 1. " RELOAD ,Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted" "Disabled,Enabled" bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid" tree.end width 19. base ad:0x400280E0 tree "Configuration Registers" group.long 0x0++0x03 line.long 0x00 "DMA_ITRIG_INMUX0,DMA Trigger Input Mux Register 0" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 0" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x4++0x03 line.long 0x00 "DMA_ITRIG_INMUX1,DMA Trigger Input Mux Register 1" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 1" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x8++0x03 line.long 0x00 "DMA_ITRIG_INMUX2,DMA Trigger Input Mux Register 2" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 2" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0xC++0x03 line.long 0x00 "DMA_ITRIG_INMUX3,DMA Trigger Input Mux Register 3" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 3" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x10++0x03 line.long 0x00 "DMA_ITRIG_INMUX4,DMA Trigger Input Mux Register 4" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 4" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x14++0x03 line.long 0x00 "DMA_ITRIG_INMUX5,DMA Trigger Input Mux Register 5" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 5" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x18++0x03 line.long 0x00 "DMA_ITRIG_INMUX6,DMA Trigger Input Mux Register 6" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 6" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x1C++0x03 line.long 0x00 "DMA_ITRIG_INMUX7,DMA Trigger Input Mux Register 7" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 7" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x20++0x03 line.long 0x00 "DMA_ITRIG_INMUX8,DMA Trigger Input Mux Register 8" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 8" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x24++0x03 line.long 0x00 "DMA_ITRIG_INMUX9,DMA Trigger Input Mux Register 9" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 9" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x28++0x03 line.long 0x00 "DMA_ITRIG_INMUX10,DMA Trigger Input Mux Register 10" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 10" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x2C++0x03 line.long 0x00 "DMA_ITRIG_INMUX11,DMA Trigger Input Mux Register 11" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 11" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x30++0x03 line.long 0x00 "DMA_ITRIG_INMUX12,DMA Trigger Input Mux Register 12" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 12" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x34++0x03 line.long 0x00 "DMA_ITRIG_INMUX13,DMA Trigger Input Mux Register 13" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 13" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x38++0x03 line.long 0x00 "DMA_ITRIG_INMUX14,DMA Trigger Input Mux Register 14" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 14" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." group.long 0x3C++0x03 line.long 0x00 "DMA_ITRIG_INMUX15,DMA Trigger Input Mux Register 15" bitfld.long 0x00 0.--3. " INP_N ,Trigger input number decimal value to DMA channel 15" "ADC0_SEQA_IRQ,ADC0_SEQB_IRQ,CT16B0_MAT0,CT16B1_MAT0,CT32B0_MAT0,CT32B1_MAT0,PINT0,PINT1,SCT0_DMA0,SCT0_DMA1,SCT1_DMA0,SCT1_DMA1,?..." tree.end width 0x0B tree.end endif tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)" sif cpuis("LPC11U6*") tree "USART0" base ad:0x40008000 width 15. if (((per.l(ad:0x40008000+0x0C))&0x80)==0x00) hgroup.long 0x00++0x03 hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register" in group.long 0x04++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " ABEOINTEN ,End of auto-baud interrupt enable" "Disabled,Enabled" sif cpuis("LPC11D14")||cpuis("LPC11C*") bitfld.long 0x00 2. " RXLIE ,RX line interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " THREIE ,THRE interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RBRIE ,RBR interrupt enable" "Disabled,Enabled" else bitfld.long 0x00 3. " MSINTEN ,Modem status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RLSINTEN ,Receive line status interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " THREINTEN ,THRE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RBRINTEN ,RBR interrupt enable" "Disabled,Enabled" endif else group.long 0x00++0x07 line.long 0x00 "DLL,Divisor Latch LSB" hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,USART divisor latch LSB" line.long 0x04 "DLM,Divisor Latch MSB" hexmask.long.byte 0x04 0.--7. 1. " DLMSB ,USART divisor latch MSB" endif rgroup.long 0x08++0x03 line.long 0x00 "IIR,Interrupt ID" bitfld.long 0x00 9. " ABTOINT ,Auto-baud timeout interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " ABEOINT ,End of auto-baud interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6.--7. " FIFOEN ,FIFO enable" "0,1,2,3" sif cpuis("LPC11C*") bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem interrupt,THRE,RDA,RLS,,,CTI,?..." else bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem status,THRE,RDA,RLS,,,CTI,?..." endif newline bitfld.long 0x00 0. " INTSTATUS ,Interrupt status" "Pending,Not pending" wgroup.long 0x08++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 6.--7. " RXTL ,Rx trigger level select" "Level 0,Level 1,Level 2,Level 3" sif !cpuis("LPC11D14")&&!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11C*") bitfld.long 0x00 3. " DMAMODE ,DMA mode enable" "Disable,Enable" endif newline bitfld.long 0x00 2. " TXFIFORES ,Transmitter FIFO reset" "No effect,Clear" bitfld.long 0x00 1. " RXFIFORES ,Receiver FIFO reset" "No effect,Clear" bitfld.long 0x00 0. " FIFOEN ,FIFO enable" "Disable,Enable" if (((per.l(ad:0x40008000+0x0C))&0x03)==0x00) group.long 0x0C++0x03 line.long 0x00 "LCR,Line Control Register" bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled" bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled" bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0" bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,1.5 bits" bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit" else group.long 0x0C++0x03 line.long 0x00 "LCR,Line Control Register" bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled" bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled" bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0" bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,2 bits" bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit" endif group.long 0x10++0x03 line.long 0x00 "MCR,USART0 Modem Control Register" bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 4. " LMS ,Loopback mode select" "Disabled,Enabled" bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Active,Inactive" newline bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Active,Inactive" hgroup.long 0x14++0x03 hide.long 0x00 "LSR,Line Status Register" in hgroup.long 0x18++0x03 hide.long 0x00 "MSR,Modem Status Register" in group.long 0x1C++0x07 line.long 0x00 "SCR,Scratch Pad Register" hexmask.long.byte 0x00 0.--7. 1. " PAD ,A readable/writable byte" line.long 0x04 "ACR,Auto-Baud Control Register" bitfld.long 0x04 9. " ABTOINTCLR ,Auto-baud timeout interrupt clear bit" "No effect,Cleared" bitfld.long 0x04 8. " ABEOINTCLR ,End of auto-baud interrupt clear bit" "No effect,Cleared" sif cpuis("LPC11C*") bitfld.long 0x04 2. " AUTORESTART ,Automatic restart enable" "Disabled,Enabled" bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1" else bitfld.long 0x04 2. " AUTORESTART ,Start mode" "Not restarted,Restarted" bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1" endif newline bitfld.long 0x04 0. " START ,Auto-baud start" "Stopped,Started" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") group.long 0x24++0x03 line.long 0x00 "ICR,IrDA Control Register" bitfld.long 0x00 3.--5. " PULSEDIV ,Pulse width configure" "3/(16*baud rate),2*Tpclk,4*Tpclk,8*Tpclk,16*Tpclk,32*Tpclk,64*Tpclk,128*Tpclk" bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed pulse width mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " IRDAINV ,Serial input invert" "Not inverted,Inverted" bitfld.long 0x00 0. " IRDAEN ,IrDA mode enable" "Disabled,Enabled" endif group.long 0x28++0x03 line.long 0x00 "FDR,Fractional Divider Register" bitfld.long 0x00 4.--7. " MULVAL ,Baud rate pre-scaler multiplier value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DIVADDVAL ,Baud rate pre-scaler divisor value" ",None,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") if (((per.l(ad:0x40008000+0x48))&0x01)==0x00) group.long 0x2C++0x03 line.long 0x00 "OSR,Oversampling Register" bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875" else group.long 0x2C++0x03 line.long 0x00 "OSR,Oversampling Register" hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field" bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875" endif endif group.long 0x30++0x03 line.long 0x00 "TER,Transmit Enable Register" bitfld.long 0x00 7. " TXEN ,Transmission enable" "Disabled,Enabled" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") group.long 0x40++0x03 line.long 0x00 "HDEN,USART Half-Duplex Enable Register" bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled" if (((per.l(ad:0x40008000+0x48))&0x04)==0x00) group.long 0x48++0x03 line.long 0x00 "SCICTRL,Smart Card Interface Control Register" hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs" bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1" bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes" newline bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "SCICTRL,Smart Card Interface Control Register" hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs" bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1" bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled" endif endif group.long 0x4C++0x0B line.long 0x00 "RS485CTRL,RS485 Control Register" bitfld.long 0x00 5. " OINV ,Polarity control" "Not inverted,Inverted" bitfld.long 0x00 4. " DCTRL ,Auto direction control enable" "Disabled,Enabled" bitfld.long 0x00 3. " SEL ,Direction control pin select" "RTS,DTR" bitfld.long 0x00 2. " AADEN ,Auto address detect enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes" bitfld.long 0x00 0. " NMMEN ,Normal multidrop mode enable" "Disabled,Enabled" line.long 0x04 "RS485ADRMATCH,RS485 Address Match Register" hexmask.long.byte 0x04 0.--7. 1. " ADRMATCH ,Address match value" line.long 0x08 "RS485DLY,RS-485 Delay Value Register" hexmask.long.byte 0x08 0.--7. 1. " DLY ,Direction control RTS or DTR delay value" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") if (((per.l(ad:0x40008000+0x58))&0x02)==0x02) group.long 0x58++0x03 line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register" bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware" bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent" bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous" newline bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling" bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master" bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled" else group.long 0x58++0x03 line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register" bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware" bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent" bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous" bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling" newline bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master" bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled" endif endif width 0x0B tree.end tree "USART1" base ad:0x4006C000 width 15. if (((per.l(ad:0x4006C000))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration Register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..." bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits" bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x4006C000))&0x01)==0x01)&&(((per.l(ad:0x4006C000+0x08))&0x03)==0x03) group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" newline bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" else group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" endif group.long 0x08++0x0F line.long 0x00 "STAT,USART Status Register" eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred" eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred" newline eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started" eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected" rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received" eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred" newline rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected" rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High" rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle" newline rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register" setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled" hgroup.long 0x14++0x03 hide.long 0x00 "RXDAT,Receiver Data Register" in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register" in group.long 0x1C++0x07 line.long 0x00 "TXDAT,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register" line.long 0x04 "BRG,Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error" bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error" newline bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error" bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active" bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register For Automatic Address Matching" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching" width 0x0B tree.end tree "USART2" base ad:0x40070000 width 15. if (((per.l(ad:0x40070000))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration Register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..." bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits" bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x40070000))&0x01)==0x01)&&(((per.l(ad:0x40070000+0x08))&0x03)==0x03) group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" newline bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" else group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" endif group.long 0x08++0x0F line.long 0x00 "STAT,USART Status Register" eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred" eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred" newline eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started" eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected" rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received" eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred" newline rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected" rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High" rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle" newline rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register" setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled" hgroup.long 0x14++0x03 hide.long 0x00 "RXDAT,Receiver Data Register" in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register" in group.long 0x1C++0x07 line.long 0x00 "TXDAT,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register" line.long 0x04 "BRG,Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error" bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error" newline bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error" bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active" bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register For Automatic Address Matching" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching" width 0x0B tree.end sif cpuis("LPC11U68JBD100") tree "USART3" base ad:0x40074000 width 15. if (((per.l(ad:0x40074000))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration Register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..." bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits" bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x40074000))&0x01)==0x01)&&(((per.l(ad:0x40074000+0x08))&0x03)==0x03) group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" newline bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" else group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" endif group.long 0x08++0x0F line.long 0x00 "STAT,USART Status Register" eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred" eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred" newline eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started" eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected" rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received" eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred" newline rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected" rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High" rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle" newline rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register" setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled" hgroup.long 0x14++0x03 hide.long 0x00 "RXDAT,Receiver Data Register" in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register" in group.long 0x1C++0x07 line.long 0x00 "TXDAT,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register" line.long 0x04 "BRG,Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error" bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error" newline bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error" bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active" bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register For Automatic Address Matching" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching" width 0x0B tree.end tree "USART4" base ad:0x4004C000 width 15. if (((per.l(ad:0x4004C000))&0x800)==0x800) group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration Register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,?..." bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CFG,USART Configuration register" bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Not inverted,Inverted" bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Not inverted,Inverted" bitfld.long 0x00 21. " OEPOL ,Output enable polarity" "Low,High" bitfld.long 0x00 20. " OESEL ,Output enable select" "Disabled,Enabled" newline bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled" bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled" bitfld.long 0x00 15. " LOOP ,Data loopback mode select" "Normal,Loopback" bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master" newline bitfld.long 0x00 12. " CLKPOL ,Clock polarity and sampling edge of received data in synchronous mode select" "Falling,Rising" bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous" bitfld.long 0x00 9. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 7. " MODE32K ,Standard or 32 kHz clocking mode select" "Standard,32kHz" newline bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 bit,2 bits" bitfld.long 0x00 4.--5. " PARITYSEL ,Type of parity used by the USART select" "No parity,,Even,Odd" bitfld.long 0x00 2.--3. " DATALEN ,Data size for the USART select" "7 bit,8 bit,9 bit,?..." bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled" endif if (((per.l(ad:0x4004C000))&0x01)==0x01)&&(((per.l(ad:0x4004C000+0x08))&0x03)==0x03) group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 16. " AUTOBAUD ,Autobaud enable" "Disabled,Enabled" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" newline bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" else group.long 0x04++0x0F line.long 0x00 "CTL,USART Control Register" bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear" bitfld.long 0x00 8. " CC ,Continuous clock generation" "On character,Continuous" bitfld.long 0x00 6. " TXDIS ,Transmit disable" "No,Yes" bitfld.long 0x00 2. " ADDRDET ,Address detect mode enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Disabled,Enabled" endif group.long 0x08++0x0F line.long 0x00 "STAT,USART Status Register" eventfld.long 0x00 16. " ABERR ,Autobaud error" "Not occurred,Occurred" eventfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "Not occurred,Occurred" newline eventfld.long 0x00 12. " START ,Receiving start" "Not started,Started" eventfld.long 0x00 11. " DELTARXBRK ,Receiver detection break" "Not detected,Detected" rbitfld.long 0x00 10. " RXBRK ,Received break" "Not received,Received" eventfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "Not occurred,Occurred" newline rbitfld.long 0x00 6. " TXDISSTAT ,Transmitter disabled interrupt flag" "Not occurred,Occurred" eventfld.long 0x00 5. " DELTACTS ,CTS change interrupt flag" "Not detected,Detected" rbitfld.long 0x00 4. " CTS ,Current CTS state reflection" "Low,High" rbitfld.long 0x00 3. " TXIDLE ,Transmitter idle" "Busy,Idle" newline rbitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" rbitfld.long 0x00 1. " RXIDLE ,Receiver idle" "Busy,Idle" rbitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" line.long 0x04 "INTENSET/CLR,Interrupt Enable Read And Set Register" setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ABERREN ,Autobaud error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x08 15. " RXNOISEEN ,Noise detection interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " PARITYERREN ,Parity error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 13. 0x04 13. 0x08 13. " FRAMERREN ,Framing error interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 12. 0x04 12. 0x08 12. " STARTEN ,Received start bit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " OVERRUNEN ,Overrun error interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x08 6. " TXDISEN ,Fully transmitter disable interrupt enable" "Disabled,Enabled" newline setclrfld.long 0x04 5. 0x04 5. 0x08 5. " DELTACTSEN ,CTS change interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x08 3. " TXIDLEEN ,Transmitter idle interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " TXRDYEN ,TXDAT register ready to take another character to transmit interrupt enable" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x08 0. " RXRDYEN ,Character ready to read from RXDAT interrupt enable" "Disabled,Enabled" hgroup.long 0x14++0x03 hide.long 0x00 "RXDAT,Receiver Data Register" in hgroup.long 0x18++0x03 hide.long 0x00 "RXDATSTAT,Receiver Data With Status Register" in group.long 0x1C++0x07 line.long 0x00 "TXDAT,Transmit Data Register" hexmask.long.word 0x00 0.--8. 1. " TXDAT ,USART transmit data register" line.long 0x04 "BRG,Baud Rate Generator Register" hexmask.long.word 0x04 0.--15. 1. " BRGVAL ,USART input clock divide value" rgroup.long 0x24++0x03 line.long 0x00 "INTSTAT,Interrupt Status Register" bitfld.long 0x00 16. " ABERR ,Autobaud error flag" "No error,Error" bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No error,Error" bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No error,Error" newline bitfld.long 0x00 12. " START ,Received start bit interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 11. " DELTARXBRK ,Change of state occurred in the detection of a received break condition interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 8. " OVERRUNINT ,Overrun error interrupt flag" "No error,Error" bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt" newline bitfld.long 0x00 5. " DELTACTS ,CTS state change interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not active,Active" bitfld.long 0x00 2. " TXRDY ,Transmitter ready flag" "Not ready,Ready" bitfld.long 0x00 0. " RXRDY ,Receiver ready flag" "Not ready,Ready" group.long 0x28++0x07 line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication" bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "ADDR,Address Register For Automatic Address Matching" hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching" width 0x0B tree.end endif else base ad:0x40008000 width 15. if (((per.l(ad:0x40008000+0x0C))&0x80)==0x00) hgroup.long 0x00++0x03 hide.long 0x00 "RBR/THR,Receiver/Transmitter Holding Register" in group.long 0x04++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 9. " ABTOINTEN ,Auto-baud timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " ABEOINTEN ,End of auto-baud interrupt enable" "Disabled,Enabled" sif cpuis("LPC11D14")||cpuis("LPC11C*") bitfld.long 0x00 2. " RXLIE ,RX line interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " THREIE ,THRE interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " RBRIE ,RBR interrupt enable" "Disabled,Enabled" else bitfld.long 0x00 3. " MSINTEN ,Modem status interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RLSINTEN ,Receive line status interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " THREINTEN ,THRE interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " RBRINTEN ,RBR interrupt enable" "Disabled,Enabled" endif else group.long 0x00++0x07 line.long 0x00 "DLL,Divisor Latch LSB" hexmask.long.byte 0x00 0.--7. 1. " DLLSB ,USART divisor latch LSB" line.long 0x04 "DLM,Divisor Latch MSB" hexmask.long.byte 0x04 0.--7. 1. " DLMSB ,USART divisor latch MSB" endif rgroup.long 0x08++0x03 line.long 0x00 "IIR,Interrupt ID" bitfld.long 0x00 9. " ABTOINT ,Auto-baud timeout interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " ABEOINT ,End of auto-baud interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6.--7. " FIFOEN ,FIFO enable" "0,1,2,3" sif cpuis("LPC11C*") bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem interrupt,THRE,RDA,RLS,,,CTI,?..." else bitfld.long 0x00 1.--3. " INTID ,Interrupt identification" "Modem status,THRE,RDA,RLS,,,CTI,?..." endif newline bitfld.long 0x00 0. " INTSTATUS ,Interrupt status" "Pending,Not pending" wgroup.long 0x08++0x03 line.long 0x00 "FCR,FIFO Control Register" bitfld.long 0x00 6.--7. " RXTL ,Rx trigger level select" "Level 0,Level 1,Level 2,Level 3" sif !cpuis("LPC11D14")&&!cpuis("LPC11U1*")&&!cpuis("LPC11U2*")&&!cpuis("LPC11U3*")&&!cpuis("LPC11C*") bitfld.long 0x00 3. " DMAMODE ,DMA mode enable" "Disable,Enable" endif newline bitfld.long 0x00 2. " TXFIFORES ,Transmitter FIFO reset" "No effect,Clear" bitfld.long 0x00 1. " RXFIFORES ,Receiver FIFO reset" "No effect,Clear" bitfld.long 0x00 0. " FIFOEN ,FIFO enable" "Disable,Enable" if (((per.l(ad:0x40008000+0x0C))&0x03)==0x00) group.long 0x0C++0x03 line.long 0x00 "LCR,Line Control Register" bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled" bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled" bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0" bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,1.5 bits" bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit" else group.long 0x0C++0x03 line.long 0x00 "LCR,Line Control Register" bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled" bitfld.long 0x00 6. " BC ,Break control" "Disabled,Enabled" bitfld.long 0x00 4.--5. " PS ,Parity select" "Odd,Even,Forced 1,Forced 0" bitfld.long 0x00 3. " PE ,Parity enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " SBS ,Stop bit select" "1 bit,2 bits" bitfld.long 0x00 0.--1. " WLS ,Word length select" "5-bit,6-bit,7-bit,8-bit" endif group.long 0x10++0x03 line.long 0x00 "MCR,USART0 Modem Control Register" bitfld.long 0x00 7. " CTSEN ,CTS enable" "Disabled,Enabled" bitfld.long 0x00 6. " RTSEN ,RTS enable" "Disabled,Enabled" bitfld.long 0x00 4. " LMS ,Loopback mode select" "Disabled,Enabled" bitfld.long 0x00 1. " RTSCTRL ,Source for modem output pin RTS" "Active,Inactive" newline bitfld.long 0x00 0. " DTRCTRL ,Source for modem output pin DTR" "Active,Inactive" hgroup.long 0x14++0x03 hide.long 0x00 "LSR,Line Status Register" in hgroup.long 0x18++0x03 hide.long 0x00 "MSR,Modem Status Register" in group.long 0x1C++0x07 line.long 0x00 "SCR,Scratch Pad Register" hexmask.long.byte 0x00 0.--7. 1. " PAD ,A readable/writable byte" line.long 0x04 "ACR,Auto-Baud Control Register" bitfld.long 0x04 9. " ABTOINTCLR ,Auto-baud timeout interrupt clear bit" "No effect,Cleared" bitfld.long 0x04 8. " ABEOINTCLR ,End of auto-baud interrupt clear bit" "No effect,Cleared" sif cpuis("LPC11C*") bitfld.long 0x04 2. " AUTORESTART ,Automatic restart enable" "Disabled,Enabled" bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1" else bitfld.long 0x04 2. " AUTORESTART ,Start mode" "Not restarted,Restarted" bitfld.long 0x04 1. " MODE ,Auto-baud mode select" "Mode 0,Mode 1" endif newline bitfld.long 0x04 0. " START ,Auto-baud start" "Stopped,Started" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") group.long 0x24++0x03 line.long 0x00 "ICR,IrDA Control Register" bitfld.long 0x00 3.--5. " PULSEDIV ,Pulse width configure" "3/(16*baud rate),2*Tpclk,4*Tpclk,8*Tpclk,16*Tpclk,32*Tpclk,64*Tpclk,128*Tpclk" bitfld.long 0x00 2. " FIXPULSEEN ,IrDA fixed pulse width mode enable" "Disabled,Enabled" bitfld.long 0x00 1. " IRDAINV ,Serial input invert" "Not inverted,Inverted" bitfld.long 0x00 0. " IRDAEN ,IrDA mode enable" "Disabled,Enabled" endif group.long 0x28++0x03 line.long 0x00 "FDR,Fractional Divider Register" bitfld.long 0x00 4.--7. " MULVAL ,Baud rate pre-scaler multiplier value" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DIVADDVAL ,Baud rate pre-scaler divisor value" ",None,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") if (((per.l(ad:0x40008000+0x48))&0x01)==0x00) group.long 0x2C++0x03 line.long 0x00 "OSR,Oversampling Register" bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875" else group.long 0x2C++0x03 line.long 0x00 "OSR,Oversampling Register" hexmask.long.byte 0x00 8.--14. 1. " FDINT ,These bits act as a more-significant extension of the OSint field" bitfld.long 0x00 4.--7. " OSINT ,Integer part of the oversampling ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 1.--3. " OSFRAC ,Fractional part of the oversampling ratio" ",0.125,0.250,0.375,0.5,0.625,0.750,0.875" endif endif group.long 0x30++0x03 line.long 0x00 "TER,Transmit Enable Register" bitfld.long 0x00 7. " TXEN ,Transmission enable" "Disabled,Enabled" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") group.long 0x40++0x03 line.long 0x00 "HDEN,USART Half-Duplex Enable Register" bitfld.long 0x00 0. " HDEN ,Half-duplex mode enable" "Disabled,Enabled" if (((per.l(ad:0x40008000+0x48))&0x04)==0x00) group.long 0x48++0x03 line.long 0x00 "SCICTRL,Smart Card Interface Control Register" hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs" bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1" bitfld.long 0x00 1. " NACKDIS ,NACK response disable" "No,Yes" newline bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled" else group.long 0x48++0x03 line.long 0x00 "SCICTRL,Smart Card Interface Control Register" hexmask.long.byte 0x00 8.--15. 1. " XTRAGUARD ,This field indicates the number of bit times ETUs" bitfld.long 0x00 5.--7. " TXRETRY ,Controls the maximum number of retransmissions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " PROTSEL ,Protocol selection as defined in the ISO7816-3 standard" "T=0,T=1" bitfld.long 0x00 0. " SCIEN ,Smart card interface enable" "Disabled,Enabled" endif endif group.long 0x4C++0x0B line.long 0x00 "RS485CTRL,RS485 Control Register" bitfld.long 0x00 5. " OINV ,Polarity control" "Not inverted,Inverted" bitfld.long 0x00 4. " DCTRL ,Auto direction control enable" "Disabled,Enabled" bitfld.long 0x00 3. " SEL ,Direction control pin select" "RTS,DTR" bitfld.long 0x00 2. " AADEN ,Auto address detect enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " RXDIS ,The receiver disable" "No,Yes" bitfld.long 0x00 0. " NMMEN ,Normal multidrop mode enable" "Disabled,Enabled" line.long 0x04 "RS485ADRMATCH,RS485 Address Match Register" hexmask.long.byte 0x04 0.--7. 1. " ADRMATCH ,Address match value" line.long 0x08 "RS485DLY,RS-485 Delay Value Register" hexmask.long.byte 0x08 0.--7. 1. " DLY ,Direction control RTS or DTR delay value" sif !cpuis("LPC11D14")&&!cpuis("LPC11C*") if (((per.l(ad:0x40008000+0x58))&0x02)==0x02) group.long 0x58++0x03 line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register" bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware" bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent" bitfld.long 0x00 4. " CSCEN ,Continuous master clock enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous" newline bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling" bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master" bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled" else group.long 0x58++0x03 line.long 0x00 "SYNCCTRL,Synchronous Mode Control Register" bitfld.long 0x00 6. " CCCLR ,Continuous clock clear" "Software,Hardware" bitfld.long 0x00 5. " SSDIS ,Start/stop bits" "Sent,Not sent" bitfld.long 0x00 3. " TSBYPASS ,Transmit synchronization bypass in synchronous slave mode" "Synchronous,Asynchronous" bitfld.long 0x00 2. " FES ,Falling edge sampling" "Rising,Falling" newline bitfld.long 0x00 1. " CSRC ,Clock source select" "Slave,Master" bitfld.long 0x00 0. " SYNC ,Synchronous mode enable" "Disabled,Enabled" endif endif width 0x0B endif tree.end tree "I2C-Bus Interface" sif cpuis("LPC11U6*") tree "I2C0" base ad:0x40000000 width 17. group.long 0x00++0x03 line.long 0x00 "CONSET,Control Set Register" setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_SET/CLR ,I2C-bus interface enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_SET/CLR ,START flag" "Not started,Started" bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stopped" setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_SET/CLR ,I2C interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_SET/CLR ,Assert acknowledge flag" "Not asserted,Asserted" rgroup.long 0x04++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "0x00,0x08,0x10,0x18,0x20,0x28,0x30,0x38,0x40,0x48,0x50,0x58,0x60,0x68,0x70,0x78,0x80,0x88,0x90,0x98,0xA0,0xA8,0xB0,0xB8,0xC0,0xC8,,,,,,0xF8" group.long 0x08++0x0F line.long 0x00 "DAT,Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data that have been received or is to be transmitted" line.long 0x04 "ADR0,Slave Address Register" hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Device address in slave mode" bitfld.long 0x04 0. " GC ,General call enable bit" "Not recognized,Recognized" line.long 0x08 "SCLH,SCL High Duty Cycle Register" hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL high time period selection" line.long 0x0C "SCLL,SCL Low Duty Cycle Register" hexmask.long.word 0x0C 0.--15. 1. " SCLH ,Count for SCL low time period selection" if (((per.l(ad:0x40000000+0x1C))&0x01)==0x01) group.long 0x1C++0x03 line.long 0x00 "MMCTRL,Monitor Mode Control Register" bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address" bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled" bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "MMCTRL,Monitor Mode Control Register" bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "No effect,No effect" bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "No effect,No effect" bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "ADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" group.long 0x24++0x03 line.long 0x00 "ADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" group.long 0x28++0x03 line.long 0x00 "ADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" rgroup.long 0x2C++0x03 line.long 0x00 "DATA_BUFFER,Data Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Content of the DAT shift register" newline group.long 0x30++0x03 line.long 0x00 "MASK0,I2C Mask Register 0" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x34++0x03 line.long 0x00 "MASK1,I2C Mask Register 1" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x38++0x03 line.long 0x00 "MASK2,I2C Mask Register 2" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x3C++0x03 line.long 0x00 "MASK3,I2C Mask Register 3" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" width 0x0B tree.end tree "I2C1" base ad:0x40020000 width 17. group.long 0x00++0x03 line.long 0x00 "CONSET,Control Set Register" setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_SET/CLR ,I2C-bus interface enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_SET/CLR ,START flag" "Not started,Started" bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stopped" setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_SET/CLR ,I2C interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_SET/CLR ,Assert acknowledge flag" "Not asserted,Asserted" rgroup.long 0x04++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "0x00,0x08,0x10,0x18,0x20,0x28,0x30,0x38,0x40,0x48,0x50,0x58,0x60,0x68,0x70,0x78,0x80,0x88,0x90,0x98,0xA0,0xA8,0xB0,0xB8,0xC0,0xC8,,,,,,0xF8" group.long 0x08++0x0F line.long 0x00 "DAT,Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data that have been received or is to be transmitted" line.long 0x04 "ADR0,Slave Address Register" hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Device address in slave mode" bitfld.long 0x04 0. " GC ,General call enable bit" "Not recognized,Recognized" line.long 0x08 "SCLH,SCL High Duty Cycle Register" hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL high time period selection" line.long 0x0C "SCLL,SCL Low Duty Cycle Register" hexmask.long.word 0x0C 0.--15. 1. " SCLH ,Count for SCL low time period selection" if (((per.l(ad:0x40020000+0x1C))&0x01)==0x01) group.long 0x1C++0x03 line.long 0x00 "MMCTRL,Monitor Mode Control Register" bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address" bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled" bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "MMCTRL,Monitor Mode Control Register" bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "No effect,No effect" bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "No effect,No effect" bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "ADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" group.long 0x24++0x03 line.long 0x00 "ADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" group.long 0x28++0x03 line.long 0x00 "ADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" rgroup.long 0x2C++0x03 line.long 0x00 "DATA_BUFFER,Data Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Content of the DAT shift register" newline group.long 0x30++0x03 line.long 0x00 "MASK0,I2C Mask Register 0" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x34++0x03 line.long 0x00 "MASK1,I2C Mask Register 1" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x38++0x03 line.long 0x00 "MASK2,I2C Mask Register 2" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x3C++0x03 line.long 0x00 "MASK3,I2C Mask Register 3" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" width 0x0B tree.end else base ad:0x40000000 width 17. group.long 0x00++0x03 line.long 0x00 "CONSET,Control Set Register" setclrfld.long 0x00 6. 0x00 6. 0x18 6. " I2EN_SET/CLR ,I2C-bus interface enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x18 5. " STA_SET/CLR ,START flag" "Not started,Started" bitfld.long 0x00 4. " STO ,STOP flag" "No effect,Stopped" setclrfld.long 0x00 3. 0x00 3. 0x18 3. " SI_SET/CLR ,I2C interrupt flag" "Not occurred,Occurred" setclrfld.long 0x00 2. 0x00 2. 0x18 2. " AA_SET/CLR ,Assert acknowledge flag" "Not asserted,Asserted" rgroup.long 0x04++0x03 line.long 0x00 "STAT,Status Register" bitfld.long 0x00 3.--7. " STATUS ,Actual status information about I2C interface" "0x00,0x08,0x10,0x18,0x20,0x28,0x30,0x38,0x40,0x48,0x50,0x58,0x60,0x68,0x70,0x78,0x80,0x88,0x90,0x98,0xA0,0xA8,0xB0,0xB8,0xC0,0xC8,,,,,,0xF8" group.long 0x08++0x0F line.long 0x00 "DAT,Data Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data that have been received or is to be transmitted" line.long 0x04 "ADR0,Slave Address Register" hexmask.long.byte 0x04 1.--7. 0x02 " ADDRESS ,Device address in slave mode" bitfld.long 0x04 0. " GC ,General call enable bit" "Not recognized,Recognized" line.long 0x08 "SCLH,SCL High Duty Cycle Register" hexmask.long.word 0x08 0.--15. 1. " SCLH ,Count for SCL high time period selection" line.long 0x0C "SCLL,SCL Low Duty Cycle Register" hexmask.long.word 0x0C 0.--15. 1. " SCLH ,Count for SCL low time period selection" if (((per.l(ad:0x40000000+0x1C))&0x01)==0x01) group.long 0x1C++0x03 line.long 0x00 "MMCTRL,Monitor Mode Control Register" bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "Match address,Any address" bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "Disabled,Enabled" bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "MMCTRL,Monitor Mode Control Register" bitfld.long 0x00 2. " MATCH_ALL ,Select interrupt register match" "No effect,No effect" bitfld.long 0x00 1. " ENA_SCL ,SCL output enable" "No effect,No effect" bitfld.long 0x00 0. " MM_ENA ,Monitor mode enable" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "ADR1,Slave Address Register 1" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" group.long 0x24++0x03 line.long 0x00 "ADR2,Slave Address Register 2" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" group.long 0x28++0x03 line.long 0x00 "ADR3,Slave Address Register 3" hexmask.long.byte 0x00 1.--7. 0x02 " ADDRESS ,The I2C device address for slave mode" bitfld.long 0x00 0. " GC ,General call enable bit" "Not recognized,Recognized" rgroup.long 0x2C++0x03 line.long 0x00 "DATA_BUFFER,Data Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Content of the DAT shift register" newline group.long 0x30++0x03 line.long 0x00 "MASK0,I2C Mask Register 0" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x34++0x03 line.long 0x00 "MASK1,I2C Mask Register 1" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x38++0x03 line.long 0x00 "MASK2,I2C Mask Register 2" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" group.long 0x3C++0x03 line.long 0x00 "MASK3,I2C Mask Register 3" bitfld.long 0x00 7. " MASK[7] ,ADDR7 compare mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,ADDR6 compare mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,ADDR5 compare mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,ADDR4 compare mask" "Not masked,Masked" bitfld.long 0x00 3. " [3] ,ADDR3 compare mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,ADDR2 compare mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,ADDR1 compare mask" "Not masked,Masked" width 0x0B endif tree.end tree "SSP (Synchronous Serial Port)" tree "SSP/SPI0" base ad:0x40040000 width 7. if (((per.l(ad:0x40040000+0x00))&0x30)==0x00) group.long 0x00++0x03 line.long 0x00 "CR0,Control Register 0" hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate" bitfld.long 0x00 7. " CPHA ,Clock out phase" "First,Second" bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High" newline bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..." bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" else group.long 0x00++0x03 line.long 0x00 "CR0,Control Register 0" hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate" newline bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..." bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" endif if (((per.l(ad:0x40040000+0x04))&0x04)==0x04) group.long 0x04++0x03 line.long 0x00 "CR1,Control Register 1" bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes" newline bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave" bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled" bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback" else group.long 0x04++0x03 line.long 0x00 "CR1,Control Register 1" newline bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave" bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled" bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback" endif group.long 0x08++0x03 line.long 0x00 "DR,Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data value" rgroup.long 0x0C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy" bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full" bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty" bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full" bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty" newline group.long 0x10++0x07 line.long 0x00 "CPSR,Clock Prescale Register" hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,PCLK divisor value" line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register" bitfld.long 0x04 3. " TXIM ,TX FIFO half empty interrupt mask" "Disabled,Enabled" bitfld.long 0x04 2. " RXIM ,RX FIFO half full interrupt mask" "Disabled,Enabled" bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt mask" "Disabled,Enabled" bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt mask" "Disabled,Enabled" rgroup.long 0x18++0x07 line.long 0x00 "RIS,Raw Interrupt Status Register" bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty" "Not half empty,Half empty" bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full" "Not half full,Half full" bitfld.long 0x00 1. " RTRIS ,Receive timeout" "Not received,Received" bitfld.long 0x00 0. " RORRIS ,Frame received when RxFIFO full" "Not received,Received" line.long 0x04 "MIS,Masked Interrupt Status Register" bitfld.long 0x04 3. " TXMIS ,TX FIFO half empty interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " RXMIS ,RX FIFO half full interrupt" "No interrupt,Interrupt" bitfld.long 0x04 1. " RTMIS ,Receive timeout interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " RORMIS ,Frame received when RxFIFO full interrupt" "No interrupt,Interrupt" wgroup.long 0x20++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 1. " RTIC ,Receive timeout clear" "No effect,Clear" bitfld.long 0x00 0. " RORIC ,Clear frame received when RxFIFO full" "No effect,Clear" sif cpuis("LPC11U6*") group.long 0x24++0x03 line.long 0x00 "DMACR,DMA Control Register" bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled" endif width 0x0B tree.end tree "SSP/SPI1" base ad:0x40058000 width 7. if (((per.l(ad:0x40058000+0x00))&0x30)==0x00) group.long 0x00++0x03 line.long 0x00 "CR0,Control Register 0" hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate" bitfld.long 0x00 7. " CPHA ,Clock out phase" "First,Second" bitfld.long 0x00 6. " CPOL ,Clock out polarity" "Low,High" newline bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..." bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" else group.long 0x00++0x03 line.long 0x00 "CR0,Control Register 0" hexmask.long.byte 0x00 8.--15. 1. " SCR ,Serial clock rate" newline bitfld.long 0x00 4.--5. " FRF ,Frame format" "SPI,TI,Microwire,?..." bitfld.long 0x00 0.--3. " DSS ,Data size select" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit" endif if (((per.l(ad:0x40058000+0x04))&0x04)==0x04) group.long 0x04++0x03 line.long 0x00 "CR1,Control Register 1" bitfld.long 0x00 3. " SOD ,Slave output disable" "No,Yes" newline bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave" bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled" bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback" else group.long 0x04++0x03 line.long 0x00 "CR1,Control Register 1" newline bitfld.long 0x00 2. " MS ,Master/slave mode" "Master,Slave" bitfld.long 0x00 1. " SSE ,SSP enable" "Disabled,Enabled" bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback" endif group.long 0x08++0x03 line.long 0x00 "DR,Data Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data value" rgroup.long 0x0C++0x03 line.long 0x00 "SR,Status Register" bitfld.long 0x00 4. " BSY ,Busy" "Idle,Busy" bitfld.long 0x00 3. " RFF ,Receive FIFO full" "Not full,Full" bitfld.long 0x00 2. " RNE ,Receive FIFO not empty" "Empty,Not empty" bitfld.long 0x00 1. " TNF ,Transmit FIFO not full" "Full,Not full" bitfld.long 0x00 0. " TFE ,Transmit FIFO empty" "Not empty,Empty" newline group.long 0x10++0x07 line.long 0x00 "CPSR,Clock Prescale Register" hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,PCLK divisor value" line.long 0x04 "IMSC,Interrupt Mask Set/Clear Register" bitfld.long 0x04 3. " TXIM ,TX FIFO half empty interrupt mask" "Disabled,Enabled" bitfld.long 0x04 2. " RXIM ,RX FIFO half full interrupt mask" "Disabled,Enabled" bitfld.long 0x04 1. " RTIM ,Receive timeout interrupt mask" "Disabled,Enabled" bitfld.long 0x04 0. " RORIM ,Receive overrun interrupt mask" "Disabled,Enabled" rgroup.long 0x18++0x07 line.long 0x00 "RIS,Raw Interrupt Status Register" bitfld.long 0x00 3. " TXRIS ,Tx FIFO half empty" "Not half empty,Half empty" bitfld.long 0x00 2. " RXRIS ,Rx FIFO half full" "Not half full,Half full" bitfld.long 0x00 1. " RTRIS ,Receive timeout" "Not received,Received" bitfld.long 0x00 0. " RORRIS ,Frame received when RxFIFO full" "Not received,Received" line.long 0x04 "MIS,Masked Interrupt Status Register" bitfld.long 0x04 3. " TXMIS ,TX FIFO half empty interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " RXMIS ,RX FIFO half full interrupt" "No interrupt,Interrupt" bitfld.long 0x04 1. " RTMIS ,Receive timeout interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " RORMIS ,Frame received when RxFIFO full interrupt" "No interrupt,Interrupt" wgroup.long 0x20++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 1. " RTIC ,Receive timeout clear" "No effect,Clear" bitfld.long 0x00 0. " RORIC ,Clear frame received when RxFIFO full" "No effect,Clear" sif cpuis("LPC11U6*") group.long 0x24++0x03 line.long 0x00 "DMACR,DMA Control Register" bitfld.long 0x00 1. " TXDMAE ,Transmit DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " RXDMAE ,Receive DMA enable" "Disabled,Enabled" endif width 0x0B tree.end tree.end tree "USB 2.0 (USB 2.0 Full-Speed Device Controller)" base ad:0x40080000 width 14. group.long 0x00++0x2F line.long 0x00 "DEVCMDSTAT,USB Device Command/Status Register" rbitfld.long 0x00 28. " VBUSDEBOUNCED ,Vbus detect indication" "Not detected,Detected" eventfld.long 0x00 26. " DRES_C ,Device status - reset change" "No reset,Reset" eventfld.long 0x00 25. " DSUS_C ,Device status - suspend change" "Not toggled,Toggled" eventfld.long 0x00 24. " DCON_C ,Device status - connect change" "Not occurred,Occurred" newline rbitfld.long 0x00 20. " LPM_REWP ,LPM remote wake-up enabled by USB host" "Disabled,Enabled" bitfld.long 0x00 19. " LPM_SUS ,Device status - LPM suspend" "Not suspended,Suspended" bitfld.long 0x00 17. " DSUS ,Device status - suspend" "Not suspended,Suspended" bitfld.long 0x00 16. " DCON ,Device status - connect" "Not connected,Connected" newline bitfld.long 0x00 15. " INTONNAK_CI ,Interrupt on NAK for control IN EP" "AK,AK & NAK" bitfld.long 0x00 14. " INTONNAK_CO ,Interrupt on NAK for control OUT EP" "AK,AK & NAK" bitfld.long 0x00 13. " INTONNAK_AI ,Interrupt on NAK for interrupt and bulk IN EP" "AK,AK & NAK" bitfld.long 0x00 12. " INTONNAK_AO ,Interrupt on NAK for interrupt and bulk OUT EP" "AK,AK & NAK" newline bitfld.long 0x00 11. " LPM_SUP ,LPM support" "Not supported,Supported" bitfld.long 0x00 9. " PLL_ON ,PLL clock on" "Functional,High" eventfld.long 0x00 8. " SETUP ,SETUP token received" "Not received,Received" bitfld.long 0x00 7. " DEV_EN ,USB device enable" "Disabled,Enabled" newline hexmask.long.byte 0x00 0.--6. 0x01 " DEV_ADDR ,USB device address" line.long 0x04 "INFO,USB Info Register" bitfld.long 0x04 11.--14. " ERR_CODE ,Last occurred error code" "No error,PID encoding error,PID unknown,Packet unexpected,Token CRC error,Data CRC error,Time out,Babble,Truncated EOP,Sent/Received NAK,Sent Stall,Overrun,Sent empty packet,Bitstuff error,Sync error,Wrong data toggle" hexmask.long.word 0x04 0.--10. 1. " FRAME_NR ,Frame number" line.long 0x08 "EPLISTSTART,USB EP Command/Status List Start Address" hexmask.long.tbyte 0x08 8.--31. 0x01 " EP_LIST ,Start address of the USB EP command/status list" line.long 0x0C "DATABUFSTART,USB Data Buffer Start Address" hexmask.long.word 0x0C 22.--31. 0x40 " DA_BUF ,Start address of the buffer pointer page" line.long 0x10 "LPM,Link Power Management" bitfld.long 0x10 8. " DATA_PENDING ,Data pending" "Not pending,Pending" bitfld.long 0x10 4.--7. " HIRD_SW ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x10 0.--3. " HIRD_HW ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "EPSKIP,USB Endpoint Skip" bitfld.long 0x14 29. " SKIP[29] ,Endpoint 29 skip request" "Not occurred,Occurred" bitfld.long 0x14 28. " [28] ,Endpoint 28 skip request" "Not occurred,Occurred" bitfld.long 0x14 27. " [27] ,Endpoint 27 skip request" "Not occurred,Occurred" bitfld.long 0x14 26. " [26] ,Endpoint 26 skip request" "Not occurred,Occurred" newline bitfld.long 0x14 25. " [25] ,Endpoint 25 skip request" "Not occurred,Occurred" bitfld.long 0x14 24. " [24] ,Endpoint 24 skip request" "Not occurred,Occurred" bitfld.long 0x14 23. " [23] ,Endpoint 23 skip request" "Not occurred,Occurred" bitfld.long 0x14 22. " [22] ,Endpoint 22 skip request" "Not occurred,Occurred" newline bitfld.long 0x14 21. " [21] ,Endpoint 21 skip request" "Not occurred,Occurred" bitfld.long 0x14 20. " [20] ,Endpoint 20 skip request" "Not occurred,Occurred" bitfld.long 0x14 19. " [19] ,Endpoint 19 skip request" "Not occurred,Occurred" bitfld.long 0x14 18. " [18] ,Endpoint 18 skip request" "Not occurred,Occurred" newline bitfld.long 0x14 17. " [17] ,Endpoint 17 skip request" "Not occurred,Occurred" bitfld.long 0x14 16. " [16] ,Endpoint 16 skip request" "Not occurred,Occurred" bitfld.long 0x14 15. " [15] ,Endpoint 15 skip request" "Not occurred,Occurred" bitfld.long 0x14 14. " [14] ,Endpoint 14 skip request" "Not occurred,Occurred" newline bitfld.long 0x14 13. " [13] ,Endpoint 13 skip request" "Not occurred,Occurred" bitfld.long 0x14 12. " [12] ,Endpoint 12 skip request" "Not occurred,Occurred" bitfld.long 0x14 11. " [11] ,Endpoint 11 skip request" "Not occurred,Occurred" bitfld.long 0x14 10. " [10] ,Endpoint 10 skip request" "Not occurred,Occurred" newline bitfld.long 0x14 9. " [9] ,Endpoint 9 skip request" "Not occurred,Occurred" bitfld.long 0x14 8. " [8] ,Endpoint 8 skip request" "Not occurred,Occurred" bitfld.long 0x14 7. " [7] ,Endpoint 7 skip request" "Not occurred,Occurred" bitfld.long 0x14 6. " [6] ,Endpoint 6 skip request" "Not occurred,Occurred" newline bitfld.long 0x14 5. " [5] ,Endpoint 5 skip request" "Not occurred,Occurred" bitfld.long 0x14 4. " [4] ,Endpoint 4 skip request" "Not occurred,Occurred" bitfld.long 0x14 3. " [3] ,Endpoint 3 skip request" "Not occurred,Occurred" bitfld.long 0x14 2. " [2] ,Endpoint 2 skip request" "Not occurred,Occurred" newline bitfld.long 0x14 1. " [1] ,Endpoint 1 skip request" "Not occurred,Occurred" bitfld.long 0x14 0. " [0] ,Endpoint 0 skip request" "Not occurred,Occurred" line.long 0x18 "EPINUSE,USB Endpoint Buffer In Use" bitfld.long 0x18 9. " BUF[9] ,Endpoint 9 buffer in use" "Buffer 0,Buffer 1" bitfld.long 0x18 8. " [8] ,Endpoint 8 buffer in use" "Buffer 0,Buffer 1" bitfld.long 0x18 7. " [7] ,Endpoint 7 buffer in use" "Buffer 0,Buffer 1" bitfld.long 0x18 6. " [6] ,Endpoint 6 buffer in use" "Buffer 0,Buffer 1" newline bitfld.long 0x18 5. " [5] ,Endpoint 5 buffer in use" "Buffer 0,Buffer 1" bitfld.long 0x18 4. " [4] ,Endpoint 4 buffer in use" "Buffer 0,Buffer 1" bitfld.long 0x18 3. " [3] ,Endpoint 3 buffer in use" "Buffer 0,Buffer 1" bitfld.long 0x18 2. " [2] ,Endpoint 2 buffer in use" "Buffer 0,Buffer 1" line.long 0x1C "EPBUFCFG,USB Endpoint Buffer Configuration" bitfld.long 0x1C 9. " BUF_SB[9] ,Endpoint 9 buffer usage" "Single-buffer,Double-buffer" bitfld.long 0x1C 8. " [8] ,Endpoint 8 buffer usage" "Single-buffer,Double-buffer" bitfld.long 0x1C 7. " [7] ,Endpoint 7 buffer usage" "Single-buffer,Double-buffer" bitfld.long 0x1C 6. " [6] ,Endpoint 6 buffer usage" "Single-buffer,Double-buffer" newline bitfld.long 0x1C 5. " [5] ,Endpoint 5 buffer usage" "Single-buffer,Double-buffer" bitfld.long 0x1C 4. " [4] ,Endpoint 4 buffer usage" "Single-buffer,Double-buffer" bitfld.long 0x1C 3. " [3] ,Endpoint 3 buffer usage" "Single-buffer,Double-buffer" bitfld.long 0x1C 2. " [2] ,Endpoint 2 buffer usage" "Single-buffer,Double-buffer" line.long 0x20 "INTSTAT,USB Interrupt Status Register" eventfld.long 0x20 31. " DEV_INT ,Device status interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 30. " FRAME_INT ,Frame interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 9. " EP4IN ,EP4 IN interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 8. " EP4OUT ,EP4 OUT interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x20 7. " EP3IN ,EP3 IN interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 6. " EP3OUT ,EP3 OUT interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 5. " EP2IN ,EP2 IN interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 4. " EP2OUT ,EP2 OUT interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x20 3. " EP1IN ,EP1 IN interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 2. " EP1OUT ,EP1 OUT interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 1. " EP0IN ,EP0 IN interrupt status" "No interrupt,Interrupt" eventfld.long 0x20 0. " EP0OUT ,EP0 OUT interrupt status" "No interrupt,Interrupt" line.long 0x24 "INTEN,USB Interrupt Enable Register" bitfld.long 0x24 31. " DEV_INT_EN ,DEV interrupt enable" "Disabled,Enabled" bitfld.long 0x24 30. " FRAME_INT_EN ,FRAME interrupt enable" "Disabled,Enabled" bitfld.long 0x24 9. " EP4IN_INT_EN ,EP4IN interrupt enable" "Disabled,Enabled" bitfld.long 0x24 8. " EP4OUT_INT_EN ,EP4OUT interrupt enable" "Disabled,Enabled" newline bitfld.long 0x24 7. " EP3IN_INT_EN ,EP3IN interrupt enable" "Disabled,Enabled" bitfld.long 0x24 6. " EP3OUT_INT_EN ,EP3OUT interrupt enable" "Disabled,Enabled" bitfld.long 0x24 5. " EP2IN_INT_EN ,EP2IN interrupt enable" "Disabled,Enabled" bitfld.long 0x24 4. " EP2OUT_INT_EN ,EP2OUT interrupt enable" "Disabled,Enabled" newline bitfld.long 0x24 3. " EP1IN_INT_EN ,EP1IN interrupt enable" "Disabled,Enabled" bitfld.long 0x24 2. " EP1OUT_INT_EN ,EP1OUT interrupt enable" "Disabled,Enabled" bitfld.long 0x24 1. " EP0IN_INT_EN ,EP0IN interrupt enable" "Disabled,Enabled" bitfld.long 0x24 0. " EP0OUT_INT_EN ,EP0OUT interrupt enable" "Disabled,Enabled" line.long 0x28 "INTSETSTAT,USB Set Interrupt Status Register" bitfld.long 0x28 31. " DEV_SET_INT ,DEV set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 30. " FRAME_SET_INT ,FRAME set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 9. " EP4IN_SET_INT ,EP4IN set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 8. " EP4OUT_SET_INT ,EP4OUT set interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x28 7. " EP3IN_SET_INT ,EP3IN set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 6. " EP3OUT_SET_INT ,EP3OUT set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 5. " EP2IN_SET_INT ,EP2IN set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 4. " EP2OUT_SET_INT ,EP2OUT set interrupt status" "No interrupt,Interrupt" newline bitfld.long 0x28 3. " EP1IN_SET_INT ,EP1IN set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 2. " EP1OUT_SET_INT ,EP1OUT set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 1. " EP0IN_SET_INT ,EP0IN set interrupt status" "No interrupt,Interrupt" bitfld.long 0x28 0. " EP0OUT_SET_INT ,EP0OUT set interrupt status" "No interrupt,Interrupt" line.long 0x2C "INTROUTING,USB Interrupt Routing Register" bitfld.long 0x2C 31. " DEV_INT_ROUTE_INT ,Hardware interrupt line for DEV_INT select" "IRQ,FIQ" bitfld.long 0x2C 30. " FRAME_INT_ROUTE_INT ,Hardware interrupt line for FRAME_INT select" "IRQ,FIQ" bitfld.long 0x2C 9. " EP4IN_ROUTE_INT ,Hardware interrupt line for EP4IN select" "IRQ,FIQ" bitfld.long 0x2C 8. " EP4OUT_ROUTE_INT ,Hardware interrupt line for EP4OUT select" "IRQ,FIQ" newline bitfld.long 0x2C 7. " EP3IN_ROUTE_INT ,Hardware interrupt line for EP3IN select" "IRQ,FIQ" bitfld.long 0x2C 6. " EP3OUT_ROUTE_INT ,Hardware interrupt line for EP3OUT select" "IRQ,FIQ" bitfld.long 0x2C 5. " EP2IN_ROUTE_INT ,Hardware interrupt line for EP2IN select" "IRQ,FIQ" bitfld.long 0x2C 4. " EP2OUT_ROUTE_INT ,Hardware interrupt line for EP2OUT select" "IRQ,FIQ" newline bitfld.long 0x2C 3. " EP1IN_ROUTE_INT ,Hardware interrupt line for EP1IN select" "IRQ,FIQ" bitfld.long 0x2C 2. " EP1OUT_ROUTE_INT ,Hardware interrupt line for EP1OUT select" "IRQ,FIQ" bitfld.long 0x2C 1. " EP0IN_ROUTE_INT ,Hardware interrupt line for EP0IN select" "IRQ,FIQ" bitfld.long 0x2C 0. " EP0OUT_ROUTE_INT ,Hardware interrupt line for EP0OUT select" "IRQ,FIQ" rgroup.long 0x34++0x03 line.long 0x00 "EPTOGGLE,USB Endpoint Toggle" bitfld.long 0x00 9. " EP4IN_TOGGLE ,Endpoint EP4IN data toggle value" "0,1" bitfld.long 0x00 8. " EP4OUT_TOGGLE ,Endpoint EP4OUT data toggle value" "0,1" bitfld.long 0x00 7. " EP3IN_TOGGLE ,Endpoint EP3IN data toggle value" "0,1" bitfld.long 0x00 6. " EP3OUT_TOGGLE ,Endpoint EP3OUT data toggle value" "0,1" newline bitfld.long 0x00 5. " EP2IN_TOGGLE ,Endpoint EP2IN data toggle value" "0,1" bitfld.long 0x00 4. " EP2OUT_TOGGLE ,Endpoint EP2OUT data toggle value" "0,1" bitfld.long 0x00 3. " EP1IN_TOGGLE ,Endpoint EP1IN data toggle value" "0,1" bitfld.long 0x00 2. " EP1OUT_TOGGLE ,Endpoint EP1OUT data toggle value" "0,1" newline bitfld.long 0x00 1. " EP0IN_TOGGLE ,Endpoint EP0IN data toggle value" "0,1" bitfld.long 0x00 0. " EP0OUT_TOGGLE ,Endpoint EP0OUT data toggle value" "0,1" width 0x0B tree.end sif cpuis("LPC11U6*") tree "SCT (State Configurable Timer)" tree "SCT0" base ad:0x5000C000 width 15. group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT Configuration Register" bitfld.long 0x00 18. " AUTOLIMIT_H ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto" bitfld.long 0x00 17. " AUTOLIMIT_L ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto" newline sif cpuis("LPC11U6?JBD48") bitfld.long 0x00 10. " INSYNC[1] ,Synchronization for input 1" "Not synchronized,Synchronized" elif cpuis("LPC11U6?JBD64") bitfld.long 0x00 12. " INSYNC[3] ,Synchronization for input 3" "Not synchronized,Synchronized" bitfld.long 0x00 11. " [2] ,Synchronization for input 2" "Not synchronized,Synchronized" bitfld.long 0x00 10. " [1] ,Synchronization for input 1" "Not synchronized,Synchronized" else bitfld.long 0x00 12. " INSYNC[3] ,Synchronization for input 3" "Not synchronized,Synchronized" bitfld.long 0x00 11. " [2] ,Synchronization for input 2" "Not synchronized,Synchronized" bitfld.long 0x00 10. " [1] ,Synchronization for input 1" "Not synchronized,Synchronized" bitfld.long 0x00 9. " [0] ,Synchronization for input 0" "Not synchronized,Synchronized" endif newline bitfld.long 0x00 8. " NORELOAD_H ,Prevent the higher match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented" bitfld.long 0x00 7. " NORELOAD_L ,Prevent the lower match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented" newline sif cpuis("LPC11U6?JBD48") bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input" "Rising 1,Falling 1,?..." elif cpuis("LPC11U6?JBD64") bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input" ",,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..." else bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..." endif newline bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT" bitfld.long 0x00 0. " UNIFY ,SCT operate as unified 32-bit counter" "Not unified,Unified" if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x04))&0x06)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL,SCT Control Register" hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock" rbitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down" rbitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared" bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted" newline bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped" rbitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down" else group.long 0x04++0x03 line.long 0x00 "CTRL,SCT Control Register" hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock" bitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down" bitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared" bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted" newline bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped" bitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down" endif group.long 0x08++0x0F line.long 0x00 "LIMIT,SCT Limit Register" bitfld.long 0x00 5. " LIMMSK[5] ,Event 5 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 4. " [4] ,Event 4 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 3. " [3] ,Event 3 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 2. " [2] ,Event 2 use as counter limit for unified counter" "Not used,Used" newline bitfld.long 0x00 1. " [1] ,Event 1 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 0. " [0] ,Event 0 use as counter limit for unified counter" "Not used,Used" line.long 0x04 "HALT,SCT Halt Condition Register" bitfld.long 0x04 5. " HALTMSK[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 3. " [3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 2. " [2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set" newline bitfld.long 0x04 1. " [1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set" line.long 0x08 "STOP,SCT Stop Condition Register" bitfld.long 0x08 5. " STOPMSK[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 4. " [4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 3. " [3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 2. " [2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set" newline bitfld.long 0x08 1. " [1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 0. " [0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set" line.long 0x0C "START,SCT Start Condition Register" bitfld.long 0x0C 5. " STARTMSK[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 4. " [4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 3. " [3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 2. " [2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared" newline bitfld.long 0x0C 1. " [1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 0. " [0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared" if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00) rgroup.long 0x40++0x07 line.long 0x00 "COUNT,SCT Counter Register" line.long 0x04 "STATE,SCT State Register" bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x40++0x07 line.long 0x00 "COUNT,SCT Counter Register" line.long 0x04 "STATE,SCT State Register" bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x48++0x03 line.long 0x00 "INPUT,SCT Input Register" sif cpuis("LPC11U6?JBD48") bitfld.long 0x00 17. " SIN[1] ,Input 1 state" "Low,High" bitfld.long 0x00 1. " AIN[1] ,Input 1 state direct read" "Low,High" elif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 18. " [2] ,Input 2 state" "Low,High" bitfld.long 0x00 17. " [1] ,Input 1 state" "Low,High" bitfld.long 0x00 3. " AIN[3] ,Input 3 state direct read" "Low,High" newline bitfld.long 0x00 2. " [2] ,Input 2 state direct read" "Low,High" bitfld.long 0x00 1. " [1] ,Input 1 state direct read" "Low,High" else bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 18. " [2] ,Input 2 state" "Low,High" bitfld.long 0x00 17. " [1] ,Input 1 state" "Low,High" bitfld.long 0x00 16. " [0] ,Input 0 state" "Low,High" newline bitfld.long 0x00 3. " AIN[3] ,Input 3 state direct read" "Low,High" bitfld.long 0x00 2. " [2] ,Input 2 state direct read" "Low,High" bitfld.long 0x00 1. " [1] ,Input 1 state direct read" "Low,High" bitfld.long 0x00 0. " [0] ,Input 0 state direct read" "Low,High" endif group.long 0x4C++0x03 line.long 0x00 "REGMODE,SCT Match/Capture Registers Mode Register" bitfld.long 0x00 4. " REGMOD[4] ,Pair 4 of match/capture register operation mode" "Match,Capture" bitfld.long 0x00 3. " [3] ,Pair 3 of match/capture register operation mode" "Match,Capture" bitfld.long 0x00 2. " [2] ,Pair 2 of match/capture register operation mode" "Match,Capture" bitfld.long 0x00 1. " [1] ,Pair 1 of match/capture register operation mode" "Match,Capture" newline bitfld.long 0x00 0. " [0] ,Pair 0 of match/capture register operation mode" "Match,Capture" else if (((per.w(ad:0x5000C000+0x04))&0x06)==0x00) group.word 0x04++0x03 line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock" rbitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down" rbitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped" rbitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down" else group.word 0x04++0x03 line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock" bitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down" bitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped" bitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down" endif if (((per.w(ad:0x5000C000+0x06))&0x06)==0x00) group.word 0x06++0x01 line.word 0x00 "CTRL_H,SCT Control Register High Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock" rbitfld.word 0x00 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down" rbitfld.word 0x00 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_H ,H counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_H ,H counter stop" "Not stopped,Stopped" rbitfld.word 0x00 0. " DOWN_H ,H counter counting down" "Counting up,Counting down" else group.word 0x06++0x01 line.word 0x00 "CTRL_H,SCT Control Register High Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock" bitfld.word 0x00 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down" bitfld.word 0x00 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_H ,H counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_H ,H counter stop" "Not stopped,Stopped" bitfld.word 0x00 0. " DOWN_H ,H counter counting down" "Counting up,Counting down" endif group.word 0x08++0x0F line.word 0x00 "LIMIT_L,SCT Limit Register Low Counter 16-bit" bitfld.word 0x00 5. " LIMMSK_L[5] ,Event 5 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 4. " [4] ,Event 4 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 3. " [3] ,Event 3 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 2. " [2] ,Event 2 use as counter limit for L counter" "Not used,Used" newline bitfld.word 0x00 1. " [1] ,Event 1 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 0. " [0] ,Event 0 use as counter limit for L counter" "Not used,Used" line.word 0x02 "LIMIT_H,SCT Limit Register High Counter 16-bit" bitfld.word 0x02 5. " LIMMSK_H[5] ,Event 5 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 4. " [4] ,Event 4 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 3. " [3] ,Event 3 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 2. " [2] ,Event 2 use as counter limit for H counter" "Not used,Used" newline bitfld.word 0x02 1. " [1] ,Event 1 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 0. " [0] ,Event 0 use as counter limit for H counter" "Not used,Used" line.word 0x04 "HALT_L,SCT Halt Condition Register Low Counter 16-bit" bitfld.word 0x04 5. " HALTMSK_L[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 4. " [4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 3. " [3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 2. " [2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set" newline bitfld.word 0x04 1. " [1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 0. " [0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set" line.word 0x06 "HALT_H,SCT Halt Condition Register High Counter 16-bit" bitfld.word 0x06 5. " HALTMSK_H[5] ,Event 5 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 4. " [4] ,Event 4 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 3. " [3] ,Event 3 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 2. " [2] ,Event 2 sets HALT_H bit in CTRL register" "Not set,Set" newline bitfld.word 0x06 1. " [1] ,Event 1 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 0. " [0] ,Event 0 sets HALT_H bit in CTRL register" "Not set,Set" line.word 0x08 "STOP_L,SCT Stop Condition Register Low Counter 16-bit" bitfld.word 0x08 5. " STOPMSK_L[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 4. " [4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 3. " [3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 2. " [2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set" newline bitfld.word 0x08 1. " [1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 0. " [0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set" line.word 0x0A "STOP_H,SCT Stop Condition Register High Counter 16-bit" bitfld.word 0x0A 5. " STOPMSK_H[5] ,Event 5 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 4. " [4] ,Event 4 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 3. " [3] ,Event 3 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 2. " [2] ,Event 2 sets STOP_H bit in CTRL register" "Not set,Set" newline bitfld.word 0x0A 1. " [1] ,Event 1 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 0. " [0] ,Event 0 sets STOP_H bit in CTRL register" "Not set,Set" line.word 0x0C "START_L,SCT Start Condition Register Low Counter 16-bit" bitfld.word 0x0C 5. " STARTMSK_L[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 4. " [4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 3. " [3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 2. " [2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared" newline bitfld.word 0x0C 1. " [1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 0. " [0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared" line.word 0x0E "START_H,SCT Start Condition Register High Counter 16-bit" bitfld.word 0x0E 5. " STARTMSK_H[5] ,Event 5 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 4. " [4] ,Event 4 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 3. " [3] ,Event 3 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 2. " [2] ,Event 2 clears STOP_H bit in CTRL register" "Not cleared,Cleared" newline bitfld.word 0x0E 1. " [1] ,Event 1 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 0. " [0] ,Event 0 clears STOP_H bit in CTRL register" "Not cleared,Cleared" if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04) group.word 0x40++0x07 line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit" line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit" line.word 0x04 "STATE_L,SCT State Register Low Counter 16-bit" bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "STATE_H,SCT State Register High Counter 16-bit" bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.word 0x40++0x07 line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit" line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit" line.word 0x04 "STATE_L,SCT State Register Low Counter 16-bit" bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "STATE_H,SCT State Register High Counter 16-bit" bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x48++0x03 line.long 0x00 "INPUT,SCT Input Register" sif cpuis("LPC11U6?JBD48") bitfld.long 0x00 17. " SIN[1] ,Input 1 state" "Low,High" bitfld.long 0x00 1. " AIN[1] ,Input 1 state direct read" "Low,High" elif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 18. " [2] ,Input 2 state" "Low,High" bitfld.long 0x00 17. " [1] ,Input 1 state" "Low,High" bitfld.long 0x00 3. " AIN[3] ,Input 3 state direct read" "Low,High" newline bitfld.long 0x00 2. " [2] ,Input 2 state direct read" "Low,High" bitfld.long 0x00 1. " [1] ,Input 1 state direct read" "Low,High" else bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 18. " [2] ,Input 2 state" "Low,High" bitfld.long 0x00 17. " [1] ,Input 1 state" "Low,High" bitfld.long 0x00 16. " [0] ,Input 0 state" "Low,High" newline bitfld.long 0x00 3. " AIN[3] ,Input 3 state direct read" "Low,High" bitfld.long 0x00 2. " [2] ,Input 2 state direct read" "Low,High" bitfld.long 0x00 1. " [1] ,Input 1 state direct read" "Low,High" bitfld.long 0x00 0. " [0] ,Input 0 state direct read" "Low,High" endif group.word 0x4C++0x03 line.word 0x00 "REGMODE_L,SCT Match/capture Registers Mode Register Low Counter 16-bit" bitfld.word 0x00 4. " REGMOD_L[4] ,Pair 4 of match/capture register operation mode" "Match,Capture" bitfld.word 0x00 3. " [3] ,Pair 3 of match/capture register operation mode" "Match,Capture" bitfld.word 0x00 2. " [2] ,Pair 2 of match/capture register operation mode" "Match,Capture" bitfld.word 0x00 1. " [1] ,Pair 1 of match/capture register operation mode" "Match,Capture" newline bitfld.word 0x00 0. " [0] ,Pair 0 of match/capture register operation mode" "Match,Capture" line.word 0x02 "REGMODE_H,SCT Match/capture Registers Mode Register High Counter 16-bit" bitfld.word 0x02 4. " REGMOD_H[4] ,Pair 4 of match/capture register operation mode" "Match,Capture" bitfld.word 0x02 3. " [3] ,Pair 3 of match/capture register operation mode" "Match,Capture" bitfld.word 0x02 2. " [2] ,Pair 2 of match/capture register operation mode" "Match,Capture" bitfld.word 0x02 1. " [1] ,Pair 1 of match/capture register operation mode" "Match,Capture" newline bitfld.word 0x02 0. " [0] ,Pair 0 of match/capture register operation mode" "Match,Capture" endif sif cpuis("LPC11U6?JBD48") if (((((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)&&(((per.l(ad:0x5000C000))&0x01)==0x00))||((((per.l(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.l(ad:0x5000C000))&0x01)==0x01))) group.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" bitfld.long 0x00 1. " [1] ,Set high on output 1" "Low,High" else rgroup.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" bitfld.long 0x00 1. " [1] ,Set high on output 1" "Low,High" endif if (((per.l(ad:0x5000C000))&0x01)==0x00) group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 2.--3. " [1] ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." else group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 2.--3. " [1] ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." endif group.long 0x58++0x03 line.long 0x00 "RES,SCT Conflict Resolution Register" bitfld.long 0x00 6.--7. " O[3]RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle" bitfld.long 0x00 4.--5. " [2] ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle" bitfld.long 0x00 2.--3. " [1] ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle" else if (((((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04)&&(((per.l(ad:0x5000C000))&0x01)==0x00))||((((per.l(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.l(ad:0x5000C000))&0x01)==0x01))) group.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" bitfld.long 0x00 1. " [1] ,Set high on output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Set high on output 0" "Low,High" else rgroup.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" bitfld.long 0x00 1. " [1] ,Set high on output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Set high on output 0" "Low,High" endif if (((per.l(ad:0x5000C000))&0x01)==0x00) group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 2.--3. " [1] ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 0.--1. " [0] ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." else group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 2.--3. " [1] ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 0.--1. " [0] ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." endif group.long 0x58++0x03 line.long 0x00 "RES,SCT Conflict Resolution Register" bitfld.long 0x00 6.--7. " O[3]RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle" bitfld.long 0x00 4.--5. " [2] ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle" bitfld.long 0x00 2.--3. " [1] ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle" bitfld.long 0x00 0.--1. " [0] ,Effect of simultaneous set and clear on output 0" "No change,Set,Clear,Toggle" endif group.long 0x5C++0x07 line.long 0x00 "DMAREQ0,SCT DMA Request 0 Register" rbitfld.long 0x00 31. " DRQ0 ,Indicates the state of DMA request 0" "Low,High" bitfld.long 0x00 30. " DRL0 ,SCT set DMA request 0 when it loads the match_l/unified registers from the reload_l/unified registers" "Low,High" newline bitfld.long 0x00 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 sets DMA request 0" "Not set,Set" bitfld.long 0x00 3. " [3] ,Event 3 sets DMA request 0" "Not set,Set" bitfld.long 0x00 2. " [2] ,Event 2 sets DMA request 0" "Not set,Set" newline bitfld.long 0x00 1. " [1] ,Event 1 sets DMA request 0" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 sets DMA request 0" "Not set,Set" line.long 0x04 "DMAREQ1,SCT DMA Request 1 Register" rbitfld.long 0x04 31. " DRQ1 ,Indicates the state of DMA request 1" "Low,High" bitfld.long 0x04 30. " DRL1 ,SCT set DMA request 1 when it loads the match_l/unified registers from the reload_l/unified registers" "Low,High" newline bitfld.long 0x04 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 sets DMA request 1" "Not set,Set" bitfld.long 0x04 3. " [3] ,Event 3 sets DMA request 1" "Not set,Set" bitfld.long 0x04 2. " [2] ,Event 2 sets DMA request 1" "Not set,Set" newline bitfld.long 0x04 1. " [1] ,Event 1 sets DMA request 1" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 sets DMA request 1" "Not set,Set" group.long 0xF0++0x07 line.long 0x00 "EVEN,SCT Event Enable Register" bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,SCT conflict 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,SCT conflict 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,SCT conflict 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,SCT conflict 0 enable" "Disabled,Enabled" line.long 0x04 "EVFLAG,SCT Event Flag Register" bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 4. " [4] ,Event 4 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 3. " [3] ,Event 3 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 2. " [2] ,Event 2 occurred flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " [1] ,Event 1 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 0. " [0] ,Event 0 occurred flag" "Not occurred,Occurred" sif cpuis("LPC11U6?JBD48") group.long 0xF8++0x07 line.long 0x00 "CONEN,SCT Conflict Enable Register" bitfld.long 0x00 3. " NCEN[3] ,SCT conflict 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,SCT conflict 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,SCT conflict 1 enable" "Disabled,Enabled" line.long 0x04 "CONFLAG,SCT Conflict Flag Register" bitfld.long 0x04 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the output register when the H counter was not halted" "No error,Error" bitfld.long 0x04 30. " BUSERRL ,Error writing CTR l/unified STATE l/unified MATCH l/unified or the output register when the L/U counter was not halted" "No error,Error" bitfld.long 0x04 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred" bitfld.long 0x04 2. " [2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " [1] ,No-change event occurred on output 1 flag" "Not occurred,Occurred" else group.long 0xF8++0x07 line.long 0x00 "CONEN,SCT Conflict Enable Register" bitfld.long 0x00 3. " NCEN[3] ,SCT conflict 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,SCT conflict 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,SCT conflict 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,SCT conflict 0 enable" "Disabled,Enabled" line.long 0x04 "CONFLAG,SCT Conflict Flag Register" bitfld.long 0x04 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the output register when the H counter was not halted" "No error,Error" bitfld.long 0x04 30. " BUSERRL ,Error writing CTR l/unified STATE l/unified MATCH l/unified or the output register when the L/U counter was not halted" "No error,Error" bitfld.long 0x04 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred" bitfld.long 0x04 2. " [2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " [1] ,No-change event occurred on output 1 flag" "Not occurred,Occurred" bitfld.long 0x04 0. " [0] ,No-change event occurred on output 0 flag" "Not occurred,Occurred" endif width 10. tree "Match Value And Capture Registers" if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000C000+0x4C))&0x01)==0x01) rgroup.long 0x100++0x03 line.long 0x00 "CAP0,SCT Capture Register Of Capture Channel 0" else rgroup.long 0x100++0x03 line.long 0x00 "MATCH0,SCT Match Value Register Of Match Channel 0" endif else if (((per.l(ad:0x5000C000+0x4C))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "CAP0,SCT Capture Register Of Capture Channel 0" else group.long 0x100++0x03 line.long 0x00 "MATCH0,SCT Match Value Register Of Match Channel 0" endif endif else if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x01)==0x01) group.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else group.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x01)==0x01) group.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 High Counter 16-bit" else group.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x01)==0x01) rgroup.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else rgroup.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x01)==0x01) group.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 High Counter 16-bit" else group.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x01)==0x01) group.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else group.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x01)==0x01) rgroup.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else rgroup.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif else if (((per.w(ad:0x5000C000+0x4C))&0x01)==0x01) rgroup.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else rgroup.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x01)==0x01) rgroup.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 High Counter 16-bit" else rgroup.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000C000+0x4C))&0x02)==0x02) rgroup.long 0x104++0x03 line.long 0x00 "CAP1,SCT Capture Register Of Capture Channel 1" else rgroup.long 0x104++0x03 line.long 0x00 "MATCH1,SCT Match Value Register Of Match Channel 1" endif else if (((per.l(ad:0x5000C000+0x4C))&0x02)==0x02) group.long 0x104++0x03 line.long 0x00 "CAP1,SCT Capture Register Of Capture Channel 1" else group.long 0x104++0x03 line.long 0x00 "MATCH1,SCT Match Value Register Of Match Channel 1" endif endif else if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x02)==0x02) group.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else group.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x02)==0x02) group.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 High Counter 16-bit" else group.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x02)==0x02) rgroup.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else rgroup.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x02)==0x02) group.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 High Counter 16-bit" else group.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x02)==0x02) group.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else group.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x02)==0x02) rgroup.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else rgroup.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif else if (((per.w(ad:0x5000C000+0x4C))&0x02)==0x02) rgroup.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else rgroup.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x02)==0x02) rgroup.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 High Counter 16-bit" else rgroup.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000C000+0x4C))&0x04)==0x04) rgroup.long 0x108++0x03 line.long 0x00 "CAP2,SCT Capture Register Of Capture Channel 2" else rgroup.long 0x108++0x03 line.long 0x00 "MATCH2,SCT Match Value Register Of Match Channel 2" endif else if (((per.l(ad:0x5000C000+0x4C))&0x04)==0x04) group.long 0x108++0x03 line.long 0x00 "CAP2,SCT Capture Register Of Capture Channel 2" else group.long 0x108++0x03 line.long 0x00 "MATCH2,SCT Match Value Register Of Match Channel 2" endif endif else if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x04)==0x04) group.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else group.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x04)==0x04) group.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 High Counter 16-bit" else group.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x04)==0x04) rgroup.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else rgroup.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x04)==0x04) group.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 High Counter 16-bit" else group.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x04)==0x04) group.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else group.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x04)==0x04) rgroup.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else rgroup.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif else if (((per.w(ad:0x5000C000+0x4C))&0x04)==0x04) rgroup.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else rgroup.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x04)==0x04) rgroup.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 High Counter 16-bit" else rgroup.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000C000+0x4C))&0x08)==0x08) rgroup.long 0x10C++0x03 line.long 0x00 "CAP3,SCT Capture Register Of Capture Channel 3" else rgroup.long 0x10C++0x03 line.long 0x00 "MATCH3,SCT Match Value Register Of Match Channel 3" endif else if (((per.l(ad:0x5000C000+0x4C))&0x08)==0x08) group.long 0x10C++0x03 line.long 0x00 "CAP3,SCT Capture Register Of Capture Channel 3" else group.long 0x10C++0x03 line.long 0x00 "MATCH3,SCT Match Value Register Of Match Channel 3" endif endif else if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x08)==0x08) group.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else group.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x08)==0x08) group.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 High Counter 16-bit" else group.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x08)==0x08) rgroup.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else rgroup.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x08)==0x08) group.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 High Counter 16-bit" else group.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x08)==0x08) group.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else group.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x08)==0x08) rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif else if (((per.w(ad:0x5000C000+0x4C))&0x08)==0x08) rgroup.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else rgroup.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x08)==0x08) rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 High Counter 16-bit" else rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000C000+0x4C))&0x10)==0x10) rgroup.long 0x110++0x03 line.long 0x00 "CAP4,SCT Capture Register Of Capture Channel 4" else rgroup.long 0x110++0x03 line.long 0x00 "MATCH4,SCT Match Value Register Of Match Channel 4" endif else if (((per.l(ad:0x5000C000+0x4C))&0x10)==0x10) group.long 0x110++0x03 line.long 0x00 "CAP4,SCT Capture Register Of Capture Channel 4" else group.long 0x110++0x03 line.long 0x00 "MATCH4,SCT Match Value Register Of Match Channel 4" endif endif else if (((per.w(ad:0x5000C000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10) group.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else group.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10) group.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 High Counter 16-bit" else group.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10) rgroup.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else rgroup.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10) group.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 High Counter 16-bit" else group.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 High Counter 16-bit" endif elif (((per.w(ad:0x5000C000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10) group.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else group.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10) rgroup.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else rgroup.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif else if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10) rgroup.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else rgroup.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10) rgroup.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 High Counter 16-bit" else rgroup.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 High Counter 16-bit" endif endif endif tree.end width 13. tree "Match Reload And Capture Control Registers" if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x4C))&0x01)==0x01) group.long 0x200++0x03 line.long 0x00 "CAPCTRL0 ,SCT Capture Control Register 0 " bitfld.long 0x00 5. " CAPCON0 [5] ,Event 5 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP0 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP0 register" "Not occurred,Occurred" else group.long 0x200++0x03 line.long 0x00 "MATCHREL0 ,SCT Match Reload Value Register 0 " endif else if (((per.w(ad:0x5000C000+0x4C))&0x01)==0x01) group.word 0x200++0x01 line.word 0x00 "CAPCTRL0 _L,SCT Capture Control Register 0 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON0 _L[5] ,Event 5 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP0 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP0 _L register" "Not occurred,Occurred" else group.word 0x200++0x01 line.word 0x00 "MATCHREL0 _L,SCT Match Reload Value Register 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x01)==0x01) group.word (0x200+0x02)++0x01 line.word 0x00 "CAPCTRL0 _H,SCT Capture Control Register 0 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON0 _H[5] ,Event 5 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP0 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP0 _H register" "Not occurred,Occurred" else group.word (0x200+0x02)++0x01 line.word 0x00 "MATCHREL0 _H,SCT Match Reload Value Register 0 High Counter 16-bit" endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x4C))&0x02)==0x02) group.long 0x204++0x03 line.long 0x00 "CAPCTRL1 ,SCT Capture Control Register 1 " bitfld.long 0x00 5. " CAPCON1 [5] ,Event 5 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP1 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP1 register" "Not occurred,Occurred" else group.long 0x204++0x03 line.long 0x00 "MATCHREL1 ,SCT Match Reload Value Register 1 " endif else if (((per.w(ad:0x5000C000+0x4C))&0x02)==0x02) group.word 0x204++0x01 line.word 0x00 "CAPCTRL1 _L,SCT Capture Control Register 1 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON1 _L[5] ,Event 5 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP1 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP1 _L register" "Not occurred,Occurred" else group.word 0x204++0x01 line.word 0x00 "MATCHREL1 _L,SCT Match Reload Value Register 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x02)==0x02) group.word (0x204+0x02)++0x01 line.word 0x00 "CAPCTRL1 _H,SCT Capture Control Register 1 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON1 _H[5] ,Event 5 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP1 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP1 _H register" "Not occurred,Occurred" else group.word (0x204+0x02)++0x01 line.word 0x00 "MATCHREL1 _H,SCT Match Reload Value Register 1 High Counter 16-bit" endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x4C))&0x04)==0x04) group.long 0x208++0x03 line.long 0x00 "CAPCTRL2 ,SCT Capture Control Register 2 " bitfld.long 0x00 5. " CAPCON2 [5] ,Event 5 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP2 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP2 register" "Not occurred,Occurred" else group.long 0x208++0x03 line.long 0x00 "MATCHREL2 ,SCT Match Reload Value Register 2 " endif else if (((per.w(ad:0x5000C000+0x4C))&0x04)==0x04) group.word 0x208++0x01 line.word 0x00 "CAPCTRL2 _L,SCT Capture Control Register 2 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON2 _L[5] ,Event 5 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP2 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP2 _L register" "Not occurred,Occurred" else group.word 0x208++0x01 line.word 0x00 "MATCHREL2 _L,SCT Match Reload Value Register 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x04)==0x04) group.word (0x208+0x02)++0x01 line.word 0x00 "CAPCTRL2 _H,SCT Capture Control Register 2 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON2 _H[5] ,Event 5 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP2 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP2 _H register" "Not occurred,Occurred" else group.word (0x208+0x02)++0x01 line.word 0x00 "MATCHREL2 _H,SCT Match Reload Value Register 2 High Counter 16-bit" endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x4C))&0x08)==0x08) group.long 0x20C++0x03 line.long 0x00 "CAPCTRL3 ,SCT Capture Control Register 3 " bitfld.long 0x00 5. " CAPCON3 [5] ,Event 5 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP3 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP3 register" "Not occurred,Occurred" else group.long 0x20C++0x03 line.long 0x00 "MATCHREL3 ,SCT Match Reload Value Register 3 " endif else if (((per.w(ad:0x5000C000+0x4C))&0x08)==0x08) group.word 0x20C++0x01 line.word 0x00 "CAPCTRL3 _L,SCT Capture Control Register 3 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON3 _L[5] ,Event 5 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP3 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP3 _L register" "Not occurred,Occurred" else group.word 0x20C++0x01 line.word 0x00 "MATCHREL3 _L,SCT Match Reload Value Register 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x08)==0x08) group.word (0x20C+0x02)++0x01 line.word 0x00 "CAPCTRL3 _H,SCT Capture Control Register 3 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON3 _H[5] ,Event 5 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP3 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP3 _H register" "Not occurred,Occurred" else group.word (0x20C+0x02)++0x01 line.word 0x00 "MATCHREL3 _H,SCT Match Reload Value Register 3 High Counter 16-bit" endif endif if (((per.l(ad:0x5000C000))&0x01)==0x01) if (((per.l(ad:0x5000C000+0x4C))&0x10)==0x10) group.long 0x210++0x03 line.long 0x00 "CAPCTRL4 ,SCT Capture Control Register 4 " bitfld.long 0x00 5. " CAPCON4 [5] ,Event 5 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP4 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP4 register" "Not occurred,Occurred" else group.long 0x210++0x03 line.long 0x00 "MATCHREL4 ,SCT Match Reload Value Register 4 " endif else if (((per.w(ad:0x5000C000+0x4C))&0x10)==0x10) group.word 0x210++0x01 line.word 0x00 "CAPCTRL4 _L,SCT Capture Control Register 4 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON4 _L[5] ,Event 5 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP4 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP4 _L register" "Not occurred,Occurred" else group.word 0x210++0x01 line.word 0x00 "MATCHREL4 _L,SCT Match Reload Value Register 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000C000+0x4E))&0x10)==0x10) group.word (0x210+0x02)++0x01 line.word 0x00 "CAPCTRL4 _H,SCT Capture Control Register 4 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON4 _H[5] ,Event 5 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP4 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP4 _H register" "Not occurred,Occurred" else group.word (0x210+0x02)++0x01 line.word 0x00 "MATCHREL4 _H,SCT Match Reload Value Register 4 High Counter 16-bit" endif endif tree.end width 11. tree "Event State And Control Registers" group.long 0x300++0x03 line.long 0x00 "EV0 _STATE,SCT Event State Register 0 " bitfld.long 0x00 7. " STATEMSK0 [7] ,State 7 of event 0 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 0 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 0 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 0 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 0 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 0 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 0 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 0 select" "Not selected,Selected" if (((per.l(ad:0x5000C000))&0x01)==0x01) group.long (0x300+0x04)++0x03 line.long 0x00 "EV0 _CTRL,SCT Event Control Register 0 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x300+0x04)++0x03 line.long 0x00 "EV0 _CTRL,SCT Event Control Register 0 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x308++0x03 line.long 0x00 "EV1 _STATE,SCT Event State Register 1 " bitfld.long 0x00 7. " STATEMSK1 [7] ,State 7 of event 1 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 1 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 1 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 1 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 1 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 1 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 1 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 1 select" "Not selected,Selected" if (((per.l(ad:0x5000C000))&0x01)==0x01) group.long (0x308+0x04)++0x03 line.long 0x00 "EV1 _CTRL,SCT Event Control Register 1 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x308+0x04)++0x03 line.long 0x00 "EV1 _CTRL,SCT Event Control Register 1 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x310++0x03 line.long 0x00 "EV2 _STATE,SCT Event State Register 2 " bitfld.long 0x00 7. " STATEMSK2 [7] ,State 7 of event 2 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 2 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 2 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 2 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 2 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 2 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 2 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 2 select" "Not selected,Selected" if (((per.l(ad:0x5000C000))&0x01)==0x01) group.long (0x310+0x04)++0x03 line.long 0x00 "EV2 _CTRL,SCT Event Control Register 2 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x310+0x04)++0x03 line.long 0x00 "EV2 _CTRL,SCT Event Control Register 2 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x318++0x03 line.long 0x00 "EV3 _STATE,SCT Event State Register 3 " bitfld.long 0x00 7. " STATEMSK3 [7] ,State 7 of event 3 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 3 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 3 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 3 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 3 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 3 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 3 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 3 select" "Not selected,Selected" if (((per.l(ad:0x5000C000))&0x01)==0x01) group.long (0x318+0x04)++0x03 line.long 0x00 "EV3 _CTRL,SCT Event Control Register 3 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x318+0x04)++0x03 line.long 0x00 "EV3 _CTRL,SCT Event Control Register 3 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x320++0x03 line.long 0x00 "EV4 _STATE,SCT Event State Register 4 " bitfld.long 0x00 7. " STATEMSK4 [7] ,State 7 of event 4 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 4 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 4 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 4 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 4 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 4 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 4 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 4 select" "Not selected,Selected" if (((per.l(ad:0x5000C000))&0x01)==0x01) group.long (0x320+0x04)++0x03 line.long 0x00 "EV4 _CTRL,SCT Event Control Register 4 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x320+0x04)++0x03 line.long 0x00 "EV4 _CTRL,SCT Event Control Register 4 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x328++0x03 line.long 0x00 "EV5 _STATE,SCT Event State Register 5 " bitfld.long 0x00 7. " STATEMSK5 [7] ,State 7 of event 5 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 5 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 5 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 5 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 5 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 5 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 5 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 5 select" "Not selected,Selected" if (((per.l(ad:0x5000C000))&0x01)==0x01) group.long (0x328+0x04)++0x03 line.long 0x00 "EV5 _CTRL,SCT Event Control Register 5 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x328+0x04)++0x03 line.long 0x00 "EV5 _CTRL,SCT Event Control Register 5 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 10. tree "Output Set/Clear Registers" sif cpuis("LPC11U6?JBD48") group.long 0x508++0x07 line.long 0x00 "OUT1_SET,SCT Output 1 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 1" "Not cleared,Cleared" bitfld.long 0x00 4. " [4] ,Event 4 set output 1" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 1" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 1" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 1" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 1" "Not cleared,Cleared" line.long 0x04 "OUT1_CLR,SCT Output 1 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 1" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 1" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 1" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 1" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 1" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 1" "Not cleared,Cleared" group.long 0x510++0x07 line.long 0x00 "OUT2_SET,SCT Output 2 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not cleared,Cleared" bitfld.long 0x00 4. " [4] ,Event 4 set output 2" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 2" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 2" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 2" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 2" "Not cleared,Cleared" line.long 0x04 "OUT2_CLR,SCT Output 2 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 2" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 2" "Not cleared,Cleared" group.long 0x518++0x07 line.long 0x00 "OUT3_SET,SCT Output 3 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not cleared,Cleared" bitfld.long 0x00 4. " [4] ,Event 4 set output 3" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 3" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 3" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 3" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 3" "Not cleared,Cleared" line.long 0x04 "OUT3_CLR,SCT Output 3 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 3" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 3" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 3" "Not cleared,Cleared" else group.long 0x500++0x07 line.long 0x00 "OUT0_SET,SCT Output 0 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 0" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 0" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 0" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 0" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 0" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 0" "Not cleared,Cleared" line.long 0x04 "OUT0_CLR,SCT Output 0 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 0" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 0" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 0" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 0" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 0" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 0" "Not cleared,Cleared" group.long 0x508++0x07 line.long 0x00 "OUT1_SET,SCT Output 1 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 1" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 1" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 1" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 1" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 1" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 1" "Not cleared,Cleared" line.long 0x04 "OUT1_CLR,SCT Output 1 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 1" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 1" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 1" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 1" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 1" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 1" "Not cleared,Cleared" group.long 0x510++0x07 line.long 0x00 "OUT2_SET,SCT Output 2 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 2" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 2" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 2" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 2" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 2" "Not cleared,Cleared" line.long 0x04 "OUT2_CLR,SCT Output 2 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 2" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 2" "Not cleared,Cleared" group.long 0x518++0x07 line.long 0x00 "OUT3_SET,SCT Output 3 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 3" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 3" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 3" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 3" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 3" "Not cleared,Cleared" line.long 0x04 "OUT3_CLR,SCT Output 3 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 3" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 3" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 3" "Not cleared,Cleared" endif tree.end width 0x0B tree.end tree "SCT1" base ad:0x5000E000 width 15. group.long 0x00++0x03 line.long 0x00 "CONFIG,SCT Configuration Register" bitfld.long 0x00 18. " AUTOLIMIT_H ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto" bitfld.long 0x00 17. " AUTOLIMIT_L ,Match on match register 0 is treated as a LIMIT condition" "Manual,Auto" newline sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 12. " INSYNC[3] ,Synchronization for input 3" "Not synchronized,Synchronized" elif cpuis("LPC11U6?JBD100") bitfld.long 0x00 12. " INSYNC[3] ,Synchronization for input 3" "Not synchronized,Synchronized" bitfld.long 0x00 11. " [2] ,Synchronization for input 2" "Not synchronized,Synchronized" bitfld.long 0x00 10. " [1] ,Synchronization for input 1" "Not synchronized,Synchronized" bitfld.long 0x00 9. " [0] ,Synchronization for input 0" "Not synchronized,Synchronized" endif newline bitfld.long 0x00 8. " NORELOAD_H ,Prevent the higher match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented" bitfld.long 0x00 7. " NORELOAD_L ,Prevent the lower match and fractional match registers from being reloaded from their respective reload registers" "Allowed,Prevented" newline sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input" ",,,,,,Rising 3,Falling 3,?..." elif cpuis("LPC11U6?JBD100") bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input" "Rising 0,Falling 0,Rising 1,Falling 1,Rising 2,Falling 2,Rising 3,Falling 3,?..." else bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select on input" "?..." endif newline bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "Bus for all,Bus for SCT,CKSEL for all,Prescaled SCT" bitfld.long 0x00 0. " UNIFY ,SCT operate as unified 32-bit counter" "Not unified,Unified" if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x04))&0x06)==0x00) group.long 0x04++0x03 line.long 0x00 "CTRL,SCT Control Register" hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock" rbitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down" rbitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared" bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted" newline bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped" rbitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down" else group.long 0x04++0x03 line.long 0x00 "CTRL,SCT Control Register" hexmask.long.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce unified counter clock" bitfld.long 0x00 4. " BIDIR ,Unified counter direction select" "Limit then zero,Limit then down" bitfld.long 0x00 3. " CLRCTR ,Unified counter clear" "Not cleared,Cleared" bitfld.long 0x00 2. " HALT ,Unified counter halt" "Not halted,Halted" newline bitfld.long 0x00 1. " STOP ,Unified counter stop" "Not stopped,Stopped" bitfld.long 0x00 0. " DOWN ,Unified counter counting down" "Counting up,Counting down" endif group.long 0x08++0x0F line.long 0x00 "LIMIT,SCT Limit Register" bitfld.long 0x00 5. " LIMMSK[5] ,Event 5 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 4. " [4] ,Event 4 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 3. " [3] ,Event 3 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 2. " [2] ,Event 2 use as counter limit for unified counter" "Not used,Used" newline bitfld.long 0x00 1. " [1] ,Event 1 use as counter limit for unified counter" "Not used,Used" bitfld.long 0x00 0. " [0] ,Event 0 use as counter limit for unified counter" "Not used,Used" line.long 0x04 "HALT,SCT Halt Condition Register" bitfld.long 0x04 5. " HALTMSK[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 3. " [3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 2. " [2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set" newline bitfld.long 0x04 1. " [1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set" line.long 0x08 "STOP,SCT Stop Condition Register" bitfld.long 0x08 5. " STOPMSK[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 4. " [4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 3. " [3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 2. " [2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set" newline bitfld.long 0x08 1. " [1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.long 0x08 0. " [0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set" line.long 0x0C "START,SCT Start Condition Register" bitfld.long 0x0C 5. " STARTMSK[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 4. " [4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 3. " [3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 2. " [2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared" newline bitfld.long 0x0C 1. " [1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.long 0x0C 0. " [0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared" if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00) rgroup.long 0x40++0x07 line.long 0x00 "COUNT,SCT Counter Register" line.long 0x04 "STATE,SCT State Register" bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x40++0x07 line.long 0x00 "COUNT,SCT Counter Register" line.long 0x04 "STATE,SCT State Register" bitfld.long 0x04 0.--4. " STATE ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x48++0x03 line.long 0x00 "INPUT,SCT Input Register" sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 3. " AIN[3] ,Input 3 state direct read" "Low,High" elif cpuis("LPC11U6?JBD100") bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 18. " [2] ,Input 2 state" "Low,High" bitfld.long 0x00 17. " [1] ,Input 1 state" "Low,High" bitfld.long 0x00 16. " [0] ,Input 0 state" "Low,High" newline bitfld.long 0x00 3. " AIN[3] ,Input 3 state direct read" "Low,High" bitfld.long 0x00 2. " [2] ,Input 2 state direct read" "Low,High" bitfld.long 0x00 1. " [1] ,Input 1 state direct read" "Low,High" bitfld.long 0x00 0. " [0] ,Input 0 state direct read" "Low,High" endif group.long 0x4C++0x03 line.long 0x00 "REGMODE,SCT Match/Capture Registers Mode Register" bitfld.long 0x00 4. " REGMOD[4] ,Pair 4 of match/capture register operation mode" "Match,Capture" bitfld.long 0x00 3. " [3] ,Pair 3 of match/capture register operation mode" "Match,Capture" bitfld.long 0x00 2. " [2] ,Pair 2 of match/capture register operation mode" "Match,Capture" bitfld.long 0x00 1. " [1] ,Pair 1 of match/capture register operation mode" "Match,Capture" newline bitfld.long 0x00 0. " [0] ,Pair 0 of match/capture register operation mode" "Match,Capture" else if (((per.w(ad:0x5000E000+0x04))&0x06)==0x00) group.word 0x04++0x03 line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock" rbitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down" rbitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped" rbitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down" else group.word 0x04++0x03 line.word 0x00 "CTRL_L,SCT Control Register Low Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_L ,Factor by which the SCT clock is prescaled to produce L counter clock" bitfld.word 0x00 4. " BIDIR_L ,L counter direction select" "Limit then zero,Limit then down" bitfld.word 0x00 3. " CLRCTR_L ,L counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_L ,L counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_L ,L counter stop" "Not stopped,Stopped" bitfld.word 0x00 0. " DOWN_L ,L counter counting down" "Counting up,Counting down" endif if (((per.w(ad:0x5000E000+0x06))&0x06)==0x00) group.word 0x06++0x01 line.word 0x00 "CTRL_H,SCT Control Register High Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock" rbitfld.word 0x00 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down" rbitfld.word 0x00 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_H ,H counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_H ,H counter stop" "Not stopped,Stopped" rbitfld.word 0x00 0. " DOWN_H ,H counter counting down" "Counting up,Counting down" else group.word 0x06++0x01 line.word 0x00 "CTRL_H,SCT Control Register High Counter 16-bit" hexmask.word.byte 0x00 5.--12. 1. " PRE_H ,Factor by which the SCT clock is prescaled to produce H counter clock" bitfld.word 0x00 4. " BIDIR_H ,H counter direction select" "Limit then zero,Limit then down" bitfld.word 0x00 3. " CLRCTR_H ,H counter clear" "Not cleared,Cleared" bitfld.word 0x00 2. " HALT_H ,H counter halt" "Not halted,Halted" newline bitfld.word 0x00 1. " STOP_H ,H counter stop" "Not stopped,Stopped" bitfld.word 0x00 0. " DOWN_H ,H counter counting down" "Counting up,Counting down" endif group.word 0x08++0x0F line.word 0x00 "LIMIT_L,SCT Limit Register Low Counter 16-bit" bitfld.word 0x00 5. " LIMMSK_L[5] ,Event 5 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 4. " [4] ,Event 4 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 3. " [3] ,Event 3 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 2. " [2] ,Event 2 use as counter limit for L counter" "Not used,Used" newline bitfld.word 0x00 1. " [1] ,Event 1 use as counter limit for L counter" "Not used,Used" bitfld.word 0x00 0. " [0] ,Event 0 use as counter limit for L counter" "Not used,Used" line.word 0x02 "LIMIT_H,SCT Limit Register High Counter 16-bit" bitfld.word 0x02 5. " LIMMSK_H[5] ,Event 5 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 4. " [4] ,Event 4 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 3. " [3] ,Event 3 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 2. " [2] ,Event 2 use as counter limit for H counter" "Not used,Used" newline bitfld.word 0x02 1. " [1] ,Event 1 use as counter limit for H counter" "Not used,Used" bitfld.word 0x02 0. " [0] ,Event 0 use as counter limit for H counter" "Not used,Used" line.word 0x04 "HALT_L,SCT Halt Condition Register Low Counter 16-bit" bitfld.word 0x04 5. " HALTMSK_L[5] ,Event 5 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 4. " [4] ,Event 4 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 3. " [3] ,Event 3 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 2. " [2] ,Event 2 sets HALT_L bit in CTRL register" "Not set,Set" newline bitfld.word 0x04 1. " [1] ,Event 1 sets HALT_L bit in CTRL register" "Not set,Set" bitfld.word 0x04 0. " [0] ,Event 0 sets HALT_L bit in CTRL register" "Not set,Set" line.word 0x06 "HALT_H,SCT Halt Condition Register High Counter 16-bit" bitfld.word 0x06 5. " HALTMSK_H[5] ,Event 5 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 4. " [4] ,Event 4 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 3. " [3] ,Event 3 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 2. " [2] ,Event 2 sets HALT_H bit in CTRL register" "Not set,Set" newline bitfld.word 0x06 1. " [1] ,Event 1 sets HALT_H bit in CTRL register" "Not set,Set" bitfld.word 0x06 0. " [0] ,Event 0 sets HALT_H bit in CTRL register" "Not set,Set" line.word 0x08 "STOP_L,SCT Stop Condition Register Low Counter 16-bit" bitfld.word 0x08 5. " STOPMSK_L[5] ,Event 5 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 4. " [4] ,Event 4 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 3. " [3] ,Event 3 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 2. " [2] ,Event 2 sets STOP_L bit in CTRL register" "Not set,Set" newline bitfld.word 0x08 1. " [1] ,Event 1 sets STOP_L bit in CTRL register" "Not set,Set" bitfld.word 0x08 0. " [0] ,Event 0 sets STOP_L bit in CTRL register" "Not set,Set" line.word 0x0A "STOP_H,SCT Stop Condition Register High Counter 16-bit" bitfld.word 0x0A 5. " STOPMSK_H[5] ,Event 5 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 4. " [4] ,Event 4 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 3. " [3] ,Event 3 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 2. " [2] ,Event 2 sets STOP_H bit in CTRL register" "Not set,Set" newline bitfld.word 0x0A 1. " [1] ,Event 1 sets STOP_H bit in CTRL register" "Not set,Set" bitfld.word 0x0A 0. " [0] ,Event 0 sets STOP_H bit in CTRL register" "Not set,Set" line.word 0x0C "START_L,SCT Start Condition Register Low Counter 16-bit" bitfld.word 0x0C 5. " STARTMSK_L[5] ,Event 5 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 4. " [4] ,Event 4 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 3. " [3] ,Event 3 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 2. " [2] ,Event 2 clears STOP_L bit in CTRL register" "Not cleared,Cleared" newline bitfld.word 0x0C 1. " [1] ,Event 1 clears STOP_L bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0C 0. " [0] ,Event 0 clears STOP_L bit in CTRL register" "Not cleared,Cleared" line.word 0x0E "START_H,SCT Start Condition Register High Counter 16-bit" bitfld.word 0x0E 5. " STARTMSK_H[5] ,Event 5 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 4. " [4] ,Event 4 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 3. " [3] ,Event 3 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 2. " [2] ,Event 2 clears STOP_H bit in CTRL register" "Not cleared,Cleared" newline bitfld.word 0x0E 1. " [1] ,Event 1 clears STOP_H bit in CTRL register" "Not cleared,Cleared" bitfld.word 0x0E 0. " [0] ,Event 0 clears STOP_H bit in CTRL register" "Not cleared,Cleared" if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04) group.word 0x40++0x07 line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit" line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit" line.word 0x04 "STATE_L,SCT State Register Low Counter 16-bit" bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "STATE_H,SCT State Register High Counter 16-bit" bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else rgroup.word 0x40++0x07 line.word 0x00 "COUNT_L,SCT Counter Register Low Counter 16-bit" line.word 0x02 "COUNT_H,SCT Counter Register High Counter 16-bit" line.word 0x04 "STATE_L,SCT State Register Low Counter 16-bit" bitfld.word 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.word 0x06 "STATE_H,SCT State Register High Counter 16-bit" bitfld.word 0x06 0.--4. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x48++0x03 line.long 0x00 "INPUT,SCT Input Register" sif cpuis("LPC11U6?JBD64") bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 3. " AIN[3] ,Input 3 Statedirect read" "Low,High" elif cpuis("LPC11U6?JBD100") bitfld.long 0x00 19. " SIN[3] ,Input 3 state" "Low,High" bitfld.long 0x00 18. " [2] ,Input 2 state" "Low,High" bitfld.long 0x00 17. " [1] ,Input 1 state" "Low,High" bitfld.long 0x00 16. " [0] ,Input 0 state" "Low,High" newline bitfld.long 0x00 3. " AIN[3] ,Input 3 Statedirect read" "Low,High" bitfld.long 0x00 2. " [2] ,Input 2 Statedirect read" "Low,High" bitfld.long 0x00 1. " [1] ,Input 1 Statedirect read" "Low,High" bitfld.long 0x00 0. " [0] ,Input 0 Statedirect read" "Low,High" endif group.word 0x4C++0x03 line.word 0x00 "REGMODE_L,SCT Match/capture Registers Mode Register Low Counter 16-bit" bitfld.word 0x00 4. " REGMOD_L[4] ,Pair 4 of match/capture register operation mode" "Match,Capture" bitfld.word 0x00 3. " [3] ,Pair 3 of match/capture register operation mode" "Match,Capture" bitfld.word 0x00 2. " [2] ,Pair 2 of match/capture register operation mode" "Match,Capture" bitfld.word 0x00 1. " [1] ,Pair 1 of match/capture register operation mode" "Match,Capture" newline bitfld.word 0x00 0. " [0] ,Pair 0 of match/capture register operation mode" "Match,Capture" line.word 0x02 "REGMODE_H,SCT Match/capture Registers Mode Register High Counter 16-bit" bitfld.word 0x02 4. " REGMOD_H[4] ,Pair 4 of match/capture register operation mode" "Match,Capture" bitfld.word 0x02 3. " [3] ,Pair 3 of match/capture register operation mode" "Match,Capture" bitfld.word 0x02 2. " [2] ,Pair 2 of match/capture register operation mode" "Match,Capture" bitfld.word 0x02 1. " [1] ,Pair 1 of match/capture register operation mode" "Match,Capture" newline bitfld.word 0x02 0. " [0] ,Pair 0 of match/capture register operation mode" "Match,Capture" endif sif cpuis("LPC11U6?JBD64") if (((((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)&&(((per.l(ad:0x5000E000))&0x01)==0x00))||((((per.l(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.l(ad:0x5000E000))&0x01)==0x01))) group.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" else rgroup.long 0x50++0x03 line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" endif if (((per.l(ad:0x5000E000))&0x01)==0x00) group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." else group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." endif group.long 0x58++0x03 line.long 0x00 "RES,SCT Conflict Resolution Register" bitfld.long 0x00 6.--7. " O[3]RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle" bitfld.long 0x00 4.--5. " [2] ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle" else if (((((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04)&&(((per.l(ad:0x5000E000))&0x01)==0x00))||((((per.l(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.l(ad:0x5000E000))&0x01)==0x01))) group.long 0x50++0x0B line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" bitfld.long 0x00 1. " [1] ,Set high on output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Set high on output 0" "Low,High" else rgroup.long 0x50++0x0B line.long 0x00 "OUTPUT,SCT Output Register" bitfld.long 0x00 3. " OUT[3] ,Set high on output 3" "Low,High" bitfld.long 0x00 2. " [2] ,Set high on output 2" "Low,High" bitfld.long 0x00 1. " [1] ,Set high on output 1" "Low,High" bitfld.long 0x00 0. " [0] ,Set high on output 0" "Low,High" endif if (((per.l(ad:0x5000E000))&0x01)==0x00) group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 2.--3. " [1] ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." bitfld.long 0x00 0.--1. " [0] ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,Reversed when H,?..." else group.long 0x54++0x03 line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register" bitfld.long 0x00 6.--7. " SETCLR[3] ,Set/clear operation on output 3 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 4.--5. " [2] ,Set/clear operation on output 2 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 2.--3. " [1] ,Set/clear operation on output 1 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." bitfld.long 0x00 0.--1. " [0] ,Set/clear operation on output 0 depending on which counter is counting down" "Independent,Reversed when L or uni,?..." endif group.long 0x58++0x03 line.long 0x00 "RES,SCT Conflict Resolution Register" bitfld.long 0x00 6.--7. " O[3]RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle" bitfld.long 0x00 4.--5. " [2] ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle" bitfld.long 0x00 2.--3. " [1] ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle" bitfld.long 0x00 0.--1. " [0] ,Effect of simultaneous set and clear on output 0" "No change,Set,Clear,Toggle" endif group.long 0x5C++0x07 line.long 0x00 "DMAREQ0,SCT DMA Request 0 Register" rbitfld.long 0x00 31. " DRQ0 ,Indicates the state of DMA request 0" "Low,High" bitfld.long 0x00 30. " DRL0 ,SCT set DMA request 0 when it loads the match_l/unified registers from the reload_l/unified registers" "Low,High" newline bitfld.long 0x00 5. " DEV_0[5] ,Event 5 sets DMA request 0" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 sets DMA request 0" "Not set,Set" bitfld.long 0x00 3. " [3] ,Event 3 sets DMA request 0" "Not set,Set" bitfld.long 0x00 2. " [2] ,Event 2 sets DMA request 0" "Not set,Set" newline bitfld.long 0x00 1. " [1] ,Event 1 sets DMA request 0" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 sets DMA request 0" "Not set,Set" line.long 0x04 "DMAREQ1,SCT DMA Request 1 Register" rbitfld.long 0x04 31. " DRQ1 ,Indicates the state of DMA request 1" "Low,High" bitfld.long 0x04 30. " DRL1 ,SCT set DMA request 1 when it loads the match_l/unified registers from the reload_l/unified registers" "Low,High" newline bitfld.long 0x04 5. " DEV_1[5] ,Event 5 sets DMA request 1" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 sets DMA request 1" "Not set,Set" bitfld.long 0x04 3. " [3] ,Event 3 sets DMA request 1" "Not set,Set" bitfld.long 0x04 2. " [2] ,Event 2 sets DMA request 1" "Not set,Set" newline bitfld.long 0x04 1. " [1] ,Event 1 sets DMA request 1" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 sets DMA request 1" "Not set,Set" group.long 0xF0++0x07 line.long 0x00 "EVEN,SCT Event Enable Register" bitfld.long 0x00 5. " IEN[5] ,Event 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Event 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,SCT conflict 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,SCT conflict 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,SCT conflict 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,SCT conflict 0 enable" "Disabled,Enabled" line.long 0x04 "EVFLAG,SCT Event Flag Register" bitfld.long 0x04 5. " FLAG[5] ,Event 5 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 4. " [4] ,Event 4 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 3. " [3] ,Event 3 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 2. " [2] ,Event 2 occurred flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " [1] ,Event 1 occurred flag" "Not occurred,Occurred" bitfld.long 0x04 0. " [0] ,Event 0 occurred flag" "Not occurred,Occurred" sif cpuis("LPC11U6?JBD64") group.long 0xF8++0x07 line.long 0x00 "CONEN,SCT Conflict Enable Register" bitfld.long 0x00 3. " NCEN[3] ,SCT conflict 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,SCT conflict 2 enable" "Disabled,Enabled" line.long 0x04 "CONFLAG,SCT Conflict Flag Register" bitfld.long 0x04 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the output register when the H counter was not halted" "No error,Error" bitfld.long 0x04 30. " BUSERRL ,Error writing CTR l/unified STATE l/unified MATCH l/unified or the output register when the L/U counter was not halted" "No error,Error" bitfld.long 0x04 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred" bitfld.long 0x04 2. " [2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred" elif cpuis("LPC11U6?JBD100") group.long 0xF8++0x07 line.long 0x00 "CONEN,SCT Conflict Enable Register" bitfld.long 0x00 3. " NCEN[3] ,SCT conflict 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,SCT conflict 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,SCT conflict 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,SCT conflict 0 enable" "Disabled,Enabled" line.long 0x04 "CONFLAG,SCT Conflict Flag Register" bitfld.long 0x04 31. " BUSERRH ,Error writing CTR_H/STATE_H/MATCH_H or the output register when the H counter was not halted" "No error,Error" bitfld.long 0x04 30. " BUSERRL ,Error writing CTR l/unified STATE l/unified MATCH l/unified or the output register when the L/U counter was not halted" "No error,Error" bitfld.long 0x04 3. " NCFLAG[3] ,No-change event occurred on output 3 flag" "Not occurred,Occurred" bitfld.long 0x04 2. " [2] ,No-change event occurred on output 2 flag" "Not occurred,Occurred" newline bitfld.long 0x04 1. " [1] ,No-change event occurred on output 1 flag" "Not occurred,Occurred" bitfld.long 0x04 0. " [0] ,No-change event occurred on output 0 flag" "Not occurred,Occurred" endif width 10. tree "Match Value And Capture Registers" if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000E000+0x4C))&0x01)==0x01) rgroup.long 0x100++0x03 line.long 0x00 "CAP0,SCT Capture Register Of Capture Channel 0" else rgroup.long 0x100++0x03 line.long 0x00 "MATCH0,SCT Match Value Register Of Match Channel 0" endif else if (((per.l(ad:0x5000E000+0x4C))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "CAP0,SCT Capture Register Of Capture Channel 0" else group.long 0x100++0x03 line.long 0x00 "MATCH0,SCT Match Value Register Of Match Channel 0" endif endif else if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x01)==0x01) group.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else group.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x01)==0x01) group.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 High Counter 16-bit" else group.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x01)==0x01) rgroup.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else rgroup.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x01)==0x01) group.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 High Counter 16-bit" else group.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x01)==0x01) group.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else group.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x01)==0x01) rgroup.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else rgroup.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif else if (((per.w(ad:0x5000E000+0x4C))&0x01)==0x01) rgroup.word 0x100++0x01 line.word 0x00 "CAP0_L,SCT Capture Register Of Capture Channel 0 Low Counter 16-bit" else rgroup.word 0x100++0x01 line.word 0x00 "MATCH0_L,SCT Match Value Register Of Match Channel 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x01)==0x01) rgroup.word (0x100+0x02)++0x01 line.word 0x00 "CAP0_H,SCT Capture Register Of Capture Channel 0 High Counter 16-bit" else rgroup.word (0x100+0x02)++0x01 line.word 0x00 "MATCH0_H,SCT Match Value Register Of Match Channel 0 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000E000+0x4C))&0x02)==0x02) rgroup.long 0x104++0x03 line.long 0x00 "CAP1,SCT Capture Register Of Capture Channel 1" else rgroup.long 0x104++0x03 line.long 0x00 "MATCH1,SCT Match Value Register Of Match Channel 1" endif else if (((per.l(ad:0x5000E000+0x4C))&0x02)==0x02) group.long 0x104++0x03 line.long 0x00 "CAP1,SCT Capture Register Of Capture Channel 1" else group.long 0x104++0x03 line.long 0x00 "MATCH1,SCT Match Value Register Of Match Channel 1" endif endif else if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x02)==0x02) group.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else group.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x02)==0x02) group.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 High Counter 16-bit" else group.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x02)==0x02) rgroup.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else rgroup.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x02)==0x02) group.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 High Counter 16-bit" else group.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x02)==0x02) group.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else group.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x02)==0x02) rgroup.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else rgroup.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif else if (((per.w(ad:0x5000E000+0x4C))&0x02)==0x02) rgroup.word 0x104++0x01 line.word 0x00 "CAP1_L,SCT Capture Register Of Capture Channel 1 Low Counter 16-bit" else rgroup.word 0x104++0x01 line.word 0x00 "MATCH1_L,SCT Match Value Register Of Match Channel 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x02)==0x02) rgroup.word (0x104+0x02)++0x01 line.word 0x00 "CAP1_H,SCT Capture Register Of Capture Channel 1 High Counter 16-bit" else rgroup.word (0x104+0x02)++0x01 line.word 0x00 "MATCH1_H,SCT Match Value Register Of Match Channel 1 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000E000+0x4C))&0x04)==0x04) rgroup.long 0x108++0x03 line.long 0x00 "CAP2,SCT Capture Register Of Capture Channel 2" else rgroup.long 0x108++0x03 line.long 0x00 "MATCH2,SCT Match Value Register Of Match Channel 2" endif else if (((per.l(ad:0x5000E000+0x4C))&0x04)==0x04) group.long 0x108++0x03 line.long 0x00 "CAP2,SCT Capture Register Of Capture Channel 2" else group.long 0x108++0x03 line.long 0x00 "MATCH2,SCT Match Value Register Of Match Channel 2" endif endif else if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x04)==0x04) group.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else group.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x04)==0x04) group.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 High Counter 16-bit" else group.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x04)==0x04) rgroup.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else rgroup.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x04)==0x04) group.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 High Counter 16-bit" else group.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x04)==0x04) group.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else group.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x04)==0x04) rgroup.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else rgroup.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif else if (((per.w(ad:0x5000E000+0x4C))&0x04)==0x04) rgroup.word 0x108++0x01 line.word 0x00 "CAP2_L,SCT Capture Register Of Capture Channel 2 Low Counter 16-bit" else rgroup.word 0x108++0x01 line.word 0x00 "MATCH2_L,SCT Match Value Register Of Match Channel 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x04)==0x04) rgroup.word (0x108+0x02)++0x01 line.word 0x00 "CAP2_H,SCT Capture Register Of Capture Channel 2 High Counter 16-bit" else rgroup.word (0x108+0x02)++0x01 line.word 0x00 "MATCH2_H,SCT Match Value Register Of Match Channel 2 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000E000+0x4C))&0x08)==0x08) rgroup.long 0x10C++0x03 line.long 0x00 "CAP3,SCT Capture Register Of Capture Channel 3" else rgroup.long 0x10C++0x03 line.long 0x00 "MATCH3,SCT Match Value Register Of Match Channel 3" endif else if (((per.l(ad:0x5000E000+0x4C))&0x08)==0x08) group.long 0x10C++0x03 line.long 0x00 "CAP3,SCT Capture Register Of Capture Channel 3" else group.long 0x10C++0x03 line.long 0x00 "MATCH3,SCT Match Value Register Of Match Channel 3" endif endif else if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x08)==0x08) group.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else group.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x08)==0x08) group.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 High Counter 16-bit" else group.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x08)==0x08) rgroup.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else rgroup.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x08)==0x08) group.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 High Counter 16-bit" else group.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x08)==0x08) group.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else group.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x08)==0x08) rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif else if (((per.w(ad:0x5000E000+0x4C))&0x08)==0x08) rgroup.word 0x10C++0x01 line.word 0x00 "CAP3_L,SCT Capture Register Of Capture Channel 3 Low Counter 16-bit" else rgroup.word 0x10C++0x01 line.word 0x00 "MATCH3_L,SCT Match Value Register Of Match Channel 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x08)==0x08) rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "CAP3_H,SCT Capture Register Of Capture Channel 3 High Counter 16-bit" else rgroup.word (0x10C+0x02)++0x01 line.word 0x00 "MATCH3_H,SCT Match Value Register Of Match Channel 3 High Counter 16-bit" endif endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x04))&0x04)==0x00) if (((per.l(ad:0x5000E000+0x4C))&0x10)==0x10) rgroup.long 0x110++0x03 line.long 0x00 "CAP4,SCT Capture Register Of Capture Channel 4" else rgroup.long 0x110++0x03 line.long 0x00 "MATCH4,SCT Match Value Register Of Match Channel 4" endif else if (((per.l(ad:0x5000E000+0x4C))&0x10)==0x10) group.long 0x110++0x03 line.long 0x00 "CAP4,SCT Capture Register Of Capture Channel 4" else group.long 0x110++0x03 line.long 0x00 "MATCH4,SCT Match Value Register Of Match Channel 4" endif endif else if (((per.w(ad:0x5000E000+0x04))&0x04)==0x04)&&(((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10) group.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else group.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10) group.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 High Counter 16-bit" else group.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x06))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10) rgroup.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else rgroup.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10) group.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 High Counter 16-bit" else group.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 High Counter 16-bit" endif elif (((per.w(ad:0x5000E000+0x04))&0x04)==0x04) if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10) group.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else group.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10) rgroup.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else rgroup.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif else if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10) rgroup.word 0x110++0x01 line.word 0x00 "CAP4_L,SCT Capture Register Of Capture Channel 4 Low Counter 16-bit" else rgroup.word 0x110++0x01 line.word 0x00 "MATCH4_L,SCT Match Value Register Of Match Channel 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10) rgroup.word (0x110+0x02)++0x01 line.word 0x00 "CAP4_H,SCT Capture Register Of Capture Channel 4 High Counter 16-bit" else rgroup.word (0x110+0x02)++0x01 line.word 0x00 "MATCH4_H,SCT Match Value Register Of Match Channel 4 High Counter 16-bit" endif endif endif tree.end width 13. tree "Match Reload And Capture Control Registers" if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x4C))&0x01)==0x01) group.long 0x200++0x03 line.long 0x00 "CAPCTRL0 ,SCT Capture Control Register 0 " bitfld.long 0x00 5. " CAPCON0 [5] ,Event 5 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP0 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP0 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP0 register" "Not occurred,Occurred" else group.long 0x200++0x03 line.long 0x00 "MATCHREL0 ,SCT Match Reload Value Register 0 " endif else if (((per.w(ad:0x5000E000+0x4C))&0x01)==0x01) group.word 0x200++0x01 line.word 0x00 "CAPCTRL0 _L,SCT Capture Control Register 0 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON0 _L[5] ,Event 5 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP0 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP0 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP0 _L register" "Not occurred,Occurred" else group.word 0x200++0x01 line.word 0x00 "MATCHREL0 _L,SCT Match Reload Value Register 0 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x01)==0x01) group.word (0x200+0x02)++0x01 line.word 0x00 "CAPCTRL0 _H,SCT Capture Control Register 0 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON0 _H[5] ,Event 5 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP0 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP0 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP0 _H register" "Not occurred,Occurred" else group.word (0x200+0x02)++0x01 line.word 0x00 "MATCHREL0 _H,SCT Match Reload Value Register 0 High Counter 16-bit" endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x4C))&0x02)==0x02) group.long 0x204++0x03 line.long 0x00 "CAPCTRL1 ,SCT Capture Control Register 1 " bitfld.long 0x00 5. " CAPCON1 [5] ,Event 5 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP1 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP1 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP1 register" "Not occurred,Occurred" else group.long 0x204++0x03 line.long 0x00 "MATCHREL1 ,SCT Match Reload Value Register 1 " endif else if (((per.w(ad:0x5000E000+0x4C))&0x02)==0x02) group.word 0x204++0x01 line.word 0x00 "CAPCTRL1 _L,SCT Capture Control Register 1 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON1 _L[5] ,Event 5 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP1 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP1 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP1 _L register" "Not occurred,Occurred" else group.word 0x204++0x01 line.word 0x00 "MATCHREL1 _L,SCT Match Reload Value Register 1 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x02)==0x02) group.word (0x204+0x02)++0x01 line.word 0x00 "CAPCTRL1 _H,SCT Capture Control Register 1 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON1 _H[5] ,Event 5 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP1 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP1 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP1 _H register" "Not occurred,Occurred" else group.word (0x204+0x02)++0x01 line.word 0x00 "MATCHREL1 _H,SCT Match Reload Value Register 1 High Counter 16-bit" endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x4C))&0x04)==0x04) group.long 0x208++0x03 line.long 0x00 "CAPCTRL2 ,SCT Capture Control Register 2 " bitfld.long 0x00 5. " CAPCON2 [5] ,Event 5 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP2 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP2 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP2 register" "Not occurred,Occurred" else group.long 0x208++0x03 line.long 0x00 "MATCHREL2 ,SCT Match Reload Value Register 2 " endif else if (((per.w(ad:0x5000E000+0x4C))&0x04)==0x04) group.word 0x208++0x01 line.word 0x00 "CAPCTRL2 _L,SCT Capture Control Register 2 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON2 _L[5] ,Event 5 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP2 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP2 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP2 _L register" "Not occurred,Occurred" else group.word 0x208++0x01 line.word 0x00 "MATCHREL2 _L,SCT Match Reload Value Register 2 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x04)==0x04) group.word (0x208+0x02)++0x01 line.word 0x00 "CAPCTRL2 _H,SCT Capture Control Register 2 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON2 _H[5] ,Event 5 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP2 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP2 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP2 _H register" "Not occurred,Occurred" else group.word (0x208+0x02)++0x01 line.word 0x00 "MATCHREL2 _H,SCT Match Reload Value Register 2 High Counter 16-bit" endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x4C))&0x08)==0x08) group.long 0x20C++0x03 line.long 0x00 "CAPCTRL3 ,SCT Capture Control Register 3 " bitfld.long 0x00 5. " CAPCON3 [5] ,Event 5 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP3 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP3 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP3 register" "Not occurred,Occurred" else group.long 0x20C++0x03 line.long 0x00 "MATCHREL3 ,SCT Match Reload Value Register 3 " endif else if (((per.w(ad:0x5000E000+0x4C))&0x08)==0x08) group.word 0x20C++0x01 line.word 0x00 "CAPCTRL3 _L,SCT Capture Control Register 3 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON3 _L[5] ,Event 5 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP3 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP3 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP3 _L register" "Not occurred,Occurred" else group.word 0x20C++0x01 line.word 0x00 "MATCHREL3 _L,SCT Match Reload Value Register 3 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x08)==0x08) group.word (0x20C+0x02)++0x01 line.word 0x00 "CAPCTRL3 _H,SCT Capture Control Register 3 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON3 _H[5] ,Event 5 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP3 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP3 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP3 _H register" "Not occurred,Occurred" else group.word (0x20C+0x02)++0x01 line.word 0x00 "MATCHREL3 _H,SCT Match Reload Value Register 3 High Counter 16-bit" endif endif if (((per.l(ad:0x5000E000))&0x01)==0x01) if (((per.l(ad:0x5000E000+0x4C))&0x10)==0x10) group.long 0x210++0x03 line.long 0x00 "CAPCTRL4 ,SCT Capture Control Register 4 " bitfld.long 0x00 5. " CAPCON4 [5] ,Event 5 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 4. " [4] ,Event 4 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 3. " [3] ,Event 3 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 2. " [2] ,Event 2 causes load of CAP4 register" "Not occurred,Occurred" newline bitfld.long 0x00 1. " [1] ,Event 1 causes load of CAP4 register" "Not occurred,Occurred" bitfld.long 0x00 0. " [0] ,Event 0 causes load of CAP4 register" "Not occurred,Occurred" else group.long 0x210++0x03 line.long 0x00 "MATCHREL4 ,SCT Match Reload Value Register 4 " endif else if (((per.w(ad:0x5000E000+0x4C))&0x10)==0x10) group.word 0x210++0x01 line.word 0x00 "CAPCTRL4 _L,SCT Capture Control Register 4 Low Counter 16-bit" bitfld.word 0x00 5. " CAPCON4 _L[5] ,Event 5 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP4 _L register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP4 _L register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP4 _L register" "Not occurred,Occurred" else group.word 0x210++0x01 line.word 0x00 "MATCHREL4 _L,SCT Match Reload Value Register 4 Low Counter 16-bit" endif if (((per.w(ad:0x5000E000+0x4E))&0x10)==0x10) group.word (0x210+0x02)++0x01 line.word 0x00 "CAPCTRL4 _H,SCT Capture Control Register 4 High Counter 16-bit" bitfld.word 0x00 5. " CAPCON4 _H[5] ,Event 5 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 4. " [4] ,Event 4 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 3. " [3] ,Event 3 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 2. " [2] ,Event 2 causes load of CAP4 _H register" "Not occurred,Occurred" newline bitfld.word 0x00 1. " [1] ,Event 1 causes load of CAP4 _H register" "Not occurred,Occurred" bitfld.word 0x00 0. " [0] ,Event 0 causes load of CAP4 _H register" "Not occurred,Occurred" else group.word (0x210+0x02)++0x01 line.word 0x00 "MATCHREL4 _H,SCT Match Reload Value Register 4 High Counter 16-bit" endif endif tree.end width 11. tree "Event State And Control Registers" group.long 0x300++0x03 line.long 0x00 "EV0 _STATE,SCT Event State Register 0 " bitfld.long 0x00 7. " STATEMSK0 [7] ,State 7 of event 0 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 0 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 0 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 0 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 0 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 0 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 0 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 0 select" "Not selected,Selected" if (((per.l(ad:0x5000E000))&0x01)==0x01) group.long (0x300+0x04)++0x03 line.long 0x00 "EV0 _CTRL,SCT Event Control Register 0 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x300+0x04)++0x03 line.long 0x00 "EV0 _CTRL,SCT Event Control Register 0 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 0 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x308++0x03 line.long 0x00 "EV1 _STATE,SCT Event State Register 1 " bitfld.long 0x00 7. " STATEMSK1 [7] ,State 7 of event 1 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 1 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 1 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 1 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 1 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 1 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 1 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 1 select" "Not selected,Selected" if (((per.l(ad:0x5000E000))&0x01)==0x01) group.long (0x308+0x04)++0x03 line.long 0x00 "EV1 _CTRL,SCT Event Control Register 1 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x308+0x04)++0x03 line.long 0x00 "EV1 _CTRL,SCT Event Control Register 1 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 1 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x310++0x03 line.long 0x00 "EV2 _STATE,SCT Event State Register 2 " bitfld.long 0x00 7. " STATEMSK2 [7] ,State 7 of event 2 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 2 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 2 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 2 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 2 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 2 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 2 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 2 select" "Not selected,Selected" if (((per.l(ad:0x5000E000))&0x01)==0x01) group.long (0x310+0x04)++0x03 line.long 0x00 "EV2 _CTRL,SCT Event Control Register 2 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x310+0x04)++0x03 line.long 0x00 "EV2 _CTRL,SCT Event Control Register 2 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 2 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x318++0x03 line.long 0x00 "EV3 _STATE,SCT Event State Register 3 " bitfld.long 0x00 7. " STATEMSK3 [7] ,State 7 of event 3 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 3 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 3 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 3 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 3 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 3 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 3 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 3 select" "Not selected,Selected" if (((per.l(ad:0x5000E000))&0x01)==0x01) group.long (0x318+0x04)++0x03 line.long 0x00 "EV3 _CTRL,SCT Event Control Register 3 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x318+0x04)++0x03 line.long 0x00 "EV3 _CTRL,SCT Event Control Register 3 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 3 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x320++0x03 line.long 0x00 "EV4 _STATE,SCT Event State Register 4 " bitfld.long 0x00 7. " STATEMSK4 [7] ,State 7 of event 4 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 4 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 4 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 4 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 4 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 4 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 4 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 4 select" "Not selected,Selected" if (((per.l(ad:0x5000E000))&0x01)==0x01) group.long (0x320+0x04)++0x03 line.long 0x00 "EV4 _CTRL,SCT Event Control Register 4 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x320+0x04)++0x03 line.long 0x00 "EV4 _CTRL,SCT Event Control Register 4 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 4 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x328++0x03 line.long 0x00 "EV5 _STATE,SCT Event State Register 5 " bitfld.long 0x00 7. " STATEMSK5 [7] ,State 7 of event 5 select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,State 6 of event 5 select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,State 5 of event 5 select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,State 4 of event 5 select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,State 3 of event 5 select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,State 2 of event 5 select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,State 1 of event 5 select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,State 0 of event 5 select" "Not selected,Selected" if (((per.l(ad:0x5000E000))&0x01)==0x01) group.long (0x328+0x04)++0x03 line.long 0x00 "EV5 _CTRL,SCT Event Control Register 5 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long (0x328+0x04)++0x03 line.long 0x00 "EV5 _CTRL,SCT Event Control Register 5 " bitfld.long 0x00 21.--22. " DIRECTION ,Direction qualifier for event generation" "Independent,Counting up,Counting down,?..." bitfld.long 0x00 20. " MATCHMEM ,Enable COMBMODE to specify match component to the triggering of this event" "Disabled,Enabled" bitfld.long 0x00 15.--19. " STATEV ,Value loaded into or added to the state selected by HEVENT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " STATELD ,Controls how the STATEV value modifies the state selected by HEVENT" "Add into STATE,Load into STATE" newline bitfld.long 0x00 12.--13. " COMBMODE ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,I/O,AND" bitfld.long 0x00 10.--11. " IOCOND ,Selects the I/O condition for event 5 " "LOW,Rise,Fall,HIGH" bitfld.long 0x00 6.--9. " IOSEL ,Selects the input or output signal associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " OUTSEL ,Input/output select" "Input,Output" newline bitfld.long 0x00 4. " HEVENT ,Select L/H counter" "L selected,H selected" bitfld.long 0x00 0.--3. " MATCHSEL ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 10. tree "Output Set/Clear Registers" sif cpuis("LPC11U6?JBD64") group.long 0x510++0x07 line.long 0x00 "OUT2_SET,SCT Output 2 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 2" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 2" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 2" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 2" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 2" "Not cleared,Cleared" line.long 0x04 "OUT2_CLR,SCT Output 2 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 2" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 2" "Not cleared,Cleared" group.long 0x518++0x07 line.long 0x00 "OUT3_SET,SCT Output 3 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 3" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 3" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 3" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 3" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 3" "Not cleared,Cleared" line.long 0x04 "OUT3_CLR,SCT Output 3 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 3" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 3" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 3" "Not cleared,Cleared" elif cpuis("LPC11U6?JBD100") group.long 0x500++0x07 line.long 0x00 "OUT0_SET,SCT Output 0 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 0" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 0" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 0" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 0" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 0" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 0" "Not cleared,Cleared" line.long 0x04 "OUT0_CLR,SCT Output 0 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 0" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 0" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 0" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 0" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 0" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 0" "Not cleared,Cleared" group.long 0x508++0x07 line.long 0x00 "OUT1_SET,SCT Output 1 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 1" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 1" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 1" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 1" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 1" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 1" "Not cleared,Cleared" line.long 0x04 "OUT1_CLR,SCT Output 1 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 1" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 1" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 1" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 1" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 1" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 1" "Not cleared,Cleared" group.long 0x510++0x07 line.long 0x00 "OUT2_SET,SCT Output 2 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 2" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 2" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 2" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 2" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 2" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 2" "Not cleared,Cleared" line.long 0x04 "OUT2_CLR,SCT Output 2 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 2" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 2" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 2" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 2" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 2" "Not cleared,Cleared" group.long 0x518++0x07 line.long 0x00 "OUT3_SET,SCT Output 3 Set Register" bitfld.long 0x00 5. " SET[5] ,Event 5 set output 3" "Not set,Set" bitfld.long 0x00 4. " [4] ,Event 4 set output 3" "Not cleared,Cleared" bitfld.long 0x00 3. " [3] ,Event 3 set output 3" "Not cleared,Cleared" bitfld.long 0x00 2. " [2] ,Event 2 set output 3" "Not cleared,Cleared" newline bitfld.long 0x00 1. " [1] ,Event 1 set output 3" "Not set,Set" bitfld.long 0x00 0. " [0] ,Event 0 set output 3" "Not cleared,Cleared" line.long 0x04 "OUT3_CLR,SCT Output 3 Clear Register" bitfld.long 0x04 5. " CLR[5] ,Event 5 clear output 3" "Not set,Set" bitfld.long 0x04 4. " [4] ,Event 4 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 3. " [3] ,Event 3 clear output 3" "Not cleared,Cleared" bitfld.long 0x04 2. " [2] ,Event 2 clear output 3" "Not cleared,Cleared" newline bitfld.long 0x04 1. " [1] ,Event 1 clear output 3" "Not set,Set" bitfld.long 0x04 0. " [0] ,Event 0 clear output 3" "Not cleared,Cleared" endif tree.end width 0x0B tree.end tree.end endif tree "CT16B0/1 (16-Bit Counter/Timers)" tree "CT16B0" base ad:0x4000C000 width 6. group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" sif cpuis("LPC11U6*") eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred" eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*") eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline endif endif eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred" newline sif cpuis("LPC11U3*") sif cpuis("LPC11U3*BD64*")||cpuis("LPC11U35FET48*") eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred" newline endif elif !cpuis("LPC11U1*201")&&!cpuis("LPC11U2*301")&&!cpuis("LPC11U2/401")&&!cpuis("LPC11U22FBD48") eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred" newline endif eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred" newline eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred" eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 1. " CRST ,Counter reset" "No reset,Reset" bitfld.long 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.long 0x08++0x0B line.long 0x00 "TC,Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value" line.long 0x04 "PR,Prescale Register" hexmask.long.word 0x04 0.--15. 1. " PCVAL ,Prescale value" line.long 0x08 "PC,Prescale Counter Register" hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled" bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled" bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled" newline bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled" bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled" bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled" newline bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled" bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled" bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled" newline bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled" bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled" bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled" group.long 0x18++0x0F line.long 0x00 "MR0,Match Register 0" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value" line.long 0x04 "MR1,Match Register 1" hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value" line.long 0x08 "MR2,Match Register 2" hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value" line.long 0x0C "MR3,Match Register 3" hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value" group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled" bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 8. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 6. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline endif endif bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled" bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable" rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" sif cpuis("LPC11U6*") rgroup.long 0x34++0x03 line.long 0x00 "CR1,Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") rgroup.long 0x34++0x03 line.long 0x00 "CR1,Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" endif endif group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High" bitfld.long 0x00 2. " [2] ,External match 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,External match 1" "Low,High" bitfld.long 0x00 0. " [0] ,External match 0" "Low,High" if ((per.l(ad:0x4000C000+0x70)&0x13)==0x00) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x4000C000+0x70)&0x13)<=0x03)&&((per.l(ad:0x4000C000+0x70)&0x13)>(0x00)) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline sif cpuis("LPC11U6*") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,,CAP1,?..." newline else newline endif else newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x4000C000+0x70)&0x13)==0x10) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,,,Rising CAP1,Falling CAP1,?..." newline else newline endif else newline endif bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" else group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,,,Rising CAP1,Falling CAP1,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,,CAP1,?..." newline else newline newline newline endif else newline newline newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" endif group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control register" bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled" width 0x0B tree.end tree "CT16B1" base ad:0x40010000 width 6. group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" sif cpuis("LPC11U6*") eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred" eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*") eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline endif endif eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred" newline sif cpuis("LPC11U3*") sif cpuis("LPC11U3*BD64*")||cpuis("LPC11U35FET48*") eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred" eventfld.long 0x00 2. " MR2IN ,Interrupt flag for match channel 2" "Not occurred,Occurred" newline endif elif !cpuis("LPC11U1*201")&&!cpuis("LPC11U2*301")&&!cpuis("LPC11U22FBD48") eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred" eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred" newline elif cpuis("LPC11U2/401") eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred" newline endif eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred" eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 1. " CRST ,Counter reset" "No reset,Reset" bitfld.long 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.long 0x08++0x0B line.long 0x00 "TC,Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " TC ,Timer counter value" line.long 0x04 "PR,Prescale Register" hexmask.long.word 0x04 0.--15. 1. " PCVAL ,Prescale value" line.long 0x08 "PC,Prescale Counter Register" hexmask.long.word 0x08 0.--15. 1. " PC ,Prescale counter value" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled" bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled" bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled" newline bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled" bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled" bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled" newline bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled" bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled" bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled" newline bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled" bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled" bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled" group.long 0x18++0x0F line.long 0x00 "MR0,Match Register 0" hexmask.long.word 0x00 0.--15. 1. " MATCH ,Timer counter match value" line.long 0x04 "MR1,Match Register 1" hexmask.long.word 0x04 0.--15. 1. " MATCH ,Timer counter match value" line.long 0x08 "MR2,Match Register 2" hexmask.long.word 0x08 0.--15. 1. " MATCH ,Timer counter match value" line.long 0x0C "MR3,Match Register 3" hexmask.long.word 0x0C 0.--15. 1. " MATCH ,Timer counter match value" group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled" bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline endif endif bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled" bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable" rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" sif cpuis("LPC11U6*") rgroup.long 0x30++0x03 line.long 0x00 "CR1,Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") rgroup.long 0x30++0x03 line.long 0x00 "CR1,Capture Register 1" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" endif endif group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High" bitfld.long 0x00 2. " [2] ,External match 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,External match 1" "Low,High" bitfld.long 0x00 0. " [0] ,External match 0" "Low,High" if ((per.l(ad:0x40010000+0x70)&0x13)==0x00) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x40010000+0x70)&0x13)<=0x03)&&((per.l(ad:0x40010000+0x70)&0x13)>(0x00)) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline sif cpuis("LPC11U6*") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,?..." newline else newline endif else newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x40010000+0x70)&0x13)==0x10) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..." newline else newline endif else newline endif bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" else group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif !cpuis("LPC11U1*") sif cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,?..." newline else newline newline newline endif else newline newline newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" endif group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control register" bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled" width 0x0B tree.end tree.end tree "CT32B0/1 (32-Bit Counter/Timers)" tree "CT32B0" base ad:0x40014000 width 6. group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" sif cpuis("LPC11U6*") eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred" eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline elif !cpuis("LPC11U*33*") eventfld.long 0x00 6. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline endif eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred" eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred" newline eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred" newline eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred" eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 1. " CRST ,Counter reset" "No reset,Reset" bitfld.long 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.long 0x08++0x0B line.long 0x00 "TC,Timer Counter Register" line.long 0x04 "PR,Prescale Register" line.long 0x08 "PC,Prescale Counter Register" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled" bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled" bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled" newline bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled" bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled" bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled" newline bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled" bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled" bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled" newline bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled" bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled" bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled" group.long 0x18++0x0F line.long 0x00 "MR0,Match Register 0" line.long 0x04 "MR1,Match Register 1" line.long 0x08 "MR2,Match Register 2" line.long 0x0C "MR3,Match Register 3" group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled" bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline elif !cpuis("LPC11U*33*") bitfld.long 0x00 8. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 6. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled" bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable" rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" sif cpuis("LPC11U6*") rgroup.long 0x30++0x07 line.long 0x00 "CR1,Capture Register 1" line.long 0x04 "CR2,Capture Register 2" elif !cpuis("LPC11U*33*") rgroup.long 0x34++0x03 line.long 0x00 "CR1,Capture Register 1" endif group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High" bitfld.long 0x00 2. " [2] ,External match 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,External match 1" "Low,High" bitfld.long 0x00 0. " [0] ,External match 0" "Low,High" if ((per.l(ad:0x40014000+0x70)&0x13)==0x00) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x40014000+0x70)&0x13)<=0x03)&&((per.l(ad:0x40014000+0x70)&0x13)>(0x00)) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline sif cpuis("LPC11U6*") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif !cpuis("LPC11U*33*") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,,CAP1,?..." newline else newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x40014000+0x70)&0x13)==0x10) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline elif !cpuis("LPC11U*33*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,,,Rising CAP1,Falling CAP1,?..." newline else newline endif bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" else group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif !cpuis("LPC11U*33*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,,,Rising CAP1,Falling CAP1,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,,CAP1,?..." newline else newline newline newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" endif group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control register" bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled" width 0x0B tree.end tree "CT32B1" base ad:0x40018000 width 6. group.long 0x00++0x03 line.long 0x00 "IR,Interrupt Register" sif cpuis("LPC11U6*") eventfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "Not occurred,Occurred" eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline elif cpuis("LPC11U??FE*")||cpuis("LPC11U*64*") eventfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "Not occurred,Occurred" newline endif eventfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "Not occurred,Occurred" eventfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3" "Not occurred,Occurred" newline eventfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2" "Not occurred,Occurred" newline eventfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1" "Not occurred,Occurred" eventfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0" "Not occurred,Occurred" group.long 0x04++0x03 line.long 0x00 "TCR,Timer Control Register" bitfld.long 0x00 1. " CRST ,Counter reset" "No reset,Reset" bitfld.long 0x00 0. " CEN ,Counter enable" "Disabled,Enabled" group.long 0x08++0x0B line.long 0x00 "TC,Timer Counter Register" line.long 0x04 "PR,Prescale Register" line.long 0x08 "PC,Prescale Counter Register" group.long 0x14++0x03 line.long 0x00 "MCR,Match Control Register" bitfld.long 0x00 11. " MR3S ,Stop on MR3" "Disabled,Enabled" bitfld.long 0x00 10. " MR3R ,Reset on MR3" "Disabled,Enabled" bitfld.long 0x00 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled" newline bitfld.long 0x00 8. " MR2S ,Stop on MR2" "Disabled,Enabled" bitfld.long 0x00 7. " MR2R ,Reset on MR2" "Disabled,Enabled" bitfld.long 0x00 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled" newline bitfld.long 0x00 5. " MR1S ,Stop on MR1" "Disabled,Enabled" bitfld.long 0x00 4. " MR1R ,Reset on MR1" "Disabled,Enabled" bitfld.long 0x00 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled" newline bitfld.long 0x00 2. " MR0S ,Stop on MR0" "Disabled,Enabled" bitfld.long 0x00 1. " MR0R ,Reset on MR0" "Disabled,Enabled" bitfld.long 0x00 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled" group.long 0x18++0x0F line.long 0x00 "MR0,Match Register 0" line.long 0x04 "MR1,Match Register 1" line.long 0x08 "MR2,Match Register 2" line.long 0x0C "MR3,Match Register 3" group.long 0x28++0x03 line.long 0x00 "CCR,Capture Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 8. " CAP2I ,Generate interrupt on channel 2 capture event" "Disabled,Enabled" bitfld.long 0x00 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled" bitfld.long 0x00 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline elif cpuis("LPC11U??FE*")||cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5. " CAP1I ,Generate interrupt on channel 1 capture event" "Disabled,Enabled" bitfld.long 0x00 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled" bitfld.long 0x00 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled" newline endif bitfld.long 0x00 2. " CAP0I ,Generate interrupt on channel 0" "Disabled,Enabled" bitfld.long 0x00 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled" bitfld.long 0x00 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enable" rgroup.long 0x2C++0x03 line.long 0x00 "CR0,Capture Register 0" hexmask.long.word 0x00 0.--15. 1. " CAP ,Timer counter capture value" sif cpuis("LPC11U6*")||cpuis("LPC11U??FE*")||cpuis("LPC11U*64*")||cpuis("LPC11U24/401") rgroup.long 0x30++0x03 line.long 0x00 "CR1,Capture Register 1" endif group.long 0x3C++0x03 line.long 0x00 "EMR,External Match Register" bitfld.long 0x00 10.--11. " EMC[3] ,External match control 3" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 8.--9. " [2] ,External match control 2" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 6.--7. " [1] ,External match control 1" "No operation,Cleared,Set,Toggled" bitfld.long 0x00 4.--5. " [0] ,External match control 0" "No operation,Cleared,Set,Toggled" newline bitfld.long 0x00 3. " EM[3] ,External match 3" "Low,High" bitfld.long 0x00 2. " [2] ,External match 2" "Low,High" newline bitfld.long 0x00 1. " [1] ,External match 1" "Low,High" bitfld.long 0x00 0. " [0] ,External match 0" "Low,High" if ((per.l(ad:0x40018000+0x70)&0x13)==0x00) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x40018000+0x70)&0x13)<=0x03)&&((per.l(ad:0x40018000+0x70)&0x13)>(0x00)) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline sif cpuis("LPC11U6*") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif cpuis("LPC11U??FE*")||cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,?..." newline else newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" elif ((per.l(ad:0x40018000+0x70)&0x13)==0x10) group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline elif cpuis("LPC11U??FE*")||cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..." newline else newline endif bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline newline bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" else group.long 0x70++0x03 line.long 0x00 "CTCR,Count Control Register" sif cpuis("LPC11U6*") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,Rising CAP2,Falling CAP2,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,CAP2,?..." newline elif cpuis("LPC11U??FE*")||cpuis("LPC11U*64*")||cpuis("LPC11U24/401") bitfld.long 0x00 5.--7. " SELCC ,Capture-edge event select" "Rising CAP0,Falling CAP0,Rising CAP1,Falling CAP1,?..." newline bitfld.long 0x00 4. " ENCC ,Clear timer and prescaler on SELCC event enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " CIS ,Counter input select" "CAP0,CAP1,?..." newline else newline newline newline endif bitfld.long 0x00 0.--1. " CTM ,Counter/timer mode" "Timer,Counter-rising,Counter-falling,Counter-both" endif group.long 0x74++0x03 line.long 0x00 "PWMC,PWM Control register" bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enabled for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PWM mode enabled for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PWM mode enabled for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,PWM mode enabled for channel 0" "Disabled,Enabled" width 0x0B tree.end tree.end sif cpuis("LPC11U6*") tree "RTC (Real-Time Clock)" base ad:0x40024000 width 7. sif cpuis("LPC11U6*") group.long 0x00++0x03 line.long 0x00 "CTRL,RTC Control Register" bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled" bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1.024 kHz clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1.024 kHz timer wake-up enable for deep power-down" "Disabled,Enabled" bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAKE1KHZ ,RTC 1.024 kHz timer wake-up flag status" "Run,Time-out" bitfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm" bitfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected" bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset" elif cpuis("LPC11E6*") group.long 0x00++0x03 line.long 0x00 "CTRL,RTC Control Register" bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled" bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1 kHz clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1 kHz timer wake-up enable for deep power-down" "Disabled,Enabled" bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled" newline eventfld.long 0x00 3. " WAKE1KHZ ,RTC 1 kHz timer wake-up flag status" "Run,Time-out" eventfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm" eventfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected" bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset" else group.long 0x00++0x03 line.long 0x00 "CTRL,RTC Control Register" bitfld.long 0x00 7. " RTC_EN ,RTC enable" "Disabled,Enabled" bitfld.long 0x00 6. " RTC1KHZ_EN ,RTC 1 kHz clock enable" "Disabled,Enabled" bitfld.long 0x00 5. " WAKEDPD_EN ,RTC 1 kHz timer wake-up enable for deep power-down" "Disabled,Enabled" bitfld.long 0x00 4. " ALARMDPD_EN ,RTC 1 Hz timer alarm enable for deep power-down" "Disabled,Enabled" newline bitfld.long 0x00 3. " WAKE1KHZ ,RTC 1 kHz timer wake-up flag status" "Run,Time-out" bitfld.long 0x00 2. " ALARM1HZ ,RTC 1 Hz timer alarm flag status" "No alarm,Alarm" bitfld.long 0x00 1. " OFD ,Oscillator fail detect status" "Not detected,Detected" bitfld.long 0x00 0. " SWRESET ,Software reset control" "No reset,Reset" endif group.long 0x04++0x03 line.long 0x00 "MATCH,RTC Match Register" if (((per.l((ad:0x40024000)))&0x80)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "COUNT,RTC Counter Register" else group.long 0x08++0x03 line.long 0x00 "COUNT,RTC Counter Register" endif group.long 0x0C++0x03 line.long 0x00 "WAKE,RTC High-Resolution/Wake-Up Timer Control Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,High-resolution/Wake-up timer current value" width 0x0B tree.end endif tree "WWDT (Windowed Watchdog Timer)" base ad:0x40004000 width 9. group.long 0x00++0x07 line.long 0x00 "MOD,Watchdog Mode Register" bitfld.long 0x00 5. " LOCK ,Prevents disabling or powering down the watchdog oscillator" "Not locked,Locked" bitfld.long 0x00 4. " WDPROTECT ,Watchdog update mode" "Flexible,Threshold" bitfld.long 0x00 3. " WDINT ,Warning interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 2. " WDTOF ,Watchdog time-out flag" "No timeout,Timeout" newline bitfld.long 0x00 1. " WDRESET ,Watchdog reset enable" "Disabled,Enabled" bitfld.long 0x00 0. " WDEN ,Watchdog enable" "Disabled,Enabled" line.long 0x04 "TC,Watchdog Timer Constant Register" hexmask.long.tbyte 0x04 0.--23. 1. " COUNT ,Watchdog time-out value" wgroup.long 0x08++0x03 line.long 0x00 "FEED,Watchdog Feed Register" hexmask.long.byte 0x00 0.--7. 1. " FEED ,Feed value" rgroup.long 0x0C++0x03 line.long 0x00 "TV,Watchdog Timer Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " COUNT ,Counter timer value" sif cpuis("LPC11E*")||cpuis("LPC11U*")||cpuis("LPC11U6*") group.long 0x10++0x03 line.long 0x00 "CLKSEL,Watchdog Clock Select Register" bitfld.long 0x00 31. " LOCK ,Lock" "Not locked,Locked" bitfld.long 0x00 0. " CLKSEL ,Selects source of WDT clock" "IRC,WDOSC" endif group.long 0x14++0x07 line.long 0x00 "WARNINT,Watchdog Timer Warning Interrupt Register" hexmask.long.word 0x00 0.--9. 1. " WARNINT ,Watchdog warning interrupt compare value" line.long 0x04 "WINDOW,Watchdog Timer Window Register" hexmask.long.tbyte 0x04 0.--23. 1. " WINDOW ,Watchdog window value" width 0x0B tree.end sif cpuis("LPC11U6*") tree "CRC (Cyclic Redundancy Check)" base ad:0x50000000 width 9. group.long 0x00++0x07 line.long 0x00 "MODE,CRC Mode Register" bitfld.long 0x00 5. " CMPL_SUM ,Data 1's complement enable for CRC_SUM" "Disabled,Enabled" bitfld.long 0x00 4. " BIT_RVS_SUM ,Bit order for CRC_SUM" "Not reversed,Reversed" bitfld.long 0x00 3. " CMPL_WR ,Data 1's complement enable for CRC_WR_DATA" "Disabled,Enabled" newline bitfld.long 0x00 2. " BIT_RVS_WR ,Bit order for CRC_WR_DATA" "Not reversed,Reversed" bitfld.long 0x00 0.--1. " CRC_POLY ,CRC polynomial select" "CRC-CCITT,CRC-16,CRC-32,CRC-32" line.long 0x04 "SEED,CRC Seed Register" rgroup.long 0x08++0x03 line.long 0x00 "SUM,CRC Checksum Register" wgroup.long 0x08++0x03 line.long 0x00 "WR_DATA,CRC Data Register" width 0x0B tree.end endif tree "ADC (Analog-To-Digital Converter)" sif cpuis("LPC11U6*") base ad:0x4001C000 width 13. group.long 0x00++0x03 line.long 0x00 "CTRL,A/D Control Register" bitfld.long 0x00 30. " CALMODE ,Self-calibration cycle initiation" "Not initiated,Initiated" bitfld.long 0x00 10. " LPWRMODE ,Low-power ADC mode enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock divide value" if (((per.l((ad:0x4001C000+0x08)))&0x80000000)==0x0) group.long 0x08++0x03 line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register" bitfld.long 0x00 31. " SEQA_ENA ,Sequence enable" "Disabled,Enabled" bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence" bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High" bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled" bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched" bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed" bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge" newline bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included" newline sif !cpuis("LPC11U6??BD48") bitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included" newline endif bitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included" bitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included" bitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included" bitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included" newline sif cpuis("LPC11U6?JBD100") bitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included" bitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included" newline endif bitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included" bitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included" bitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included" sif !cpuis("LPC11U6??BD48") newline bitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included" endif else group.long 0x08++0x03 line.long 0x00 "SEQA_CTRL,A/D Conversion Sequence-A Control Register" bitfld.long 0x00 31. " SEQA_ENA ,Sequence enable" "Disabled,Enabled" bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence" bitfld.long 0x00 29. " LOWPRIO ,Set priority for sequence A" "Low,High" bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled" newline bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled" bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched" bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed" bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge" newline bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included" newline sif !cpuis("LPC11U6??BD48") rbitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included" newline endif rbitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included" newline sif cpuis("LPC11U6?JBD100") rbitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included" newline endif rbitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included" sif !cpuis("LPC11U6??BD48") newline rbitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included" endif endif if (((per.l((ad:0x4001C000+0x0C)))&0x80000000)==0x0) group.long 0x0C++0x03 line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register" bitfld.long 0x00 31. " SEQB_ENA ,Sequence enable" "Disabled,Enabled" bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence" bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled" bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled" newline bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched" bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed" bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge" bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included" newline sif !cpuis("LPC11U6??BD48") bitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included" newline endif bitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included" bitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included" bitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included" bitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included" newline sif cpuis("LPC11U6?JBD100") bitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included" bitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included" newline endif bitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included" bitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included" bitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included" sif !cpuis("LPC11U6??BD48") newline bitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included" endif else group.long 0x0C++0x03 line.long 0x00 "SEQB_CTRL,A/D Conversion Sequence-B Control Register" bitfld.long 0x00 31. " SEQB_ENA ,Sequence enable" "Disabled,Enabled" bitfld.long 0x00 30. " MODE ,Retrieving conversion results method" "End of conversion,End of sequence" bitfld.long 0x00 28. " SINGLESTEP ,Single conversion enable" "Disabled,Enabled" bitfld.long 0x00 27. " BURST ,Enable conversion sequence to be continuously cycled through" "Disabled,Enabled" newline bitfld.long 0x00 26. " START ,Launch one pass through conversion sequence" "Not launched,Launched" bitfld.long 0x00 19. " SYNCBYPASS ,Bypass synchronization" "Not bypassed,Bypassed" bitfld.long 0x00 18. " TRIGPOL ,Select the polarity of the selected input trigger for this conversion sequence" "Negative edge,Positive edge" bitfld.long 0x00 12.--14. " TRIGGER ,Trigger input number causing conversion sequence to be initiated" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 11. " CHANNEL[11] ,Include channel 11 in conversion sequence" "Excluded,Included" newline sif !cpuis("LPC11U6??BD48") rbitfld.long 0x00 10. " [10] ,Include channel 10 in conversion sequence" "Excluded,Included" newline endif rbitfld.long 0x00 9. " [9] ,Include channel 9 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 8. " [8] ,Include channel 8 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 7. " [7] ,Include channel 7 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 6. " [6] ,Include channel 6 in conversion sequence" "Excluded,Included" newline sif cpuis("LPC11U6?JBD100") rbitfld.long 0x00 5. " [5] ,Include channel 5 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 4. " [4] ,Include channel 4 in conversion sequence" "Excluded,Included" newline endif rbitfld.long 0x00 3. " [3] ,Include channel 3 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 2. " [2] ,Include channel 2 in conversion sequence" "Excluded,Included" rbitfld.long 0x00 1. " [1] ,Include channel 1 in conversion sequence" "Excluded,Included" sif !cpuis("LPC11U6??BD48") newline rbitfld.long 0x00 0. " [0] ,Include channel 0 in conversion sequence" "Excluded,Included" endif endif newline group.long 0x10++0x07 line.long 0x00 "SEQA_GDAT,A/D Sequence-A Global Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" newline bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" line.long 0x04 "SEQB_GDAT,A/D Sequence-B Global Data Register" bitfld.long 0x04 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x04 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x04 26.--29. " CHN ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x04 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" newline bitfld.long 0x04 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x04 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" width 7. tree "Channels 0-11 Data Registers" sif !cpuis("LPC11U6??BD48") rgroup.long 0x20++0x03 line.long 0x00 "DAT0,A/D Channel 0 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" endif rgroup.long 0x24++0x03 line.long 0x00 "DAT1,A/D Channel 1 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" rgroup.long 0x28++0x03 line.long 0x00 "DAT2,A/D Channel 2 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" rgroup.long 0x2C++0x03 line.long 0x00 "DAT3,A/D Channel 3 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" sif cpuis("LPC11U6?JBD100") rgroup.long 0x30++0x03 line.long 0x00 "DAT4,A/D Channel 4 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" rgroup.long 0x34++0x03 line.long 0x00 "DAT5,A/D Channel 5 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" endif rgroup.long 0x38++0x03 line.long 0x00 "DAT6,A/D Channel 6 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" rgroup.long 0x3C++0x03 line.long 0x00 "DAT7,A/D Channel 7 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" rgroup.long 0x40++0x03 line.long 0x00 "DAT8,A/D Channel 8 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" rgroup.long 0x44++0x03 line.long 0x00 "DAT9,A/D Channel 9 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" sif !cpuis("LPC11U6??BD48") rgroup.long 0x48++0x03 line.long 0x00 "DAT10,A/D Channel 10 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" endif rgroup.long 0x4C++0x03 line.long 0x00 "DAT11,A/D Channel 11 Data Register" bitfld.long 0x00 31. " DATAVALID ,Converted data is valid" "Invalid,Valid" bitfld.long 0x00 30. " OVERRUN ,Conversion result is loaded into the RESULT field before a previous result has been read" "No overrun,Overrun" bitfld.long 0x00 26.--29. " CHANNEL ,Channel from which the RESULT bits were converted" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 18.--19. " THCMPCROSS ,Crossing of the threshold level established by the designated LOW threshold comparison register" "No crossing,,Downward,Upward" textline " " bitfld.long 0x00 16.--17. " THCMPRANGE ,Conversion performed was above below or within the range established by threshold comparison registers" "Within,Below,Above,?..." hexmask.long.word 0x00 4.--15. 1. " RESULT ,Conversion result from the most recent conversion" tree.end width 13. newline group.long 0x50++0x1F line.long 0x00 "THR0_LOW,A/D Low Compare Threshold Register 0" hexmask.long.word 0x00 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared" line.long 0x04 "THR1_LOW,A/D Low Compare Threshold Register 1" hexmask.long.word 0x04 4.--15. 1. " THRLOW ,Low threshold value against which A/D results will be compared" line.long 0x08 "THR0_HIGH,A/D High Compare Threshold Register 0" hexmask.long.word 0x08 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared" line.long 0x0C "THR1_HIGH,A/D High Compare Threshold Register 1" hexmask.long.word 0x0C 4.--15. 1. " THRHIGH ,High threshold value against which A/D results will be compared" line.long 0x10 "CHAN_THRSEL,A/D Channel-Threshold Select Register" bitfld.long 0x10 11. " CH[11]_THRSEL ,Threshold select by channel 11" "Threshold 0,Threshold 1" newline sif !cpuis("LPC11U6??BD48") bitfld.long 0x10 10. " [10] ,Threshold select by channel 10" "Threshold 0,Threshold 1" newline endif bitfld.long 0x10 9. " [9] ,Threshold select by channel 9" "Threshold 0,Threshold 1" bitfld.long 0x10 8. " [8] ,Threshold select by channel 8" "Threshold 0,Threshold 1" bitfld.long 0x10 7. " [7] ,Threshold select by channel 7" "Threshold 0,Threshold 1" bitfld.long 0x10 6. " [6] ,Threshold select by channel 6" "Threshold 0,Threshold 1" newline sif cpuis("LPC11U6?JBD100") bitfld.long 0x10 5. " [5] ,Threshold select by channel 5" "Threshold 0,Threshold 1" bitfld.long 0x10 4. " [4] ,Threshold select by channel 4" "Threshold 0,Threshold 1" newline endif bitfld.long 0x10 3. " [3] ,Threshold select by channel 3" "Threshold 0,Threshold 1" bitfld.long 0x10 2. " [2] ,Threshold select by channel 2" "Threshold 0,Threshold 1" bitfld.long 0x10 1. " [1] ,Threshold select by channel 1" "Threshold 0,Threshold 1" sif !cpuis("LPC11U6??BD48") newline bitfld.long 0x10 0. " [0] ,Threshold select by channel 0" "Threshold 0,Threshold 1" endif line.long 0x14 "INTEN,A/D Interrupt Enable Register" bitfld.long 0x14 25.--26. " ADCMPINTEN[11] ,Threshold comparison for channel 11 interrupt enable" "Disabled,Outside,Crossing,?..." newline sif !cpuis("LPC11U6??BD48") bitfld.long 0x14 23.--24. " [10] ,Threshold comparison for channel 10 interrupt enable" "Disabled,Outside,Crossing,?..." newline endif bitfld.long 0x14 21.--22. " [9] ,Threshold comparison for channel 9 interrupt enable" "Disabled,Outside,Crossing,?..." bitfld.long 0x14 19.--20. " [8] ,Threshold comparison for channel 8 interrupt enable" "Disabled,Outside,Crossing,?..." bitfld.long 0x14 17.--18. " [7] ,Threshold comparison for channel 7 interrupt enable" "Disabled,Outside,Crossing,?..." bitfld.long 0x14 15.--16. " [6] ,Threshold comparison for channel 6 interrupt enable" "Disabled,Outside,Crossing,?..." newline sif cpuis("LPC11U6?JBD100") bitfld.long 0x14 13.--14. " [5] ,Threshold comparison for channel 5 interrupt enable" "Disabled,Outside,Crossing,?..." bitfld.long 0x14 11.--12. " [4] ,Threshold comparison for channel 4 interrupt enable" "Disabled,Outside,Crossing,?..." newline endif bitfld.long 0x14 9.--10. " [3] ,Threshold comparison for channel 3 interrupt enable" "Disabled,Outside,Crossing,?..." bitfld.long 0x14 7.--8. " [2] ,Threshold comparison for channel 2 interrupt enable" "Disabled,Outside,Crossing,?..." bitfld.long 0x14 5.--6. " [1] ,Threshold comparison for channel 1 interrupt enable" "Disabled,Outside,Crossing,?..." newline sif !cpuis("LPC11U6??BD48") bitfld.long 0x14 3.--4. " [0] ,Threshold comparison for channel 0 interrupt enable" "Disabled,Outside,Crossing,?..." newline endif bitfld.long 0x14 2. " OVR_INTEN ,Overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x14 1. " SEQB_INTEN ,Sequence B interrupt enable" "Disabled,Enabled" bitfld.long 0x14 0. " SEQA_INTEN ,Sequence A interrupt enable" "Disabled,Enabled" line.long 0x18 "FLAGS,A/D Flags Register" bitfld.long 0x18 31. " OVR_INT ,Overrun interrupt flag" "No interrupt,Interrupt" bitfld.long 0x18 30. " THCMP_INT ,Threshold comparison interrupt" "No interrupt,Interrupt" bitfld.long 0x18 29. " SEQB_INT ,Sequence B interrupt/DMA trigger" "No interrupt,Interrupt" bitfld.long 0x18 28. " SEQA_INT ,Sequence A interrupt/DMA trigger" "No interrupt,Interrupt" newline bitfld.long 0x18 25. " SEQB_OVR ,Mirrors the global OVERRUN status flag in the SEQB_GDAT register" "No overrun,Overrun" bitfld.long 0x18 24. " SEQA_OVR ,Mirrors the global overrun status flag in the SEQA_GDAT register" "No overrun,Overrun" newline bitfld.long 0x18 23. " OVERRUN[11] ,Mirrors the overrun status flag from the result register for A/D channel 11" "No overrun,Overrun" newline sif !cpuis("LPC11U6??BD48") bitfld.long 0x18 22. " [10] ,Mirrors the overrun status flag from the result register for A/D channel 10" "No overrun,Overrun" newline endif bitfld.long 0x18 21. " [9] ,Mirrors the overrun status flag from the result register for A/D channel 9" "No overrun,Overrun" bitfld.long 0x18 20. " [8] ,Mirrors the overrun status flag from the result register for A/D channel 8" "No overrun,Overrun" bitfld.long 0x18 19. " [7] ,Mirrors the overrun status flag from the result register for A/D channel 7" "No overrun,Overrun" bitfld.long 0x18 18. " [6] ,Mirrors the overrun status flag from the result register for A/D channel 6" "No overrun,Overrun" newline sif cpuis("LPC11U6?JBD100") bitfld.long 0x18 17. " [5] ,Mirrors the overrun status flag from the result register for A/D channel 5" "No overrun,Overrun" bitfld.long 0x18 16. " [4] ,Mirrors the overrun status flag from the result register for A/D channel 4" "No overrun,Overrun" newline endif bitfld.long 0x18 15. " [3] ,Mirrors the overrun status flag from the result register for A/D channel 3" "No overrun,Overrun" bitfld.long 0x18 14. " [2] ,Mirrors the overrun status flag from the result register for A/D channel 2" "No overrun,Overrun" bitfld.long 0x18 13. " [1] ,Mirrors the overrun status flag from the result register for A/D channel 1" "No overrun,Overrun" newline sif !cpuis("LPC11U6??BD48") bitfld.long 0x18 12. " [0] ,Mirrors the overrun status flag from the result register for A/D channel 0" "No overrun,Overrun" newline endif eventfld.long 0x18 11. " THCMP[11] ,Threshold comparison event on channel 11" "Not occurred,Occurred" newline sif !cpuis("LPC11U6??BD48") eventfld.long 0x18 10. " [10] ,Threshold comparison event on channel 10" "Not occurred,Occurred" newline endif eventfld.long 0x18 9. " [9] ,Threshold comparison event on channel 9" "Not occurred,Occurred" eventfld.long 0x18 8. " [8] ,Threshold comparison event on channel 8" "Not occurred,Occurred" eventfld.long 0x18 7. " [7] ,Threshold comparison event on channel 7" "Not occurred,Occurred" eventfld.long 0x18 6. " [6] ,Threshold comparison event on channel 6" "Not occurred,Occurred" newline sif cpuis("LPC11U6?JBD100") eventfld.long 0x18 5. " [5] ,Threshold comparison event on channel 5" "Not occurred,Occurred" eventfld.long 0x18 4. " [4] ,Threshold comparison event on channel 4" "Not occurred,Occurred" newline endif eventfld.long 0x18 3. " [3] ,Threshold comparison event on channel 3" "Not occurred,Occurred" eventfld.long 0x18 2. " [2] ,Threshold comparison event on channel 2" "Not occurred,Occurred" eventfld.long 0x18 1. " [1] ,Threshold comparison event on channel 1" "Not occurred,Occurred" sif !cpuis("LPC11U6??BD48") newline eventfld.long 0x18 0. " [0] ,Threshold comparison event on channel 0" "Not occurred,Occurred" endif line.long 0x1C "TRM,A/D Trim Register" bitfld.long 0x1C 5. " VRANGE ,Voltage supply range" "2.7 V - 3.6 V,2.4 V - 2.7 V" width 0x0B elif cpuis("LPC11U*") base ad:0x4001C000 width 10. if ((per.l(ad:0x4001C000)&0x07000000)==(0x00||0x1000000)) group.long 0x00++0x03 line.long 0x00 "CR,A/D Control Register" textfld " " sif cpuis("LPC11C*") bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on PIO0_2/SSEL/CT16B0_CAP0,Edge on PIO1_5/DIR/CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1" bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits" bitfld.long 0x00 16. " BURST ,Burst mode" "Software,Hardware" else bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on CT16B0_CAP0,Edge on CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1" bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits" bitfld.long 0x00 16. " BURST ,Conversion control mode" "Software,Repeated" endif newline hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider" newline bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,AD.2 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion select" "Not selected,Selected" newline else group.long 0x00++0x03 line.long 0x00 "CR,A/D Control Register" bitfld.long 0x00 27. " EDGE ,Start conversion edge" "Rising,Falling" sif cpuis("LPC11C*") bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on PIO0_2/SSEL/CT16B0_CAP0,Edge on PIO1_5/DIR/CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1" bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits" bitfld.long 0x00 16. " BURST ,Burst mode" "Software,Hardware" else bitfld.long 0x00 24.--26. " START ,Start conversion control" "Not started,Started,Edge on CT16B0_CAP0,Edge on CT32B0_CAP0,Edge on CT32B0_MAT0,Edge on CT32B0_MAT1,Edge on CT16B0_MAT0,Edge on CT16B0_MAT1" bitfld.long 0x00 17.--19. " CLKS ,Number of clocks for each conversion in burst mode" "11 clocks/10 bits,10 clocks/9 bits,9 clocks/8 bits,8 clocks/7 bits,7 clocks/6 bits,6 clocks/5 bits,5 clocks/4 bits,4 clocks/3 bits" bitfld.long 0x00 16. " BURST ,Conversion control mode" "Software,Repeated" endif newline hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divider" newline bitfld.long 0x00 7. " SEL[7] ,AD7 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,AD6 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 5. " [5] ,AD5 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,AD4 sampling and conversion select" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,AD3 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,AD.2 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 1. " [1] ,AD1 sampling and conversion select" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,AD0 sampling and conversion select" "Not selected,Selected" newline endif hgroup.long 0x04++0x03 hide.long 0x00 "GDR,A/D Global Data Register" in newline group.long 0x0C++0x03 line.long 0x00 "INTEN,A/D Interrupt Enable Register" sif cpuis("LPC11C*") bitfld.long 0x00 8. " ADGINTEN ,A/D global interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " ADINTEN[7] ,Conversion completion interrupts for channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Conversion completion interrupts for channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Conversion completion interrupts for channel 5 enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " [4] ,Conversion completion interrupts for channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,Conversion completion interrupts for channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Conversion completion interrupts for channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Conversion completion interrupts for channel 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Conversion completion interrupts for channel 0 enable" "Disabled,Enabled" newline else bitfld.long 0x00 8. " ADGINTEN ,Source of generated interrupt" "Individual,Global" newline bitfld.long 0x00 7. " ADINTEN[7] ,Interrupted when conversion on channel 7 completed" "Not interrupted,Interrupted" bitfld.long 0x00 6. " [6] ,Interrupted when conversion on channel 6 completed" "Not interrupted,Interrupted" bitfld.long 0x00 5. " [5] ,Interrupted when conversion on channel 5 completed" "Not interrupted,Interrupted" newline bitfld.long 0x00 4. " [4] ,Interrupted when conversion on channel 4 completed" "Not interrupted,Interrupted" bitfld.long 0x00 3. " [3] ,Interrupted when conversion on channel 3 completed" "Not interrupted,Interrupted" bitfld.long 0x00 2. " [2] ,Interrupted when conversion on channel 2 completed" "Not interrupted,Interrupted" bitfld.long 0x00 1. " [1] ,Interrupted when conversion on channel 1 completed" "Not interrupted,Interrupted" newline bitfld.long 0x00 0. " [0] ,Interrupted when conversion on channel 0 completed" "Not interrupted,Interrupted" newline endif hgroup.long 0x10++0x03 hide.long 0x00 "DR0,A/D Channel 0 Data Register" in hgroup.long 0x14++0x03 hide.long 0x00 "DR1,A/D Channel 1 Data Register" in hgroup.long 0x18++0x03 hide.long 0x00 "DR2,A/D Channel 2 Data Register" in hgroup.long 0x1C++0x03 hide.long 0x00 "DR3,A/D Channel 3 Data Register" in hgroup.long 0x20++0x03 hide.long 0x00 "DR4,A/D Channel 4 Data Register" in hgroup.long 0x24++0x03 hide.long 0x00 "DR5,A/D Channel 5 Data Register" in hgroup.long 0x28++0x03 hide.long 0x00 "DR6,A/D Channel 6 Data Register" in hgroup.long 0x2C++0x03 hide.long 0x00 "DR7,A/D Channel 7 Data Register" in newline rgroup.long 0x30++0x03 line.long 0x00 "STAT,A/D Status Register" bitfld.long 0x00 16. " ADINT ,A/D interrupt flag" "Not interrupted,Interrupted" newline bitfld.long 0x00 15. " OVERRUN[7] ,Mirrors OVERRUN status flag for channel 7" "No overrun,Overrun" bitfld.long 0x00 14. " [6] ,Mirrors OVERRUN status flag for channel 6" "No overrun,Overrun" bitfld.long 0x00 13. " [5] ,Mirrors OVERRUN status flag for channel 5" "No overrun,Overrun" bitfld.long 0x00 12. " [4] ,Mirrors OVERRUN status flag for channel 4" "No overrun,Overrun" newline bitfld.long 0x00 11. " [3] ,Mirrors OVERRUN status flag for channel 3" "No overrun,Overrun" bitfld.long 0x00 10. " [2] ,Mirrors OVERRUN status flag for channel 2" "No overrun,Overrun" bitfld.long 0x00 9. " [1] ,Mirrors OVERRUN status flag for channel 1" "No overrun,Overrun" bitfld.long 0x00 8. " [0] ,Mirrors OVERRUN status flag for channel 0" "No overrun,Overrun" newline bitfld.long 0x00 7. " DONE[7] ,Mirrors DONE status flag for channel 7" "Not done,Done" bitfld.long 0x00 6. " [6] ,Mirrors DONE status flag for channel 6" "Not done,Done" bitfld.long 0x00 5. " [5] ,Mirrors DONE status flag for channel 5" "Not done,Done" bitfld.long 0x00 4. " [4] ,Mirrors DONE status flag for channel 4" "Not done,Done" newline bitfld.long 0x00 3. " [3] ,Mirrors DONE status flag for channel 3" "Not done,Done" bitfld.long 0x00 2. " [2] ,Mirrors DONE status flag for channel 2" "Not done,Done" bitfld.long 0x00 1. " [1] ,Mirrors DONE status flag for channel 1" "Not done,Done" bitfld.long 0x00 0. " [0] ,Mirrors DONE status flag for channel 0" "Not done,Done" width 0x0B endif tree.end tree "FMC (Flash Memory Controller)" base ad:0x4003C000 width 11. sif cpuis("LPC11U6*") group.long 0x10++0x03 line.long 0x00 "FLASHCFG,Flash Configuration Register" bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 system clock,2 system clocks,3 system clocks,?..." group.long 0x20++0x07 line.long 0x00 "FMSSTART,Flash Module Signature Start Register" hexmask.long.tbyte 0x00 0.--16. 0x01 " START ,Start address for signature generation" line.long 0x04 "FMSSTOP,Flash Module Signature Stop Register" bitfld.long 0x04 17. " STRTBIST ,Signature generation start" "Not started,Started" hexmask.long.tbyte 0x04 0.--16. 0x01 " STOPA ,Stop address for signature generation" rgroup.long 0x2C++0x03 line.long 0x00 "FMSW0,Signature Generation Result Register" elif cpuis("LPC11U*") group.long 0x9C++0x07 line.long 0x00 "EEMSSTART,EEPROM BIST Start Address Register" hexmask.long.word 0x00 0.--13. 0x01 " STARTA ,BIST start address" line.long 0x04 "EEMSSTOP,EEPROM BIST Stop Address Register" bitfld.long 0x04 31. " STRTBIST ,BIST start" "Not started,Started" bitfld.long 0x04 30. " DEVSEL ,BIST device select" "Multiple EEPROM devices,Single EEPROM device" hexmask.long.word 0x04 0.--13. 0x01 " STOPA ,BIST stop address" rgroup.long 0xA4++0x03 line.long 0x00 "EEMSSIG,EEPROM BIST Signature Register" hexmask.long.word 0x00 16.--31. 1. " PARITY_SIG ,BIST 16-bit signature calculated from only the parity bits of the data bytes" hexmask.long.word 0x00 0.--15. 1. " DATA_SIG ,BIST 16-bit signature calculated from only the data bytes" group.long 0x10++0x03 line.long 0x00 "FLASHCFG,Flash Configuration Register" bitfld.long 0x00 0.--1. " FLASHTIM ,Flash memory access time" "1 system clock,2 system clocks,3 system clocks,?..." group.long 0x20++0x07 line.long 0x00 "FMSSTART,Flash Module Signature Start Register" hexmask.long.tbyte 0x00 0.--16. 0x01 " START ,Start address for signature generation" line.long 0x04 "FMSSTOP, Flash Module Signature Stop Address Register" bitfld.long 0x04 17. " SIG_START ,Signature generation start" "Not started,Started" hexmask.long.tbyte 0x04 0.--16. 0x01 " STOP ,Stop address for signature generation" rgroup.long 0x2C++0x0F line.long 0x00 "FMSW0,Word 0 Of 128-Bit Signature Register" line.long 0x04 "FMSW1,Word 1 Of 128-Bit Signature Register" line.long 0x08 "FMSW2,Word 2 Of 128-Bit Signature Register" line.long 0x0C "FMSW3,Word 3 Of 128-Bit Signature Register" rgroup.long 0xFE0++0x03 line.long 0x00 "FMSTAT,Flash Module Status Register" bitfld.long 0x00 2. " SIG_DONE ,Previously started signature generation has completed" "Not completed,Completed" wgroup.long 0xFE8++0x03 line.long 0x00 "FMSTATCLR,Flash Module Status Clear Register" bitfld.long 0x00 2. " SIG_DONE_CLR ,SIG_DONE flag clear" "Not cleared,Cleared" endif width 0x0B tree.end textline ""