; --------------------------------------------------------------------------------
; @Title: LH77790 On-Chip Peripherals
; @Props: Released
; @Author: SYL
; @Changelog: 2005-02-21 SYL
; @Manufacturer: SHARP - SHARP
; @Core: ARM7DI
; @Chip: LH77790
; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perlh77790.per 17441 2024-02-02 17:32:46Z kwisniewski $

config 16. 8.
width 0x0B
base ad:0x00000000
tree "Cache"
width 0x05
group (0xFFFFA400+0x0)--(0xFFFFA400+0x0)
line.byte 0x00 "CCR,Cache Control Register"
bitfld.byte 0x00 3. " I ,Cache Mode Bit" "Disabled,Enabled"
bitfld.byte 0x00 2. "  F ,SRAM Mode Bit" "Disabled,Enabled"
bitfld.byte 0x00 1. "  S ,Flush Mode Bit" "Disabled,Enabled"
bitfld.byte 0x00 0. "  E ,Invalidate Mode Bit" "Valid,Invalid"
width 0x0B
tree.end
tree "Local SRAM"
width 0x06
group (0xFFFFA400+0x4)--(0xFFFFA400+0x4)
line.byte 0x00 "LSCR,Local SRAM Control Register"
bitfld.byte 0x00 1. " L ,Local SRAM Enable Bit" "Disabled,Enabled"
bitfld.byte 0x00 0. "  E ,Local SRAM Location" "0x00000000:0x000007FF,0x60000000:0x600007FF"
width 0x0B
tree.end
tree "Memory and Peripheral Interface"
width 0x08 0x08
group (0xFFFFA000+0x00)--(0xFFFFA000+0x063)
line.long 0x00 "START0,Segment 0 START"
hexmask.long 0x00 10.--31. 1024. " START_Addr ,Segment 0 START Address"
line.long 0x04 "START1,Segment 1 START"
hexmask.long 0x04 10.--31. 1024. " START_Addr ,Segment 1 START Address"
line.long 0x08 "START2,Segment 2 START"
hexmask.long 0x08 10.--31. 1024. " START_Addr ,Segment 2 START Address"
line.long 0x0C "START3,Segment 3 START"
hexmask.long 0x0C 10.--31. 1024. " START_Addr ,Segment 3 START Address"
line.long 0x10 "START4,Segment 4 START"
hexmask.long 0x10 10.--31. 1024. " START_Addr ,Segment 4 START Address"
line.long 0x14 "START5,Segment 5 START"
hexmask.long 0x14 10.--31. 1024. " START_Addr ,Segment 5 START Address"
line.long 0x18 "START6,Segment 6 START"
hexmask.long 0x18 10.--31. 1024. " START_Addr ,Segment 6 START Address"
line.long 0x1C "START7,Segment 7 START"
hexmask.long 0x1C 10.--31. 1024. " START_Addr ,Segment 7 START Address"
line.long 0x20 "STOP0,Segment 0 STOP"
hexmask.long 0x20 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.long 0x24 "STOP1,Segment 1 STOP"
hexmask.long 0x24 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.long 0x28 "STOP2,Segment 2 STOP"
hexmask.long 0x28 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.long 0x2C "STOP3,Segment 3 STOP"
hexmask.long 0x2C 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.long 0x30 "STOP4,Segment 4 STOP"
hexmask.long 0x30 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.long 0x34 "STOP5,Segment 5 STOP"
hexmask.long 0x34 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.long 0x38 "STOP6,Segment 6 STOP"
hexmask.long 0x38 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.long 0x3C "STOP7,Segment 7 STOP"
hexmask.long 0x3C 10.--31. 1024. " STOP_Addr  ,Segment 0 STOP Address"
line.word 0x40 "SDR0,Segment 0 Descriptor"
bitfld.word 0x40 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x40 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x40 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x40 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x40 " BSEL       ,Bank Select"
line.word 0x44 "SDR1,Segment 1 Descriptor"
bitfld.word 0x44 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x44 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x44 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x44 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x44 " BSEL       ,Bank Select"
line.word 0x48 "SDR2,Segment 2 Descriptor"
bitfld.word 0x48 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x48 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x48 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x48 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x48 " BSEL       ,Bank Select"
line.word 0x4C "SDR3,Segment 3 Descriptor"
bitfld.word 0x4C 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x4C 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x4C 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x4C 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x4C " BSEL       ,Bank Select"
line.word 0x50 "SDR4,Segment 4 Descriptor"
bitfld.word 0x50 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x50 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x50 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x50 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x50 " BSEL       ,Bank Select"
line.word 0x54 "SDR5,Segment 5 Descriptor"
bitfld.word 0x54 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x54 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x54 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x54 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x54 " BSEL       ,Bank Select"
line.word 0x58 "SDR6,Segment 6 Descriptor"
bitfld.word 0x58 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x58 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x58 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x58 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x58 " BSEL       ,Bank Select"
line.word 0x5C "SDR7,Segment 7 Descriptor"
bitfld.word 0x5C 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x5C 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x5C 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x5C 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x5C " BSEL       ,Bank Select"
line.word 0x60 "SDR8,Segment 8 Descriptor"
bitfld.word 0x60 13.--14. "     SPR        ,System Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x60 11.--12. "  UPR   ,User Privilege" "No priviliges,Read only,Write only,Read/Write"
bitfld.word 0x60 10. "  C     ,Cacheability" "Not cacheable,Cacheable"
bitfld.word 0x60 8. "                  HW    ,Half-Word Mode" "32-bit,16-bit"
textline "                 "
hexfld.byte 0x60 " BSEL       ,Bank Select"
group (0xFFFFA100+0x00)--(0xFFFFA100+0x02B)
line.word 0x00 "BCR0,Bank Control 0 (SRAM)"
bitfld.word 0x00 15. "     MS         ,External SRAM Bus Size" "x8,x16"
bitfld.word 0x00 12.--14. "            WAIT  ,Wait Cycles for external SRAM" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 10.--11. "              ECE5  ,External Chip 5 Enable Control" "00,01,10,11"
bitfld.word 0x00 8.--9. "                             ECE4  ,External Chip 4 Enable Control" "00,01,10,11"
textline "                 "
bitfld.word 0x00 6.--7. " ECE3       ,External Chip 3 Enable Control" "00,01,10,11"
bitfld.word 0x00 4.--5. "             ECE2  ,External Chip 2 Enable Control" "00,01,10,11"
bitfld.word 0x00 2.--3. "             ECE1  ,External Chip 1 Enable Control" "00,01,10,11"
bitfld.word 0x00 0.--1. "                             ECE0  ,External Chip 0 Enable Control" "00,01,10,11"
line.word 0x04 "BCR1,Bank Control 1 (SRAM)"
bitfld.word 0x04 15. "     MS         ,External SRAM Bus Size" "x8,x16"
bitfld.word 0x04 12.--14. "            WAIT  ,Wait Cycles for external SRAM" "0,1,2,3,4,5,6,7"
bitfld.word 0x04 10.--11. "              ECE5  ,External Chip 5 Enable Control" "00,01,10,11"
bitfld.word 0x04 8.--9. "                             ECE4  ,External Chip 4 Enable Control" "00,01,10,11"
textline "                 "
bitfld.word 0x04 6.--7. " ECE3       ,External Chip 3 Enable Control" "00,01,10,11"
bitfld.word 0x04 4.--5. "             ECE2  ,External Chip 2 Enable Control" "00,01,10,11"
bitfld.word 0x04 2.--3. "             ECE1  ,External Chip 1 Enable Control" "00,01,10,11"
bitfld.word 0x04 0.--1. "                             ECE0  ,External Chip 0 Enable Control" "00,01,10,11"
line.word 0x08 "BCR2,Bank Control 2 (SRAM)"
bitfld.word 0x08 15. "     MS         ,External SRAM Bus Size" "x8,x16"
bitfld.word 0x08 12.--14. "            WAIT  ,Wait Cycles for external SRAM" "0,1,2,3,4,5,6,7"
bitfld.word 0x08 10.--11. "              ECE5  ,External Chip 5 Enable Control" "00,01,10,11"
bitfld.word 0x08 8.--9. "                             ECE4  ,External Chip 4 Enable Control" "00,01,10,11"
textline "                 "
bitfld.word 0x08 6.--7. " ECE3       ,External Chip 3 Enable Control" "00,01,10,11"
bitfld.word 0x08 4.--5. "             ECE2  ,External Chip 2 Enable Control" "00,01,10,11"
bitfld.word 0x08 2.--3. "             ECE1  ,External Chip 1 Enable Control" "00,01,10,11"
bitfld.word 0x08 0.--1. "                             ECE0  ,External Chip 0 Enable Control" "00,01,10,11"
line.word 0x0C "BCR3,Bank Control 3 (SRAM)"
bitfld.word 0x0C 15. "     MS         ,External SRAM Bus Size" "x8,x16"
bitfld.word 0x0C 12.--14. "            WAIT  ,Wait Cycles for external SRAM" "0,1,2,3,4,5,6,7"
bitfld.word 0x0C 10.--11. "              ECE5  ,External Chip 5 Enable Control" "00,01,10,11"
bitfld.word 0x0C 8.--9. "                             ECE4  ,External Chip 4 Enable Control" "00,01,10,11"
textline "                 "
bitfld.word 0x0C 6.--7. " ECE3       ,External Chip 3 Enable Control" "00,01,10,11"
bitfld.word 0x0C 4.--5. "             ECE2  ,External Chip 2 Enable Control" "00,01,10,11"
bitfld.word 0x0C 2.--3. "             ECE1  ,External Chip 1 Enable Control" "00,01,10,11"
bitfld.word 0x0C 0.--1. "                             ECE0  ,External Chip 0 Enable Control" "00,01,10,11"
line.word 0x10 "BCR4,Bank Control 4 (SRAM)"
bitfld.word 0x10 15. "     MS         ,External SRAM Bus Size" "x8,x16"
bitfld.word 0x10 12.--14. "            WAIT  ,Wait Cycles for external SRAM" "0,1,2,3,4,5,6,7"
bitfld.word 0x10 10.--11. "              ECE5  ,External Chip 5 Enable Control" "00,01,10,11"
bitfld.word 0x10 8.--9. "                             ECE4  ,External Chip 4 Enable Control" "00,01,10,11"
textline "                 "
bitfld.word 0x10 6.--7. " ECE3       ,External Chip 3 Enable Control" "00,01,10,11"
bitfld.word 0x10 4.--5. "             ECE2  ,External Chip 2 Enable Control" "00,01,10,11"
bitfld.word 0x10 2.--3. "             ECE1  ,External Chip 1 Enable Control" "00,01,10,11"
bitfld.word 0x10 0.--1. "                             ECE0  ,External Chip 0 Enable Control" "00,01,10,11"
line.word 0x14 "BCR5,Bank Control 5 (SRAM)"
bitfld.word 0x14 15. "     MS         ,External SRAM Bus Size" "x8,x16"
bitfld.word 0x14 12.--14. "            WAIT  ,Wait Cycles for external SRAM" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 10.--11. "              ECE5  ,External Chip 5 Enable Control" "00,01,10,11"
bitfld.word 0x14 8.--9. "                             ECE4  ,External Chip 4 Enable Control" "00,01,10,11"
textline "                 "
bitfld.word 0x14 6.--7. " ECE3       ,External Chip 3 Enable Control" "00,01,10,11"
bitfld.word 0x14 4.--5. "             ECE2  ,External Chip 2 Enable Control" "00,01,10,11"
bitfld.word 0x14 2.--3. "             ECE1  ,External Chip 1 Enable Control" "00,01,10,11"
bitfld.word 0x14 0.--1. "                             ECE0  ,External Chip 0 Enable Control" "00,01,10,11"
line.word 0x18 "BCR6a,Bank Control 6a (DRAM)"
bitfld.word 0x18 15. "     MS         ,External DRAM Bus Size" "x8,x16"
bitfld.word 0x18 12.--14. "            FCAS  ,First Transfer CAS Width" "000,001,010,011,100,101,110,111"
bitfld.word 0x18 10.--11. "            ECAS5 ,External CAS5 Controls" "00,01,10,11"
bitfld.word 0x18 8.--9. "                             ECAS4 ,External CAS4 Controls" "00,01,10,11"
textline "                 "
bitfld.word 0x18 6.--7. " ECAS3      ,External CAS3 Controls" "00,01,10,11"
bitfld.word 0x18 4.--5. "             ECAS2 ,External CAS2 Controls" "00,01,10,11"
bitfld.word 0x18 2.--3. "             ECAS1 ,External CAS1 Controls" "00,01,10,11"
bitfld.word 0x18 0.--1. "                             ECAS0 ,External CAS0 Controls" "00,01,10,11"
line.word 0x1C "BCR7a,Bank Control 7a (DRAM)"
bitfld.word 0x1C 15. "     MS         ,External DRAM Bus Size" "x8,x16"
bitfld.word 0x1C 12.--14. "            FCAS  ,First Transfer CAS Width" "000,001,010,011,100,101,110,111"
bitfld.word 0x1C 10.--11. "            ECAS5 ,External CAS5 Controls" "00,01,10,11"
bitfld.word 0x1C 8.--9. "                             ECAS4 ,External CAS4 Controls" "00,01,10,11"
textline "                 "
bitfld.word 0x1C 6.--7. " ECAS3      ,External CAS3 Controls" "00,01,10,11"
bitfld.word 0x1C 4.--5. "             ECAS2 ,External CAS2 Controls" "00,01,10,11"
bitfld.word 0x1C 2.--3. "             ECAS1 ,External CAS1 Controls" "00,01,10,11"
bitfld.word 0x1C 0.--1. "                             ECAS0 ,External CAS0 Controls" "00,01,10,11"
line.byte 0x20 "BCR6b,Bank Control 6b (DRAM)"
bitfld.byte 0x20 5.--6. "     BCAS       ,Burst Transfer CAS Width" "1.5 cycles,1.5 cycles,2.5 cycles,3.5 cycles"
bitfld.byte 0x20 4. "     R     ,Refresh Active" "Not active,Active"
bitfld.byte 0x20 1.--3. "     BS    ,DRAM Bank Size" "256Kx8 512Kx8 256Kx16 512Kx16,1Mx8 2Mx8 1Mx16 2Mx16,4Mx8 8Mx8 4Mx16 8Mx16,16Mx8 32Mx8 16Mx16 32Mx16,64Mx8 128Mx8 64Mx16,?..."
bitfld.byte 0x20 0. "  PM    ,DRAM Page Mode" "Normal mode,Page mode"
line.byte 0x24 "BCR7b,Bank Control 7b (DRAM)"
bitfld.byte 0x24 5.--6. "     BCAS       ,Burst Transfer CAS Width" "1.5 cycles,1.5 cycles,2.5 cycles,3.5 cycles"
bitfld.byte 0x24 4. "     R     ,Refresh Active" "Not active,Active"
bitfld.byte 0x24 1.--3. "     BS    ,DRAM Bank Size" "256Kx8 512Kx8 256Kx16 512Kx16,1Mx8 2Mx8 1Mx16 2Mx16,4Mx8 8Mx8 4Mx16 8Mx16,16Mx8 32Mx8 16Mx16 32Mx16,64Mx8 128Mx8 64Mx16,?..."
bitfld.byte 0x24 0. "  PM    ,DRAM Page Mode" "Normal mode,Page mode"
line.word 0x28 "DRR,DRAM Refresh"
width 0x0B
tree.end
tree "UARTs"
tree "UART0"
width 0x06
if (((data.byte(sd:(0xFFFF0000+0x0C)))&0x80)==0x00)
rgroup (0xFFFF0000+0x00)--(0xFFFF0000+0x00)
line.byte 0x00 "RBR0,UART0 Receive Buffer Register"
wgroup (0xFFFF0000+0x00)--(0xFFFF0000+0x00)
hide.byte 0x00 "THR0,UART0 Transmitter Holding Register"
in
group (0xFFFF0000+0x04)--(0xFFFF0000+0x04)
line.byte 0x00 "IER0,UART0 Interrupt Enable Register"
bitfld.byte 0x00 3. " EDSSI ,Enable Modem Status Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 2. "              ELSI ,Enable Receiver Line Status Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 1. "         ETBEI  ,Enable Transmit Holding Register Empty Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 0. "     ERBFI ,Enable Receiver Buffer Interrupt" "Disabled,Enabled"
else
group (0xFFFF0000+0x00)--(0xFFFF0000+0x00)
line.byte 0x00 "DLL0,UART0 Divisor Latch LSB Register"
group (0xFFFF0000+0x04)--(0xFFFF0000+0x04)
line.byte 0x00 "DLM0,UART0 Divisor Latch MSB Register"
endif
rgroup (0xFFFF0000+0x08)--(0xFFFF0000+0x08)
line.byte 0x00 "IIR0,UART0 Interrupt Identification Register"
bitfld.byte 0x00 0.--2. " IIR   ,Interrupt Identification" "Modem Status,No interrupt,THR Empty,Reserved,Receiver Buffer,Reserved,Receiver Line Status,?..."
if (((data.byte(sd:(0xFFFF0000+0x0C)))&0x03)==0x00)
group (0xFFFF0000+0x0C)--(0xFFFF0000+0x0C)
line.byte 0x00 "LCR0,UART0 Line Control Register"
bitfld.byte 0x00 7. " DLAB  ,Divisor Latch Access Bit" "RBR/THR/IER,DLL/DLM"
bitfld.byte 0x00 6. "           SB   ,Set Break" "Normal,TxD forced to 0"
bitfld.byte 0x00 4.--5. "  PARITY ,Parity Type" "Odd,Even,Force 1,Force 0"
bitfld.byte 0x00 3. "      PEN   ,Parity Enable" "Disabled,Enabled"
textline "           "
bitfld.byte 0x00 2. " STB   ,STOP bits" "1 bit,1.5 bits"
bitfld.byte 0x00 0.--1. "              CL   ,Character Length" "5 bits,6 bits,7 bits,8 bits"
else
group (0xFFFF0000+0x0C)--(0xFFFF0000+0x0C)
line.byte 0x00 "LCR0,UART0 Line Control Register"
bitfld.byte 0x00 7. " DLAB  ,Divisor Latch Access Bit" "RBR/THR/IER,DLL/DLM"
bitfld.byte 0x00 6. "           SB   ,Set Break" "Normal,TxD forced to 0"
bitfld.byte 0x00 4.--5. "  PARITY ,Parity Type" "Odd,Even,Force 1,Force 0"
bitfld.byte 0x00 3. "      PEN   ,Parity Enable" "Disabled,Enabled"
textline "           "
bitfld.byte 0x00 2. " STB   ,STOP bits" "1 bit,2 bits  "
bitfld.byte 0x00 0.--1. "              CL   ,Character Length" "5 bits,6 bits,7 bits,8 bits"
endif
group (0xFFFF0000+0x10)--(0xFFFF0000+0x10)
line.byte 0x00 "MCR0,UART0 Modem Control Register"
bitfld.byte 0x00 4. " Loop  ,Loop Back Mode" "Disabled,Enabled"
bitfld.byte 0x00 3. "              OUT2 ,Controls /OUT2 output in normal and loop back operation" "High,Low"
bitfld.byte 0x00 2. "             OUT1   ,Controls /OUT1 Output in normal and loop back operation" "High,Low"
bitfld.byte 0x00 1. "         RTS   ,Controls /RTS Output in normal and loop back operation" "High,Low"
textline "           "
bitfld.byte 0x00 0. " DTR   ,Controls /DTR Output in normal and loop back operation" "High,Low"
rgroup (0xFFFF0000+0x14)--(0xFFFF0000+0x14)
line.byte 0x00 "LSR0,UART0 Line Status Register"
bitfld.byte 0x00 6. " TEMT  ,Transmitter Empty" "Not empty,Empty"
bitfld.byte 0x00 5. "             THRE ,Transmitter Holding Register Empty" "Not empty,Empty"
bitfld.byte 0x00 4. "        BI     ,Break Interrupt" "Not occured,Occured"
bitfld.byte 0x00 3. "  FE    ,Frame Error" "No error,Error"
textline "           "
bitfld.byte 0x00 2. " PE    ,PARITY Error" "No error,Error"
bitfld.byte 0x00 1. "              OE   ,Overrun Error" "No error,Error"
bitfld.byte 0x00 0. "         DR     ,Data Ready" "Not ready,Ready"
if (((data.byte(sd:(0xFFFF0000+0x10)))&0x10)==0x00)
group (0xFFFF0000+0x18)--(0xFFFF0000+0x18)
line.byte 0x00 "MSR0,UART0 Modem Status Register"
bitfld.byte 0x00 7. " DCD   ,Data Carrier Detect - Reflects the Complement of the external /DCD input" "High,Low"
bitfld.byte 0x00 6. "                  RI   ,Ring Indicator - Reflects the Complement of the external /RI input" "High,Low"
bitfld.byte 0x00 5. "             DSR    ,Data Set Ready - Reflects the complement of the external /DSR input" "High,Low"
bitfld.byte 0x00 4. "         CTS   ,Clear to Send - Reflects the complement of the external /CTS input" "High,Low"
textline "           "
bitfld.byte 0x00 3. " DDCD  ,Delta Data Carrier Detect" "Not changed,Changed"
bitfld.byte 0x00 2. "           TERI ,Trailing Edge Ring Indicator" "Not occured,Occured"
bitfld.byte 0x00 1. "      DDSR   ,Delta Data Set Ready" "Not changed,Changed"
bitfld.byte 0x00 0. "  DCTS  ,Delta Clear to Send" "Not changed,Changed"
else
group (0xFFFF0000+0x18)--(0xFFFF0000+0x18)
line.byte 0x00 "MSR0,UART0 Modem Status Register"
bitfld.byte 0x00 7. " DCD   ,Data Carrier Detect - Reflects the value of OUT2 bit in MCR" "High,Low"
bitfld.byte 0x00 6. "                  RI   ,Ring Indicator - Reflects the value of OUT1 bit in MCR" "High,Low"
bitfld.byte 0x00 5. "             DSR    ,Data Set Ready - Reflects the value of DTR bit in MCR" "High,Low"
bitfld.byte 0x00 4. "         CTS   ,Clear to Send - Reflects the value of RTS bit in MCR" "High,Low"
textline "           "
bitfld.byte 0x00 3. " DDCD  ,Delta Data Carrier Detect" "Not changed,Changed"
bitfld.byte 0x00 2. "           TERI ,Trailing Edge Ring Indicator" "Not occured,Occured"
bitfld.byte 0x00 1. "      DDSR   ,Delta Data Set Ready" "Not changed,Changed"
bitfld.byte 0x00 0. "  DCTS  ,Delta Clear to Send" "Not changed,Changed"
endif
group (0xFFFF0000+0x1C)--(0xFFFF0000+0x1C)
line.byte 0x00 "SCR0,UART0 Scratch Pad Register"
width 0x0B
tree.end
tree "UART1"
width 0x06
if (((data.byte(sd:(0xFFFF0400+0x0C)))&0x80)==0x00)
rgroup (0xFFFF0400+0x00)--(0xFFFF0400+0x00)
line.byte 0x00 "RBR1,UART1 Receive Buffer Register"
wgroup (0xFFFF0400+0x00)--(0xFFFF0400+0x00)
hide.byte 0x00 "THR1,UART1 Transmitter Holding Register"
in
group (0xFFFF0400+0x04)--(0xFFFF0400+0x04)
line.byte 0x00 "IER1,UART1 Interrupt Enable Register"
bitfld.byte 0x00 3. " EDSSI ,Enable Modem Status Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 2. "              ELSI ,Enable Receiver Line Status Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 1. "         ETBEI  ,Enable Transmit Holding Register Empty Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 0. "     ERBFI ,Enable Receiver Buffer Interrupt" "Disabled,Enabled"
else
group (0xFFFF0400+0x00)--(0xFFFF0400+0x00)
line.byte 0x00 "DLL1,UART1 Divisor Latch LSB Register"
group (0xFFFF0400+0x04)--(0xFFFF0400+0x04)
line.byte 0x00 "DLM1,UART1 Divisor Latch MSB Register"
endif
rgroup (0xFFFF0400+0x08)--(0xFFFF0400+0x08)
line.byte 0x00 "IIR1,UART1 Interrupt Identification Register"
bitfld.byte 0x00 0.--2. " IIR   ,Interrupt Identification" "Modem Status,No interrupt,THR Empty,Reserved,Receiver Buffer,Reserved,Receiver Line Status,?..."
if (((data.byte(sd:(0xFFFF0400+0x0C)))&0x03)==0x00)
group (0xFFFF0400+0x0C)--(0xFFFF0400+0x0C)
line.byte 0x00 "LCR1,UART1 Line Control Register"
bitfld.byte 0x00 7. " DLAB  ,Divisor Latch Access Bit" "RBR/THR/IER,DLL/DLM"
bitfld.byte 0x00 6. "           SB   ,Set Break" "Normal,TxD forced to 0"
bitfld.byte 0x00 4.--5. "  PARITY ,Parity Type" "Odd,Even,Force 1,Force 0"
bitfld.byte 0x00 3. "      PEN   ,Parity Enable" "Disabled,Enabled"
textline "           "
bitfld.byte 0x00 2. " STB   ,STOP bits" "1 bit,1.5 bits"
bitfld.byte 0x00 0.--1. "              CL   ,Character Length" "5 bits,6 bits,7 bits,8 bits"
else
group (0xFFFF0400+0x0C)--(0xFFFF0400+0x0C)
line.byte 0x00 "LCR1,UART1 Line Control Register"
bitfld.byte 0x00 7. " DLAB  ,Divisor Latch Access Bit" "RBR/THR/IER,DLL/DLM"
bitfld.byte 0x00 6. "           SB   ,Set Break" "Normal,TxD forced to 0"
bitfld.byte 0x00 4.--5. "  PARITY ,Parity Type" "Odd,Even,Force 1,Force 0"
bitfld.byte 0x00 3. "      PEN   ,Parity Enable" "Disabled,Enabled"
textline "           "
bitfld.byte 0x00 2. " STB   ,STOP bits" "1 bit,2 bits  "
bitfld.byte 0x00 0.--1. "              CL   ,Character Length" "5 bits,6 bits,7 bits,8 bits"
endif
group (0xFFFF0400+0x10)--(0xFFFF0400+0x10)
line.byte 0x00 "MCR1,UART1 Modem Control Register"
bitfld.byte 0x00 4. " Loop  ,Loop Back Mode" "Disabled,Enabled"
bitfld.byte 0x00 3. "              OUT2 ,Controls /OUT2 output in normal and loop back operation" "High,Low"
bitfld.byte 0x00 2. "             OUT1   ,Controls /OUT1 Output in normal and loop back operation" "High,Low"
bitfld.byte 0x00 1. "         RTS   ,Controls /RTS Output in normal and loop back operation" "High,Low"
textline "           "
bitfld.byte 0x00 0. " DTR   ,Controls /DTR Output in normal and loop back operation" "High,Low"
rgroup (0xFFFF0400+0x14)--(0xFFFF0400+0x14)
line.byte 0x00 "LSR1,UART1 Line Status Register"
bitfld.byte 0x00 6. " TEMT  ,Transmitter Empty" "Not empty,Empty"
bitfld.byte 0x00 5. "             THRE ,Transmitter Holding Register Empty" "Not empty,Empty"
bitfld.byte 0x00 4. "        BI     ,Break Interrupt" "Not occured,Occured"
bitfld.byte 0x00 3. "  FE    ,Frame Error" "No error,Error"
textline "           "
bitfld.byte 0x00 2. " PE    ,PARITY Error" "No error,Error"
bitfld.byte 0x00 1. "              OE   ,Overrun Error" "No error,Error"
bitfld.byte 0x00 0. "         DR     ,Data Ready" "Not ready,Ready"
if (((data.byte(sd:(0xFFFF0400+0x10)))&0x10)==0x00)
group (0xFFFF0400+0x18)--(0xFFFF0400+0x18)
line.byte 0x00 "MSR1,UART1 Modem Status Register"
bitfld.byte 0x00 7. " DCD   ,Data Carrier Detect - Reflects the Complement of the external /DCD input" "High,Low"
bitfld.byte 0x00 6. "                  RI   ,Ring Indicator - Reflects the Complement of the external /RI input" "High,Low"
bitfld.byte 0x00 5. "             DSR    ,Data Set Ready - Reflects the complement of the external /DSR input" "High,Low"
bitfld.byte 0x00 4. "         CTS   ,Clear to Send - Reflects the complement of the external /CTS input" "High,Low"
textline "           "
bitfld.byte 0x00 3. " DDCD  ,Delta Data Carrier Detect" "Not changed,Changed"
bitfld.byte 0x00 2. "           TERI ,Trailing Edge Ring Indicator" "Not occured,Occured"
bitfld.byte 0x00 1. "      DDSR   ,Delta Data Set Ready" "Not changed,Changed"
bitfld.byte 0x00 0. "  DCTS  ,Delta Clear to Send" "Not changed,Changed"
else
group (0xFFFF0400+0x18)--(0xFFFF0400+0x18)
line.byte 0x00 "MSR1,UART1 Modem Status Register"
bitfld.byte 0x00 7. " DCD   ,Data Carrier Detect - Reflects the value of OUT2 bit in MCR" "High,Low"
bitfld.byte 0x00 6. "                  RI   ,Ring Indicator - Reflects the value of OUT1 bit in MCR" "High,Low"
bitfld.byte 0x00 5. "             DSR    ,Data Set Ready - Reflects the value of DTR bit in MCR" "High,Low"
bitfld.byte 0x00 4. "         CTS   ,Clear to Send - Reflects the value of RTS bit in MCR" "High,Low"
textline "           "
bitfld.byte 0x00 3. " DDCD  ,Delta Data Carrier Detect" "Not changed,Changed"
bitfld.byte 0x00 2. "           TERI ,Trailing Edge Ring Indicator" "Not occured,Occured"
bitfld.byte 0x00 1. "      DDSR   ,Delta Data Set Ready" "Not changed,Changed"
bitfld.byte 0x00 0. "  DCTS  ,Delta Clear to Send" "Not changed,Changed"
endif
group (0xFFFF0400+0x1C)--(0xFFFF0400+0x1C)
line.byte 0x00 "SCR1,UART1 Scratch Pad Register"
width 0x0B
tree.end
tree "UART2"
width 0x06
if (((data.byte(sd:(0xFFFF0800+0x0C)))&0x80)==0x00)
rgroup (0xFFFF0800+0x00)--(0xFFFF0800+0x00)
line.byte 0x00 "RBR2,UART2 Receive Buffer Register"
wgroup (0xFFFF0800+0x00)--(0xFFFF0800+0x00)
hide.byte 0x00 "THR2,UART2 Transmitter Holding Register"
in
group (0xFFFF0800+0x04)--(0xFFFF0800+0x04)
line.byte 0x00 "IER2,UART2 Interrupt Enable Register"
bitfld.byte 0x00 3. " EDSSI ,Enable Modem Status Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 2. "              ELSI ,Enable Receiver Line Status Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 1. "         ETBEI  ,Enable Transmit Holding Register Empty Interrupt" "Disabled,Enabled"
bitfld.byte 0x00 0. "     ERBFI ,Enable Receiver Buffer Interrupt" "Disabled,Enabled"
else
group (0xFFFF0800+0x00)--(0xFFFF0800+0x00)
line.byte 0x00 "DLL2,UART2 Divisor Latch LSB Register"
group (0xFFFF0800+0x04)--(0xFFFF0800+0x04)
line.byte 0x00 "DLM2,UART2 Divisor Latch MSB Register"
endif
rgroup (0xFFFF0800+0x08)--(0xFFFF0800+0x08)
line.byte 0x00 "IIR2,UART2 Interrupt Identification Register"
bitfld.byte 0x00 0.--2. " IIR   ,Interrupt Identification" "Modem Status,No interrupt,THR Empty,Reserved,Receiver Buffer,Reserved,Receiver Line Status,?..."
if (((data.byte(sd:(0xFFFF0800+0x0C)))&0x03)==0x00)
group (0xFFFF0800+0x0C)--(0xFFFF0800+0x0C)
line.byte 0x00 "LCR2,UART2 Line Control Register"
bitfld.byte 0x00 7. " DLAB  ,Divisor Latch Access Bit" "RBR/THR/IER,DLL/DLM"
bitfld.byte 0x00 6. "           SB   ,Set Break" "Normal,TxD forced to 0"
bitfld.byte 0x00 4.--5. "  PARITY ,Parity Type" "Odd,Even,Force 1,Force 0"
bitfld.byte 0x00 3. "      PEN   ,Parity Enable" "Disabled,Enabled"
textline "           "
bitfld.byte 0x00 2. " STB   ,STOP bits" "1 bit,1.5 bits"
bitfld.byte 0x00 0.--1. "              CL   ,Character Length" "5 bits,6 bits,7 bits,8 bits"
else
group (0xFFFF0800+0x0C)--(0xFFFF0800+0x0C)
line.byte 0x00 "LCR2,UART2 Line Control Register"
bitfld.byte 0x00 7. " DLAB  ,Divisor Latch Access Bit" "RBR/THR/IER,DLL/DLM"
bitfld.byte 0x00 6. "           SB   ,Set Break" "Normal,TxD forced to 0"
bitfld.byte 0x00 4.--5. "  PARITY ,Parity Type" "Odd,Even,Force 1,Force 0"
bitfld.byte 0x00 3. "      PEN   ,Parity Enable" "Disabled,Enabled"
textline "           "
bitfld.byte 0x00 2. " STB   ,STOP bits" "1 bit,2 bits  "
bitfld.byte 0x00 0.--1. "              CL   ,Character Length" "5 bits,6 bits,7 bits,8 bits"
endif
group (0xFFFF0800+0x10)--(0xFFFF0800+0x10)
line.byte 0x00 "MCR2,UART2 Modem Control Register"
bitfld.byte 0x00 4. " Loop  ,Loop Back Mode" "Disabled,Enabled"
bitfld.byte 0x00 3. "              OUT2 ,Controls /OUT2 output in normal and loop back operation" "High,Low"
bitfld.byte 0x00 2. "             OUT1   ,Controls /OUT1 Output in normal and loop back operation" "High,Low"
bitfld.byte 0x00 1. "         RTS   ,Controls /RTS Output in normal and loop back operation" "High,Low"
textline "           "
bitfld.byte 0x00 0. " DTR   ,Controls /DTR Output in normal and loop back operation" "High,Low"
rgroup (0xFFFF0800+0x14)--(0xFFFF0800+0x14)
line.byte 0x00 "LSR2,UART2 Line Status Register"
bitfld.byte 0x00 6. " TEMT  ,Transmitter Empty" "Not empty,Empty"
bitfld.byte 0x00 5. "             THRE ,Transmitter Holding Register Empty" "Not empty,Empty"
bitfld.byte 0x00 4. "        BI     ,Break Interrupt" "Not occured,Occured"
bitfld.byte 0x00 3. "  FE    ,Frame Error" "No error,Error"
textline "           "
bitfld.byte 0x00 2. " PE    ,PARITY Error" "No error,Error"
bitfld.byte 0x00 1. "              OE   ,Overrun Error" "No error,Error"
bitfld.byte 0x00 0. "         DR     ,Data Ready" "Not ready,Ready"
if (((data.byte(sd:(0xFFFF0800+0x10)))&0x10)==0x00)
group (0xFFFF0800+0x18)--(0xFFFF0800+0x18)
line.byte 0x00 "MSR2,UART2 Modem Status Register"
bitfld.byte 0x00 7. " DCD   ,Data Carrier Detect - Reflects the Complement of the external /DCD input" "High,Low"
bitfld.byte 0x00 6. "                  RI   ,Ring Indicator - Reflects the Complement of the external /RI input" "High,Low"
bitfld.byte 0x00 5. "             DSR    ,Data Set Ready - Reflects the complement of the external /DSR input" "High,Low"
bitfld.byte 0x00 4. "         CTS   ,Clear to Send - Reflects the complement of the external /CTS input" "High,Low"
textline "           "
bitfld.byte 0x00 3. " DDCD  ,Delta Data Carrier Detect" "Not changed,Changed"
bitfld.byte 0x00 2. "           TERI ,Trailing Edge Ring Indicator" "Not occured,Occured"
bitfld.byte 0x00 1. "      DDSR   ,Delta Data Set Ready" "Not changed,Changed"
bitfld.byte 0x00 0. "  DCTS  ,Delta Clear to Send" "Not changed,Changed"
else
group (0xFFFF0800+0x18)--(0xFFFF0800+0x18)
line.byte 0x00 "MSR2,UART2 Modem Status Register"
bitfld.byte 0x00 7. " DCD   ,Data Carrier Detect - Reflects the value of OUT2 bit in MCR" "High,Low"
bitfld.byte 0x00 6. "                  RI   ,Ring Indicator - Reflects the value of OUT1 bit in MCR" "High,Low"
bitfld.byte 0x00 5. "             DSR    ,Data Set Ready - Reflects the value of DTR bit in MCR" "High,Low"
bitfld.byte 0x00 4. "         CTS   ,Clear to Send - Reflects the value of RTS bit in MCR" "High,Low"
textline "           "
bitfld.byte 0x00 3. " DDCD  ,Delta Data Carrier Detect" "Not changed,Changed"
bitfld.byte 0x00 2. "           TERI ,Trailing Edge Ring Indicator" "Not occured,Occured"
bitfld.byte 0x00 1. "      DDSR   ,Delta Data Set Ready" "Not changed,Changed"
bitfld.byte 0x00 0. "  DCTS  ,Delta Clear to Send" "Not changed,Changed"
endif
group (0xFFFF0800+0x1C)--(0xFFFF0800+0x1C)
line.byte 0x00 "SCR2,UART2 Scratch Pad Register"
width 0x0B
tree.end
tree.end
tree "Serial Infrared Interface"
width 0x0A
group (0xFFFF0C00+0x0)--(0xFFFF0C00+0x0)
line.byte 0x00 "SIR_CTRL,SIR Control Register"
bitfld.byte 0x00 3. " TxP ,Tx Polarity (UART and IrDA modes only)" "Not inverted,Inverted"
bitfld.byte 0x00 2. "  RxP ,Rx Polarity (UART and IrDA modes only)" "Not inverted,Inverted"
bitfld.byte 0x00 0.--1. "  Mode ,UART2 Operation Mode" "UART,DASK,IrDA,?..."
width 0x0B
tree.end
tree "Pulse Width Modulator"
width 0x0B
wgroup (0xFFFF1000+0x00)--(0xFFFF1000+0x78)
line.byte 0x00 "PWM0_TC,PWM0 Terminal Count"
hexfld.byte 0x00 " TERMINAL_COUNT ,PWM0 Terminal Count"
line.byte 0x04 "PWM0_DC,PWM0 Duty Cycle"
hexfld.byte 0x04 " DUTY_CYCLE     ,PWM0 Duty Cycle"
line.byte 0x08 "PWM0_ENB,PWM0 Enable"
bitfld.byte 0x08 0. " ENB            ,Enable PWM0" "Disabled,Enabled"
line.byte 0x0C "PWM0_DIV,PWM0 Divide Value"
bitfld.byte 0x0C 0.--5. " DV             ,Divide Value" "Illegal,Illegal,/2,/2,/4,/4,/6,/6,/8,/8,/10,/10,/12,/12,/14,/14,/16,/16,/18,/18,/20,/20,/22,/22,/24,/24,/26,/26,/28,/28,/30,/30,/32,/32,/34,/34,/36,/36,/38,/38,/40,/40,/42,/42,/44,/44,/46,/46,/48,/48,/50,/50,/52,/52,/54,/54,/56,/56,/58,/58,/60,/60,/62,/62"
line.byte 0x10 "PWM0_SYNC,PWM0 Synchronous"
bitfld.byte 0x10 0. " SYNC           ,PWM0 Synchronous mode" "Normal,Synchronous"
line.byte 0x14 "PWM0_INV,PWM0 Invert"
bitfld.byte 0x14 0. " INV            ,Invert PWM0 Output" "Not inverted,Inverted"
line.byte 0x18 "PWM0_UPDT,PWM0 Update"
bitfld.byte 0x18 0. " UPDT           ,Update a Stopped PWM0" "Update,Update"
line.byte 0x20 "PWM1_TC,PWM1 Terminal Count"
hexfld.byte 0x20 " TERMINAL_COUNT ,PWM1 Terminal Count"
line.byte 0x24 "PWM1_DC,PWM1 Duty Cycle"
hexfld.byte 0x24 " DUTY_CYCLE     ,PWM1 Duty Cycle"
line.byte 0x28 "PWM1_ENB,PWM1 Enable"
bitfld.byte 0x28 0. " ENB            ,Enable PWM1" "Disabled,Enabled"
line.byte 0x2C "PWM1_DIV,PWM1 Divide Value"
bitfld.byte 0x2C 0.--5. " DV             ,Divide Value" "Illegal,Illegal,/2,/2,/4,/4,/6,/6,/8,/8,/10,/10,/12,/12,/14,/14,/16,/16,/18,/18,/20,/20,/22,/22,/24,/24,/26,/26,/28,/28,/30,/30,/32,/32,/34,/34,/36,/36,/38,/38,/40,/40,/42,/42,/44,/44,/46,/46,/48,/48,/50,/50,/52,/52,/54,/54,/56,/56,/58,/58,/60,/60,/62,/62"
line.byte 0x30 "PWM1_SYNC,PWM1 Synchronous"
bitfld.byte 0x30 0. " SYNC           ,PWM1 Synchronous mode" "Normal,Synchronous"
line.byte 0x34 "PWM1_INV,PWM1 Invert"
bitfld.byte 0x34 0. " INV            ,Invert PWM1 Output" "Not inverted,Inverted"
line.byte 0x38 "PWM1_UPDT,PWM1 Update"
bitfld.byte 0x38 0. " UPDT           ,Update a Stopped PWM1" "Update,Update"
line.word 0x40 "PWM2_TC,PWM2 Terminal Count"
hexfld.word 0x40 " TERMINAL_COUNT ,PWM2 Terminal Count"
line.word 0x44 "PWM2_DC,PWM2 Duty Cycle"
hexfld.word 0x44 " DUTY_CYCLE     ,PWM2 Duty Cycle"
line.byte 0x48 "PWM2_ENB,PWM2 Enable"
bitfld.byte 0x48 0. " ENB            ,Enable PWM2" "Disabled,Enabled"
line.byte 0x4C "PWM2_DIV,PWM2 Divide Value"
bitfld.byte 0x4C 0.--5. " DV             ,Divide Value" "Illegal,Illegal,/2,/2,/4,/4,/6,/6,/8,/8,/10,/10,/12,/12,/14,/14,/16,/16,/18,/18,/20,/20,/22,/22,/24,/24,/26,/26,/28,/28,/30,/30,/32,/32,/34,/34,/36,/36,/38,/38,/40,/40,/42,/42,/44,/44,/46,/46,/48,/48,/50,/50,/52,/52,/54,/54,/56,/56,/58,/58,/60,/60,/62,/62"
line.byte 0x50 "PWM2_SYNC,PWM2 Synchronous"
bitfld.byte 0x50 0. " SYNC           ,PWM2 Synchronous mode" "Normal,Synchronous"
line.byte 0x54 "PWM2_INV,PWM2 Invert"
bitfld.byte 0x54 0. " INV            ,Invert PWM2 Output" "Not inverted,Inverted"
line.byte 0x58 "PWM2_UPDT,PWM2 Update"
bitfld.byte 0x58 0. " UPDT           ,Update a Stopped PWM2" "Update,Update"
line.word 0x60 "PWMA_TC,All PWMs Terminal Count"
hexfld.word 0x60 " TERMINAL_COUNT ,All PWMs Terminal Count"
line.word 0x64 "PWMA_DC,All PWMs Duty Cycle"
hexfld.word 0x64 " DUTY_CYCLE     ,All PWMs Duty Cycle"
line.byte 0x68 "PWMA_ENB,All PWMs Enable"
bitfld.byte 0x68 0. " ENB            ,Enable All PWMs" "Disabled,Enabled"
line.byte 0x6C "PWMA_DIV,All PWMs Divide Value"
bitfld.byte 0x6C 0.--5. " DV             ,Divide Value" "Illegal,Illegal,/2,/2,/4,/4,/6,/6,/8,/8,/10,/10,/12,/12,/14,/14,/16,/16,/18,/18,/20,/20,/22,/22,/24,/24,/26,/26,/28,/28,/30,/30,/32,/32,/34,/34,/36,/36,/38,/38,/40,/40,/42,/42,/44,/44,/46,/46,/48,/48,/50,/50,/52,/52,/54,/54,/56,/56,/58,/58,/60,/60,/62,/62"
line.byte 0x70 "PWMA_SYNC,All PWMs Synchronous"
bitfld.byte 0x70 0. " SYNC           ,All PWMs Synchronous mode" "Normal,Synchronous"
line.byte 0x74 "PWMA_INV,All PWMs Invert"
bitfld.byte 0x74 0. " INV            ,Invert All PWMs Output" "Not inverted,Inverted"
line.byte 0x78 "PWMA_UPDT,All PWMs Update"
bitfld.byte 0x78 0. " UPDT           ,Update All Stopped PWMs" "Update,Update"
width 0x0B
tree.end
tree "LCD Controller"
width 0x12
wgroup (0xFFFF1400+0x00)--(0xFFFF1400+0x50)
line.byte 0x00 "LCD_MODE,Mode Register"
bitfld.byte 0x00 7. " DISP ,Display ON/OFF" "OFF,ON"
bitfld.byte 0x00 6. "          REV   ,Display Mode" "Normal,Reverse"
bitfld.byte 0x00 5. "  SCAN ,Scan Mode" "Single,Dual"
bitfld.byte 0x00 4. "  OR   ,Data from two screens mode" "Division,Logically ORing"
textline "                       "
bitfld.byte 0x00 3. " GRAY ,Gray displaying mode" "Two shades,Four shades"
bitfld.byte 0x00 2. "  XSIZE ,Data transfers (per CP2 clock) to the LCD display" "4 bits,8 bits"
bitfld.byte 0x00 1. "   LCDC ,State of the LCDCNTL output signal control" "Low,High"
bitfld.byte 0x00 0. "    LCDA ,LCD Controller Activation" "Not active,Active"
line.byte 0x04 "LCD_BC,Line Display Byte Count Register"
line.byte 0x08 "LCD_CP1W,Line Pulse Width Register"
line.byte 0x0C "LCD_DUTY[7:0],Duty Cycle Register [7:0]"
line.byte 0x10 "LCD_DUTY[9:8],Duty Cycle Register [9:8]"
line.byte 0x14 "LCD_SADR1[7:0],Screen #1 Frame Buffer Start Address Register [7:0]"
line.byte 0x18 "LCD_SADR1[15:8],Screen #1 Frame Buffer Start Address Register [15:8]"
line.byte 0x1C "LCD_SADR1[23:16],Screen #1 Frame Buffer Start Address Register [23:16]"
line.byte 0x20 "LCD_SADR1[31:24],Screen #1 Frame Buffer Start Address Register [31:24]"
line.byte 0x24 "LCD_SADR2[7:0],Screen #1 Frame Buffer Start Address Register [7:0]"
line.byte 0x28 "LCD_SADR2[15:8],Screen #1 Frame Buffer Start Address Register [15:8]"
line.byte 0x2C "LCD_SADR2[23:16],Screen #1 Frame Buffer Start Address Register [23:16]"
line.byte 0x30 "LCD_SADR2[31:24],Screen #1 Frame Buffer Start Address Register [31:24]"
line.byte 0x34 "LCD_VLC1[7:0],Vertical Line Count Register [7:0]"
line.byte 0x38 "LCD_VLC1[9:8],Vertical Line Count Register [9:8]"
line.byte 0x3C "LCD_VDLT,Virtual Display Delta Register"
line.byte 0x40 "LCD_GRAY1,Gray Shade Register 1"
line.byte 0x44 "LCD_GRAY2,Gray Shade Register 2"
line.byte 0x48 "LCD_CLKDIV,Clock Frequency Divider"
line.byte 0x4C "LCD_MCLKW [7:0],MCLK Width [7:0]"
line.byte 0x50 "LCD_MCLKW [9:8],MCLK Width [9:8]"
group (0xFFFFA400+0x14)--(0xFFFFA400+0x14)
line.byte 0x00 "LCD_BITCTL,LCD Bit Control Register"
bitfld.byte 0x00 0. " LBC  ,Frame Buffer Displaying Format" "Format #0,Format #1"
width 0x0B
tree.end
tree "Counter/Timers"
width 0x0A
group (0xFFFF1800+0x00)--(0xFFFF1800+0x08)
line.byte 0x00 "CT_CNTR0,Count Register 0"
line.byte 0x04 "CT_CNTR1,Count Register 1"
line.byte 0x08 "CT_CNTR2,Count Register 2"
wgroup (0xFFFF1800+0x0C)--(0xFFFF1800+0x0C)
line.byte 0x00 "CT_CWR,Control Word Register"
bitfld.byte 0x00 6.--7. " SC ,Select Counter" "Counter 0,Counter 1,Counter 2,ReadBack Command"
bitfld.byte 0x00 4.--5. "                 RW  ,Read/Write" "CounterLatch Command,R/W LSB only,R/W MSB only,R/W LSB followed by MSB"
textline "               "
bitfld.byte 0x00 1.--3. " M  ,Counter Mode" "Interrupt On Terminal Count,Hardware Retriggerable One-Shot,Rate Generator,Square Wave Generator,Software Triggered Strobe,Hardware Triggered Strobe,?..."
bitfld.byte 0x00 0. "  BCD ,Binary Coded Decimal" "Binary Counter,BCD Counter"
width 0x0B
tree.end
tree "Programmable peripheral Interface"
width 0x0A
group (0xFFFF1C00+0x00)--(0xFFFF1C00+0x08)
line.byte 0x00 "PPI_PA,Port A"
bitfld.byte 0x00 7. " PA.7 ,Port A.7" "Low,High"
bitfld.byte 0x00 6. "  PA.6 ,Port A.6" "Low,High"
bitfld.byte 0x00 5. "  PA.5 ,Port A.5" "Low,High"
bitfld.byte 0x00 4. "  PA.4 ,Port A.4" "Low,High"
textline "                "
bitfld.byte 0x00 3. " PA.3 ,Port A.3" "Low,High"
bitfld.byte 0x00 2. "  PA.2 ,Port A.2" "Low,High"
bitfld.byte 0x00 1. "  PA.1 ,Port A.1" "Low,High"
bitfld.byte 0x00 0. "  PA.0 ,Port A.0" "Low,High"
line.byte 0x04 "PPI_PB,Port B"
bitfld.byte 0x04 7. " PB.7 ,Port B.7" "Low,High"
bitfld.byte 0x04 6. "  PB.6 ,Port B.6" "Low,High"
bitfld.byte 0x04 5. "  PB.5 ,Port B.5" "Low,High"
bitfld.byte 0x04 4. "  PB.4 ,Port B.4" "Low,High"
textline "                "
bitfld.byte 0x04 3. " PB.3 ,Port B.3" "Low,High"
bitfld.byte 0x04 2. "  PB.2 ,Port B.2" "Low,High"
bitfld.byte 0x04 1. "  PB.1 ,Port B.1" "Low,High"
bitfld.byte 0x04 0. "  PB.0 ,Port B.0" "Low,High"
line.byte 0x08 "PPI_PC,Port C"
bitfld.byte 0x08 7. " PC.7 ,Port C.7" "Low,High"
bitfld.byte 0x08 6. "  PC.6 ,Port C.6" "Low,High"
bitfld.byte 0x08 5. "  PC.5 ,Port C.5" "Low,High"
bitfld.byte 0x08 4. "  PC.4 ,Port C.4" "Low,High"
textline "                "
bitfld.byte 0x08 3. " PC.3 ,Port C.3" "Low,High"
bitfld.byte 0x08 2. "  PC.2 ,Port C.2" "Low,High"
bitfld.byte 0x08 1. "  PC.1 ,Port C.1" "Low,High"
bitfld.byte 0x08 0. "  PC.0 ,Port C.0" "Low,High"
textline ""
if (((data.byte(sd:(0xFFFF1C00+0x0C)))&0x80)==0x00)
wgroup (0xFFFF1C00+0x0C)--(0xFFFF1C00+0x0C)
line.byte 0x00 "PPI_CTRL,PPI Control Register"
bitfld.byte 0x00 7. " CRF ,Control Register Function" "Bit Set/Reset Port C,MODE Selection/Data Direction"
bitfld.byte 0x00 1.--3. "  BS   ,Port C Bit Selection" "PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7"
bitfld.byte 0x00 0. "     S/R   ,Set/Reset Function" "Reset,Set"
else
wgroup (0xFFFF1C00+0x0C)--(0xFFFF1C00+0x0C)
line.byte 0x00 "PPI_CTRL,PPI Control Register"
bitfld.byte 0x00 7. " CRF ,Control Register Function" "Bit Set/Reset Port C,MODE Selection/Data Direction"
bitfld.byte 0x00 5.--6. "  AM   ,Group A Mode Se lect" "MODE 0,MODE 1,MODE 2,MODE 2"
bitfld.byte 0x00 4. "  AI/O  ,Group A Port A Direction" "Output,Input"
bitfld.byte 0x00 3. "  CHI/O ,Group A Port C (PC[7:4]) Direction" "Output,Input"
textline "                "
bitfld.byte 0x00 2. " BM  ,Group B MODE Select" "MODE 0,MODE 1"
bitfld.byte 0x00 1. "                         BI/O ,Group B Port B Direction" "Output,Input"
bitfld.byte 0x00 0. "  CLI/O ,Group B Port C (PC[3:0]) Direction" "Output,Input"
endif
width 0x0B
tree.end
tree "Interrupt Controller"
width 0x07
group (0xFFFFA800+0x00)--(0xFFFFA800+0x04)
line.word 0x00 "ICR0,Interrupt Configuration Register 0"
bitfld.word 0x00 11. " E/L5  ,Channel 5 Trigger Mode" "Level,Edge"
bitfld.word 0x00 10. "                H/L5  ,Channel 5 Trigger Active" "Low/Falling,High/Rising"
bitfld.word 0x00 9. "          E/L4  ,Channel 4 Trigger" "Level,Edge"
bitfld.word 0x00 8. "                H/L4 ,Channel 4 Trigger Active" "Low/Falling,High/Rising"
textline "            "
bitfld.word 0x00 7. " E/L3  ,Channel 3 Trigger" "Level,Edge"
bitfld.word 0x00 6. "                H/L3  ,Channel 3 Trigger Active" "Low/Falling,High/Rising"
bitfld.word 0x00 5. "          E/L2  ,Channel 2 Trigger" "Level,Edge"
bitfld.word 0x00 4. "                H/L2 ,Channel 2 Trigger Active" "Low/Falling,High/Rising"
textline "            "
bitfld.word 0x00 3. " E/L1  ,Channel 1 Trigger" "Level,Edge"
bitfld.word 0x00 2. "                H/L1  ,Channel 1 Trigger Active" "Low/Falling,High/Rising"
bitfld.word 0x00 1. "          E/L0  ,Channel 0 Trigger" "Level,Edge"
bitfld.word 0x00 0. "                H/L0 ,Channel 0 Trigger Active" "Low/Falling,High/Rising"
line.byte 0x04 "ICR1,Interrupt Configuration Register 1"
bitfld.byte 0x04 2. " H/L_2 ,Channel 8 Trigger Active" "Low/Falling,High/Rising"
bitfld.byte 0x04 1. "          H/L_1 ,Channel 7 Trigger Active" "Low/Falling,High/Rising"
bitfld.byte 0x04 0. "          H/L_0 ,Channel 6 Trigger Active" "Low/Falling,High/Rising"
wgroup (0xFFFFA800+0x08)--(0xFFFFA800+0x09)
line.word 0x00 "ICLR,Interrupt Clear Register"
bitfld.word 0x00 9. " CH12  ,Channel 12 Interrupt Clear" "No effect,Clear"
bitfld.word 0x00 8. "            CH8   ,Channel 8 Interrupt Clear" "No effect,Clear"
bitfld.word 0x00 7. "            CH7   ,Channel 7 Interrupt Clear" "No effect,Clear"
bitfld.word 0x00 6. "            CH6  ,Channel 6 Interrupt Clear" "No effect,Clear"
textline "            "
bitfld.word 0x00 5. " CH5   ,Channel 5 Interrupt Clear" "No effect,Clear"
bitfld.word 0x00 4. "            CH4   ,Channel 4 Interrupt Clear" "No effect,Clear"
bitfld.word 0x00 3. "            CH3   ,Channel 3 Interrupt Clear" "No effect,Clear"
bitfld.word 0x00 2. "            CH2  ,Channel 2 Interrupt Clear" "No effect,Clear"
textline "            "
bitfld.word 0x00 1. " CH1   ,Channel 1 Interrupt Clear" "No effect,Clear"
bitfld.word 0x00 0. "            CH0   ,Channel 0 Interrupt Clear" "No effect,Clear"
group (0xFFFFA800+0x0C)--(0xFFFFA800+0x11)
line.word 0x00 "IRQER,IRQ interrupt Enable Register"
bitfld.word 0x00 11. " CH11  ,Channel 11 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 10. "             CH10  ,Channel 10 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 9. "             CH9   ,Channel 9 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 8. "             CH8  ,Channel 8 IRQ Interrupt Enable" "Disabled,Enabled"
textline "            "
bitfld.word 0x00 7. " CH7   ,Channel 7 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 6. "             CH6   ,Channel 6 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 5. "             CH5   ,Channel 5 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 4. "             CH4  ,Channel 4 IRQ Interrupt Enable" "Disabled,Enabled"
textline "            "
bitfld.word 0x00 3. " CH3   ,Channel 3 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 2. "             CH2   ,Channel 2 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 1. "             CH1   ,Channel 1 IRQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x00 0. "             CH0  ,Channel 0 IRQ Interrupt Enable" "Disabled,Enabled"
line.word 0x04 "FIQER,FIQ Interrupt Enable Register"
bitfld.word 0x04 11. " CH11  ,Channel 11 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 10. "             CH10  ,Channel 10 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 9. "             CH9   ,Channel 9 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 8. "             CH8  ,Channel 8 FIQ Interrupt Enable" "Disabled,Enabled"
textline "            "
bitfld.word 0x04 7. " CH7   ,Channel 7 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 6. "             CH6   ,Channel 6 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 5. "             CH5   ,Channel 5 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 4. "             CH4  ,Channel 4 FIQ Interrupt Enable" "Disabled,Enabled"
textline "            "
bitfld.word 0x04 3. " CH3   ,Channel 3 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 2. "             CH2   ,Channel 2 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 1. "             CH1   ,Channel 1 FIQ Interrupt Enable" "Disabled,Enabled"
bitfld.word 0x04 0. "             CH0  ,Channel 0 FIQ Interrupt Enable" "Disabled,Enabled"
rgroup (0xFFFFA800+0x14)--(0xFFFFA800+0x1D)
line.word 0x00 "IRQSR,IRQ Status Register"
bitfld.word 0x00 11. " CH11  ,Channel 11 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 10. "  CH10  ,Channel 10 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 9. "  CH9   ,Channel 9 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 8. "  CH8  ,Channel 8 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
textline "            "
bitfld.word 0x00 7. " CH7   ,Channel 7 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 6. "  CH6   ,Channel 6 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 5. "  CH5   ,Channel 5 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 4. "  CH4  ,Channel 4 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
textline "            "
bitfld.word 0x00 3. " CH3   ,Channel 3 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 2. "  CH2   ,Channel 2 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 1. "  CH1   ,Channel 1 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x00 0. "  CH0  ,Channel 0 IRQ Interrupt Status" "Disabled/Not active,Enabled/Active"
line.word 0x04 "FIQSR,FIQ Status Register"
bitfld.word 0x04 11. " CH11  ,Channel 11 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 10. "  CH10  ,Channel 10 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 9. "  CH9   ,Channel 9 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 8. "  CH8  ,Channel 8 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
textline "            "
bitfld.word 0x04 7. " CH7   ,Channel 7 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 6. "  CH6   ,Channel 6 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 5. "  CH5   ,Channel 5 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 4. "  CH4  ,Channel 4 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
textline "            "
bitfld.word 0x04 3. " CH3   ,Channel 3 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 2. "  CH2   ,Channel 2 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 1. "  CH1   ,Channel 1 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
bitfld.word 0x04 0. "  CH0  ,Channel 0 FIQ Interrupt Status" "Disabled/Not active,Enabled/Active"
line.word 0x08 "IPR,Interrupt Polling Register"
bitfld.word 0x08 11. " CH11  ,Channel 11 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 10. "          CH10  ,Channel 10 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 9. "          CH9   ,Channel 9 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 8. "          CH8  ,Channel 8 Interrupt Polling" "Not pending,Pending"
textline "            "
bitfld.word 0x08 7. " CH7   ,Channel 7 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 6. "          CH6   ,Channel 6 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 5. "          CH5   ,Channel 5 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 4. "          CH4  ,Channel 4 Interrupt Polling" "Not pending,Pending"
textline "            "
bitfld.word 0x08 3. " CH3   ,Channel 3 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 2. "          CH2   ,Channel 2 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 1. "          CH1   ,Channel 1 Interrupt Polling" "Not pending,Pending"
bitfld.word 0x08 0. "          CH0  ,Channel 0 Interrupt Polling" "Not pending,Pending"
width 0x0B
tree.end
tree "Clock & Power Management"
width 0x08
group (0xFFFFAC00+0x00)--(0xFFFFAC00+0x28)
line.word 0x04 "PCSR,Peripheral Clock Select Register"
bitfld.word 0x04 8. " SIRCE         ,Serial InfraRed Clock Enable" "Disabled,Enabled"
bitfld.word 0x04 7. "   PWMCE ,PWM Clock Enable" "Disabled,Enabled"
bitfld.word 0x04 6. "   LCDCE ,LCD Controller Clock Enable" "Disabled,Enabled"
bitfld.word 0x04 5. "  CT2CS ,Counter/Timer2 Clock Source" "CPMU,CTCLK pin"
textline "             "
bitfld.word 0x04 4. " CT1CS         ,Counter/Timer1 Clock Source" "CPMU,CTCLK pin"
bitfld.word 0x04 3. "  CT0CS ,Counter/Timer0 Clock Source" "CPMU,CTCLK pin"
bitfld.word 0x04 2. "  U2CS  ,UART2 Clock Source" "CPMU,UCLK pin"
bitfld.word 0x04 1. "  U1CS  ,UART1 Clock Source" "CPMU,UCLK pin"
textline "             "
bitfld.word 0x04 0. " U0CS          ,UART0 Clock Source" "CPMU,UCLK pin"
line.word 0x08 "U0CCR,UART0 Clock Control Register"
hexmask.word 0x08 0.--8. 1. " UART0_CLK_DIV ,UART0 Clock Divisor"
line.word 0x0C "U1CCR,UART1 Clock Control Register"
hexmask.word 0x0C 0.--8. 1. " UART1_CLK_DIV ,UART1 Clock Divisor"
line.word 0x10 "U2CCR,UART2 Clock Control Register"
hexmask.word 0x10 0.--8. 1. " UART2_CLK_DIV ,UART2 Clock Divisor"
line.word 0x18 "CT0CCR,Counter/Timer0 Clock Control Register"
hexmask.word 0x18 0.--8. 1. " C/T0_CLK_DIV  ,Counter/Timer0 Clock Divisor"
line.word 0x1C "CT1CCR,Counter/Timer1 Clock Control Register"
hexmask.word 0x1C 0.--8. 1. " C/T1_CLK_DIV  ,Counter/Timer1 Clock Divisor"
line.word 0x20 "CT2CCR,Counter/Timer2 Clock Control Register"
hexmask.word 0x20 0.--8. 1. " C/T2_CLK_DIV  ,Counter/Timer2 Clock Divisor"
line.byte 0x28 "CCCR,Core Clock Control Register"
hexfld.byte 0x28 " CORE_CLK_DIV  ,Core Clock Divisor"
width 0x0B
tree.end
tree "Watchdog Timer"
width 0x08
group (0xFFFFAC00+0x30)--(0xFFFFAC00+0x30)
line.byte 0x00 "WDCTLR,Watchdog Control Register"
bitfld.byte 0x00 4.--6. "     TOP        ,Time-out Period Select" "2^17,2^19,2^21,2^23,2^25,2^27,2^29,2^31"
bitfld.byte 0x00 3. "                        FRZ ,Freeze Enable/Disable" "Disabled,Enabled"
textline "                "
bitfld.byte 0x00 1.--2. "  RSP        ,Time-out Response Selection" "Non-Maskable FIQ Interrupt,Non-Maskable FIQ Interrupt,External Reset,System Reset"
bitfld.byte 0x00 0. "  EN  ,Enable/Disable Watchdog" "Disabled,Enabled"
wgroup (0xFFFFAC00+0x34)--(0xFFFFAC00+0x37)
line.long 0x00 "WDCNTR,Watchdog Counter Register"
hexfld.long 0x00 " ount_Value ,Watchdog Count Value"
width 0x0B
tree.end
tree "I/O Configuration"
width 0x06
group (0xFFFFA400+0x10)--(0xFFFFA400+0x11)
line.word 0x00 "IOCR,I/O Configuration"
bitfld.word 0x00 13.--14. " CT2G ,Counter/Timer2 Gate Source" "CTGATE2 pin,PWM2 Output,Logic 0,Logic 1"
bitfld.word 0x00 11.--12. "  CT1G ,Counter/Timer1 Gate Source" "CTGATE1 pin,PWM1 Output,Logic 0,Logic 1"
bitfld.word 0x00 9.--10. "  CT0G ,Counter/Timer0 Gate Source" "CTGATE0 pin,PWM0 Output,Logic 0,Logic 1"
bitfld.word 0x00 8. "  PU8 ,Configure PC2/DTR0 pin" "PC2,/DTR0"
textline "           "
bitfld.word 0x00 7. " PU7  ,Configure PC1/RTS0 pin" "PC1,/RTS0"
bitfld.word 0x00 6. "        PU6  ,Configure PC0/RTS1 pin" "PC0,/RTS1"
bitfld.word 0x00 5. "        PU5  ,Configure PB7/DSR0 pin" "PB7,/DSR0"
bitfld.word 0x00 4. "        PU4 ,Configure PB6/DCD0 pin" "PB6,/DCD0"
textline "           "
bitfld.word 0x00 3. " PU3  ,Configure PB5/RI0 pin" "PB5,/RI0"
bitfld.word 0x00 2. "         PU2  ,Configure PB4/CTS0 pin" "PB4,/CTS0"
bitfld.word 0x00 1. "        PU1  ,Configure PB3/CTS1 pin" "PB3,/CTS1"
bitfld.word 0x00 0. "        PU0 ,Configure PB2/RI1 pin" "PB2,/RI1"
width 0x0B
tree.end
tree "Reset"
width 0x07
group (0xFFFFAC00+0x38)--(0xFFFFAC00+0x38)
line.byte 0x00 "SWRST,Software Controlled Reset"
bitfld.byte 0x00 0. " SWRST ,Software Controlled Reset" "/RESETO is driven HIGH,/RESETO is driven LOW"
width 0x0B
tree.end
tree "Identification"
width 0x05
rgroup (0xFFFFA400+0x0C)--(0xFFFFA400+0x0D)
line.word 0x00 "IDR,Identification Register"
bitfld.word 0x00 13.--15. " FAM ,Family Name" "000,Summit Family (LH77790A),010,011,100,101,110,111"
bitfld.word 0x00 12. "  T ,Thumb Aware" "Not supported,Supported"
hexmask.word.byte 0x00 6.--11. 1. "  MEM ,Member Name"
hexmask.word.byte 0x00 0.--5. 1. "  PROD ,Production Revision"
width 0x0B
tree.end